RADIATION-EMPLOYING SEMICONDUCTOR CHIP

Abstract

A radiation-emitting semiconductor chip (1) configured to emit electromagnetic radiation from a radiation-emitting surface (2) during operation, comprising: - a substrate (3) on which a first epitaxial semiconductor layer sequence (4) of a first conductivity type and a second epitaxial semiconductor layer sequence (5) of a second conductivity type different from the first conductivity type are arranged, - a first current expansion layer (7) arranged between the first semiconductor layer sequence (4) and the substrate (3), - a second current expansion layer (8) arranged between the first current expansion layer (7) and the substrate (3), - a dielectric layer (9) arranged region by region between the first current expansion layer (7) and the second current expansion layer (8), - a reflective layer (10) arranged between the second current expansion layer (8) and the substrate (3),- an electrically insulating layer (11) which is arranged in certain areas between the second current expansion layer (8) and the reflective layer (10), and- the reflective layer (10) and the second current expansion layer (8) are in electrically conductive contact, and- the reflective layer (10) and the second current expansion layer (8) are in direct contact in certain areas.

Description

A radiation-emitting semiconductor chip is specified. The publication DE 10 2007 022 947 A1 describes an optoelectronic semiconductor body and a method for manufacturing such a body, the publication DE 10 2008 051 050 A1 describes a module with optoelectronic semiconductor elements, the publication DE 10 2010 025 320 A1 describes an optoelectronic component and a method for manufacturing it, and the publication DE 10 2011 015 821 A1 describes an optoelectronic semiconductor chip. One problem to be solved is to specify a radiation-emitting semiconductor chip that exhibits particularly homogeneous brightness. In particular, the radiation-emitting semiconductor chip should have a particularly good quantum efficiency. These problems are solved by a radiation-emitting semiconductor chip with the features of claim 1. Advantageous embodiments of the radiation-emitting semiconductor chip are the subject of the dependent claims. The radiation-emitting semiconductor chip is designed to emit electromagnetic radiation from a radiation-emitting surface during operation. The electromagnetic radiation emitted by the radiation-emitting semiconductor chip can be near-ultraviolet radiation, visible light, and / or near-infrared radiation. The radiation-emitting semiconductor chip preferably has a principal extension plane. A vertical direction preferably extends perpendicular to the principal extension plane, and a lateral direction preferably extends parallel to the principal extension plane. The radiation-emitting semiconductor chip comprises a substrate on which a first epitaxial semiconductor layer sequence of a first conductivity type and a second epitaxial semiconductor layer sequence of a second conductivity type different from the first are arranged. Preferably, the first semiconductor layer sequence and the second semiconductor layer sequence are epitaxially grown one above the other. That is, the first semiconductor layer sequence and the second semiconductor layer sequence are stacked vertically on top of each other. Preferably, the first semiconductor layer sequence is p-doped and thus p-type. Furthermore, the second semiconductor layer sequence is preferably n-doped and thus n-type. Thus, the first conductivity type is preferably a p-type and the second conductivity type is preferably an n-type. An active region is preferably arranged between the first and second semiconductor layer sequences. The active region is configured to generate electromagnetic radiation during operation, which is emitted from the radiation exit surface. The active region preferably borders directly on the first and second semiconductor layer sequences. The active region preferably features a pn junction for generating the electromagnetic radiation, such as a double heterostructure, a single quantum well structure, or a multiple quantum well structure. The first and second semiconductor layer sequences are preferably based on a III-V compound semiconductor material. This compound semiconductor material can be a nitride compound semiconductor material. Nitride compound semiconductor materials are compound semiconductor materials containing nitride, which are the materials from the system InxAlyGa1-x-yN with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The first semiconductor layer sequence is preferably arranged on the substrate with one of its base surfaces opposite the radiation emission surface. That is, the substrate, the first semiconductor layer sequence, and the second semiconductor layer sequence are preferably stacked vertically on top of each other. In this embodiment, the first semiconductor layer sequence is preferably located closer to the substrate than the second semiconductor layer sequence. The support is preferably a mechanically stabilizing component of the radiation-emitting semiconductor chip. The support can be, for example, a printed circuit board (PCB) or a lead frame. The radiation-emitting semiconductor chip comprises a first current-expansion layer arranged between the first semiconductor layer sequence and the substrate. In this embodiment, the substrate, the first current-expansion layer, and the first semiconductor layer sequence are stacked vertically on top of each other, particularly in the specified order. The first current-expansion layer is preferably in direct contact with the first semiconductor layer sequence. Furthermore, the first current-expansion layer is preferably arranged on the bottom surface of the first semiconductor layer sequence. The first current-expansion layer preferably covers a large portion of the base area of ​​the first semiconductor layer sequence. "Large portion" here means, in particular, that the first current-expansion layer covers at least 90%, and especially preferably 95%, of the base area of ​​the first semiconductor layer sequence. Furthermore, it is possible for the first current-expansion layer to completely cover the base area of ​​the first semiconductor layer sequence. The radiation-emitting semiconductor chip comprises a second current-expansion layer arranged between the first current-expansion layer and the substrate. In this embodiment, the substrate, the second current-expansion layer, the first current-expansion layer, the first semiconductor layer sequence, and the second semiconductor layer sequence are arranged vertically stacked on top of each other, particularly in the specified order. The first current expansion layer and / or the second current expansion layer are preferably transparent to the electromagnetic radiation generated during the operation of the radiation-emitting semiconductor chip. Preferably, the first current expansion layer and / or the second current expansion layer are formed with a transparent, electrically conductive material. The first current expansion layer and / or the second current expansion layer is preferably configured to absorb at most 4%, and in particular at most 2%, of the electromagnetic radiation generated by the active area. Consequently, the first current expansion layer and / or the second current expansion layer transmits at least 96%, and in particular at least 98%, of the electromagnetic radiation generated by the active area. When the electromagnetic radiation generated by the active region is absorbed, this is generally due to free charge carrier absorption. The absorption is typically proportional to the thickness of the first current expansion layer and / or the second current expansion layer. The first current-expansion layer and / or the second current-expansion layer preferably consist of, or are composed of, electrically conductive metals or transparent conductive oxides (TCOs). Examples of TCOs include zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, and indium tin oxide (ITO). Typically, the TCOs are doped with a dopant. This dopant is generally designed to impart electrically conductive properties to the TCOs. Preferably, the second current-expansion layer has a lateral extent that is essentially equal to the lateral extent of the first current-expansion layer. "Essentially equal" here means that the lateral extent of the first current-expansion layer differs from the lateral extent of the second current-expansion layer by no more than 1 micrometer. The radiation-emitting semiconductor chip comprises a dielectric layer that is arranged in certain regions between the first current expansion layer and the second current expansion layer. The second current expansion layer, the dielectric layer, and the first current expansion layer are preferably stacked vertically, particularly in the specified order. Preferably, the dielectric layer is in direct contact with both the first and second current expansion layers. Furthermore, in the regions where the dielectric layer is located between the first and second current expansion layers, the first and second current expansion layers are not in direct contact. The dielectric layer preferably comprises a dielectric material or is formed from a dielectric material. Furthermore, the dielectric layer is preferably electrically insulating. The dielectric layer preferably has a refractive index that is lower than the refractive index of the first current-expansion layer and / or the refractive index of the second current-expansion layer. The refractive index of the first current-expansion layer and / or the refractive index of the second current-expansion layer is, for example, between 1.5 and 2.0, and in particular between 1.7 and 2.0. In this case, the refractive index of the dielectric layer is preferably at least 1.38 and at most 1.80, and in particular approximately 1.46 or approximately 1.50. It is particularly preferred that the refractive index of the dielectric layer is at least 0.2 lower than the refractive index of the first current-expansion layer and / or the second current-expansion layer. The radiation-emitting semiconductor chip comprises a reflective layer arranged between the second current-expansion layer and the substrate. The substrate, the reflective layer, the second current-expansion layer, the dielectric layer, the first current-expansion layer, the first semiconductor layer sequence, and the second semiconductor layer sequence are preferably arranged vertically stacked on top of each other, particularly in the specified order. The reflective layer preferably has a reflectivity of at least 90%, and in particular at least 95%, for the electromagnetic radiation generated by the active area. Preferably, the reflective layer comprises a reflective metal, such as silver. In this case, the reflective layer is generally electrically conductive. The radiation-emitting semiconductor chip comprises an electrically insulating layer that is arranged in certain regions between the second current-expansion layer and the reflective layer. Preferably, the electrically insulating layer is in direct contact with the second current-expansion layer and the reflective layer. Preferably, the second current-expansion layer and the reflective layer are not in direct contact in the regions where the insulating layer is arranged between the second current-expansion layer and the reflective layer. Preferably, the reflective layer, the electrically insulating layer, the first current expansion layer, the dielectric layer, the first current expansion layer, the first semiconductor layer sequence and the second semiconductor layer sequence are arranged one above the other in the vertical direction, particularly in the specified order. The electrically insulating layer preferably comprises an electrically insulating material, such as a dielectric material, or is formed from such a material. The material of the electrically insulating layer is, for example, silicon dioxide. The electrically insulating layer preferably has a thickness in the vertical direction of at most 50 nanometers, and in particular at most 10 nanometers. Furthermore, it is possible that the electrically insulating layer consists of at most 10 monolayers, and in particular at most 2 monolayers, of the material of the electrically insulating layer. The reflective layer and the second current expansion layer are in electrically conductive contact. According to a preferred embodiment, the radiation-emitting semiconductor chip is configured to emit electromagnetic radiation from a radiation-emitting surface during operation. The radiation-emitting semiconductor chip further comprises a substrate on which a first epitaxial semiconductor layer sequence of a first conductivity type and a second epitaxial semiconductor layer sequence of a second conductivity type different from the first are arranged. The radiation-emitting semiconductor chip also comprises a first current-expansion layer arranged between the first semiconductor layer sequence and the substrate, and a second current-expansion layer arranged between the first current-expansion layer and the substrate. A dielectric layer is arranged in a region between the first current-expansion layer and the second current-expansion layer.Furthermore, the radiation-emitting semiconductor chip comprises a reflective layer located between the second current expansion layer and the substrate, and an electrically insulating layer located in certain areas between the second current expansion layer and the reflective layer. The reflective layer and the second current expansion layer are also in electrically conductive contact. The first semiconductor layer sequence, which is typically p-doped, generally exhibits lower lateral conductivity than the second semiconductor layer sequence, which is typically n-doped. Since lateral conductivity is generally inversely proportional to sheet resistance, the first semiconductor layer sequence has a higher sheet resistance than the second. If the sheet resistances of the first and second semiconductor layer sequences differ by more than 100%, particularly by more than 50%, the current density in the active region is typically highly inhomogeneous. One feature of the radiation-emitting semiconductor chip described here is the arrangement of a first current expansion layer and a second current expansion layer on the first semiconductor layer sequence. This allows the sheet resistance of a layer sequence comprising the first semiconductor layer sequence, the first current expansion layer, and the second current expansion layer to be advantageously increased. The sheet resistance of the layer sequence can thus be advantageously matched to the sheet resistance of the second semiconductor layer sequence. Such a radiation-emitting semiconductor chip exhibits a particularly homogeneous current density in the active region. Consequently, the radiation-emitting semiconductor chip also exhibits particularly good quantum efficiency. Another feature of the radiation-emitting semiconductor chip described here is the placement of a dielectric layer in certain areas between the first and second current expansion layers. Since the dielectric layer preferably has a refractive index lower than that of the first and second current expansion layers, electromagnetic radiation is advantageously reflectable by the dielectric layer. This means that electromagnetic radiation does not have to pass completely through the current expansion layers before being reflected by the reflective layer. In this way, the current expansion layers advantageously absorb comparatively little electromagnetic radiation from the active region. If a radiation-emitting semiconductor chip lacks an electrically insulating layer, the propagation paths of charge carriers in the first and second semiconductor layer sequences are typically of different lengths. Consequently, the charge carriers imprinted in the semiconductor layer sequences are subject to different series resistances. Another feature of the radiation-emitting semiconductor chip described here is that an electrically insulating layer is positioned in certain areas between the second current-expansion layer and the reflective layer. This means that the reflective layer is only in direct contact with the second current-expansion layer in specific areas. Advantageously, the series resistances can be adjusted. This makes it possible to achieve a particularly homogeneous current density in such a radiation-emitting semiconductor chip in the active region. According to at least one embodiment of the semiconductor chip, the electrically insulating layer covers at least 90% of the second current expansion layer. Preferably, the electrically insulating layer covers at least 95%, and more preferably at least 99%, of the second current expansion layer. According to at least one embodiment of the semiconductor chip, the electrically insulating layer has at least one first recess in which the reflective layer and the second current-expansion layer are in electrically conductive contact. The first recess preferably penetrates the insulating layer completely. Preferably, charge carriers can be imprinted into the first semiconductor layer sequence exclusively through the first recess via the first current-expansion layer and the second current-expansion layer. According to at least one embodiment of the semiconductor chip, the first recess has a width of at least 100 nanometers and at most 25 micrometers. Preferably, the first recess has a width of at least 1 micrometer and at most 10 micrometers, and more preferably, at least 1 micrometer and at most 5 micrometers. For example, the first recess has a width of approximately 5 micrometers. According to at least one embodiment of the semiconductor chip, the dielectric layer is configured to reflect electromagnetic radiation towards the radiation emission surface. Preferably, the dielectric layer comprises several sublayers. These sublayers preferably also comprise a dielectric material. The dielectric layer preferably comprises alternating sublayers of a high-refractive-index and a low-refractive-index material. The sublayers preferably comprise SiO₂, Al₂O₃, TiO₂, tantalum oxide, Nb₂O₅, MgF₂, silicon nitrides, and / or silicon oxynitrides. The dielectric mirror layer preferably has a reflectivity of at least 98%, and in particular at least 99%, for the electromagnetic radiation generated in the active area. According to at least one embodiment of the semiconductor chip, the thickness of the first current expansion layer is smaller than the thickness of the second current expansion layer. The thickness of the first current expansion layer is preferably at least 5 nanometers and at most 50 nanometers, and more preferably at least 15 nanometers and at most 30 nanometers. The thickness of the second current expansion layer is preferably at least 50 nanometers and at most 1 micrometer, and more preferably at least 100 nanometers and at most 400 nanometers, and more particularly approximately 200 nanometers. Advantageously, in an arrangement described here, the thickness of the second current expansion layer does not need to be considered with regard to absorption losses of electromagnetic radiation in the second current expansion layer. According to at least one embodiment of the semiconductor chip, the dielectric layer has second recesses. The second recesses preferably penetrate the dielectric layer completely. According to at least one embodiment of the semiconductor chip, the first current expansion layer is in electrically conductive contact with the second current expansion layer in the second recesses. Preferably, charge carriers can be imprinted into the first semiconductor layer sequence exclusively via the second recesses through the first current expansion layer. According to at least one embodiment of the semiconductor chip, the second recesses are arranged at lattice points of a lattice. The lattice is preferably a polygonal lattice, such as an orthogonal lattice or a hexagonal lattice. The lattice can be a regular lattice. Alternatively, the lattice can be an irregular lattice. According to at least one embodiment of the semiconductor chip, the second recesses each have a diameter of at least 100 nanometers and at most 10 micrometers. Preferably, the diameter corresponds to the maximum lateral extent of one of the second recesses. For example, the diameters of the second recesses are each approximately 1 micrometer. Preferably, the second recesses have a surface area fraction of at most 5%, and more preferably at most 1%, of the surface area in the lateral direction of the first current expansion layer. According to at least one embodiment, the radiation-emitting semiconductor chip comprises at least one first contact structure configured to induce current in the first semiconductor layer sequence. In particular, the first contact structure is configured to induce charge carriers in the first semiconductor layer sequence. The first contact structure preferably comprises or consists of an electrically conductive metal. This metal could be, for example, one of the following materials: copper, gold, platinum, titanium, aluminum, or silver. According to at least one embodiment, the radiation-emitting semiconductor chip comprises at least a second contact structure configured to induce current in the second semiconductor layer sequence. In particular, the second contact structure is configured to induce charge carriers in the second semiconductor layer sequence. Preferably, the second contact structure is not in direct contact with the first semiconductor layer sequence at any point. Furthermore, the electrically conductive metal of the first contact structure can be the same as the electrically conductive metal of the second contact structure. Furthermore, the radiation-emitting semiconductor chip may have several second contact structures. The second contact structures are preferably arranged parallel to each other. In this case, the radiation-emitting semiconductor chip also has several first contact structures, with each first contact structure preferably arranged between two second contact structures. The first contact structures preferably extend parallel to the second contact structures. Furthermore, the first contact structures preferably cover a large portion of the area between two second contact structures. "Large portion" here means, in particular, that each first contact structure covers at least 90%, and especially preferably at least 95%, of the area between two second contact structures. According to at least one embodiment of the semiconductor chip, charge carriers imprinted in the semiconductor layer sequences propagate along different propagation paths, each of which has a series resistance. According to at least one embodiment of the semiconductor chip, each propagation path originates from the second contact structure and extends through each of the second recesses to the first recess. According to at least one embodiment of the semiconductor chip, the series resistances of different propagation paths are essentially the same. The term "essentially the same" means here and in the following that the series resistances of different propagation paths differ by no more than 5%, and in particular by no more than 1%. According to at least one embodiment of the semiconductor chip, the first contact structure is arranged between the reflective layer and the substrate. The first contact structure is preferably in direct contact with the reflective layer. According to at least one embodiment of the semiconductor chip, the second contact structure extends through a third recess through the first semiconductor layer sequence to the second semiconductor layer sequence. Preferably, the third recess partially exposes the second semiconductor layer sequence. That is, the third recess extends partially into the second semiconductor layer sequence in the vertical direction. In this case, a cover surface of the third recess is preferably formed by the second semiconductor layer sequence. The side surfaces of the third recess adjacent to the cover surface of the third recess are preferably formed by the first semiconductor layer sequence, the active area, and the second semiconductor layer sequence. The side surfaces of the third recess are preferably perpendicular to the cover surface of the third recess.Alternatively, the side surfaces of the third recess can form an angle with the top surface of the third recess that is other than 90°. In this embodiment, the second contact structure is arranged in the third recess. The second contact structure is preferably electrically connected to the second semiconductor layer sequence via the top surface of the third recess. Preferably, the first contact structure is arranged at a lateral distance from the side surfaces of the third recess. According to at least one embodiment of the semiconductor chip, a separating layer is arranged on at least one side surface of the first contact structure. According to at least one embodiment of the semiconductor chip, a separating layer is arranged on at least one side surface of the second contact structure. The separating layer preferably comprises an electrically insulating material or is formed from such a material. Furthermore, the separating layer can have at least two sublayers. The separating layer preferably comprises Al₂O₃, SiO₂, and / or Si₃N₄ or is formed from one of these materials. Preferably, the separating structure prevents any electrically conductive contact between the first and second contact structures. In particular, the separating structure electrically isolates the second contact structure from the first semiconductor layer sequence. According to at least one embodiment of the semiconductor chip, the first recess is spaced laterally from the second contact structure. For example, the lateral distance between the first recess and the second contact structure is at least 20 micrometers, and in particular at least 500 micrometers. According to at least one embodiment of the semiconductor chip, the second contact structure and the first recess extend parallel to each other. Preferably, the second contact structure and the first recess each have a length. The lengths preferably correspond to a maximum extent in the lateral direction. The lengths preferably each extend along a principal direction of extension. The principal directions of extension are preferably arranged parallel to each other and extend in the lateral direction. Such a parallel arrangement of the second contact structure and the first recess allows the charge carriers to be imprinted to spread particularly homogeneously in the first semiconductor layer sequence and / or the second semiconductor layer sequence. This advantageously results in a particularly high homogeneity of current density in the active region. The length of the second contact structure and the length of the first recess are essentially the same. The term "essentially the same" means, here and in the following, that the lengths differ by no more than 5 micrometers. The length of the second contact structure and the length of the first recess are preferably each at least 100 micrometers and at most 5 millimeters, and more preferably at least 500 micrometers and at most 1 millimeter. If the radiation-emitting semiconductor chip comprises several secondary contact structures, several primary recesses are preferably arranged in the electrically insulating layer. The secondary contact structures and the primary recesses preferably extend parallel to each other. Furthermore, the secondary contact structures and the primary recesses are preferably arranged alternately. In this case, the primary recesses are preferably located centrally between each pair of secondary contact structures. If the radiation-emitting semiconductor chip comprises several second contact structures, several second recesses are preferably arranged between each of the second contact structures and one of the first recesses. In this case, the second recesses preferably extend parallel to the first recesses and the second contact structures. According to at least one embodiment of the semiconductor chip, the second recesses and the second contact structure extend parallel to each other. Preferably, the second recesses each have a length. These lengths preferably extend along a principal direction of extension. The principal directions of extension of the second recesses are preferably arranged parallel to each other. The length of the second recess and the length of the first recess are essentially the same. The term "essentially the same" here and in the following text means that the lengths differ from each other by no more than 5 micrometers. Furthermore, the second recesses each have a lateral dimension, perpendicular to the main direction of extension of the second recesses, of at least 100 nanometers and at most 10 micrometers. For example, the lateral dimension of the second recesses is approximately 1 micrometer. The second recesses have a spacing along their main direction of extension of at least 1 micrometer and at most 100 micrometers. Preferably, the second recesses have a spacing between them of at least 10 micrometers and at most 50 micrometers. According to at least one embodiment of the semiconductor chip, the first contact structure is completely covered by the reflective layer. Furthermore, it is possible that the reflective layer extends laterally beyond the first contact structure. According to at least one embodiment of the semiconductor chip, the first contact structure and / or the second contact structure are arranged in an electrically conductive manner on the substrate. Preferably, an electrically conductive adhesive layer is arranged between the first contact structure and / or the second contact structure and the substrate. The adhesive layer preferably comprises a solderable metal or is formed from a solderable metal. The radiation-emitting semiconductor chip is explained in more detail below with reference to the figures and exemplary embodiments. Figures 1 and 2 show a schematic sectional view of a radiation-emitting semiconductor chip according to one embodiment, and Figure 3 shows a schematic top view of a radiation-emitting semiconductor chip according to one embodiment. Identical, similar, or similarly effective elements in the figures are marked with the same reference symbols. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements may be exaggerated for clarity and / or to improve representation. The radiation-emitting semiconductor chip 1 according to the embodiment shown in Figs. 1 and 2 comprises a substrate 3 on which a first epitaxial semiconductor layer sequence 4 of a first conductivity type and a second epitaxial semiconductor layer sequence 5 of a second conductivity type different from the first are arranged. In this embodiment, the first semiconductor layer sequence 4 is p-doped. Furthermore, the second semiconductor layer sequence is n-doped. An active region 6 is arranged between the first semiconductor layer sequence 4 and the second semiconductor layer sequence 5. This active region is configured to generate electromagnetic radiation during operation, which is emitted from a radiation emission surface 2 of the semiconductor chip 1. A top surface of the second semiconductor layer sequence 5, facing away from the substrate 3, encompasses the radiation emission surface 2. Furthermore, the top surface of the second semiconductor layer sequence 5 is structured. Advantageously, the electromagnetic radiation generated in the active region 6 can be coupled out particularly well. A bottom surface of the first semiconductor layer sequence 4 faces the substrate 3. Between the first semiconductor layer sequence 4 and the support 3, a first current expansion layer 7 and a second current expansion layer 8 are arranged. The first current expansion layer 7 is in direct contact with the base surface of the first semiconductor layer sequence 4. The first current expansion layer 7 and the second current expansion layer 8 are transparent to the electromagnetic radiation generated during the operation of the radiation-emitting semiconductor chip. In this embodiment, the first current expansion layer 7 and the second current expansion layer 8 are ITO or are formed from it. Furthermore, the thickness of the first current expansion layer 7 is smaller than the thickness of the second current expansion layer 8. In this embodiment, the thickness of the first current expansion layer 7 is approximately 15 nanometers. The thickness of the second current expansion layer 8 is approximately 90 nanometers. A dielectric layer 9 is arranged in a region between the first current expansion layer 7 and the second current expansion layer 8. The dielectric layer 9 is in direct contact with the first current expansion layer 7 at one of its outer surfaces facing the first current expansion layer 7. Furthermore, the dielectric layer 9 is in direct contact with the second current expansion layer 8 at one of its outer surfaces facing the second current expansion layer 8. The dielectric layer 9 also has second recesses 13. These second recesses 13 completely penetrate the dielectric layer. The first current expansion layer 7 is in direct and electrically conductive contact with the second current expansion layer 8 within these second recesses 13. Furthermore, a reflective layer 10 is arranged between the second current-expansion layer 8 and the carrier 3. In this embodiment, the reflective layer 10 comprises silver. Furthermore, an electrically insulating layer 11 is arranged in certain areas between the second current-expansion layer 8 and the reflective layer 10. The electrically insulating layer 11 is in direct contact with the reflective layer 10 and the second current-expansion layer 8 and is also electrically insulating. The electrically insulating layer 11 has a first recess 12. The first recess 12 completely penetrates the electrically insulating layer 11. The second current-expansion layer 8 is in direct and electrically conductive contact with the reflective layer 10 in the first recess 12. Furthermore, a first contact structure 14 is arranged between the reflective layer 10 and the substrate, which is designed to induce current in the first semiconductor layer sequence 4. Laterally spaced from the first contact structure 14, a third recess 16 extends through the first semiconductor layer sequence 4 to the second semiconductor layer sequence 5. The third recess 16 extends partially into the second semiconductor layer sequence 5 in a vertical direction, partially exposing it. The third recess 16 comprises a second contact structure 15, which is designed to induce current in the second semiconductor layer sequence 5. In this embodiment, a contact layer is arranged between the second contact structure 15 and the second semiconductor layer sequence 5. Furthermore, a separating layer 17 is arranged between the side surfaces of the third recess 16 and the second contact structure 15. The separating layer 17 is also arranged on the bottom surface of the second contact structure 15 facing away from the second semiconductor layer sequence 5. In this embodiment, the separating layer 17 comprises two sublayers, one of which consists of Al₂O₃ and the other of which consists of SiO₂. In this embodiment, the first contact structure 14 is electrically conductively attached to the carrier 3 by an adhesive layer 18. During operation of the radiation-emitting semiconductor chip 1, charge carriers are impressed into the second semiconductor layer sequence 5 via the second contact structure 15. The charge carriers then propagate along various propagation paths I1, I2, I3 in the first semiconductor layer sequence 4 and the second semiconductor layer sequence 5. Each of these propagation paths exhibits a series resistance. If the radiation-emitting semiconductor chip 1 does not have an electrically insulating layer 11, each propagation path I1, I2, I3 originates from the second contact structure and extends through one of the second recesses to the reflective layer 12. The propagation paths I1, I2, I3 and the corresponding series resistances are therefore all different from one another. In this case, the series resistance of propagation path I1 through the nearest second recess 13 would be lowest. The propagation path I3 through a second recess 13 located further away from the second contact structure 15 would be comparatively high in this case. In this embodiment, however, the radiation-emitting semiconductor chip 1 has the electrically insulating layer 11, so that the propagation paths I1, I2, I3 extend from the second contact structure 15 through each of the second recesses 13 to the first recess 12 of the insulating layer 11. This means that the series resistances of different propagation paths I1, I2, I3 are essentially the same. Such a radiation-emitting semiconductor chip 1 thus exhibits a particularly homogeneous current density in the active region 6. The radiation-emitting semiconductor chip 1 according to the embodiment of Fig. 3 comprises several of the third recesses 16, in each of which a second contact structure 15 is arranged. Furthermore, the radiation-emitting semiconductor chip 1 comprises several of the first recesses 12. The second contact structures 15 and the first recesses 12 extend parallel to each other. Furthermore, the second contact structures 15 and the first recesses 12 are arranged alternately. In this embodiment, the first recesses 12 are each located centrally between two second contact structures 15. Furthermore, the second recesses 13 and the second contact structure 15 extend parallel to each other. Several of the second recesses 13 are arranged between each of the second contact structures 15 and one of the first recesses 12. Priority is claimed for the German patent application DE 10 2019 126 026 A1. The features and embodiments described in connection with the figures can be combined with one another according to further embodiments, even if not all combinations are explicitly described. Furthermore, the embodiments described in connection with the figures can alternatively or additionally have further features as described in the general section. Reference symbol list 1 Radiation-emitting semiconductor chip 2 Radiation emission surface 3 Support 4 First semiconductor layer sequence 5 Second semiconductor layer sequence 6 Active region 7 First current expansion layer 8 Second current expansion layer 9 Dielectric layer 10 Reflective layer 11 Insulating layer 12 First notch 13 Second notch 14 First contact structure 15 Second contact structure 16 Third notch 17 Separator layer 18 Contact plate layer 19 Contact layer A Section I1, I2, I3 Propagation path

Claims

A radiation-emitting semiconductor chip (1) configured to emit electromagnetic radiation from a radiation-emitting surface (2) during operation, comprising: - a substrate (3) on which a first epitaxial semiconductor layer sequence (4) of a first conductivity type and a second epitaxial semiconductor layer sequence (5) of a second conductivity type different from the first conductivity type are arranged, - a first current-expansion layer (7) arranged between the first semiconductor layer sequence (4) and the substrate (3), - a second current-expansion layer (8) arranged between the first current-expansion layer (7) and the substrate (3), - a dielectric layer (9) arranged region by region between the first current-expansion layer (7) and the second current-expansion layer (8), - a reflective layer (10) arranged between the second current-expansion layer (8) and the substrate (3),- an electrically insulating layer (11) which is arranged in certain areas between the second current expansion layer (8) and the reflective layer (10), and- the reflective layer (10) and the second current expansion layer (8) are in electrically conductive contact, and- the reflective layer (10) and the second current expansion layer (8) are in direct contact in certain areas. Radiation-emitting semiconductor chip (1) according to claim 1, wherein the electrically insulating layer (11) covers at least 90% of the second current expansion layer (8). Radiation-emitting semiconductor chip (1) according to claim 2, wherein the electrically insulating layer (10) has at least a first recess (12) in which the reflective layer (10) and the second current expansion layer (8) are in electrically conductive contact. Radiation-emitting semiconductor chip (1) according to claim 3, wherein the first recess (12) has a width of at least 500 nanometers and at most 50 micrometers. Radiation-emitting semiconductor chip (1) according to one of the preceding claims, wherein the thickness of the first current expansion layer (7) is less than the thickness of the second current expansion layer (8). Radiation-emitting semiconductor chip (1) according to one of the preceding claims, wherein the dielectric layer (9) is configured to reflect electromagnetic radiation in the direction of the radiation emission surface (2). Radiation-emitting semiconductor chip (1) according to one of the preceding claims, wherein the dielectric layer (9) has second recesses (13), and the first current expansion layer (7) is in electrically conductive contact with the second current expansion layer (8) in the second recesses (13). Radiation-emitting semiconductor chip (1) according to claim 7, wherein the second recesses (13) are arranged at lattice points of a lattice, and the second recesses (13) each have a diameter of at least 100 nanometers and at most 10 micrometers. Radiation-emitting semiconductor chip (1) according to one of the preceding claims comprising: - at least a first contact structure (14) designed to induce current into the first semiconductor layer sequence (4), and - at least a second contact structure (15) designed to induce current into the second semiconductor layer sequence (5). Radiation-emitting semiconductor chip (1) according to claim 9, wherein the first contact structure (14) is arranged between the reflective layer (10) and the support (3), and the second contact structure (15) extends through a third recess (16) through the first semiconductor layer sequence (4) to the second semiconductor layer sequence (5). Radiation-emitting semiconductor chip (1) according to one of claims 9 to 10, in which a separating layer (17) is arranged on at least one side surface of the first contact structure (14), or a separating layer (17) is arranged on at least one side surface of the second contact structure (15). Radiation-emitting semiconductor chip (1) according to one of the preceding claims, wherein the first recess (12) is arranged spaced apart in the lateral direction from the second contact structure (15). Radiation-emitting semiconductor chip (1) according to claim 12, wherein the second contact structure (15) and the first recess (12) extend parallel to each other. Radiation-emitting semiconductor chip (1) according to claims 12 or 13, in which charge carriers imprinted in the semiconductor layer sequences (4, 5) propagate along different propagation paths (I1, I2, I3), each having a series resistance, each propagation path (I1, I2, I3) originates from the second contact structure (15) and extends through each of the second recesses (13) to the first recess (12), and the series resistances of different propagation paths (I1, I2, I3) are essentially the same. Radiation-emitting semiconductor chip (1) according to one of claims 9 to 14, wherein the first contact structure (14) is completely covered by the reflective layer (10). Radiation-emitting semiconductor chip (1) according to claims 7 and 9, wherein the second recesses (13) and the second contact structure (15) extend parallel to each other. Radiation-emitting semiconductor chip (1) according to claims 9 to 16, wherein the first contact structure (14) and / or the second contact structure (15) are arranged electrically conductively on the substrate (3).

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