Managing data structures in multiple memory units that require reset after initialization

Abstract

Computer program product for managing data in a plurality of memory units (1161, 1162, 116 n ) in a data processing system (104), the computer program product comprising a computer-readable storage medium having embodied thereon computer-readable code which, when executed, performs operations, the operations comprising: Indicating that data structures (1181) are reset from a first-level memory unit (1161) to a second-level memory unit (1162) during system initialization, the first-level memory unit having a lower latency than the second-level memory unit, the data structures being identified as having a file name or object name and comprising configuration information for the data processing system generated by an operating system during system initialization; and immediately copying (304), as part of completing the system initialization and generating the data structures in the first-level memory unit, the data structures indicated to be moved back from the first-level memory unit to the second-level memory unit as part of the system initialization, and removing (304) the data structures indicated to be moved back from the first-level memory unit as part of the system initialization.

Description

TECHNICAL FIELD

[0001] The present invention relates to a computer program product, a system and a method for managing data structures in a plurality of memory units, which are specified to be reset after initialization of the data structures. BACKGROUND

[0002] A Storage Class Memory (SCM) system uses low-latency dynamic random-access memory (DRAM) and one or more higher-latency NAND flash memory units, which are more cost-effective than DRAM, to provide more storage capacity at a lower cost in the memory or cache by using lower-cost, higher-latency NAND units. The SCM allows the memory to be expanded with fast-access, non-volatile NAND units.

[0003] Flash memory devices have a lower endurance than DRAM because there is a limited number of erase cycles for flash bit cells, far fewer than for DRAM cells. One prior art technique for reducing wear on flash memory devices is to use wear-leveling techniques that distribute write operations across multiple flash memory cells in the same or a different device to avoid overstressing specific flash memory devices.

[0004] There is a need in the art for improved techniques for managing the storage of data in the multiple memory units in a memory subsystem such as an SCM system.

[0005] US 2014 / 0 164 711 A1 describes a cache controller that configures a cache management mechanism. The cache controller is configured to monitor at least one structure associated with a cache to determine at least one cache block accessible during a future access to the cache. Based on the determination of the at least one cache block accessible during a future access to the cache, the cache controller configures the cache management mechanism.

[0006] US 2017 / 0 286 302 A1 describes methods and devices relating to the monitoring of storage performance.In one example, a processor includes at least one core, a performance monitoring unit, and a memory management unit with a first allocator to allocate a first virtual memory region of memory for a first data structure, a second allocator to allocate a second, different virtual memory region of memory for a second data structure, wherein the memory management unit is configured to, for each memory access request from the at least one core, set a monitor flag when a virtual address of a memory access request is in the first virtual memory region, and set the monitor flag when the virtual address of the memory access request is in the second, different virtual memory region, and enable the performance monitoring unit to monitor the memory access request when the monitor flag is set. SUMMARY OF THE INVENTION

[0007] The objects underlying the invention are achieved by the features of the independent patent claims. Embodiments of the invention are the subject of the dependent patent claims.

[0008] Provided is a computer program product, a system, and a method for managing data structures in a plurality of memory units, which are specified to be reset after initialization of the data structures. Data structures are specified to be reset from a first-level memory unit to a second-level memory unit after initialization. The first-level memory unit has a lower latency than the second-level memory unit.In response to completing the initialization of the data structures in the first-level memory unit, specifying to be moved back after initialization for the data structures that are copied from the first-level memory unit to the second-level memory unit after initialization, and deleting the data structures that are specified to be moved from the first-level memory unit after initialization.

[0009] In the above embodiment, infrequently accessed data structures may be moved to a lower-level memory unit for continuous storage because they are infrequently accessed and read access can be serviced by the lower-level memory unit. However, when there is a need to write to the data structure for which resetting is specified after initialization, the data structure may be moved to the first-level memory unit for one or more write operations to that data structure. When the write operations are completed, the data structure may be reverted from the first-level memory unit and moved to a lower-level memory tier because write access to the data structure is unlikely for a significant period of time.

[0010] In a further embodiment, access counts are maintained for the data structures stored in the first-level memory unit that are not specified to be reset after initialization, and access counts are not maintained for data structures that are specified to be reset after initialization.

[0011] In the above embodiment, no access counts are required for data structures that are automatically reset after an update or initialization, since they are released from the first-level memory unit after use without taking access counts into account.

[0012] In another embodiment, the access counts are used to select data structures to be removed from the first-level memory unit and retained in the second-level memory unit to free up memory space in the first-level memory unit. The access counts are used to determine whether accessed data structures should be removed from the second-level memory unit.

[0013] In the above embodiment, using access counts to determine whether to store data structures in low-latency or high-latency memory enables system performance to be improved by storing high-access data in low-latency memory to optimize system performance, and storing low-access data that has less impact on system performance in high-latency memory because low-access data is accessed less frequently.

[0014] In another embodiment, an update is received for a data structure that is specified to be rolled back after initialization. The data structure to be updated is copied from the second-level memory unit to the first-level memory unit to be updated. The updated data structure is copied from the first-level memory unit to the second-level memory unit, and the updated data structure is deleted from the first-level memory unit.

[0015] In the above embodiment, system performance is improved by moving the updated data structure for which a post-initialization rollback is specified to the lower-latency memory unit to perform the update. The data structure is then deleted from the first-level memory unit after the update, since access to it is unlikely, given that a post-initialization rollback data structure is rarely accessed.

[0016] Further provided is a computer program product, a system, and a method for managing data in a plurality of memory units in a data processing system. An update is received for a data structure indicated to be rolled back from a first-level memory unit. The data structure to be updated is copied from a second-level memory unit to the first-level memory unit to be updated. The first-level memory unit has a lower latency than the second-level memory unit. The updated data structure is copied from the first-level memory unit to the second-level memory unit and deleted from the first-level memory unit in response to the data structure being updated.

[0017] In the above embodiment, system performance is improved by moving the updated data structure specified for rollback to the lower-level memory unit to perform the update and then deleting it from the first-level memory unit after the update because access is unlikely and very rare given that a data structure specified for rollback after initialization is specified. Moving a rarely accessed data structure from the low-latency unit to a higher-latency unit for storage purposes improves system performance by maximizing available free space in the low-latency unit for more frequently accessed data structures.

[0018] In a further embodiment, the update for the data structure is performed on at least one field in the data structure to be updated that is smaller than all fields in the data structure. Copying the data structure comprises copying only the at least one field to be updated from the data structure to the first-level memory unit, wherein copying the updated data structure comprises copying the at least one updated field from the first-level memory unit to the second-level memory unit and deleting the updated at least one field from the first-level memory unit.

[0019] Further, in the above-mentioned embodiment, the storage space of the first-level memory with low latency is maintained and optimized only by copying fields to be updated from the data structures in the second-level memory unit to the first-level memory unit to be updated.

[0020] In another embodiment, the data structure to be updated is located in the second-level memory unit. A determination is made as to whether the update comprises one of a plurality of predefined update events. The data structures are copied to the first-level memory unit for updating in response to determining that the update comprises the update event. A plurality of writes to the data structure are performed as part of the update event. The updated data structure as part of the update event is copied from the first-level memory unit to the second-level memory unit, and the updated data structure is deleted from the first-level memory unit in response to completion of the writes for the update event.

[0021] In the above embodiment, data structures to be reverted after update or initialization are copied to the first-level memory unit when subjected to a burst of writes, even though they are generally infrequently accessed. Such data structures may be periodically staged into the first-level memory unit for a burst of writes as part of operations to update system configuration files. Since such configuration files are very infrequently updated, the system data structure may be moved back to a lower-level memory unit for storage and access after the update event. This frees up space in the first-level memory unit with faster access for other, more frequently accessed data. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates one embodiment of a computing environment including a memory subsystem having a plurality of memory devices. Fig. 2 illustrates one embodiment of data structure information for managing storage of data structures in the memory units. Fig. 3 illustrates one embodiment of operations for performing system initialization to generate first system data structures. Fig. 4 illustrates one embodiment of operations for processing an access request for a single-copy case, where only a single copy of data structures is stored in the entire memory subsystem. Fig. 5 illustrates one embodiment of operations for performing memory management operations to free space in a first-level memory unit for a single-copy case, where only a single copy of the data structures is stored in the entire memory subsystem. Fig. 6 illustrates one embodiment of operations for processing an access request for a multi-copy case, where multiple copies of data structures are stored throughout the memory subsystem. Fig. 7 illustrates one embodiment of operations for performing memory management operations to free space in a first-level memory unit for a multi-copy case, wherein multiple copies of the data structures are stored throughout the memory subsystem. Fig. 8 illustrates one embodiment of operations for processing an access request for a multi-copy case, where multiple copies of data structures with separate update and read counts are stored throughout the memory subsystem. Fig. 9 illustrates one embodiment of operations for performing memory management operations to free space in a first-level memory unit for a multi-copy case, wherein multiple copies of the data structures with separate update and read counts are stored throughout the memory subsystem. Fig. 10 illustrates one embodiment of operations for performing system initialization and generating data structures in a memory subsystem having a plurality of memory units. Fig. 11 illustrates one embodiment of operations for processing access to data structures that are returned after initialization to a memory subsystem of a plurality of memory units. Fig. 12 illustrates a data processing environment in which the components of Fig. 1 can be implemented. DETAILED DESCRIPTION

[0022] System control structures used to define logical units in the data processing system may be managed in the DRAM main memory. However, when the DRAM approaches a nearly full state, time-consuming memory management processes are used to move the data structures in the DRAM to lower-level storage, such as NAND flash memory or higher-latency disk storage.

[0023] Described embodiments provide improved computer technology for managing data structures in a memory subsystem consisting of a plurality of memory units at different levels with different characteristics, such as a first-level memory unit with the lowest latency, e.g., DRAM, and various lower-level memory units, e.g., NAND flash memory. In described embodiments, access counts are used to determine when to move data structures from the first-level memory unit to a lower-level memory unit with a higher latency.The access counts may also be used to determine whether to maintain multiple copies of a data structure in the first-level memory unit and a lower-level memory unit based on access thresholds maintained for different lower-level memory units to align placement of the data structures in lower-level memory units with appropriate resilience profiles, e.g., number of erase cycles, with the access count profile of the data structures.

[0024] In further embodiments, the access count may be used to determine whether multiple copies of a data structure should be maintained across multiple memory units when a data structure is accessed, or whether it should simply be left in the first-level memory unit. Data structures that are accessed less frequently than very frequently updated data structures may be specified as pageable to allow storage in lower-level, higher-latency memory units, whereas the most frequently accessed data structures may be non-pageable and remain in the lowest-latency first-level memory unit.

[0025] Further, the access count may have separate read and update counts, which are used to determine whether less frequently updated data structures should be moved to lower-level memory units. Further, more expensive lower-level memory units with higher resilience may be present, allowing, for example, more erase cycles, and only the data structures with the highest access counts are placed in these lower-level memory units with greater resilience. These data structures with a lower update count may be stored in less expensive lower-level memory units with lower resilience, allowing, for example, fewer erase cycles.This allows data structures to be matched by update counts with lower-level memory units based on the resilience of the lower-level memory units to optimize the placement of data structures between the lower-level memory units.

[0026] Fig. 1 illustrates one embodiment of a data processing environment. A plurality of hosts 102 may forward input / output (I / O) requests over a network 106 to a memory controller 104 to access data on volumes 108 (e.g., logical unit numbers, logical units, logical subsystems, etc.) in a memory 110. The memory controller 104 includes one or more processors 112 and a memory subsystem, such as a Storage Class Memory (SCM) system with a virtual memory manager 114 to manage the placement of tracks in one of a plurality of memory units, such as a first-level memory unit 1161, a second-level memory unit 1162, via an n-th-level memory unit 116 nThe virtual memory manager 114 manages data structure information 200 with information about data structures 1181, 1182, 1183, such as system data structures or objects generated by an operating system during system initialization, which the virtual memory manager 114 processes to allocate memory units 1161,...116 n with one or more levels at which system and other data structures are to be stored. The virtual memory manager 114 can also manage address translation tables to translate translation services and mapping traces in the disks 108 into physical or logical storage locations in the memory units 1161,...116 n The virtual memory manager 114 may further include algorithms for performing wear leveling to distribute write operations to different memory units 1162...116n and to distribute different storage locations in the memory units, such as solid-state storage units (SSDs) or flash memory, which have a limited number of erase cycles to extend the lifetime of these lower-level memory units 1161,...116 n In certain embodiments, the memory subsystem including the virtual memory manager 114 and memory units 1161,...116 n with levels, operate as a cache for the memory controller 104 or another data processing unit.

[0027] The processor 112, the virtual memory manager 114 and the memory units 1161,...116 ncan exchange data via one or more bus interfaces 120. Furthermore, the virtual memory manager 114 can communicate via different types and separate bus and device interfaces for different memory units 1161,...116 n Exchange data. For example, a local memory interface can be used to exchange data with the first-level memory unit 1161, such as a DRAM, and a memory unit interface can be used to communicate with the lower-level memory units 1162,...116 n To exchange data, such as with a Non-Volatile Memory Express (NVME) to exchange data with flash memory and SSDs.

[0028] In one embodiment, the first-level memory unit 1161 may comprise a high-cost, very low-latency unit such as dynamic random access memory (DRAM) or static random access memory (SRAM), and the lower-level memory unit 1161,...116 n may include lower-cost, high-latency, larger-capacity memory devices such as non-volatile random access memory (NVRAM), including magnetoresistive random access memory (MRAM), phase-change memory (PCM), resistive random access memory (RRAM), spin-transfer torque memory (STM-RAM), conductive bridging RAM (CBRAM), NAND memory devices such as flash memory and solid-state drives (SSDs), etc. In one embodiment, the lower-level memory device 1162,...116 nhave different resilience profiles with a different number of available erase cycles, so that higher-level memory units 1162,...116 n a higher number of erase cycles, ie greater resilience than the lower-level memory units 1162,...116 n For example, the lower-level memory unit 116 i a higher load capacity, ie a larger number of erase cycles than the main memory unit 116 j where i < j. One or more lower-level memory units 116 i to be available.

[0029] The virtual memory manager 114 may comprise a separate processing or hardware unit implemented as microcode or firmware in hardware units within the memory controller 104, such as application-specific integrated circuits (ASICs). Alternatively, the virtual memory manager 114 may comprise a system with a processor executing code loaded into a memory unit. Further still, the virtual memory manager 114 may be implemented as code loaded into the first-level memory unit 116 and executed by the processor 112.

[0030] The storage 110 may include one or more storage devices known in the art, such as a solid-state storage (SSD) device, a magnetic hard disk, an optical disk, a tape, etc. The storage devices may be further configured into an array of devices, such as a Just a Bunch of Disks (JBOD), a Random Access Storage (DASD) device, a Redundant Array of Independent Disks (RAID) array, a virtualization device, etc. Furthermore, the storage devices may include heterogeneous storage devices from different vendors or from the same vendor.

[0031] The network 106 may include a storage area network (SAN), a local area network (LAN), a wide area network (WAN), the Internet and intranet, etc. Alternatively, the hosts 102 may be connected to the storage controller 104 via a bus interface such as a Peripheral Component Interconnect (PCI) bus interface and other interfaces known in the art.

[0032] Fig. 2 illustrates an embodiment of an example of the data structure information 200 i for a data structure comprising a data structure identifier (ID) 202, such as a file or object name; a swappable flag 204 indicating whether the data structure 202 is regularly swapped between the first-level work unit 1161 and the lower-level work units 1162,...116 ncan be moved; an update number 206, which indicates how often the data structure 202 has been updated within a measurement period; a read number 208, which indicates how often the data structure 202 has been read in a measurement period; a reset after an initialization flag 210, which indicates how often the data structure 202 must be reset immediately after generation in the working memory unit at the first level 1161; and a unit pointer 212, which indicates the level of the working memory unit 1161,...116 n indicates in which the data structure 202 is currently stored.

[0033] In one embodiment, the pageable flag 204 and the rollback after the initialization flag 210 may be set by the developer or administrator of the operating system based on the estimated frequency with which the data structures are accessed. For example, data structures that are updated or accessed most frequently may be marked as pageable to always be maintained in the fastest level of the first-level memory unit 1161. The less frequently accessed data structures 1181, 1182, 1183 may occasionally be moved to the lower-level memory units 1162, 1163. n be swapped out to free up space in the first-level memory unit 1161.

[0034] The update number 206 can be used to update a lower level memory unit 116 iSelect the location on which a data structure should be stored to match the resilience or available erase cycles. For example, more frequently accessed data structures, those with a higher update count of 206, can be stored on a lower-level memory unit of 116. i with a higher load capacity. In this way, each of the lower-level memory units1162,...116 n a range of update numbers. In an alternative embodiment, only one access number for read and / or write operations may be used to determine when a data structure is swapped out of the first-level memory unit 1161 and a memory unit 116 i should be selected to store the swapped data structure.

[0035] The data structure information 200 i, which are stated to be non-pageable 204, cannot manage the access numbers 206, 208, since such data structures are not managed between the memory units on the basis of their access.

[0036] The reset after the initialization flag 210 can be configured for data structures that are also specified as non-pageable 204, which are static and infrequent, but sometimes changed. In such a case, data structures that are only rarely accessed can be transferred to a memory unit 116 for continuous storage. i at a lower level, since they are rarely read and written to and are accessed by the lower-level memory unit 116 ican be served. However, if there is a need to write to the data structure for which reset is specified after initialization 210, the data structure may be moved to the first-level memory unit 1161 for one or more write operations to that data structure. When the write operations are completed, the data structure may be reset from the first-level memory unit 1161 and moved to a lower-level memory level 116 i be postponed because write access to the data structure is unlikely for a significant period of time.

[0037] In one embodiment, the data structures managed by virtual memory manager 114 may include data structures generated during system initialization or an initial microcode load (IML) and may include structures that provide configuration information for hardware and logical devices, paths and subsystems, device characteristics, and settings. In alternative embodiments, the data structures may be generated by applications.

[0038] In certain embodiments, virtual memory manager 114 may decrease access counts, such as update 206 and read 208 counts, to reduce the weight of accesses over time. This allows the strength of the access counts to be time-sensitive and decay over time.

[0039] Fig. 3 illustrates one embodiment of operations performed for system initialization of the memory controller 100 by an operating system of the memory controller 100, which may be managed in the first-level memory unit 1161 and the virtual memory manager 114. After initiating a system initialization (at a block 300), the system data structures are generated (at a block 302) and stored in the first-level memory unit 1161. For each of the generated data structures for which rollback is indicated after initialization 210, the generated data structures are copied (at a block 304) to the lowest-level memory unit (e.g., third level) and removed from the first-level memory unit 1161.

[0040] Fig. 4 illustrates one embodiment of operations performed by the virtual memory manager 114 to process an access request, such as a read or write operation, for a single copy instance, where only one copy of a data structure 118 i in the memory units 1161...116 n is managed. After processing (at a block 400) the access request, if (at a block 402) the data structure 118 i being accessed is not swappable 204, the controller continues with Fig. 11 for processing as a non-pageable data structure. If (at block 402) the pageable flag 204 in the data structure information 200 i for the data structure 118 i being accessed indicates that the data structure 118 i is pageable, the access count is increased (at a block 406). In the embodiment of Fig. 4 and Fig. 5 there may be only one access count for read and / or write accesses.

[0041] If (at a block 408) the data structure 118 i being accessed is located in the first-level memory unit 1161, the access request is performed (at a block 410) on the first-level memory unit 1161. If the data structure 118 i is not located in the first-level memory unit 1161, the virtual memory manager 114 copies (at a block 412) the data structure 118 i from a lower-level memory unit 116 i into the first-level memory unit 1161, removes (at a block 414) the data structure 118 i from the lower-level memory unit 116 i and updates the unit pointer 212 to indicate the first level memory unit 1161.

[0042] In the embodiment of Fig. 4, the virtual memory manager 114 manages a single copy of the data structures in one of the memory units 116 i and moves a pageable data structure, when accessed, from a lower-level memory unit 116 i into the first level memory unit 1161.

[0043] Fig. 5 illustrates one embodiment of operations performed by the virtual memory manager 114 to free space in the first-level memory unit 1161 in the event that a single copy of the data structure 118 iin one of the memory units 1161. After initiating (at a block 500) memory management, if (at a block 502) the amount of free space in the first-level memory unit 1161 is above a memory threshold, control ends. If (at a block 502) the amount of free space is below the memory threshold, the memory manager 114 selects (at a block 504) data structures 118 i in the first-level memory unit 1161 that are specified as pageable with the lowest access counts corresponding to a free memory amount. The selected data structures are (at a block 506) transferred to one of the lower-level memory units 116 icopied, removed from the first-level memory unit 1161 and the unit pointers 212 for the moved data structures are updated to point to the lower-level memory units 116 i to show to which they are added.

[0044] In one embodiment, the access counts for the selected data structures may be used to determine the lower-level memory unit in which the data structures are stored. If the lower-level memory units 116 iare sorted according to their load capacity with respect to erasable numbers, with the units with lower numbers having a higher load capacity than the units with higher numbers, e.g., if the working memory unit 1162 has a greater load capacity than the working memory unit 1163, a data structure with a lowest level threshold value that exceeds the data structure access number is stored in the working memory unit 116 i placed.

[0045] In the embodiment of Fig. 5, the virtual memory manager 114 considers data structures with a lowest access count to free up memory space in the first-level memory unit 1161, since such data structures are updated and accessed less frequently and are most suitable for storage in a lower-level memory unit 1162...116 n are.

[0046] Fig. Figure 6 illustrates one embodiment of operations performed by the virtual memory manager 114 to process an access request using multiple copies of a data structure 118 i in several memory units 1161...116 n be managed. In the implementation of Fig. 6 and Fig. 7, only one access number is present, which has update 206 and / or read 208 numbers. After processing (at a block 600) the access request, if (at a block 602) the data structure 118 i being accessed is not swappable 204, the controller continues with Fig. 11 for processing as a non-pageable data structure. If (at block 602) the pageable flag 204 in the data structure information 200 i for the data structure 118 i being accessed indicates that the data structure 118 iis swappable, the access count is increased (at a block 606).

[0047] If (at a block 608) the data structure 118 i being accessed is located in the first-level memory unit 1161, the access request is performed (at a block 610) on the first-level memory unit 1161. If the data structure 118 i is not located in the first-level memory unit 1161, the virtual memory manager 114 copies (at a block 612) the data structure 118 i from a lower-level memory unit 116 iinto the first-level memory unit 1161 and updates (at a block 614) the unit pointer 212 to indicate the first-level memory unit 1161. If (at a block 616) the access request is an update, the copies of the data structures in one or more memory units are updated (at a block 616).

[0048] The virtual memory manager 114 determines (at a block 618) a lower-level memory unit 116 j with a lowest level threshold that limits the number of accesses to the data structure 118 i which is the memory unit with a load capacity that is sufficient for the access count of the selected data structure 118 i is most appropriate. If (at a block 620) the data structure 118i is not located in the particular lower-level memory unit 116 jthe virtual memory manager 114 copies (at a block 622) the data structure 118 i from the lower-level memory unit 116 i , which currently has the data structure 118 i into the lower-level memory unit 116 j , which has the determined lowest level threshold, and removes (at a block 624) the data structure 118 i from the lower-level memory unit 116 i from which the data structure was copied. If the data structure 118 i (at block 620) already in the particular lower-level memory unit 116 i or has been copied there (at block 622), the unit pointer 212 is updated (at a block 626) to indicate the lower-level memory unit 116 j which now contains the data structure 118 i has.

[0049] In the embodiment of Fig. 6, an accessed data structure is moved to the first-level memory unit 1161 and also retained in a lower-level memory unit having a resilience, erasable cycles, corresponding to the access count of the data structure. By matching the data structure by access count with a lower-level memory unit by resilience, data structures are stored in a lower-level memory unit with a resilience level most appropriate for the frequency of access to the data structure. Further, if the access count of the data structure is greater than the highest level threshold for the second-level memory unit 1162, the data structure is removed from the level of the memory unit 116 iremoved with the data structure without moving the data structure to another level of the memory unit, because the access count for lower-level memory units is 1162...116 n is too high.

[0050] Fig. Figure 7 illustrates one embodiment of operations performed by the virtual memory manager 114 to perform memory management when copies of a data structure 118 i in several levels of memory units 1161...116 nmanaged. After initiating (at a block 700) memory management for a multicopy case, if (at a block 702) the amount of free space in the first-level memory unit 1161 is above a memory threshold, control ends. If (at a block 702) the amount of free space is below the memory threshold, the memory manager 114 selects (at a block 704) data structures 118 i in the first-level memory unit 1161 that are specified as pageable with the lowest access counts corresponding to a free memory space amount. The operations at blocks 706 to 718 are performed for each of the selected data structures 118 i carried out.

[0051] The virtual memory manager 114 determines (at a block 708) a lower-level memory unit 116 jwith a lowest level threshold that limits the number of accesses to the data structure 118 i which is the memory unit with a load capacity that is sufficient for the access count of the selected data structure 118 i is most suitable. If (at a block 710) the data structure 118 i is not located in the particular lower-level memory unit 1161, the virtual memory manager 114 copies (at a block 712) the data structure 118 i from the first-level memory unit 116 i into the lower-level memory unit 1161 with the determined lowest level threshold. If the data structure 118 i (at block 710) already in the particular lower-level memory unit 116 i or has been copied there (at block 712), the data structure 118 i(at a block 714) is removed from the first-level memory unit 1161, and the unit pointer 212 is updated (at a block 716) to indicate the lower-level memory unit 116 j which now contains the data structure 118 i has.

[0052] In the embodiment of Fig. 7, the virtual memory manager 114 considers data structures with a lowest access count to free up memory space in the first-level memory unit 1161, since such data structures are less likely to be updated and accessed and are most suitable for storage in a lower-level memory unit 1162...116 n The selected data structure with the lowest access count is removed from the first-level memory unit 1161 and stored in a lower-level memory unit 116i with a level threshold that contains the access count of the data structure to be moved.

[0053] Fig. Figure 8 illustrates one embodiment of operations performed by the virtual memory manager 114 to process an access request using multiple copies of a data structure 118 i in several of the memory units 1161...116 n managed and separate update 206 and read 208 numbers are present. After processing (at a block 800) the access request, if (at a block 802) the data structure 118 i being accessed is not swappable 204, the controller continues with Fig. 11 for processing as a non-pageable data structure. If (at block 802) the pageable flag 204 in the data structure information 200 i for the data structure 118 ibeing accessed indicates that the data structure 118 i is pageable, the update count 206 (at a block (806) is incremented if the access is a write operation, and the read count 208 is incremented if the access is a read operation.

[0054] If (at a block 808) the data structure 118 i , which is accessed, is located in the first-level memory unit 1161, the access (read or write operation) is performed (at a block 810) on the first-level memory unit 1161. If (at a block 808) the data structure 118 i is not located in the first-level memory unit 1161, the virtual memory manager 114 copies (at a block 812) the data structure 118 i from a lower-level memory unit 116 iinto the first-level memory unit 1161 and updates (at a block 814) the unit pointer 212 to indicate the first-level memory unit 1161. If (at a block 816) the access request is an update, the copies of the data structures in the first-level memory units 1161 and lower-level memory units 116 i updated (at a block 818).

[0055] If the access is a read operation (from block 816) or an update of the data (from block 818), the virtual memory manager 114 determines (at a block 820) a lower-level memory unit 116 j with a lowest level threshold that is the update number 206 of the data structure 118 i which is the memory unit with a load capacity that is sufficient for the update count of the selected data structure 118i is most suitable. If (at a block 822) the data structure 118 i is not located in the particular lower-level memory unit 1161, the virtual memory manager 114 copies (at a block 824) the data structure 118 i from the lower-level memory unit 116 i with the data structure 118 i into the lower-level memory unit 1161 with the determined lowest level threshold, and the data structure 118 i is removed (at a block 826) from the lower-level memory unit 1161. If the data structure is in the particular lower-level memory unit 116 j with the lowest level threshold (from block 822 or 826), the unit pointer 212 is updated (at a block 828) to indicate the lower level memory unit 116 j which now contains the data structure 118i has.

[0056] In the embodiment of Fig. 8, an accessed data structure is moved to the first-level memory unit 1161 and also retained in a lower-level memory unit having a resilience, erasable cycles, corresponding to the update frequency of the data structure. By matching the data structure by update number with a lower-level memory unit by resilience, data structures are stored in a lower-level memory unit with a resilience level most suitable for the update frequency of the data structure. Furthermore, if the update number of the data structure is greater than the highest level threshold for the second-level memory unit 1162, the data structure is erased from the level of the memory unit 116. iremoved with the data structure without moving the data structure to another level of the memory unit because the update number for the resilience level of the lower-level memory units 1162...116 n is too high.

[0057] Fig. Figure 9 illustrates one embodiment of operations performed by the virtual memory manager 114 to perform memory management when copies of a data structure 118 i in several levels of memory units 1161...116 nmanaged. After initiating (at a block 900) memory management for a multicopy case with separate update and read counts, if (at a block 902) the amount of free space in the first-level memory unit 1161 is above a memory threshold, control ends. If (at a block 902) the amount of free space is below the memory threshold, the memory manager 114 selects (at a block 904) data structures 118 i in the first-level memory unit 1161, which are specified as pageable with the smallest update numbers 206, corresponding to a free memory space amount. The operations at blocks 906 to 918 are performed for each of the selected data structures 118 i carried out.

[0058] The virtual memory manager 114 determines (at a block 908) a lower-level memory unit 116j with a lowest level threshold that is the update number 206 of the data structure 118 i which is the memory unit with a load capacity that is sufficient for the access count of the selected data structure 118 i is most suitable. If (at a block 910) the data structure 118 i is not located in the particular lower-level memory unit 1161, the virtual memory manager 114 copies (at a block 912) the data structure 118 i from the first-level memory unit 1161 to the lower-level memory unit 116 j with the determined lowest level threshold. If the data structure 118 i (at block 910) already in the specific lower-level memory unit 116 i or has been copied there (at block 912), the data structure 118 i(at a block 914) is removed from the first-level memory unit 1161 and the unit pointer 212 is updated (at a block 916) to indicate the lower-level memory unit 116 j which now contains the data structure 118 i has.

[0059] In the embodiment of Fig. 9, the virtual memory manager 114 considers data structures with a lowest update count to free up memory space in the first-level memory unit 1161, since such data structures are updated less frequently and are most suitable for storage in a lower-level memory unit 1162...116 n The selected data structures with the lowest update numbers are removed from the first-level memory unit 1161 and stored in a lower-level memory unit 116 iwith a level threshold that contains the update count of the data structure to be moved.

[0060] Fig. 10 illustrates one embodiment of operations performed by the virtual memory manager 114 to generate data structures, such as system-type data structures during system initialization, including data structures that provide configuration information about logical subsystems, logical volumes, path groups, physical paths, logical paths, subsystem characteristics, and other configuration data. After performing system initialization (at a block 1000), which may be initiated by a Basic Input Operating System (BIOS), an initial microcode load (IML), or another boot unit, system data structures are generated and stored (at a block 1002) in the first-level memory unit 1161 as part of the system initialization. The unit pointers 212 in the data structure information 200 i for the generated system data structures 118 iare updated (at a block 1004) to indicate the first-level memory unit 1161. The virtual memory manager 114 determines (at a block 1006) the data structures 118 i , whose data structure information 200 i indicate in field 210 that the data structures are to be reset after initialization. The determined data structures are moved (at a block 1008) from the first-level memory unit 1161 to selected lower-level memory units 116 i copied. The selected lower-level memory units can be selected based on an access count or update count to select a lower-level memory unit with a resilience profile appropriate for the access or update count for the data structure, such as with respect to Fig. 7 and Fig. 9 described.

[0061] The copied specific data structures 118 i are moved (at a block 1010) from the first-level memory unit 1161, and the unit pointers 212 for the moved data structures 118 i are updated (at a block 1012) to indicate the selected lower-level memory units to which they have been moved.

[0062] In the embodiment of Fig. 10 Data structures for which a rollback is specified, which may include these system data structures that are accessed very rarely, are moved to a suitable lower-level memory unit 116 i moved because their infrequent access pattern indicates that they do not need to be stored in the first-level memory unit 1161 after they have been initialized during system initialization.

[0063] Fig. 11 illustrates one embodiment of operations performed by the virtual memory manager 114 to access non-pageable data structures 118 i to process, for example, at blocks 404, 604 and 804 in Fig. 4, Fig. 6 and Fig. 8. After initiating access (at a block 1100) to a non-pageable data structure 118 i , if (at a block 1102) for the non-pageable data structure 118 i If it is not specified in field 210 that it should be reset after initialization, the virtual memory manager 114 provides (at a block 1104) a read or write access to the data structure 118 i in the first-level memory unit 1161. If (at block 1102) the data structure 118 iafter the initialization state, if (at a block 1106) the access is a read operation, the virtual memory manager 114 provides (at a block 1108) a read access to the data structure 118 i at the level of the memory unit 116 i ready, which is indicated by the unit pointer 212 in the data structure information 200 i for the data structure 118 i has been identified that is being accessed.

[0064] If it is a write operation (at block 1006) and if (at a block 1110) the update for the data structure 118 i is not an element of a set of defined update events, the requested write operation (at a block 1112) on the lower-level memory unit 116 i which is stored in the unit pointer 212 for the data structure 118 iis specified. If (at a block 1110) the update is an element of a set of defined update events, the virtual memory manager 114 copies (at a block 1114) the data structure 114 i (or specific fields or sections to be updated) into the first-level memory unit 1161 and updates the unit pointer 212 to indicate the first-level memory unit 1161. Event writes are then (at a block 1116) for the data structure 118 i or specific fields in the data structure as part of the event. When the writes associated with an event are completed (at a block 1118), the virtual memory manager 114 copies (at a block 1120) the updated data structure 118 ior only the updated fields and sections from the first-level memory unit 1161 to a selected lower-level memory unit 116 i (e.g. lowest level selected to reduce wear leveling), removes the data structure 118 i from the first-level memory unit 1161 and updates the unit pointer 212 to indicate the selected lower-level memory unit 116 i to be specified.

[0065] In one embodiment, the defined set of events that trigger a move of the data structure to the first-level memory unit 1161 may include data structures that are system configuration files that are updated very rarely, such as adding or removing a logical subsystem, volumes, path groups, physical paths, and logical paths. The update events may also include updating configuration information with new subsystem characteristics and other information.

[0066] During the operations of Fig. 11 can be a data structure 118 i , which is identified as a rollback after an initialization, which usually occurs in a lower-level memory unit 116 istored may be periodically placed in the first-level memory unit 1161 for a batch of writes as part of operations to update system configuration files. Because such configuration files are updated very infrequently, the system data structure may be moved back to a lower-level memory unit for storage and access after the update event. This frees up space in the first-level memory unit 1161 with faster access for other, more frequently accessed data.

[0067] The present invention may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions stored thereon for causing a processor to perform aspects of the present invention.

[0068] The computer-readable storage medium may be any physical device capable of retaining and storing instructions for use by a device to execute instructions. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM).Flash memory), a static random access memory (SRAM), a portable CD-ROM, a DVD, a memory stick, a floppy disk, a mechanically encoded device such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as containing transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., pulses of light carried through a fiber optic cable), or electrical signals carried through a wire.

[0069] Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing units or to an external computer or storage unit via a network such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routers, firewalls, switching units, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing unit receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing unit.

[0070] Computer-readable program instructions for performing operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, C++, or the like, as well as conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

[0071] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented using computer-readable program instructions.

[0072] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that the instructions executing via the processor of the computer or other programmable data processing device produce a means for implementing the functions / steps specified in the flowchart and / or block diagram block(s).These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored thereon comprises an article of manufacture, including instructions that implement aspects of the function / step specified in the block(s) of the flowchart and / or block diagrams.

[0073] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / steps specified in the block(s) of flowchart and / or block diagrams.

[0074] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing the particular logical function(s). In some alternative implementations, the functions specified in the block may occur in a different order than shown in the figures. For example, two blocks shown consecutively may actually execute substantially in parallel, or the blocks may sometimes execute in the reverse order, depending on the functionality involved.It is further to be understood that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by special purpose hardware-based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0075] The computing components of Fig. 1, including the hosts 102 and the memory controller 104, may be implemented in one or more computer systems, such as the computer system 1202 shown in Fig. 12. The computer system / server 1202 may be described in the general context of instructions executable by a computer system, such as program modules executed by a computer system. In general, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. The computer system / server 1202 may operate in distributed cloud computing environments, with tasks being executed by remotely located processing units connected via a communications network. In a distributed cloud computing environment, program modules may be located on both local and remotely located computer system storage media, including memory storage units.

[0076] As in Fig. 12, the computer system / server 1202 is shown in the form of a general-purpose data processing unit. The components of the computer system / server 1202 may include, but are not limited to, one or more processors or processing units 1204, a system memory 1206, and a bus 1208 that connects various system components, including, but not limited to, the system memory 1206 to the processor 1204. The bus 1208 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using one of a variety of bus architectures.By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, a local Video Electronics Standards Association (VESA) bus, and Peripheral Component Interconnect (PCI) bus.

[0077] The computer system / server 1202 typically includes a variety of computer system-readable media. Such media may be any available media accessible by the computer system / server 1202, and may include both volatile and non-volatile media, removable and non-removable media.

[0078] System memory 1206 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 1210 and / or cache memory 1212. Computer system / server 1202 may further include other removable / non-removable, volatile / non-volatile computer system storage media. For example only, a storage system 1213 may be provided for reading from and writing to a non-removable, non-volatile magnetic disk (not shown and typically referred to as a "hard disk"). Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive may be provided for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical disk.In such cases, all may be connected to bus 1208 via one or more data storage interfaces. As further illustrated and described below, memory 1206 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the invention.

[0079] For example, and not by way of limitation, a program / utility 1214 comprising a set (at least one) of program modules 1216 may be stored in memory 1206, as may an operating system, one or more application programs, other program modules, and program data. The operating system, one or more application programs, other program modules, and program data, or a combination thereof, may comprise an implementation of a network environment. The components of computer 1202 may be implemented as program modules 1216 that generally perform the functions and / or methodologies of embodiments of the invention as described herein. The systems of Fig. 1 can be implemented in one or more computer systems 1202, wherein the computer systems, if implemented in multiple computer systems 1202, can communicate via a network.

[0080] The computer system / server 1202 may also communicate with one or more external devices 1218, such as a keyboard, a pointing device, a display 1220, etc.; one or more devices that enable a user to interact with the computer system / server 1202; and / or any devices (e.g., network card, modem, etc.) that enable the computer system / server 1202 to communicate with one or more other computing devices. Such communication may occur via input / output (I / O) interfaces 1222. Furthermore, the computer system / server 1202 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via a network adapter 1224.As illustrated, network adapter 1224 communicates with the other components of computer system / server 1202 via bus 1208. Although not shown, it should be understood that other hardware and / or software components could be used in conjunction with computer system / server 1202. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID (Redundant Array of Independent Disks) systems, tape drives, and data archiving storage systems, etc.

Claims

[1] Computer program product for managing data in a plurality of memory units (1161, 1162, 116 n ) in a data processing system (104), the computer program product comprising a computer-readable storage medium having embodied thereon computer-readable code which, when executed, performs operations, the operations comprising: Indicating that data structures (1181) are reset from a first-level memory unit (1161) to a second-level memory unit (1162) during system initialization, the first-level memory unit having a lower latency than the second-level memory unit, the data structures being identified as having a file name or object name and comprising configuration information for the data processing system generated by an operating system during system initialization; and immediately copying (304), as part of completing the system initialization and generating the data structures in the first-level memory unit, the data structures indicated to be moved back from the first-level memory unit to the second-level memory unit as part of the system initialization, and removing (304) the data structures indicated to be moved back from the first-level memory unit as part of the system initialization. [2] The computer program product of claim 1, wherein the operations further comprise: Receiving (400, 404, 1106; 600, 604, 1106; 800, 804; 1106) a read request to a data structure (1182) stored in the second-level memory unit (1162); and Returning (1108) data to the read request from the data structure stored in the second level memory unit. [3] The computer program product of claim 1, wherein the operations further comprise: Managing access counts for the data structures stored in the first-level memory unit that are not specified to be reset as part of system initialization, but not managing access counts for data structures that are specified to be reset as part of system initialization. [4] The computer program product of claim 3, wherein the operations further comprise: Using the access numbers to select (504) data structures to be removed from the first-level memory unit and retained in the second-level memory unit to free up memory space in the first-level memory unit; and Use the access counts to determine whether accessed data structures should be removed from the second-level memory unit. [5] The computer program product of claim 1, wherein the operations further comprise: Receiving an update for a data structure that is specified to be rolled back as part of system initialization; Copying (1114) the update data structure from the second-level memory unit to the first-level memory unit to be updated; Updating (1116) the data structure with the update; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit, and deleting (1120) the updated data structure from the first-level memory unit. [6] Computer program for managing data in a plurality of memory units (1161, 1162, 116 n ) in a data processing system (104), the computer program product comprising a computer-readable storage medium having embodied thereon computer-readable code which, when executed, performs operations, the operations comprising: Receiving an update for a data structure indicated to be rolled back as part of a system initialization from a first-level memory device (1161), the data structure being identified as having a file name or object name and comprising configuration information for the data processing system generated by an operating system as part of the system initialization, the data structure indicated to be rolled back as part of a system initialization being immediately rolled back from the first-level memory device in response to being generated in the first-level memory device as part of the system initialization operations; Copying (1114) the data structure to be updated from a second-level memory unit (1162) to the first-level memory unit to be updated, wherein the first-level memory unit has a lower latency than the second-level memory unit; Updating (1116) the data structure with the update; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit, and deleting (1120) the updated data structure from the first-level memory unit in response to completing the updating of the data structure. [7] The computer program product of claim 6, wherein the update to the data structure is performed for at least one field in the data structure to be updated that is smaller than all fields in the data structure, wherein copying the data structure comprises copying only the at least one field to be updated from the data structure to the first-level memory unit, wherein copying the updated data structure comprises copying the at least one updated field from the first-level memory unit to the second-level memory unit and deleting the updated at least one field from the first-level memory unit. [8] The computer program product of claim 6, wherein the data structure to be updated is located in the second-level memory unit, the operations further comprising: Determining (1110) whether the update comprises one of a plurality of predefined update events; Copying (1114) the data structure to update the first level memory unit in response to determining that the update comprises the update event; performing (1116) a plurality of writes to the data structure as part of the update event; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit in response to the update event, and deleting (1120) the updated data structure from the first-level memory unit in response to completion of the write operations for the update event. [9] The computer program product of claim 8, wherein the predefined update events comprise a plurality of update events that are a member of a subset of update events that comprise an addition or removal of a logical unit in the data processing system; a volume in the data processing system; path groups; physical paths, logical paths; and subsystem features and other configuration changes. [10] The computer program product of claim 8, wherein the operations further comprise: Performing (1112) the update to the data structure for updating the second level memory unit in response to determining (1110) that the update does not include any of the plurality of predefined update events. [11] System (104) comprising: a first level memory unit (1161); a second level memory unit (1162); a virtual memory manager (114) to perform: Indicating that data structures (1181) are reset from a first-level memory unit (1161) to a second-level memory unit (1162) during system initialization, the first-level memory unit having a lower latency than the second-level memory unit, the data structures being identified as having a file name or object name and comprising configuration information for the data processing system generated by an operating system during system initialization; and immediately copying (304), as part of completing the system initialization and generating the data structures in the first-level memory unit, the data structures indicated to be moved back from the first-level memory unit to the second-level memory unit as part of the system initialization, and removing (304) the data structures indicated to be moved back from the first-level memory unit as part of the system initialization. [12] The system of claim 11, wherein the operations further comprise: Receiving (400, 404, 1106; 600, 604, 1106; 800, 804; 1106) a read request to a data structure (1182) stored in the second-level memory unit (1162); and Returning (1108) data to the read request from the data structure stored in the second level memory unit. [13] The system of claim 11, wherein the operations further comprise: Managing access counts for the data structures stored in the first-level memory unit that are not specified to be reset as part of system initialization, but not managing access counts for data structures that are specified to be reset as part of system initialization. [14] The system of claim 13, wherein the operations further comprise: Using the access numbers to select (504) data structures to be removed from the first-level memory unit and retained in the second-level memory unit to free up memory space in the first-level memory unit; and Use the access counts to determine whether accessed data structures should be removed from the second-level memory unit. [15] The system of claim 11, wherein the operations further comprise: Receiving an update to a data structure that is specified to be rolled back as part of system initialization; Copying (1114) the update data structure from the second-level memory unit to the first-level memory unit to be updated; Updating (1116) the data structure with the update; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit, and deleting the updated data structure from the first-level memory unit. [16] System (104) comprising: a first level memory unit (1161); a second level memory unit (1162); a virtual memory manager (114) to perform: Receiving an update to a data structure indicated to be rolled back as part of a system initialization from a first-level memory device (1161), the data structure being identified as having a file name or object name and comprising configuration information for the system generated by an operating system as part of the system initialization, the data structure indicated to be rolled back as part of a system initialization being immediately rolled back by the first-level memory device in response to being generated in the first-level memory device as part of the system initialization operations; Copying (1114) the data structure to be updated from a second-level memory unit (1162) to the first-level memory unit to be updated, wherein the first-level memory unit has a lower latency than the second-level memory unit; Updating (1116) the data structure with the update; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit, and deleting (1120) the updated data structure from the first-level memory unit in response to completing the updating of the data structure. [17] The system of claim 16, wherein the update to the data structure is performed for at least one field in the data structure to be updated that is smaller than all fields in the data structure, wherein copying the data structure comprises copying only the at least one field to be updated from the data structure to the first level memory unit, wherein copying the updated data structure comprises copying the at least one updated field from the first level memory unit to the second level memory unit and deleting the updated at least one field from the first level memory unit. [18] The system of claim 16, wherein the data structure to be updated is located in the second-level memory unit, wherein the virtual memory manager performs: Determining (1110) whether the update comprises one of a plurality of predefined update events; Copying (1114) the data structure to be updated to the first-level memory unit in response to determining that the update includes the update event; performing (1116) a plurality of writes to the data structure as part of the update event; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit in response to the update event, and deleting the updated data structure from the first-level memory unit in response to completion of the write operations for the update event. [19] The system of claim 18, wherein the predefined update events comprise a plurality of update events that are a member of a subset of update events that include adding or removing a logical unit in the system; a volume in the system; path groups; physical paths; logical paths; and subsystem features and other configuration changes. [20] The system of claim 18, wherein the virtual memory manager performs: Performing (1112) the update to the data structure for updating the second level memory unit in response to determining (1110) that the update does not include any of the plurality of predefined update events. [21] Method for managing data in a plurality of memory units (1161, 1162, 116 n ) in a data processing system (104) comprising: Indicating that data structures (1181) are reset from a first-level memory unit (1161) to a second-level memory unit during system initialization, the first-level memory unit having a lower latency than the second-level memory unit, the data structures being identified as having a file name or object name and comprising configuration information for the data processing system generated by an operating system during system initialization; and immediately copying (304), as part of completing the system initialization and generating the data structures in the first-level memory unit, the data structures indicated to be moved back from the first-level memory unit to the second-level memory unit as part of the system initialization, and removing (304) the data structures indicated to be moved back from the first-level memory unit as part of the system initialization. [22] The method of claim 21, further comprising: Receiving (400, 404, 1106; 600, 604, 1106; 800, 804; 1106) a read request to a data structure (1182) stored in the second-level memory unit (1162); and Returning (1108) data to the read request from the data structure stored in the second level memory unit. [23] The method of claim 21, further comprising: Managing access counts for the data structures stored in the first-level memory unit that are not specified to be reset as part of system initialization, but not managing access counts for data structures that are specified to be reset as part of system initialization. [24] The method of claim 23, further comprising: Using the access numbers to select (504) data structures to be removed from the first-level memory unit and retained in the second-level memory unit to free up memory space in the first-level memory unit; and Use the access counts to determine whether accessed data structures should be removed from the second-level memory unit. [25] The method of claim 23, further comprising: Receiving an update for a data structure that is specified to be rolled back as part of system initialization; Copying (1114) the data structure to be updated from the second-level memory unit to the first-level memory unit to be updated; Updating (1116) the data structure with the update; and Copying (1120) the updated data structure from the first-level memory unit to the second-level memory unit, and deleting the updated data structure from the first-level memory unit.

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