SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC DEVICE

Abstract

Semiconductor device (1), comprising a first field-effect transistor (Q1) and a second field-effect transistor (Q2) housed on a semiconductor substrate (10), and an insulating layer (20) provided on a main surface of the semiconductor substrate and comprising a first insulating film (21) provided on the main surface of the semiconductor substrate, a second insulating film (22) provided on the first insulating film (21), and a third insulating film (26) covering the first insulating film (21) and the second insulating film, wherein both the first field effect transistor (Q1) and the second field effect transistor (Q2) a pair of main electrodes (16A, 17A, 16B, 17B) separated from each other in a respective direction of a gate length and provided on the main surface of the semiconductor substrate (10), a cavity part (25A 1 , 25B 1) provided in the insulating layer (20) between the pair of main electrodes (16A, 17A, 16B, 17B), surrounded by the third insulating layer, and having a width in the respective direction of the gate length between portions of the third insulating layer, and a gate electrode (31A, 31B) having a head portion (31a) positioned on the insulating layer (20) 1 , 31b 1 ) and a fuselage section (31a 2 , 31b 2 ) which is connected to the head part (31a 1 , 31b 1 ) penetrates the insulating layer (20) and in the direction of the cavity part (25A 1 , 25B 1 ) and in which the head part (31a 1 , 31b 1 ) wider than the fuselage part (31a 2 , 31b 2), wherein the third insulating film (26) covers the main surface of the semiconductor substrate (10) in the cavity part (25A1, 25B1) and surrounds the cavity part, the gate electrode (31A, 31B) is arranged on the main surface of the semiconductor substrate (10) with the third insulating film (26) therebetween, and the second insulating film over the cavity part has only a single opening, and where the width (W 2 ) of the cavity part of the second field effect transistor (Q2) of the width (W 1 ) of the cavity part of the first field effect transistor (Q1).

Description

[TECHNICAL FIELD]

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a field effect transistor and a method of manufacturing the same, and a technology effective when applied to an electronic device. [BACKGROUND TECHNOLOGY]

[0002] As a semiconductor device, a semiconductor device in which a field-effect transistor is mounted on a compound semiconductor substrate has been focused. JP H09-027505 A and JP H11-354542 A disclose a field-effect transistor in which a cavity portion is provided as a low-dielectric-constant region in an insulating layer on both sides of a gate electrode in the gate length direction between a pair of main electrodes serving as a source electrode and a drain electrode. According to this field-effect transistor, since it is possible to reduce a parasitic capacitance (Cgs) added between the gate electrode and one main electrode (source electrode) and a parasitic capacitance (Cgd) added between the gate electrode and the other main electrode (drain electrode), it is possible to reduce the on-resistance of the field-effect transistor.Further field-effect transistors with cavities between the main electrodes are known, for example, from the documents WO 2019 / 176434 A1 and US 10 388 747 B1. [SUMMARY][TECHNICAL PROBLEM]

[0003] Incidentally, in a wireless communication device in a mobile communication system or the like, a first field-effect transistor constituting a high-frequency switch and a second field-effect transistor constituting a high-frequency power amplifier have different planar sizes, and the second field-effect transistor has a larger planar size. Specifically, the length between the main electrodes of the second field-effect transistor and the length of the gate electrode in the gate width direction are longer. This is because a low turn-on and low-off voltage are required in the first field-effect transistor constituting a high-frequency switch.On-resistance is required by shortening the separation distance between the pair of main electrodes, and in the second field-effect transistor constituting a high-frequency power amplifier, a high device withstand voltage is required, which is achieved by increasing the separation distance between the pair of main electrodes. It is desirable to mount such field-effect transistors with different planar sizes together on the same semiconductor substrate and reduce the size of the wireless communication device.

[0004] However, no process for assembling field-effect transistors having a cavity part and different planar sizes together has been achieved, and it has been difficult to reduce the on-resistance of each of the field-effect transistors having different planar sizes.

[0005] An object is to provide a semiconductor device that can reduce an on-resistance of each of field effect transistors having different planar sizes, a method for manufacturing the same, and an electronic device including the semiconductor device. [SOLUTION TO THE PROBLEM]

[0006] The invention is defined in claims 1, 6, 7, and 10. Further developments are the subject of the dependent claims. [BRIEF DESCRIPTION OF THE DRAWINGS] [ Fig. 1] Fig. 1 is a chip layout diagram illustrating a configuration example of a semiconductor device according to a first embodiment. [ Fig. 2] Fig. 2 is a plan view showing a configuration example of a semiconductor chip in Fig. 1 schematically shows the first transistor. [ Fig. 3] Fig. 3 is a cross-sectional view showing a configuration example of a cross-sectional structure taken along the section line II-II in Fig. 1 schematically shows. [ Fig. 4] Fig. 4 is a plan view showing a configuration example of a semiconductor chip in Fig. 1 schematically shows the second transistor. [ Fig. 5] Fig. 5 is a cross-sectional view showing a configuration example of a cross-sectional structure taken along the section line III-III in Fig. 4 shows schematically. [ Fig. 6] Fig. 6 is a cross-sectional view schematically illustrating a state in which the first transistor in Fig. 3 and the second transistor in Fig. 5 are housed on the same semiconductor substrate. [ Fig. 7A] Fig. 7A is a process cross-sectional view of a method of manufacturing a semiconductor device according to the first embodiment. [ Fig. 7B] Fig. 7B is a process cross-sectional view of the method of manufacturing a semiconductor device according to the first embodiment. [ Fig. 8A] Fig. 8A is a process cross-sectional view showing Fig. 7A continues. [ Fig. 8B] Fig. 8B is a process cross-sectional view showing Fig. 7B continues. [ Fig. 9A] Fig. 9A is a process cross-sectional view showing Fig. 8A continues. [ Fig. 9B] Fig. 9B is a process cross-sectional view showing Fig. 8B continues. [ Fig. 10A] Fig. 10A is a process cross-sectional view showing Fig. 9A continues. [ Fig. 10B] Fig. 10B is a process cross-sectional view showing Fig. 9B continues. [ Fig. 11A] Fig. 11A is a process cross-sectional view showing Fig. 10A continues. [ Fig. 11B] Fig. 11B is a process cross-sectional view showing Fig. 10B continues. [ Fig. 12A] Fig. 12A is a process cross-sectional view showing Fig. 11A continues. [ Fig. 12B] Fig. 12B is a process cross-sectional view showing Fig. 11B continues. [ Fig. 13A] Fig. 13A is a process cross-sectional view showing Fig. 12A continues. [ Fig. 13B] Fig. 13B is a process cross-sectional view showing Fig. 12B continues. [ Fig. 14A] Fig. 14A is a process cross-sectional view showing Fig. 13A continues. [ Fig. 14B] Fig. 14B is a process cross-sectional view showing Fig. 13B continues. [ Fig. 15A] Fig. 15A is a process cross-sectional view showing Fig. 14A continues. [ Fig. 15B] Fig. 15B is a process cross-sectional view showing Fig. 14B continues. [ Fig. 16A] Fig. 16A is a cross-sectional view schematically illustrating a configuration example of a first transistor mounted on a semiconductor chip in a semiconductor device according to a second embodiment. [ Fig. 16B] Fig. 16B is a cross-sectional view schematically illustrating a configuration example of a second transistor mounted on a semiconductor chip in the semiconductor device according to the second embodiment. [ Fig. 17A] Fig. 17A is a process cross-sectional view of a method of manufacturing a semiconductor device according to the second embodiment. [ Fig. 17B] Fig. 17B is a process cross-sectional view of the method of manufacturing a semiconductor device according to the second embodiment. [ Fig. 18A] Fig. 18A is a process cross-sectional view showing Fig. 17A continues. [ Fig. 18B] Fig. 18B is a process cross-sectional view showing Fig. 17B continues. [ Fig. 19A] Fig. 19A is a process cross-sectional view showing Fig. 18A continues. [ Fig. 19B] Fig. 19B is a process cross-sectional view showing Fig. 18B continues. [ Fig. 20A] Fig. 20A is a process cross-sectional view showing Fig. 19A continues. [ Fig. 20B] Fig. 20B is a process cross-sectional view showing Fig. 19B continues. [ Fig. 21A] Fig. 21A is a cross-sectional view schematically illustrating a configuration example of a first transistor mounted on a power switch part of a semiconductor device according to an example not claimed. [ Fig. 21B] Fig. 21B is a cross-sectional view schematically illustrating a configuration example of a second transistor mounted on a power amplifier part for amplifying the semiconductor device according to the example. [ Fig. 22A] Fig. 22A is a process cross-sectional view of a method of manufacturing a semiconductor device according to the example. [ Fig. 22B] Fig. 22B is a process cross-sectional view of the method of manufacturing a semiconductor device according to the example. [ Fig. 23A] Fig. 23A is a process cross-sectional view showing Fig. 22A continues. [ Fig. 23B] Fig. 23B is a process cross-sectional view showing Fig. 22B continues. [ Fig. 24A] Fig. 24A is a process cross-sectional view showing Fig. 23A continues. [ Fig. 24B] Fig. 24B is a process cross-sectional view showing Fig. 23B continues. [ Fig. 25A] Fig. 25A is a cross-sectional view schematically illustrating a configuration example of a first transistor mounted on a power switch part of a semiconductor device according to a fourth embodiment. [ Fig. 25B] Fig. 25B is a cross-sectional view schematically illustrating a configuration example of a second transistor mounted on a power amplifier part for amplifying the semiconductor device according to the fourth embodiment. [ Fig. 26A] Fig. 26A is a process cross-sectional view of a method of manufacturing a semiconductor device according to the fourth embodiment. [ Fig. 26B] Fig. 26B is a process cross-sectional view of the method of manufacturing a semiconductor device according to the fourth embodiment. [ Fig. 27A] Fig. 27A is a process cross-sectional view showing Fig. 26A continues. [ Fig. 27B] Fig. 27B is a process cross-sectional view showing Fig. 26B continues. [ Fig. 28A] Fig. 28A is a process cross-sectional view showing Fig. 27A continues. [ Fig. 28B] Fig. 28B is a process cross-sectional view showing Fig. 27B continues. [ Fig. 29A] Fig. 29A is a process cross-sectional view showing Fig. 28A continues. [ Fig. 29B] Fig. 29B is a process cross-sectional view showing Fig. 28B continues. [ Fig. 30A] Fig. 30A is a process cross-sectional view showing Fig. 29A continues. [ Fig. 30B] Fig. 30B is a process cross-sectional view showing Fig. 29B continues. [ Fig. 31A] Fig. 31A is a process cross-sectional view showing Fig. 30A continues. [ Fig. 31B] Fig. 31B is a process cross-sectional view showing Fig. 30B continues. [ Fig. 32A] Fig. 32A is a cross-sectional view schematically illustrating a configuration example of a first transistor mounted on a power switch part of a semiconductor device according to a fifth embodiment. [ Fig. 32B] Fig. 32B is a cross-sectional view schematically illustrating a configuration example of a second transistor mounted on a power amplifier part for amplifying the semiconductor device according to the fifth embodiment. [ Fig. 33A] Fig. 33A is a process cross-sectional view of a method of manufacturing a semiconductor device according to the fifth embodiment. [ Fig. 33B] Fig. 33B is a process cross-sectional view of the method of manufacturing a semiconductor device according to the fifth embodiment. [ Fig. 34A] Fig. 34A is a process cross-sectional view showing Fig. 33A continues. [ Fig. 34B] Fig. 34B is a process cross-sectional view showing Fig. 33B continues. [ Fig. 35A] Fig. 35A is a process cross-sectional view showing Fig. 34A continues. [ Fig. 35B] Fig. 35B is a process cross-sectional view showing Fig. 34B continues. [ Fig. 36A] Fig. 36A is a process cross-sectional view showing Fig. 35A continues. [ Fig. 36B] Fig. 36B is a process cross-sectional view showing Fig. 35B continues. [ Fig. 37A] Fig. 37A is a process cross-sectional view showing Fig. 36A continues. [ Fig. 37B] Fig. 37B is a process cross-sectional view showing Fig. 36B continues. [ Fig. 38] Fig. 38 is a block diagram illustrating an example of a configuration of a wireless communication apparatus to which the semiconductor device is applied. [DESCRIPTION OF EMBODIMENTS]

[0007] Embodiments are described below with reference to the drawings.

[0008] In all drawings for describing embodiments here, those having the same function are designated by the same reference numerals and their repeated description is omitted.

[0009] Furthermore, the drawings are schematic and may differ from actual components. Furthermore, the following embodiments exemplify devices and methods for embodying the technical concepts. (First embodiment)

[0010] In the first embodiment, a semiconductor device is described in which, as field effect transistors having different separation distances between a source electrode and a drain electrode, a first field effect transistor used in a high-frequency switch and a second field effect transistor used in a high-frequency power amplifier are housed together on the same semiconductor substrate. <Konfiguration einer Halbleitervorrichtung>

[0011] As in Fig. 1, a semiconductor device 1 according to the first embodiment mainly consists of a semiconductor chip 2, which has a rectangular two-dimensional planar shape when viewed from above. The semiconductor chip 2 includes a high-frequency power amplifier section PA, a low-noise high-frequency amplifier section LNA, a high-frequency filter section BPF, and a high-frequency switch section SW. In the high-frequency switch section SW, as an element constituting a high-frequency switch, a Fig. 2, Fig. 3 and Fig. 6 is housed. In the high-frequency power amplifier section PA, an element forming a high-frequency power amplifier is Fig. 4, Fig. 5 and Fig. The second field effect transistor Q2 shown in Figure 6 is housed.

[0012] The first field-effect transistor Q1 and the second field-effect transistor Q2 have different planar sizes, and the planar size of the second field-effect transistor Q2 is larger than the planar size of the first field-effect transistor Q1. Specifically, as shown in Fig. 4 and Fig. 2, a separation distance L 2 between a pair of second main electrodes 16B and 17B, which function as the source electrode and drain electrode of the second field-effect transistor Q2, longer than a separation distance L 1 between a pair of first main electrodes 16A and 17A, which function as the source electrode and drain electrode of the first field-effect transistor Q1.

[0013] As in Fig. 3, Fig. 5 and Fig. 6, the semiconductor chip 2 comprises a semiconductor substrate 10 and an insulating layer 20 provided on the main surface of the semiconductor substrate 10.

[0014] The semiconductor substrate 10 comprises a substrate 11, a buffer layer 11a provided on the substrate 11, a channel layer 12 provided on the buffer layer 11a, and a barrier layer 13 provided on the channel layer 12. On the main surface of the semiconductor substrate 10, a first active region 10A and a second active region 10B are provided, which are separated and insulated from each other by an inactive region 15. The inactive region 15 consists of, for example, an impurity diffusion region into which boron (B + -) ions have diffused as impurities. As in Fig. 3 and Fig. Here, as shown in Figure 5, the inactive region 15 is formed deeper than a two-dimensional electron gas (2DEG) layer 14 to be described later in a depth direction from the main surface of the semiconductor substrate 10. Isolation separation (element separation) between the active regions can be performed by a method other than ion implantation. For example, the channel layer 12 can be divided by dry etching, and isolation separation can be performed between the active regions.

[0015] The substrate 11 is made of a semiconductor material. Such a substrate 11 is made of, for example, a group III-V compound semiconductor material. With respect to the substrate 11, for example, a semi-insulating single-crystal GaN (gallium nitride) substrate is used. A substrate material having a lattice constant different from a lattice constant of the channel layer 12 can be used for the substrate 11. Examples of such a material constituting the substrate 11 include SiC (silicon carbide), sapphire, and Si (silicon). In this case, the lattice constant is adjusted by the buffer layer 11a between the substrate 11 and the channel layer 12.

[0016] The buffer layer 11a is formed of, for example, a compound semiconductor layer epitaxially grown on the substrate 11 and is formed using a compound semiconductor having favorable lattice matching with the substrate 11. For example, on the substrate 11 formed of a single-crystal GaN substrate, an epitaxially grown layer of u-GaN (u- indicates that no impurities are added; the same applies hereafter) to which no impurities are added is provided. When the lattice constant of the substrate 11 is different from the lattice constant of the channel layer 12, if the buffer layer 11a is provided between the substrate 11 and the channel layer 12, it is possible to improve the crystalline state of the channel layer 12 and prevent wafer warpage.For example, if the substrate 11 is made of Si and the channel layer 12 is made of GaN, AlN (aluminum nitride), AlGaN (aluminum gallium nitride), or GaN can be used for the buffer layer 11a. The buffer layer 11a can be composed of a single layer or can have a laminated structure. If the buffer layer 11a is made of a three-dimensional material, each composition in the buffer layer 11a can gradually change.

[0017] The channel layer 12 between the buffer layer 11a and the barrier layer 13 is a current passage between the source electrode and the drain electrode. Carriers accumulate in the channel layer 12 due to polarization with respect to the barrier layer 13, and a two-dimensional electron gas (2DEG) layer 14 is provided near a bonding surface (heterobonding interface) with respect to the barrier layer 13. It is preferable that such a channel layer 12 be made of a compound semiconductor material in which carriers easily accumulate due to polarization with respect to the barrier layer 13. For example, the channel layer 12 is made of GaN epitaxially grown on the buffer layer 11a. The channel layer 12 may be made of u-GaN to which no impurities are added.In the channel layer 12 consisting of u-GaN, since a distribution of impurities of charge carriers in the channel layer 12 is limited, it is possible to improve the mobility of the charge carriers.

[0018] As in Fig. 3, Fig. 5 and Fig. 6, the insulating layer 20 includes a first insulating film 21 provided on the main surface of the semiconductor substrate 10, a second insulating film 22 provided on the first insulating film 21, and a third insulating film 26 provided on the second insulating film 22. As the first insulating film 21, for example, an aluminum oxide (Al 3 O 2 -) film is used. As the second insulating film 22, for example, a silicon oxide (SiO 2-) film having a high etching selectivity with respect to the first insulating film 21 is used. The first insulating film 21 and the second insulating film 22 are formed, for example, with a film thickness of about 50 nm.

[0019] The third insulating film 26 is formed to sandwich the first insulating film 21, the second insulating film 22 and the main surface (the barrier layer 13) of the semiconductor substrate 10 in a first cavity part 25A 1 and a second cavity part 25B 1 which will be described below. The third insulating film 26 has an insulating property with respect to the barrier layer 13, the first insulating film 21 and the second insulating film 22, which leads to the first cavity part 25A 1 and the second cavity part 25B 1exposed, the barrier layer 13 protects against impurities such as ions and is formed of a material that forms a favorable interface with the barrier layer 13 and prevents deterioration of the device characteristics. The third insulating film 26 is formed, for example, of a laminated film in which an Al 2 O 3 -film and a hafnium oxide (HfO 2 -) film with a film thickness of about 10 nm are laminated in this order. The third insulating film 26 may be made of a single Al 2 O 3 -Film or HfO 2 -Film can be formed.

[0020] As in Fig. 2, Fig. 3 and Fig. As shown in Figure 6, the first field-effect transistor Q1 is formed in the first active region 10A of the main surface of the semiconductor substrate 10. The first field-effect transistor Q1 includes the buffer layer 11a, the channel layer 12, the barrier layer 13, and the two-dimensional electron gas layer 14. Furthermore, the first field-effect transistor Q1 includes the pair of first main electrodes 16A and 17A, which are separated from each other and provided on the first active region 10A of the main surface of the semiconductor substrate 10 and function as the source electrode and the drain electrode, and the first cavity portion 25A. 1 , which is provided in the insulating layer 20 between the pair of first main electrodes 16A and 17A. Furthermore, the first field effect transistor Q1 includes a first gate electrode 31A having a head portion 31a positioned on the insulating layer 20. 1 and a body or torso part 31a 2which is from the head part 31a 1 from the insulating layer 20 and towards the first cavity part 25A 1 protrudes, and in which the head part 31a 1 wider than the fuselage section 31a 2 That is, the first field-effect transistor Q1 of the first embodiment is a GaN-based hetero-FET (HFET: hetero-field-effect transistor).

[0021] As in Fig. 2, the first gate electrode 31A has a long shape in plan view, and the gate width (Wg) is longer than the gate length (Lg). The first gate electrode 31A extends over the first active region 10A and the inactive region 15. As shown in Fig. 3 and Fig. 6, here in the first gate electrode 31A the head part 31a 1 positioned on the third insulating film 26, and the one with the head part 31a 1 integrated fuselage section 31a 2 is in the direction of the first cavity part 25A1 through a first gate opening 27A provided in the insulating layer 20 1 before.

[0022] As in Fig. 2, Fig. 3 and Fig. As shown in Figure 6, the pair of first main electrodes 16A and 17A with the first gate electrode 31A therebetween are separated from each other in the gate length direction of the first gate electrode 31A (the short direction and the width direction of the first gate electrode 31A). Here, the pair of first main electrodes 16A and 17A extend across the first active region 10A and the inactive region 15 in the gate width direction of the first gate electrode 31A (the longitudinal direction and the length direction of the first gate electrode 31A).

[0023] As in Fig. 2, the first cavity part 25A 1 , viewed in plan view, formed in a ring-shaped flat pattern which surrounds the body part 31a 2 the first gate electrode 31A. As shown in Fig. 3, the first cavity part 25A therefore comprises 1 one on one side (left side) of the fuselage part 31a 2 positioned first part 25A 1 -L and one on the other side (right side) of the fuselage part 31a 2 positioned second part 25A 1 -R in the direction of the gate length of the first gate electrode 31. In the first embodiment, the first cavity part 25A 1 here a bilaterally symmetric configuration in which the first part 25A 1 -L and the second part 25A 1 -R have substantially the same width. In the direction of the gate length of the first gate electrode 31A, the first cavity part 25A 1 wider than the fuselage section 31a 2 the first gate electrode 31A and the first gate opening 27A 1 .

[0024] As in Fig. 4, Fig. 5 and Fig. As shown in Figure 6, the second field-effect transistor Q2 is formed in the second active region 10B different from the first active region 10A of the main surface of the semiconductor substrate 10. The second field-effect transistor Q2 includes the buffer layer 11a, the channel layer 12, the barrier layer 13, and the two-dimensional electron gas layer 14. Furthermore, the second field-effect transistor Q2 includes the pair of second main electrodes 16B and 17B, which are separated from each other and provided on the second active region 10B of the main surface of the semiconductor substrate 10, and in which the separation distance L 2 (see Fig. 4 and Fig. 6) longer than the separation distance L 1 (see Fig. 2 and Fig. 6) between the pair of first main electrodes 16A and 17A of the first field effect transistor Q1 is longer, and the second cavity part 25B 1, which is provided in the insulating layer 20 between the pair of second main electrodes 16B and 17B. The pair of second main electrodes 16B and 17B function as a source electrode and a drain electrode. In addition, the second field-effect transistor Q2 includes a second gate electrode 31B having a head portion 31b positioned on the insulating layer 20. 1 and a fuselage section 31b 2 which is from the head part 31b 1 from the insulating layer 20 and towards the second cavity part 25B 1 protrudes, and in which the head part 31b 1 wider than the fuselage section 31b 2 That is, the second field-effect transistor Q2 of the first embodiment is also a GaN-based hetero-FET like the first field-effect transistor Q1.

[0025] As in Fig. 4, the second gate electrode 31B has a long shape when viewed from above, and the gate width is longer than the gate length. The second gate electrode 31B extends over the second active region 10B and the inactive region 15. The head portion 31b is formed in the second gate electrode 31B. 1 positioned on the third insulating film 26, and the one with the head part 31b 1 integrated fuselage section 31b 2 is in the direction of the second cavity part 25B 1 through a second gate opening 27B provided in the insulating layer 20 1 before.

[0026] As in Fig. 4, Fig. 5 and Fig. 6, the pair of second main electrodes 16B and 17B with the second gate electrode 31B therebetween are separated from each other in the gate length direction (the short direction and the width direction of the second gate electrode 31B) of the second gate electrode 31B. Here, the pair of second main electrodes 16B and 17B extends across the second active region 10B and the inactive region 15 in the gate width direction of the second gate electrode 31B (the longitudinal direction and the length direction of the second gate electrode 31B).

[0027] As in Fig. 4 is shown in plan view, the second cavity part 25B 1 formed in a ring-shaped flat pattern that surrounds the body part 31b 2 the second gate electrode 31B. Like the first cavity part 25A 1 therefore includes, as in Fig. 5, the second cavity part 25B 1also one on one side (left side) of the fuselage part 31b 2 positioned first part 25B 1 -L and one on the other side (right side) of the fuselage part 31b 2 positioned second part 25B 1 -R in the direction of the gate length of the second gate electrode 31B. In the first embodiment, although not limited thereto, the second cavity part 25B 1 a bilaterally symmetric configuration in which the first part 25B 1 -L and the second part 25B 1 -R have essentially the same width.

[0028] The second cavity part 25B 1 is wider than the fuselage section 31b 2 the second gate electrode 31B and the second gate opening 27B 1 in the direction of the gate length of the second gate electrode 31B. As shown in Fig. 6, here the width W 2 of the second cavity part 25B 1 wider than the width W1 of the first cavity part 25A 1 . That is, the second cavity part 25B 1 is wider than the first cavity part 25A 1 . The width W 2 of the second cavity part 25B 1 is here a length in the direction of the gate length of the second gate electrode 31B, and the width W 1 of the first cavity part 25A 1 is a length in the direction of the gate length of the first gate electrode 31A. In the first embodiment, although not limited thereto, the first gate electrode 31A and the second gate electrode 31B extend in the same direction, and as shown in Fig. 6, the respective short directions of the first gate electrode 31A and the second gate electrode 31B are in the same direction.

[0029] The interior of both the first cavity part 25A 1 as well as the second cavity part 25B 1is filled with a rare gas or in a negative pressure or vacuum state and is a low dielectric constant region having a lower dielectric constant than the surrounding first insulating film 21, the second insulating film 22 and the third insulating film 26.

[0030] As in Fig. As shown in Fig. 6, the first gate electrode 31A and the second gate electrode 31B are provided on the third insulating film 26. The first gate electrode 31A and the second gate electrode 31B are made of, for example, a laminated film in which a nickel (Ni) film and a gold (Au) film are sequentially laminated from the semiconductor substrate 10 side.

[0031] The pair of first main electrodes 16A and 17A are ohmically bonded to the barrier layer 13 in the first active region 10A. The pair of second main electrodes 16B and 17B are ohmically bonded to the barrier layer 13 in the second active region 10B. The pair of first main electrodes 16A and 17A and the pair of second main electrodes 16B and 17B are made of, for example, a laminated film in which a titanium (Ti) film, an Al film, a Ni film, and an Au film are sequentially laminated from the semiconductor substrate 10 side.

[0032] For example, when the first and second field-effect transistors Q1 and Q2 are of a depression type in which the threshold voltage is a negative voltage, if a gate voltage Vg is applied to the gate electrodes 31A and 31B, the number of carriers in a carrier-deficient region in the surface layer part of the channel layer 12 directly below the gate electrodes 31A and 31B decreases, the number of electrons in the channel layer 12 decreases, and the drain current Id hardly flows. If a positive gate voltage Vg is applied to the gate electrodes 31A and 31B, the carrier-deficient region disappears, the number of electrons in a buffer layer 12 increases, and the drain current Id is modulated.

[0033] As described above, in the semiconductor device 1 according to the first embodiment, the first field effect transistor Q1 and the second field effect transistor Q2 having a larger planar size than the first field effect transistor Q1 are housed together on the same semiconductor substrate 10. As shown in Fig. 6, it is here that the first field effect transistor Q1 covers the first cavity part 25A 1 contains, compared with a conventional field effect transistor having the same planar size as the first field effect transistor Q1 and the first cavity part 25A 1does not contain, it is possible to reduce the parasitic capacitance Cgs added between the first gate electrode 31A and a first main electrode 16A (for example, a source electrode) and the parasitic capacitance Cgd added between the first gate electrode 31A and the other first main electrode 17A (for example, a drain electrode), and thereby it is possible to reduce the on-resistance and improve the insulation characteristics. As shown in Fig. 6, it is here that the second field effect transistor Q2 covers the second cavity part 25B 1 which is wider than the first cavity part 25A 1 is, compared with a conventional field effect transistor having the same planar size as the second field effect transistor Q2 and a cavity part with the same size as the first cavity part 25A 1, it is possible to reduce the parasitic capacitance Cgs added between the second gate electrode 31B and one second main electrode 16B (for example, a source electrode) and the parasitic capacitance Cgd added between the second gate electrode 31B and the other second main electrode 17B (for example, a drain electrode), and thereby reduce the on-resistance and improve high-frequency characteristics. Therefore, according to the semiconductor device 1 of the first embodiment, it is possible to reduce the on-resistance of the first field-effect transistor Q1 and the second field-effect transistor Q2, which have different planar sizes, and improve characteristics according to each application.

[0034] In addition, the first field-effect transistor Q1 is used as an element forming the high-frequency switch part SW. In this case, according to the first field-effect transistor Q1, by reducing the separation distance L 1 between the pair of first main electrodes 16A and 17A, the planar size is reduced and thus the on-resistance can be reduced and it is possible to improve high-frequency characteristics.

[0035] On the other hand, the second field-effect transistor Q2 is used as an element forming the high-frequency power amplifier part PA. In this case, it is necessary to set the separation distance L in the second field-effect transistor Q2. 2between the pair of second main electrodes 16B and 17B and to increase a withstand voltage of the device (withstand voltage between gate / drain), and the planar size is larger than that of the first field effect transistor Q1. Therefore, like the semiconductor device 1 of the first embodiment, when the second cavity part 25B 1 of the second field effect transistor Q2 wider than the first cavity part 25A 1 of the first field effect transistor Q1, it is possible to ensure the device withstand voltage of the second field effect transistor Q2 and reduce the on-resistance.

[0036] Above the insulating layer 20, a wiring layer and other insulating layers are provided; but in Fig. 3, Fig. 5 and Fig. 6, the wiring layer and other insulating films above the insulating layer 20 are not shown.

[0037] Furthermore, in the first embodiment, the first field effect transistor Q1 and the second field effect transistor Q2 are arranged so that respective short directions of the gate electrodes 31A and 31B are the same direction; but respective short directions of the gate electrodes 31A and 31B may be different directions. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0038] Next, with reference to Fig. 7A to Fig. 15B describes a method for manufacturing the semiconductor device 1. Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A and Fig. 15A show processes for forming the first field effect transistor Q1 in the first active region 10A of the semiconductor substrate 10. Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B and Fig. 15B show processes for forming the second field effect transistor Q2 in the second active region 10B of the semiconductor substrate 10. The first field effect transistor Q1 and the second field effect transistor Q2 are formed by the same process.

[0039] First, as in Fig. 7A and Fig. 7B, the semiconductor substrate 10 is prepared. The semiconductor substrate 10 has a laminated structure in which the buffer layer 11a, the channel layer 12, and the barrier layer 13 are laminated in this order on the substrate 11. The two-dimensional electron gas layer 14 is provided near the bonding interface between the channel layer 12 and the barrier layer 13.

[0040] Next, as in Fig. 8A and Fig. 8B, the inactive region 15 which partitions and insulates and separates the first active region 10A and the second active region 10B is formed on the main surface of the semiconductor substrate 10, and also the pair of first main electrodes 16A and 17A functioning as a source electrode and a drain electrode is formed on the first active region 10A of the main surface of the semiconductor substrate, and the pair of second main electrodes 16B and 17B functioning as a source electrode and a drain electrode is formed on the second active region 10B of the main surface of the semiconductor substrate 10.

[0041] The inactive region 15 is formed by, for example, boron-(B + -)ions as impurity ions are selectively injected into the surface layer part on the main surface side of the semiconductor substrate 10 and then a heat treatment is carried out to heat the injected B + -ions to activate.

[0042] The pair of first main electrodes 16A and 17A and the pair of second main electrodes 16B and 17B are formed when a conductive film having a multilayer structure is formed by sequentially laminating, from the semiconductor substrate 10 side, a Ti film, an Al film, a Ni film, and an Au film on the entire main surface of the semiconductor substrate 10 including the first active region 10A and the second active region 10B using a CVD method or a sputtering method, and then patterning the conductive film using a well-known photolithography technique and a dry etching technique with high directivity. The pair of first main electrodes 16A and 17A are then formed in a long shape and separated from each other in the short direction (width direction) orthogonal to the longitudinal direction.The pair of second main electrodes 16B and 17B are also formed in a long shape and separated from each other in the short direction (width direction) orthogonal to the longitudinal direction. The pair of second main electrodes 16B and 17B, between which the separation distance L. 2 longer than the separation distance L 1 between the pair of first main electrodes 16A and 17A is formed separately from each other.

[0043] As in Fig. 9A and Fig. 9B, the first insulating film 21 is formed on the entire main surface of the semiconductor substrate 10 including the above first active region 10A and the second active region 10B, and thereafter, as shown in Fig. 9A and Fig. 9B, the second insulating film 22 is formed on the entire main surface of the semiconductor substrate 10, including the above first active region 10A and the second active region 10B, with the first insulating film 21 therebetween. The second insulating film 22 is made of an insulating film having a high etching selectivity with respect to the first insulating film 21. In other words, the first insulating film 21 is made of an insulating film having a low etching selectivity with respect to the second insulating film 22. For example, an aluminum oxide (Al 2 O 3 -) film as the first insulating film 21 by an atomic vapor deposition (ALD) method, and a silicon oxide (SiO 2-) film is formed as the second insulating film 22 by a chemical vapor deposition (CVD) method. According to this process, the first active region 10A and the second active region 10B of the main surface of the semiconductor substrate 10 are covered with the first insulating film 21 and the second insulating film 22.

[0044] Next, as in Fig. 10A and Fig. 10B, a first opening 24A 1 in the second insulating film 22 on the first active region 10A of the main surface of the semiconductor substrate 10 and a second opening 24B 1 formed in the second insulating film 22 on the second active region 10B of the main surface of the semiconductor substrate 10. The first opening 24A 1 and a second opening 24B 1are formed by selectively etching the second insulating film 22 using a well-known photolithography technique and a well-known high-directivity dry etching as an anisotropic etching technique.

[0045] The first opening 24A 1 is formed in plan view between the pair of first main electrodes 16A and 17A, and is formed with a long plane pattern in the longitudinal direction of the pair of first main electrodes 16A and 17A. The second opening 24B 1 is formed in plan view between the pair of the second main electrode 16B and the second main electrode 17B and is formed with a long plane pattern extending in the longitudinal direction of the pair of second main electrodes 16B and 17B.

[0046] As in Fig. 11A and Fig. 11B, next, the first cavity part 25A 1which is wider than the first opening 24A 1 is formed by the first insulating film 21 on the first active region 10A of the semiconductor substrate 10 through the first opening 24A 1 is etched, and the second cavity part 25B 1 which is wider than the second opening 24B 1 is formed by the first insulating film 21 on the second active region 10B of the semiconductor substrate 10 through the second opening 24B 1 is etched.

[0047] The first cavity part 25A 1 and the second cavity part 25B 1are formed by etching the first insulating film 21 by performing isotropic wet etching with low damage on the main surface of the semiconductor substrate 10, that is, the surface of the barrier layer 13. The wet etching of the first insulating film 21 is performed under conditions where etching selectivity with respect to the second insulating film 22 is obtained. That is, the etching is performed under conditions where a wet etching rate for the first insulating film 21 is higher than for the second insulating film 22. Higher selectivity is more preferable; but, for example, the etching is performed under conditions where the etching selectivity between the first insulating film 21 and the second insulating film 22 is 10:1 or more.

[0048] As in Fig. 12A and Fig. 12B, a mask RM1 is next formed to cover the first opening 24A 1on the first active region 10A of the semiconductor substrate 10 except for the second opening 24B 1 on the second active region 10B of the semiconductor substrate 10. The mask RM1 is formed by forming a photosensitive resist film on the entire main surface of the semiconductor substrate 10 including the above first active region 10A and the second active region 10B, and then subjecting the photosensitive resist film to photosensitivity and development treatment or the like to form a predetermined pattern.

[0049] As in Fig. 13A and Fig. 13B, next, the mask RM1 is used as an etching mask, and the width of the second cavity part 25B 1 is extended by passing the first insulating film 21 through the second opening 24B 1 is selectively etched when the first opening 24A 1covered with the mask RM1. The extension of the second cavity part 25B 1 is performed by etching the first insulating film 21 by performing isotropic wet etching with less damage on the main surface of the semiconductor substrate 10, that is, the surface of the barrier layer 13. The wet etching of the first insulating film 21 is performed under conditions where etching selectivity with respect to the second insulating film 22 is obtained. For example, the etching is performed under conditions where the etching selectivity between the first insulating film 21 and the second insulating film 22 is 10:1 or more.

[0050] According to this process, the second cavity part 25B 1 with a width W 2 (see Fig. 6), which is wider than the width W 1 (see Fig. 6) of the first cavity part 25A 1 is trained.

[0051] In addition, in this process, since the width of the second cavity part 25B 1 is selectively expanded, the first insulating film 21 between each of the pair of first main electrodes 16A and 17A and the first cavity part 25A 1 remain and the first insulating film 21 may be disposed between each of the pair of second main electrodes 16B and 17B and the second cavity part 25B 1 remain.

[0052] Next, after the mask RM1 is removed, as shown in Fig. 14A and Fig. 14B, in the first cavity part 25A 1 and the second cavity part 25B 1 the third insulating film 26 is formed covering the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the surface of the barrier layer 13), respective side walls in the first opening 24A 1 and the second opening 24B 1of the second insulating film 22 and covers the second insulating film 22. The third insulating film 26 is formed by, for example, using an ALD method, depositing an Al 2 O 3 -Film is formed. Since the ALD method enables uniform film formation, the exposed surface of the barrier layer 13, the first insulating film 21, and the second insulating film 22 is covered with the uniform third insulating film 26. In this process, the insulating layer 20, which includes the first insulating film 21, the second insulating film 22, and the third insulating film 26, is formed on the first active region 10A and the second active region 10B of the semiconductor substrate 10. In addition, in this process, since respective sidewalls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 are covered with the third insulating film 26, the first gate opening 27A 1with a narrower opening width than the first opening 24A 1 formed and becomes the second gate opening 27B 1 with a narrower opening width than the second opening 24B 1 In addition, in this process, the first cavity part 25A 1 and the second cavity part 25B 1 surrounded by the third insulating film 26. Since the third insulating film 26 is formed here with a nearly uniform film thickness, in the first cavity part 25A 1 and the second cavity part 25B 1 , which are surrounded by the third insulating film 26, the width W 2 (see Fig. 6) of the second cavity part 25B 1 wider than the width W 1 (see Fig. 6) of the first cavity part 25A 1 .

[0053] As in Fig. 15A and Fig. Next, as shown in Fig. 15B, a gate material 30 is formed on the entire surface of the third insulating film 26, including the above first active region 10a and the second active region 10B of the semiconductor substrate 10. The gate material 30 is formed by sequentially laminating a Ni film and an Au film from the semiconductor substrate 10 side by, for example, a vapor deposition method.

[0054] In this process, the inside of the first gate opening 27A 1 and the interior of the second gate opening 27B 1 filled with the gate material 30 and the gate material 30 is selectively filled into a part directly below the first gate opening 27A 1 in the first cavity part 25A 1 and a part directly below the second gate opening 27B 1 in the second cavity part 25B 1 filled.

[0055] Next, the gate material 30 is patterned using a well-known photolithography technique and a dry etching technique with high directivity, the first gate electrode 31A (see Fig. 6) is formed on the first active region 10A of the semiconductor substrate 10 and the second gate electrode 31B (see Fig. 6) is formed on the second active region 10B of the semiconductor substrate 10. Both the first gate electrode 31A and the second gate electrode 31B can be formed here using a lift-off method.

[0056] In this process, the first gate electrode 31A includes the head portion 31a positioned on the insulating layer 20 1 and the fuselage section 31a 2 , which from the headboard 31a 1 from the insulating layer 20 and towards the first cavity part 25A 1 protrudes, and the head part 31a 1 wider than the fuselage section 31a 2Similarly, the second gate electrode 31B includes the head portion 31b positioned on the insulating layer 20 1 and the fuselage section 31b 2 , which from the headboard 31b 1 from the insulating layer 20 and towards the second cavity part 25B 1 protrudes, and the head part 31b 1 wider than the fuselage section 31b 2 trained.

[0057] In addition, in this process, the first cavity part 25A 1 with almost the same cavity width on both sides of the first gate electrode 31A in the direction of the gate length is formed bilaterally symmetrically. In addition, the second cavity part 25B 1 with almost the same cavity width on both sides of the second gate electrode 31B in the direction of the gate length bilaterally symmetrically formed.

[0058] According to this process, the Fig. 2, Fig. 3 and Fig. The first field effect transistor Q1 shown in Figure 6 is almost completed and is the one shown in Fig. 4, Fig. 5 and Fig. The second field effect transistor Q2 shown in Figure 6 is almost completed.

[0059] Thereafter, a wiring layer and other insulating layers are formed on the insulating layer 20, and thus the Fig. 1 to Fig. 6, the semiconductor device 1 is almost completed.

[0060] According to the method of manufacturing the semiconductor device 1 of the first embodiment, the first cavity part 25A 1 and the second cavity part 25B 1 which is wider than the first cavity part 25A 1 is formed by the same process.

[0061] In addition, according to the method of manufacturing the semiconductor device 1 of the first embodiment, since the width of the second cavity part 25B 1of the second field effect transistor Q2 having a larger planar size than the first field effect transistor Q1 is selectively expanded, in the first field effect transistor Q1, the first insulating film 21 between each of the pair of first main electrodes 16A and 17A and the first cavity part 25A 1 remain and can thus the first cavity part 25A 1 containing first field effect transistor Q1 and the second field effect transistor Q2, which forms the second cavity part 25B 1 which is wider than the first cavity part 25A 1 and has a larger planar size than the first field effect transistor Q1, by means of the same process.

[0062] According to the method for manufacturing the semiconductor device 1 of the first embodiment, in the first field effect transistor Q1, since the first insulating film 21 is provided between each of the pair of first main electrodes 16A and 17A and the first cavity part 25A 1can remain, the planar size of the first field-effect transistor Q1 can be made smaller than that of the second field-effect transistor Q2. This makes it possible to reduce the on-resistance of the first field-effect transistor Q1 and improve high-frequency characteristics and reduce the size of the semiconductor device 1.

[0063] Moreover, in the method for manufacturing the semiconductor device 1 according to the first embodiment, since the first insulating film 21 is etched by wet etching, it is possible to prevent damage to the main surface of the semiconductor substrate 10 (the barrier layer 13). Specifically, since the main surface of the semiconductor substrate 10 is not exposed to plasma, and ions and the like in an etching gas do not penetrate into the semiconductor substrate 10 during etching, deterioration of the on-resistance (i.e., an increase in sheet resistance) and deterioration of the off-characteristics (i.e., an increase in leakage current or a decrease in withstand voltage) are not caused. (Second embodiment)<Konfiguration einer Halbleitervorrichtung>

[0064] A semiconductor device 1A according to a second embodiment has basically the same configuration as the semiconductor device 1 of the above first embodiment and includes a second field-effect transistor Q3 instead of the second field-effect transistor Q2 of the first embodiment. That is, as shown in Fig. 16A and Fig. 16B, the semiconductor device 1A according to the second embodiment includes the first field effect transistor Q1 formed in the first active region 10A of the main surface of the semiconductor substrate 10 (see Fig. 16A) and the second field effect transistor Q3 formed in the second active region 10B of the main surface of the semiconductor substrate 10 (see Fig. 16B). As in Fig. 16B, the second field effect transistor Q3 includes a second cavity portion 25B 2 instead of the second cavity part 25B 1of the second field-effect transistor Q2 of the first embodiment. The remaining configurations are the same as those in the above first embodiment.

[0065] Like the second cavity part 25B 1 of the above first embodiment, the second cavity part 25B 2 of the second field effect transistor Q3, viewed in plan view, is formed in a ring-shaped planar pattern, which covers the body part 31b 2 the second gate electrode 31B. As the second cavity part 25B 1 The above first embodiment therefore comprises, as shown in Fig. 16B, the second cavity part 25B 2 one on one side (left side) of the fuselage part 31b 2 the second gate electrode 31B positioned first part 25B 2 -L and one on the other side (right side) of the fuselage part 31b 2 the second part 25B positioned on the second gate electrode 31B 2-R in the direction of the gate length of the second gate electrode 31B. Unlike the second cavity part 25B 1 the above first embodiment, here in the second embodiment, the second cavity part 25B 2 a bilaterally asymmetric configuration in which the width of the second part 25B 2 -R wider than the width of the first part 25B 2 -L. In the direction of the gate length (longitudinal direction) of the second gate electrode 31B, the second cavity part 25B 2 wider than the fuselage section 31b 2 the second gate electrode 31B and the second gate opening 27B 1 . The width W 2 of the second cavity part 25B 2 is wider here than the width W 1 of the first cavity part 25A 1 . That is, the second cavity part 25B 2 is wider than the first cavity part 25A 1 .

[0066] According to the semiconductor device 1A according to the second embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment described above can be obtained.

[0067] In addition, if, for example, a reduction in the source resistance is important for the device characteristics, in the second field-effect transistor Q3, when a second main electrode 16B is used as a drain electrode, if the separation distance between a second main electrode 16B and the second gate electrode 31B increases, the source resistance increases and the device characteristics deteriorate. If the width of the second cavity part 25B 2-R on the side of the other second main electrode 16B functioning as a drain electrode is widened while keeping the source resistance low, an effect of reducing the parasitic capacitance (Cgd) added between the gate electrode and the other main electrode can be improved.

[0068] Here, a wiring layer and other insulating layers are provided above the insulating layer 20; but in Fig. 16A and Fig. 16B, the wiring layer and other insulating films above the insulating layer 20 are not shown. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0069] Next, with reference to Fig. 17A to Fig. 20B, a method of manufacturing the semiconductor device 1A according to the second embodiment is described. Fig. 17A, Fig. 18A, Fig. 19A and Fig. 20A show processes for forming the first field effect transistor Q1 in the first active region 10A of the semiconductor substrate 10. Fig. 17B, Fig. 18B, Fig. 19B and Fig. 20B show processes for forming the second field effect transistor Q3 in the second active region 10B of the semiconductor substrate 10. The first field effect transistor Q1 and the second field effect transistor Q3 are formed by the same process.

[0070] First, the same processes as in Fig. 7A to Fig. 10B in the first embodiment are carried out and are, as shown in Fig. 17A and Fig. 17B, ​​the pair of first main electrodes 16A and 17A, the pair of second main electrodes 16B and 17B, the first insulating film 21 and the second insulating film 22, the first opening 24A 1 and the second opening 24B 1 and the like.

[0071] Next, the same processes as in Fig. 11A and Fig. 11B in the above first embodiment, and as shown in Fig. 17A and Fig. 17B, ​​the first cavity part 25A 1 which is wider than the first opening 24A 1 is formed and the second cavity part 25B 2 which is wider than the second opening 24B 1 is trained.

[0072] As in Fig. 18A and Fig. 18B, a mask RM2 is next formed, which covers the first opening 24A 1 on the first active region 10A of the semiconductor substrate 10 and a part of both the second opening 24B 1 as well as the second cavity part 25B 2on the second active region 10B of the semiconductor substrate 10 in the width direction. That is, the mask RM2 in which the side wall of the opening end is separated from a side wall between both side walls of both the second opening 24B 1 as well as the second cavity part 25B 2 separated in the width direction is formed on the second active region 10B. Like the mask RM1 of the above first embodiment, the mask RM2 is formed by forming a photosensitive resist film on the entire main surface of the semiconductor substrate 10 including the above first active region 10A and the second active region 10B, and then subjecting the photosensitive film to photosensitivity and development treatment or the like to form a predetermined pattern.

[0073] Next, the mask RM2 is used as an etching mask and, as shown in Fig. 19A and Fig. 19B, the width of the second cavity part 25B 2 extended by passing the first insulating film 21 through the space between the side wall of the mask RM2 and the side wall of the second opening 24B 1 of the second insulating film 22 is etched when the first opening 24A 1 is covered with the mask RM2 and a part of both the first opening 24B 1 as well as the second cavity part 25B 1 in the width direction is covered with the mask RM2. As the extension of the second cavity part 25B 1 In the above first embodiment, the extension of the second cavity part 25B 2performed by etching the first insulating film 21 by performing isotropic wet etching with less damage on the main surface of the semiconductor substrate 10, that is, the surface of the barrier layer 13. Moreover, the wet etching of the first insulating film 21 is performed under conditions where etching selectivity with respect to the second insulating film 22 is obtained, as in the above first embodiment.

[0074] According to this process, the second cavity part 25B 2 formed, which has a width W 2 which is wider than the width W 1 of the first cavity part 25A 1 The width of the second cavity part 25B 2 extending from the second opening 24B 1 extending towards the second main electrode 17B is wider than the width of the second cavity part 25B 2 formed, which extends from the second opening 24B 1towards a second main electrode 16B.

[0075] In addition, in this process, since the width of the second cavity part 25B 2 is extended, the first insulating film 21 between each of the pair of first main electrodes 16A and 17A and the first cavity part 25A 1 remain and the first insulating film 21 may be disposed between each of the pair of second main electrodes 16B and 17B and the second cavity part 25B 2 remain.

[0076] After the mask RM2 is removed, the next steps are Fig. 13A and Fig. 13B in the above first embodiment 1, and, as shown in Fig. 20A and Fig. 20B, in the first cavity part 25A 1 and the second cavity part 25B 2the third insulating film 26 is formed covering the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the surface of the barrier layer 13), respective side walls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 and covers the second insulating film 22.

[0077] In this process, the insulating layer 20, which includes the first insulating film 21, the second insulating film 22, and the third insulating film 26, is formed on the first active region 10A and the second active region 10B of the semiconductor substrate 10.

[0078] In addition, in this process, since respective side walls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 are covered with the third insulating film 26, the first gate opening 27A 1 with a narrower opening width than the first opening 24A1 formed and becomes the second gate opening 27B 1 with a narrower opening width than the second opening 24B 1 trained.

[0079] In addition, in this process, the first cavity part 25A 1 and the second cavity part 25B 2 surrounded by the third insulating film 26. Since the third insulating film 26 is formed with a nearly uniform film thickness, here in the first cavity part 25A 1 and the second cavity part 25B 2 , which are surrounded by the third insulating film 26, the width W 2 (see Fig. 16B) of the second cavity part 25B 2 greater than the width W 1 (see Fig. 16A) of the first cavity part 25A 1 .

[0080] Then, the same processes as in the above first embodiment are performed, the first gate electrode 31A and the second gate electrode 31B are formed, and thus the Fig. The first field effect transistor Q1 shown in Figure 16A is almost completed and will be used in the Fig. The second field effect transistor Q3 shown in Figure 16B is almost completed.

[0081] Thereafter, as in the above first embodiment, a wiring layer and other insulating layers are formed on the insulating layer 20, and thus the semiconductor device 1A according to the second embodiment is almost completed.

[0082] According to the method for manufacturing the semiconductor device 1A of the second embodiment, the same effects as in the method for manufacturing the semiconductor device 1 according to the first embodiment described above can be obtained. Furthermore, according to the method for manufacturing the semiconductor device 1A of the second embodiment, it is possible to form a bilaterally asymmetric second cavity part 25B. 2 in which the width of the second part 25B 2 -R wider than the width of the first part 25B 2 -L. The width of the second part 25B 2 -R of the second cavity part 25B 2 can be wider than the width of the second part 25A 1 -R of the first cavity part 25A 1 be made.

[0083] In addition, the asymmetric second cavity part 25B 2 with the same number of masks as in the first embodiment. (Example)<Konfiguration einer Halbleitervorrichtung>

[0084] A semiconductor device 1B according to an example has basically the same configuration as the semiconductor device 1 of the above first embodiment and includes a second field-effect transistor Q4 instead of the second field-effect transistor Q2 of the above first embodiment. That is, as shown in Fig. 21A and Fig. 21B, the semiconductor device 1B according to this example includes the first field effect transistor Q1 formed in the first active region 10A of the main surface of the semiconductor substrate 10 (see Fig. 21A) and the second field effect transistor Q4 formed in the second active region 10B of the main surface of the semiconductor substrate 10 (see Fig. 21B). As in Fig. 21B, the second field effect transistor Q4 contains, instead of the second cavity part 25B 1of the above second field effect transistor Q2 of the first embodiment, a second cavity part 25B 3 . The remaining configurations are the same as those in the above first embodiment.

[0085] Like the second cavity part 25B 1 of the above first embodiment, the second cavity part 25B 3 of the second field effect transistor Q4, viewed in plan view, is formed in an annular planar pattern, which covers the body part 31b 2 the second gate electrode 31B. As the second cavity part 25B 1 The above first embodiment therefore comprises, as shown in Fig. 21B, the second cavity part 25B 3 one on one side (left side) of the fuselage part 31b 2 the second gate electrode 31B positioned first part 25B 3 -L and one on the other side (right side) of the fuselage part 31b 2the second part 25B positioned on the second gate electrode 31B 3 -R in the direction of the gate length of the second gate electrode 31B. Unlike the second cavity part 25B 1 of the above first embodiment, here in this example, the second cavity part 25B 3 a bilaterally asymmetric configuration in which the width of the second part 25B 3 -R wider than the width of the first part 25B 3 -L. A third opening 27C provided in the insulating layer 20 1 is here with the second part 25B 3 -R of the second cavity part 25B 3 tied together.

[0086] The second cavity part 25B 3 is wider than the fuselage section 31b 2 the second gate electrode 31B and the second gate opening 27B 1 in the direction of the gate length (longitudinal direction) of the second gate electrode 31B. The width W 2 of the second cavity part 25B 3is wider here than the width W 1 of the first cavity part 25A 1 . That is, the second cavity part 25B 3 is wider than the first cavity part 25A 1 .

[0087] According to the semiconductor device 1B according to this example, the same effects as those of the semiconductor device 1A according to the second embodiment described above can be obtained.

[0088] Here, a wiring layer and other insulating layers are provided above the insulating layer 20; but in Fig. 21A and Fig. 21B, the wiring layer and other insulating films above the insulating layer 20 are not shown. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0089] Next, with reference to Fig. 22A to Fig. 24B, a method of manufacturing the semiconductor device 1B according to the above example is described. Fig. 22A, Fig. 23A and Fig. 24A illustrate processes for forming the first field effect transistor Q1 in the first active region 10A of the semiconductor substrate 10, and Fig. 22B, Fig. 23B and Fig. 24B illustrate processes for forming the second field effect transistor Q4 in the second active region 10B of the semiconductor substrate 10. The first field effect transistor Q1 and the second field effect transistor Q4 are formed by the same process.

[0090] First, the same processes as in Fig. 7A to Fig. 9B in the first embodiment are performed, and, as shown in Fig. 22A and Fig. 22B, the pair of first main electrodes 16A and 17A, the pair of second main electrodes 16B and 17B, the first insulating film 21 and the second insulating film 22, and the like are formed.

[0091] Next, as in Fig. 22A and Fig. 22B shows the first opening 24A 1 in the second insulating film 22 on the first active region 10A of the main surface of the semiconductor substrate 10 and the second opening 24B 1 and a third opening 24C 1 , which are adjacent to each other, are formed in the second insulating film 22 on the second active region 10B of the main surface of the semiconductor substrate 10. The first opening 24A 1 , the second opening 24B 1 and the third opening 24C 1 are formed by etching the second insulating film 22 using a well-known photolithography technique and a well-known high-directivity dry etching technique as an anisotropic etching technique as in the above first embodiment.

[0092] The first opening 24A 1is formed in plan view between the pair of first main electrodes 16A and 17A and is formed with a long plane pattern in the longitudinal direction of the pair of first main electrodes 16A and 17A. The second opening 24B 1 and the third opening 24C 1 are formed in plan view between the pair of second main electrodes 16B and 17B and are formed with a long plane pattern in the longitudinal direction of the pair of second main electrodes 16B and 17B.

[0093] As in Fig. 23A and Fig. 23B, next the first cavity part 25A 1 which is wider than the first opening 24A 1 is formed by the first insulating film 21 on the first active region 10A of the semiconductor substrate 10 through the first opening 24A 1 is etched, and the second cavity part 25B 3 which is wider than the first cavity part 25A 1is formed by the first insulating film 21 on the second active region 10B of the semiconductor substrate 10 through the second opening 24B 1 and the third opening 24C 1 is etched.

[0094] The first cavity part 24A 1 and the second cavity part 25B 3 are formed by etching the first insulating film 21 by performing isotropic wet etching with less damage on the main surface of the semiconductor substrate 10, that is, the surface of the barrier layer 13. The wet etching of the first insulating film 21 is performed under conditions where etching selectivity with respect to the second insulating film 22 is obtained, as in the above first embodiment.

[0095] Since in this process the first insulating film 21 on the second active region 10B is etched with an etching solution passing through two openings (the second opening 24B 1 and the third opening 24C 1), the second cavity part 25B 3 with width W 2 (see Fig. 21B) which is wider than the width W 1 (see Fig. 21A) of the first cavity part 25A 1 formed with an etching solution supplied through an opening. Since the third opening 24C 1 in plan view between the second opening 24B 1 and the other second main electrode 17B, the width of the second cavity part 25B 3 extending from the second opening 24B 1 extending towards the other second main electrode 17B, is wider than the width of the second cavity 25B 3 extending from the second opening 24B 1 to a second main electrode 16B.

[0096] Next, the same processes as in Fig. 13A and Fig. 13B in the above first embodiment 1, and, as shown in Fig. 24A and Fig. 24B, in the first cavity part 25A 1 and the second cavity part 25B 3 the third insulating film 26 is formed covering the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the surface of the barrier layer 13), respective side walls in the first opening 24A 1 , the second opening 24B 1 and the third opening 24C 1 of the second insulating film 22 and covers the second insulating film 22.

[0097] In this process, the insulating layer 20 comprising the first insulating film 21, the second insulating film 22 and the third insulating film 26 is formed on the first active region 10A and the second active region 10B of the semiconductor substrate 10.

[0098] In addition, in this process, since respective side walls in the first opening 24A 1 and a second opening 24B 1 of the second insulating film 22 are covered with the third insulating film 26, the first gate opening 27A 1 with a narrower opening width than the first opening 24A 1 formed and become a second gate opening 27B 2 with a narrower opening width than the second opening 24B 1 and the third opening 27C 1 with a narrower opening width than the third opening 24C 1 trained.

[0099] In addition, in this process, the first cavity part 25A 1 and the second cavity part 25B 3 surrounded by the third insulating film 26. Since the third insulating film 26 is formed with a nearly uniform film thickness, here in the first cavity part 25A 1 and the second cavity part 25B 3, which are surrounded by the third insulating film 26, the width W 2 (see Fig. 21B) of the second cavity part 25B 3 wider than the width W 1 (see Fig. 21A) of the first cavity part 25A 1 .

[0100] Thereafter, the same processes as in the above first embodiment are performed, the first gate electrode 31A and the second gate electrode 31B are formed, and thus the Fig. The first field effect transistor Q1 shown in Figure 21A is almost completed and will be Fig. The second field effect transistor Q4 shown in Figure 21B is almost completed.

[0101] Thereafter, as in the above first embodiment, a wiring layer and other insulating layers are formed on the insulating layer 20, and thus the semiconductor device 1 according to the second embodiment is almost completed.

[0102] According to the method for manufacturing the semiconductor device 1B of this example, the same effects as in the method for manufacturing a semiconductor device according to the first embodiment described above can be obtained.

[0103] Furthermore, according to the method for manufacturing the semiconductor device 1B of this example, it is possible to form the bilaterally asymmetric second cavity part 25B 3 in which the width of the second part 25B 3 -R wider than the width of the first part 25B 3 -L is.

[0104] Since the second cavity part 25B 3 which is wider than the first cavity part 25A 1can be formed without using an etching mask, it is also possible to reduce the number of production processes compared with the above first embodiment and second embodiment, and it is possible to reduce the production cost of the semiconductor device 1B.

[0105] In the example above, two openings (the second opening 24B 1 and the second opening 24C 1 ) is formed in the second insulating film 22 on the second active region 10B; however, three or more openings may be formed in the second insulating film 22 on the second active region 10B. A plurality of openings are arranged at predetermined intervals in the arrangement direction of the pair of second main electrodes 17A and 17B. (Fourth Embodiment)<Konfiguration einer Halbleitervorrichtung>

[0106] As in Fig. 25A and Fig. 25B, a semiconductor device 1C according to a fourth embodiment includes the semiconductor substrate 10, a first insulating layer 20A provided on the first active region 10A of the main surface of the semiconductor substrate 10, and a second insulating layer 20B provided on the second active region 10B different from the first active region 10A of the main surface of the semiconductor substrate 10. Furthermore, the semiconductor device 1C includes a first field-effect transistor Q5 formed in the first active region 10A of the main surface of the semiconductor substrate 10 and a second field-effect transistor Q6 formed in the second active region 10B of the main surface of the semiconductor substrate 10. The first field-effect transistor Q5 is a high-frequency switch of the type described in Fig. 1. The second field effect transistor Q6 is a high-frequency power amplifier of the Fig. 1 is an element forming the high-frequency power amplifier part PA.

[0107] As in Fig. 25A, the first insulating layer 20A includes a pair of first etching stopper parts 21A 1 and 21A 2 , which are arranged on the first active region 10A of the main surface of the semiconductor substrate 10, the second insulating film 22 which is arranged on the pair of first etching stopper parts 21A 1 and 21A 2 and the third insulating film 26 provided on the second insulating film 22.

[0108] As in Fig. 25B, the second insulating layer 20B includes a pair of second etching stopper parts 21B 1 and 21B 2 provided on the second active region 10B of the main surface of the semiconductor substrate 10, the second insulating film 22 provided on the pair of second etching stopper parts 21B 1 and 21B 2and the third insulating film 26 provided on the second insulating film 22.

[0109] The first insulating film 21 (see Fig. 28A and Fig. 28B) is made of, for example, an Al 3 O 2 -film formed. The pair of first etching stopper parts 21A 1 and 21A 2 and the pair of second etching stopper parts 21B 1 and 21B 2 are formed from, for example, a crystallization region in which a heat treatment is carried out on the first insulating film 21 (see Fig. 28A and Fig. 28B) to increase the chemical resistance to an etching solution during wet etching. The second insulating film 22 is made of, for example, SiO 2 -Film with high etching selectivity with respect to the first insulating film 21. The first insulating film 21 is formed with, for example, a film thickness of about 50 nm. The pair of first etching stopper parts 21A 1 and 21A2 , the pair of second etching stopper parts 21B 1 and 21B 2 and the second insulating film 22 are formed with, for example, a film thickness of about 50 nm.

[0110] As in Fig. 25A, the third insulating film 26 is formed to sandwich the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the barrier layer 13) in a first cavity part 25A 2 which will be described below. In addition, as described in Fig. 25B, the third insulating film 26 is formed to sandwich the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the barrier layer 13) in a second cavity part 25B 4 which will be described below.

[0111] As in Fig. As shown in Figure 25A, the first field-effect transistor Q5 includes the buffer layer 11a, the channel layer 12, the barrier layer 13, and the two-dimensional electron gas layer 14. Furthermore, the first field-effect transistor Q5 includes the pair of first main electrodes 16A and 17A, which are separated from each other and provided on the first active region 10A of the main surface of the semiconductor substrate 10 and function as the source electrode and the drain electrode, and the first hollow portion 25A. 2 , which is provided in the first insulating layer 20A between the pair of first main electrodes 16A and 17A. In addition, the first field effect transistor Q5 includes the first gate electrode 31A, which covers the head portion 31a positioned on the first insulating layer 20A. 1 and the fuselage section 31a 2 which is from the head part 31a 1 from the first insulating layer 20A and towards the first cavity part 25A 2protrudes, and in which the head part 31a 1 wider than the fuselage section 31a 2 That is, the first field-effect transistor Q5 of the first embodiment is a GaN-based hetero-FET.

[0112] The first gate electrode 31A has a long shape when viewed from above, and the gate width is longer than the gate length. The first gate electrode 31A extends over the first active region 10A and the inactive region 15. The head portion 31a is formed in the first gate electrode 31A. 1 positioned on the third insulating film 26, and the one with the head part 31a 1 integrated fuselage section 31a 2 is in the direction of the first cavity part 25A 2 through the first gate opening 27A provided in the first insulating layer 20A 1 before.

[0113] The pair of first main electrodes 16A and 17A with the gate electrode 31A therebetween are separated from each other in the direction of the gate length of the first gate electrode 31A. Here, the pair of first main electrodes 16A and 17A extend across the first active region 10A and the inactive region 15A in the direction of the gate width of the first gate electrode 31A.

[0114] The plane pattern of the first cavity part 25A 2 is a circular plane pattern viewed in plan view, which forms the fuselage part 31a 2 the first gate electrode 31A. As shown in Fig. 25A, the first cavity part 25A therefore comprises 2 one on one side (left side) of the fuselage part 31a 2 positioned first part 25A 2 -L and one on the other side (right side) of the fuselage part 31a 2 positioned second part 25A 2-R in the direction of the gate length of the first gate electrode 31A. In the fourth embodiment, the first cavity part 25A 2 a bilaterally symmetrical configuration in which the first part 25A 2 -L and the second part 25A 2 -R have substantially the same width. In the direction of the gate length (longitudinal direction) of the first gate electrode 31A, the first cavity part 25A 2 wider than the fuselage section 31a 2 the first gate electrode 31A and the first gate opening 27A 1 .

[0115] As in Fig. 25B, the second field-effect transistor Q6 includes the buffer layer 11a, the channel layer 12, the barrier layer 13, and the two-dimensional electron gas layer 14. Furthermore, the second field-effect transistor Q6 includes the pair of second main electrodes 16B and 17B, which are separated from each other and provided on the second active region 10B of the main surface of the semiconductor substrate 10, and in which the separation distance L 2 longer than the separation distance L 1 between the pair of first main electrodes 16A and 17A of the first field effect transistor Q5 (see Fig. 25A) and the second cavity part 25B 4, which is provided in the insulating layer 20B between the pair of second main electrodes 16B and 17B. The pair of second main electrodes 16B and 17B function as a source electrode and a drain electrode. In addition, the second field-effect transistor Q6 includes the second gate electrode 31B, which contacts the head portion 31b positioned on the second insulating layer 20B. 1 and the fuselage section 31b 2 which is from the head part 31b 1 from the second insulating layer 20B and towards the second cavity part 25B 4 protrudes, and in which the head part 31b 1 wider than the fuselage section 31b 2 That is, the second field-effect transistor Q6 of the fourth embodiment is also a GaN-based hetero-FET, like the first field-effect transistor Q5.

[0116] The second gate electrode 31B has a long shape when viewed from above, and the gate width is longer than the gate length. The second gate electrode 31B extends over the second active region 10B and the inactive region 15. The head portion 31b is formed in the second gate electrode 31B. 1 positioned on the third insulating film 26, and the one with the head part 31b 1 integrated fuselage section 31b 2 through the second gate opening 27B provided in the second insulating layer 20B 1 towards the second cavity part 25B 4 before.

[0117] The pair of second main electrodes 16B and 17B with the second gate electrode 31B therebetween are separated from each other in the direction of the gate length of the second gate electrode 31B. Here, the pair of second main electrodes 16B and 17B extends across the second active region 10B and the inactive region 15 in the direction of the gate width of the second gate electrode 31B.

[0118] The plane pattern of the second cavity 25B 4 is viewed from above a fuselage part 31b 2 the second gate electrode 31B surrounding a circular plane pattern. Like the first cavity part 25A 2 therefore includes, as in Fig. 25B, the second cavity part 25B 4 one on one side (left side) of the fuselage part 31b 2 positioned first part 25B 4- -L and one on the other side (right side) of the fuselage part 31b 2 positioned second part 25B 4 -R in the direction of the gate length of the second gate electrode 31B. In the fourth embodiment, although not limited thereto, the second cavity part 25B 4 a bilaterally symmetric configuration in which the first part 25B 4 -L and the second part 25B 4 -R have essentially the same width.

[0119] In the direction of the gate length (longitudinal direction) of the second gate electrode 31B, the second cavity 25B 4 wider than the fuselage section 31b 2 the second gate electrode 31B and the second gate opening 27B 1 . As in Fig. 25B and Fig. 25A, here the width W 2 of the second cavity part 25B 4 wider than the width W 1 of the first cavity part 25A 2 . That is, the second cavity part 25B 4 is wider than the first cavity part 25A 2 .

[0120] As in Fig. 25A, the upper part of the first cavity part 25A 2 covered with the second insulating film 22 and are the side parts of the first cavity 25A 2 in the width direction with the pair of first etching stopper parts 21A 1 and 21A 2 covered. As in Fig. 25B, the upper part of the second cavity part 25B 4 covered with the second insulating film 22 and are the side parts of the second cavity part 25B 4 in the width direction with the pair of second etching stopper parts 21B 1 and 21B 2 covered.

[0121] According to the semiconductor device 1C of the fourth embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment described above can be obtained.

[0122] A wiring layer and other insulating layers are provided above the insulating layer 20; but in Fig. 25A and Fig. 25B, the wiring layer and other insulating films above the insulating layer 20 are not shown. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0123] Next, with reference to Fig. 26A to Fig. 31B, a method of manufacturing the semiconductor device 1C according to the fourth embodiment is described. Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A, Fig. 30A and Fig. 31A show processes for forming the first field effect transistor Q5 in the first active region 10A of the semiconductor substrate 10, and Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B and Fig. 31B show processes for forming the second field effect transistor Q6 in the second active region 10B of the semiconductor substrate 10. The first field effect transistor Q5 and the second field effect transistor Q6 are formed by the same process.

[0124] First, the same processes as in Fig. 7A to Fig. 9B in the first embodiment, and are carried out as shown in Fig. 26A and Fig. 26B, the pair of first main electrodes 16A and 17A, the pair of second main electrodes 16B and 17B, the first insulating film 21 and the second insulating film 22 and the like are formed.

[0125] Next, the second insulating film 22 and the first insulating film 21 are successively patterned, and, as shown in Fig. 27A, the second insulating film 22 and the first insulating film 21 having a pattern in which ends (side walls) in the width direction are terminated on the pair of first main electrodes 16A and 17A are formed on the first active region 10A, and are, as shown in Fig. 27B, the second insulating film 22 and the first insulating film 21 having a pattern in which ends in the width direction are terminated on the pair of second main electrodes 16B and 17B are formed on the second active region 10B. The second insulating film 22 and the first insulating film 21 are patterned using a well-known photolithography technique and an anisotropic dry etching technique.

[0126] In this process, since the separation distance L 2 between the pair of second main electrodes 16B and 17B (see Fig. 25B) longer than the separation distance L 1 between the pair of first main electrodes 16A and 17A (see Fig. 25A) is, as in Fig. 27A and Fig. 27B, the width of the first insulating film 21 and the second insulating film 22 on the second active region 10B is longer than the width of both the first insulating film 21 and the second insulating film 22 on the first active region 10a.

[0127] Next, a heat treatment is performed on the first insulating film 21, and, as shown in Fig. 28A and Fig. 28B, the pair of first etching stopper parts 21A 1 and 21A 2 with a higher etching selectivity than the first insulating film 21 at one end side and the other end side of the first insulating film 21 on the first active region 10A in the width direction and the pair of second etching stopper parts 21B 1 and 21B 2 which have a higher etching selectivity than the first insulating film 21 and between which the separation distance is longer than the separation distance between the pair of first etching stopper parts 21A 1 and 21A2 is formed on one end side and the other end side of the first insulating film 21 on the second active region 10B in the width direction.

[0128] In this process, since the upper surface of the Al 2 O 3 -film is covered with the second insulating film 22, a crystallization region in which chemical resistance is strong during dry etching is created from the end to the inside according to a heat treatment. Since this crystallization region has high etching selectivity with respect to the first insulating film 21, in which no crystallization region is created, it functions as the first etching stopper parts 21A. 1 and 21A 2 and the second etching stopper parts 21B 1 and 21B 2 when the first insulating film 21 is wet-etched to form a cavity part.

[0129] Next, the same processes as in Fig. 10A and Fig. 10B in the above first embodiment, and, as shown in Fig. 29A and Fig. 29B, the first opening 24A 1 in the second insulating film 22 on the first active region 10A of the semiconductor substrate 10 and the second opening 24B 1 formed in the second insulating film 22 on the second active region 10B of the main surface of the semiconductor substrate 10. The first opening 24A 1 is, for example, at the middle position between the pair of first etching stopper parts 21A in plan view 1 and 21A 2 formed. In addition, the second opening 24B 1 in plan view, for example, at the middle position between the pair of second etching stopper parts 21B 1 and 21B 2 trained.

[0130] As in Fig. 30A and Fig. 30B, next, the first cavity part 25A 2which is wider than the first opening 24A 1 is formed by the first insulating film 21 on the first active region 10A of the semiconductor substrate 10 through the first opening 24A 1 is etched, and the second cavity part 25B 4 which is wider than the first cavity part 25A 2 is formed by the first insulating film 21 on the second active region 10B of the semiconductor substrate 10 through the second opening 24B 1 etched. As in the above first embodiment, the etching of the first insulating film 21 is performed by performing isotropic wet etching with low damage on the main surface of the semiconductor substrate (the surface of the barrier layer 13). The wet etching of the first insulating film 21 is performed under conditions where etching selectivity with respect to the second insulating film 22, the pair of first etching stopper parts 21A 1 and 21A 2and the pair of second etching stopper parts 21B 1 and 21B 2 is received.

[0131] In this process, it is because the pair of first etching stopper parts 21A 1 and 21A 2 has a higher etching selectivity with respect to the first insulating film 21, it is possible to prevent excessive expansion of the first cavity 25A 2 in the width direction (lateral direction). Since the pair of second etching stopper parts 21B 1 and 21B 2 has a higher etching selectivity than the first insulating film 21, it is also possible to prevent excessive expansion of the second cavity part 25B 4 in the width direction (lateral direction). That is, the width of the first cavity part 25A 2 can be used according to the pair of first etching stopper parts 21A 1 and 21A 2 controlled and the width of the second cavity part 25B 4 can be used according to the pair of second etching stopper parts 21B1 and 21B 2 be controlled.

[0132] Next, the same processes as in Fig. 14A and Fig. 14B in the above first embodiment 1, and, as shown in Fig. 31A and Fig. 31B, in the first cavity part 25A 2 and in the second cavity part 25B 4 the third insulating film 26 is formed covering the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the surface of the barrier layer 13), respective side walls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 and covers the second insulating film 22.

[0133] In this process, the first insulating layer 20A, which has a pair of first etching stopper parts 21A 1 and 21A 2, the second insulating film 22 and the third insulating film 26 is formed on the first active region 10A of the main surface of the semiconductor substrate 10, and the second insulating layer 20B, which includes a pair of etching stopper parts 21B 1 and 21B 2 , the second insulating film 22 and the third insulating film 26, is formed on the second active region 10B of the main surface of the semiconductor substrate 10.

[0134] In addition, in this process, since the respective side walls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 are covered with the third insulating film 26, the first gate opening 27A 1 with a narrower opening width than the first opening 24A 1 formed and becomes the second gate opening 27B 1 with a narrower opening width than the second opening 24B 1 formed. In addition, in this process, the first cavity part 25A2 and the second cavity part 25B 4 surrounded by the third insulating film 26. Since the third insulating film 26 is formed here with a nearly uniform film thickness, in the first cavity part 25A 2 and the second cavity part 25B 4 , which are surrounded by the third insulating film 26, the width W 2 (see Fig. 25B) of the second cavity part 25B 4 wider than the width W 1 (see Fig. 25A) of the first cavity part 25A 2 .

[0135] Thereafter, the same processes as those in the above first embodiment are performed, the first gate electrode 31A and the second gate electrode 31B are formed, and thus the Fig. The first field effect transistor Q5 shown in Figure 25A is almost completed and will be Fig. The second field effect transistor Q6 shown in Figure 25B is almost completed.

[0136] Thereafter, as in the above first embodiment, a wiring layer and other insulating layers are formed on the first insulating layer 20A and the second insulating layer 20B, and thus the semiconductor device 1C according to the fourth embodiment is almost completed.

[0137] According to the method for manufacturing the semiconductor device 1C of the fourth embodiment, as in the method for manufacturing the semiconductor device 1 according to the above first embodiment, the first cavity part 25A 2 and the second cavity part 25B 4 which is wider than the first cavity part 25A 2 is formed by the same process.

[0138] Since the second cavity part 25B 4 which is wider than the first cavity part 25A 2can be formed without using an etching mask, it is also possible to reduce the number of production steps compared with the above first embodiment and second embodiment, and it is possible to reduce production costs of the semiconductor device 1C.

[0139] Since the width of the first cavity part 25A 2 according to the separation distance between the pair of first etching stopper parts 21A 1 and 21A 2 can be controlled and the width of the second cavity part 25B 4 according to the separation distance between the pair of second etching stopper parts 21B 1 and 21B 2 can be controlled, it is also possible to adjust the widths of the first cavity part 25A 2 and the second cavity part 25B 4 to be freely determined.

[0140] In the fourth embodiment, a case has been described here in which the first cavity part 25A 2and the second cavity part 25B 4 are bilaterally symmetrical. However, the present examples are not limited to the bilaterally symmetrical first cavity part 25A 2 and second cavity part 25B 4 limited. If the first opening 24A 1 , which toward any one of the pair of first etching stopper parts 21A 1 and 21A 2 eccentric (prestressed), is formed in the second insulating film 22, for example, a bilaterally asymmetric first cavity part 25A 2 When the second opening 24B 1 which are directed toward any one of the pair of second etching stopper parts 21B 1 and 21B 2 eccentric, is formed in the second insulating film 22, similarly, the bilaterally asymmetric second cavity part 25B 1 be trained. (Fifth embodiment)<Konfiguration einer Halbleitervorrichtung>

[0141] As in Fig. 32A and Fig. 32B, a semiconductor device 1D according to a fifth embodiment includes the semiconductor substrate 10 and the insulating layer 20 provided on the first active region 10A and the second active region 10B of the main surface of the semiconductor substrate 10. Furthermore, the semiconductor device 1D includes a first field-effect transistor Q7 formed in the first active region 10A of the main surface of the semiconductor substrate 10 and a second field-effect transistor Q8 formed in the second active region 10B different from the first active region 10A of the main surface of the semiconductor substrate 10. The first field-effect transistor Q7 is a high-frequency switch of the type shown in Fig. 1. The second field effect transistor Q8 is a high-frequency power amplifier of the Fig. 1 is an element forming the high-frequency power amplifier part PA.

[0142] The insulating layer 20 includes the first insulating film 21 provided on the main surface of the semiconductor substrate 10, the second insulating film 22 provided on the first insulating film 21, and the third insulating film 26 provided on the second insulating film 22. The first insulating film 21 is made of, for example, Al 3 O 2 -film. The second insulating film 22 is made of, for example, a SiO 2 -Film with high etching selectivity with respect to the first insulating film 21. The first insulating film 21 is formed with, for example, a film thickness of about 50 nm, and the second insulating film 22 is formed with, for example, a film thickness of about 50 nm.

[0143] The third insulating film 26 is formed to sandwich the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the barrier layer 13) in a first cavity part 25A 3and a second cavity part 25B 5 covered, which will be described below.

[0144] As in Fig. 32A, the first field-effect transistor Q7 includes the buffer layer 11a, the channel layer 12, the barrier layer 13, and the two-dimensional electron gas layer 14. Furthermore, the first field-effect transistor Q7 includes the pair of first main electrodes 16A and 17A, which are separated from each other and provided on the first active region 10A of the main surface of the semiconductor substrate 10 and function as a source electrode and a drain electrode, and the first cavity portion 25A. 3 , which is provided in the first insulating layer 20A between the pair of first main electrodes 16A and 17A. In addition, the first field effect transistor Q7 includes the first gate electrode 31A, which covers the head portion 31a positioned on the insulating layer 20A. 1 and the fuselage section 31a 2 which is from the head part 31a 1from the insulating layer 20 and towards the first cavity part 25A 3 protrudes, and in which the head part 31a 1 wider than the fuselage section 31a 2 That is, the first field-effect transistor Q7 of the first embodiment is a GaN-based hetero-FET.

[0145] The first gate electrode 31A has a long shape when viewed from above, and the gate width is longer than the gate length. The first gate electrode 31A extends over the first active region 10A and the inactive region 15. The head portion 31a is formed in the first gate electrode 31A. 1 positioned on the third insulating film 26, and the one with the head part 31a 1 integrated fuselage section 31a 2 protrudes through the first gate opening 27A provided in the insulating layer 20 1 towards the first cavity part 25A 3 before.

[0146] The pair of first main electrodes 16A and 17A with the first gate electrode 31A therebetween are separated from each other in the direction of the gate length of the first gate electrode 31A. Here, the pair of first main electrodes 16A and 17A extends across the first active region 10A and the inactive region 15A in the direction of the gate width of the first gate electrode 31A.

[0147] The plane direction of the first cavity part 25A 3 is viewed from above a fuselage part 31a 2 the first gate electrode 31A surrounding circular plane pattern. As shown in Fig. 32A, the first cavity portion 25A therefore comprises 3 one on one side (left side) of the fuselage part 31a 2 positioned first part 25A 3 -L and one on the other side (right side) of the fuselage part 31a 2 positioned second part 25A 3-R in the direction of the gate length of the first gate electrode 31A. In the fifth embodiment, the first cavity part 25A 3 a bilaterally symmetric configuration in which the first part 25A 3 -L and the second part 25A 3 -R have substantially the same width. In the direction of the gate length (short direction) of the first gate electrode 31A, the first cavity part 25A 3 wider than the fuselage section 31a 2 the first gate electrode 31A and the gate opening 27A 1 .

[0148] As in Fig. 32B, the second field-effect transistor Q8 includes the buffer layer 11a, the channel layer 12, the barrier layer 13, and the two-dimensional electron gas layer 14. Furthermore, the second field-effect transistor Q8 includes a pair of second main electrodes 16B and 17B, which are separated from each other and provided on the second active region 10B of the main surface of the semiconductor substrate 10, and in which the separation distance L 2 longer than the separation distance L 1 (see Fig. 32A) between the pair of first main electrodes 16A and 17A of the first field effect transistor Q7, and the second cavity part 25B 5, which is provided in the insulating layer 20 between the pair of second main electrodes 16B and 17B. The pair of second main electrodes 16B and 17B function as a source electrode and a drain electrode. In addition, the second field-effect transistor Q8 includes the second gate electrode 31B, which supports the head portion 31b positioned on the insulating layer 20. 1 and the fuselage section 31b 2 which is from the head part 31b 1 from the second insulating layer 20B and towards the second cavity part 25B 5 protrudes, and in which the head part 31b 1 wider than the fuselage section 31b 2 That is, the second field-effect transistor Q8 of the fifth embodiment is also a GaN-based hetero-FET like the first field-effect transistor Q7.

[0149] The second gate electrode 31B has a long shape when viewed from above, and the gate width is longer than the gate length. The second gate electrode 31B extends over the second active region 10B and the inactive region 15. The head portion 31b is formed in the second gate electrode 31B. 1 positioned on the third insulating film 26, and the one with the head part 31b 1 integrated fuselage section 31b 2 protrudes through the second gate opening 27B provided in the second insulating layer 20B 1 towards the second cavity part 25B 5 before.

[0150] The pair of second main electrodes 16B and 17B with the second gate electrode 31B therebetween are separated from each other in the gate length direction (the short direction and the width direction) of the second gate electrode 31B. Here, the pair of second main electrodes 16B and 17B extend across the second active region 10B and the inactive region 15 in the gate width direction (the longitudinal direction and the length direction) of the second gate electrode 31B.

[0151] The plane pattern of the second cavity part 25B 5 is viewed from above a fuselage part 31b 2 the second gate electrode 31B surrounding a circular plane pattern. Like the first cavity part 25A 3 therefore includes, as in Fig. 32B, the second cavity part 25B 5 one on one side (left side) of the fuselage part 31b 2 positioned first part 25B 5-L and one on the other side (right side) of the fuselage part 31b 2 positioned second part 25B 5 -R in the direction of the gate length of the second gate electrode 31B. In contrast to the second cavity part 25B 1 the above first embodiment, here in the fifth embodiment, the second cavity part 25B 5 a bilaterally asymmetric configuration in which the width of the second part 25B 5 -R wider than the width of the first part 25B 5 -L is.

[0152] In the direction of the gate length (longitudinal direction) of the second gate electrode 31B, the second cavity part 25B 5 wider than the fuselage section 31b 2 the second gate electrode 31B and the second gate opening 27B 1 . As in Fig. 32B, here the width W 2 of the second cavity part 25B 5 wider than the width W 1 of the first cavity part 25A3 , which in Fig. 32A. That is, the second cavity part 25B 5 is wider than the first cavity part 25A 3 .

[0153] As in Fig. 32A, a first stopper opening 21A 3 in which the second insulating film 22 is embedded, between a first main electrode 16A and the first cavity part 25A 3 between the pair of first main electrodes 16A and 17A. The first stopper opening 21A 3 extends in the longitudinal direction of a first main electrode 16A. In addition, a first stopper opening 21A 4 in which the second insulating film 22 is embedded, between the other first main electrode 17A and the first cavity part 25A 3 The first stopper opening 21A 2 extends in the longitudinal direction of the other first main electrode 17A.

[0154] As in Fig. 32B, a second stopper opening 21B 3 in which the second insulating film 22 is embedded, between a second main electrode 16B and the second cavity part 25B 5 between the pair of second main electrodes 16B and 17B. The second stopper opening 21B 3 extends in the longitudinal direction of a second main electrode 16B.

[0155] Since the inside of each of the pair of first stopper openings 21A 3 and 21A 4 positioned second insulating film 22 (see Fig. 32A) is formed of an insulating film having a higher etching rate than the first insulating film 21, it functions as an etching stopper when the first insulating film 21 is etched to form the first cavity part 25A 3 Since the inside of the second stopper opening 21B 3positioned second insulating film 22 is formed of an insulating film having a higher etching rate than the first insulating film 21, it functions as an etching stopper when the first insulating film 21 is etched to form the second cavity part 25B 5 to train.

[0156] According to the semiconductor device 1D of the fifth embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment described above can be obtained.

[0157] A wiring layer and other insulating layers are formed here above the insulating layer 20; but in Fig. 32A and Fig. 32B, the wiring layer and other insulating layers above the insulating layer 20 are not shown. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0158] Next, with reference to Fig. 33A to Fig. 37B, a method of manufacturing the semiconductor device 1D according to the fifth embodiment is described. Fig. 33A, Fig. 34A, Fig. 35A, Fig. 36A and Fig. 37A show processes for forming the first field effect transistor Q7 in the first active region 10A of the semiconductor substrate 10. Fig. 33B, Fig. 34B, Fig. 35B, Fig. 36B and Fig. 37B show processes for forming the second field effect transistor Q8 in the second active region 10B of the semiconductor substrate 10. The first field effect transistor Q7 and the second field effect transistor Q8 are formed by the same process.

[0159] First, the same processes as in Fig. 7A to Fig. 9B in the first embodiment, and, as shown in Fig. 33A and Fig. 33B, the pair of first main electrodes 16A and 17A, the pair of second main electrodes 16B and 17B, the first insulating film 21, and the like are formed.

[0160] As in Fig. 33A and Fig. 33B, next, the pair of first stopper openings 21A 3 and 21A 4 which are separated from each other, in the first insulating film 21 on the first active region 10A of the main surface of the semiconductor substrate 10 and the second stopper opening 21B 3 formed in the first insulating film 21 on the second active region 10B of the main surface of the semiconductor substrate 10. The pair of first stopper openings 21A 3 and 21A 4 and the second stopper opening 21B 3 are formed using a well-known photolithography technique and an anisotropic dry etching technique. The pair of first stopper openings 21A 3 and 21A 4is arranged between the pair of first main electrodes 16A and 17A. A first stopper opening 21A 3 extends here along a first main electrode 16A, and the other first stopper opening 21A 4 extends along the other first main electrode 17A. The second stopper opening 21B 3 is arranged between the pair of second main electrodes 16B and 17B. The second stopper opening 21B 3 is eccentric here toward any one of the pair of second main electrodes 16B and 17B and in the fifth embodiment toward a second main electrode 16B and extends along a second main electrode 16B.

[0161] Next, as in Fig. 34A and Fig. 34B, the second insulating film 22 is formed on the first active region 10A and the second active region 10B of the main surface of the semiconductor substrate 10 with the first insulating film 21 therebetween to insulate the inside of the pair of first stopper openings 21A 3 and 21A 4 and the inside of the second stopper opening 21B 3 The second insulating film 22 is formed from an insulating film having a high etching selectivity with respect to the first insulating film 21. For example, an Al 2 O 3 -film formed. A SiO 2 film is then formed as the second insulating film 22 by a CVD method.

[0162] As in Fig. 35A and Fig. 35B, the first opening 24A 1 which, in plan view, is located between the pair of first stopper openings 21A 3 and 21A 4positioned in the second insulating film 22 on the first active region 10A of the main surface of the semiconductor substrate 10 and is formed in the second stopper opening 21B 3 adjacent second opening 24B 1 formed in the second insulating film 22 on the second active region 10B of the main surface of the semiconductor substrate 10. The first opening 24A 1 and the second opening 24B 1 are formed by etching the second insulating film 22 using a well-known photolithography technique and a well-known high-directivity dry etching technique.

[0163] The first opening 24A 1 is in plan view at the middle position between the pair of first main electrodes 16A and 17A, in other words the pair of first stopper openings 21A 3 and 21A 4, and formed with a long plane pattern in the longitudinal direction of the pair of first main electrodes 16A and 17A. The second opening 24B 1 is eccentrically positioned in the direction of the second stopper opening 21B 3 between the pair of second main electrodes 16B and 17B, in other words between the second stopper opening 21B 3 and the other second main electrode 17B, and formed with a long plane pattern in the longitudinal direction of the pair of second main electrodes 16B and 17B.

[0164] As in Fig. 36A and Fig. 36B, next, the first cavity part 24A 3 which is wider than the first opening 24A 1 is formed by the first insulating film 21 on the first active region 10A of the semiconductor substrate 10 through the first opening 24A 1 is etched, and the second cavity part 25B 5which is wider than the first cavity part 25A 3 is formed by the first insulating film 21 on the second active region 10B of the semiconductor substrate 10 through the second opening 24B 1 is etched.

[0165] The first cavity part 25A 3 and the second cavity part 25B 5 are formed by etching the first insulating film 21 by performing isotropic wet etching with less damage on the first main surface of the semiconductor substrate 10, that is, the surface of the barrier layer 13. The wet etching of the first insulating film 21 is performed under conditions where etching selectivity with respect to the second insulating film 22 is obtained, as in the above first embodiment.

[0166] In this process, since the second insulating film 22 having a high etching selectivity with respect to the first insulating film 21 is formed forward in the direction in which the first cavity part 25A 3 extends, it is possible to prevent excessive expansion of the first cavity part 25A 3 in the width direction (lateral direction). Since the second insulating film 22 with a high etching selectivity with respect to the first insulating film 21 is provided forward in the direction in which the second cavity part 25B 5 extends, it is also possible to prevent excessive expansion of the second cavity part 25B 5 in the width direction (lateral direction). That is, the width of the first cavity part 25A 3 can be controlled according to the second insulating film 22 inserted into each of the pair of first stopper openings 21A 3 and 21A 4embedded, and the width of the second cavity part 25B 5 can be adjusted according to the second insulating film 22 inserted into the second stopper opening 21B 3 embedded, can be controlled.

[0167] Next, the same processes as in Fig. 14A and Fig. 14B in the above first embodiment 1, and, as shown in Fig. 37A and Fig. 37B, the third insulating film 26 is formed which covers the first insulating film 21, the second insulating film 22 and the main surface of the semiconductor substrate 10 (the surface of the barrier layer 13) in the first cavity part 25A 3 and the second cavity part 25B 5 covered, respective side walls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 and covers the second insulating film 22.

[0168] In this process, the insulating layer 20 comprising the first insulating film 21, the second insulating film 22 and the third insulating film 26 is formed on the first active region 10A and the second active region 10B of the semiconductor substrate 10.

[0169] In addition, in this process, since respective side walls in the first opening 24A 1 and the second opening 24B 1 of the second insulating film 22 are covered with the third insulating film 26, the first gate opening 27A 1 with a narrower opening width than the first opening 24A 1 formed and becomes the second gate opening 27B 1 with a narrower opening width than the second opening 24B 1 formed. In addition, in this process, the first cavity part 25A 3 and the second cavity part 25B 5surrounded by the third insulating film 26. Since the third insulating film 26 is formed with a nearly uniform film thickness, here in the first cavity part 25A 3 and the second cavity part 25B 5 , which are surrounded by the third insulating film 26, the width W 2 (see Fig. 37B) of the second cavity part 25B 5 wider than the width W 1 (see

[0170] Fig. 37A) of the first cavity part 25A 3 .

[0171] Thereafter, the same processes as in the above first embodiment are performed and the first gate electrode 31A and the second gate electrode 31B are formed, and thus the Fig. The first field effect transistor Q7 shown in Figure 32A is almost completed and will be Fig. The second field effect transistor Q8 shown in Figure 32B is almost completed.

[0172] Thereafter, as in the above first embodiment, a wiring layer and other insulating layers are formed on the insulating layer 20, and thus the semiconductor device 1 according to the fifth embodiment is almost completed.

[0173] According to the method for manufacturing the semiconductor device 1D of the fifth embodiment, the same effects as in the method for manufacturing the semiconductor device 1 according to the first embodiment described above can be obtained.

[0174] Furthermore, according to the method of manufacturing the semiconductor device 1D of the fifth embodiment, it is possible to form the bilaterally asymmetric second cavity part 25B 5 in which the width of the second part 25B 5 -R wider than the width of the first part 25B 5 -L is.

[0175] Since the second cavity part 25B 5 which is wider than the first cavity part 25A3 can be formed without using an etching mask, it is also possible to reduce the number of production processes compared with the above first embodiment and second embodiment, and it is possible to reduce the production cost of the semiconductor device 1D.

[0176] Since the width of the first cavity part 25A 3 according to the separation distance of the first stopper openings 21A in each of the pair 3 and 21A 4 embedded second insulating film 22 can be controlled and the width of the second cavity part 25B 5 according to the second stopper opening 21B 3 can be controlled, it is also possible to adjust the widths of the first cavity part 25A 3 and the second cavity part 25B 5 to be freely determined.

[0177] In the above first embodiment to the fifth embodiment, a case was described where the pair of main electrodes 16A and 17A and the pair of main electrodes 16B and 17B are formed before the insulating layer 20 is formed. However, the present invention is not limited to this. For example, the present invention can also be applied to a case where the pair of main electrodes 16A and 17A and the pair of main electrodes 16B and 17B are formed after the insulating layer 20 is formed.

[0178] In addition, in the above first embodiment to the fifth embodiment, the insulating layer 20, the first insulating layer 20A, and the second insulating layer 20B, which include the first insulating film 21, the second insulating film 22, and the third insulating film 26, were described. However, the present invention is not limited to this. For example, the present invention can be applied to a case where the insulating layer includes the first insulating film 21 and the second insulating film 22 except for the third insulating film 26.

[0179] Furthermore, in the above first embodiment to the fifth embodiment, respective layers on the upper part of the substrate 10 are formed of a GaN-based compound semiconductor. However, the present invention is not limited to such a configuration. For example, a compound semiconductor such as GaAs may be used, or a semiconductor layer made of silicon may be used. (Application examples)

[0180] Fig.38 shows an example of a configuration of a wireless communication device (wireless communication device 4). The wireless communication device 4 is, for example, a mobile phone system having a variety of functions such as audio and data communication and LAN connection. The wireless communication device 4 includes, for example, an antenna ANT, an antenna switching circuit 5, a high-power amplifier HPA, a radio frequency integrated circuit (RFIC), a baseband part BB, an audio output unit MIC, a data output unit DT, and an interface part I / F (for example, wireless LAN (W-LAN; wireless local area network) and Bluetooth (registered trademark)). The radio frequency integrated circuit RFIC and the baseband part BB are connected via an interface part I / F.For example, the antenna circuit 5 or the high power amplifier HPA includes any one of the semiconductor devices 1, 1A and 1B.

[0181] In the wireless communication device 4, during transmission, that is, when a transmission signal is output from a transmission system of the wireless communication device 4 to the antenna ANT, the transmission signal output from the baseband part BB is output to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA and the antenna switching circuit 5.

[0182] During reception, that is, when a signal received by the antenna ANT is input to a receiving system of the wireless communication device, the received signal is input to the baseband part BB via the antenna circuit 5 and the radio frequency integrated circuit RFIC. The signal processed by the baseband part BB is output from an output unit such as an audio output unit MIC, a data output unit DT, and an interface part I / F.

[0183] The wireless communication device 4 includes at least one of the above semiconductor devices 1 and 1A to 1D. [LIST OF REFERENCE SYMBOLS] 1 semiconductor device 2 semiconductor chips 10 Semiconductor substrate 11 Substrat 12 Buffer layer 13 Barrier layer 14 Layer of a two-dimensional electron gas 15 inactive area 16A, 17A Pair of first main electrodes (source electrode and drain electrode) 16B, 17B Pair of second main electrodes (source electrode and drain electrode) 20 Insulation layer 20A first insulation layer 20B second insulation layer 21 first insulating film 21A 1 , 21A 2 first etch stopper part 21B 1 , 21B 2 second etch stopper part 21A 3 , 21A 4 Opening for first stopper 21B 3 Opening for second stopper 22 second insulating film 23 third insulating film 24A 1 first opening 24B 1 second opening 24C 1 third opening 25A 1 , 25A 2 , 25A 3 first cavity part 25B 1 , 25B 2 , 25B 3 , 25B 4 , 25B 5 second cavity part 26 third insulating film 27A 1 first gate opening 27B 1 second gate opening 30 gate material 31A first gate electrode 31B second gate electrode 31a 1 , 31b 1 headboard 31a 2 , 31b 2 fuselage part SW high-frequency switch part BPF high-frequency filter part PA high-frequency power amplifier section LNA low-noise amplifier section Q1, Q5, Q7 first field effect transistor Q2, Q3, Q4, Q6, Q8 second field effect transistor RM1, RM2 mask

Claims

[1] Semiconductor device (1), comprising a first field-effect transistor (Q1) and a second field-effect transistor (Q2) housed on a semiconductor substrate (10), and an insulating layer (20) provided on a main surface of the semiconductor substrate and comprising a first insulating film (21) provided on the main surface of the semiconductor substrate, a second insulating film (22) provided on the first insulating film (21), and a third insulating film (26) covering the first insulating film (21) and the second insulating film, wherein both the first field effect transistor (Q1) and the second field effect transistor (Q2) a pair of main electrodes (16A, 17A, 16B, 17B) separated from each other in a respective direction of a gate length and provided on the main surface of the semiconductor substrate (10), a cavity part (25A 1 , 25B 1) provided in the insulating layer (20) between the pair of main electrodes (16A, 17A, 16B, 17B), surrounded by the third insulating layer, and having a width in the respective direction of the gate length between portions of the third insulating layer, and a gate electrode (31A, 31B) having a head portion (31a) positioned on the insulating layer (20) 1 , 31b 1 ) and a fuselage section (31a 2 , 31b 2 ) which is connected to the head part (31a 1 , 31b 1 ) penetrates the insulating layer (20) and in the direction of the cavity part (25A 1 , 25B 1 ) and in which the head part (31a 1 , 31b 1 ) wider than the fuselage part (31a 2 , 31b 2), wherein the third insulating film (26) covers the main surface of the semiconductor substrate (10) in the cavity part (25A1, 25B1) and surrounds the cavity part, the gate electrode (31A, 31B) is arranged on the main surface of the semiconductor substrate (10) with the third insulating film (26) therebetween, and the second insulating film over the cavity part has only a single opening, and where the width (W 2 ) of the cavity part of the second field effect transistor (Q2) of the width (W 1 ) of the cavity part of the first field effect transistor (Q1). [2] A semiconductor device (1) according to claim 1, wherein the respective cavity part (25A1, 25B1) of the first field effect transistor and the second field effect transistor is provided on both sides of the respective gate electrode (31A, 31B) in the respective direction of the gate length. [3] A semiconductor device (1) according to claim 1 or 2, wherein the respective cavity part (25A1 , 25B1) of the first field effect transistor and the second field effect transistor are provided bilaterally symmetrically on both sides of the respective gate electrode (31A, 31B) in the respective direction of the gate length. [4] Semiconductor device (1) according to claim 1 or 2, wherein the cavity part (25A 1 ) of the first field effect transistor (Q1) is provided bilaterally symmetrically on both sides of the gate electrode (31A) in the direction of the gate length and wherein the cavity part (25A 1 , 25B 1 ) of the second field effect transistor (Q2) is provided bilaterally asymmetrically on both sides of the gate electrode (31B) in the direction of the gate length. [5] A semiconductor device (1) according to any one of the preceding claims, wherein a separation distance (L 2 ) between the pair of main electrodes (16B, 17B) of the second field effect transistor (Q2) is longer than a separation distance (L 1) between the pair of main electrodes (16A, 17A) of the first field effect transistor (Q1). [6] An electronic device comprising a semiconductor device (1) according to any one of the preceding claims. [7] A method of manufacturing a semiconductor device according to any one of claims 1 to 5, the method comprising: forming the second insulating film (22) on a first active region (10A) for the first field effect transistor on the main surface of the semiconductor substrate (10) and on a second active region (10B) for the second field effect transistor different from the first active region (10A) with the first insulating film (21) therebetween; forming the first opening (24A 1 ) in the second insulating film (22) on the first active region (10A) and forming the second opening (24B 2 ) in the second insulating film (22) on the second active region (10B); forming a first cavity part (25A 1 ), which is wider than the first opening (24A 1 ) by passing the first insulating film (21) through the first opening (24A 1 ) is etched, and forming a second cavity part (25B 1 ), which is wider than the second opening (24B 1 ) by passing the first insulating film (21) through the second opening (24B 1 ) is etched; and an extension of the width of the second cavity part (25 B 1 ) by passing the first insulating film (21) through the second opening (24B 1 ) is etched selectively to the second insulating film (22). [8] A method of manufacturing a semiconductor device according to claim 7, wherein the first insulating film (21) is formed through the second opening (24B 1 ) is etched when the first opening (24A 1 ) is selectively covered with a mask (RM1). [9] A method of manufacturing a semiconductor device according to claim 7 or 8, wherein etching of the first insulating film (21) is performed by wet etching in which etching selectivity with respect to the second insulating film (22) is obtained. [10] A method of manufacturing a semiconductor device according to any one of claims 1 to 5, the method comprising: forming the second insulating film (22) on a first active region (10A) for the first field effect transistor of the main surface of the semiconductor substrate (10) and on a second active region (10B) for the second field effect transistor different from the first active region (10A) with the first insulating film (21) therebetween; forming a pair of first etching stopper parts (21A 1 , 21A 2) on one end side and the other end side of the first insulating film on the first active region (10A) in the direction of the gate length of the first field effect transistor and forming a pair of second etching stopper parts (21B 1 , 21B 2 ) provided on one end side and the other end side of the first insulating film (21) on the second active region (10B) in the direction of the gate length of the first field effect transistor, and between which a separation distance (W2) is longer than a separation distance (W1) between the pair of first etching stopper parts (21A 1 , 21A 2 ); forming a first opening (24A 1 ) in the second insulating film (22) on the first active region (10A) and forming a second opening (24B 1 ) in the second insulating film (22) on the second active region (10B); and forming a first cavity part (25A 2 ), which is wider than the first opening (24A1 ) by passing the first insulating film (21) through the first opening (24A 1 ) is etched, and forming a second cavity part (25B 4 ), which is wider than the first cavity part (25A 2 ) by passing the first insulating film (21) through the second opening (24B 1 ) is etched. [11] A method of manufacturing a semiconductor device according to claim 10, wherein the pair of first etching stopper parts (21A 1 , 21A 2 ) and the pair of second etching stopper parts (21B 1 , 21B 2 ) are formed by performing a heat treatment on the first insulating film (21). [12] A method of manufacturing a semiconductor device according to claim 10 or 11, wherein the second insulating film (22) is an insulating film having a high etching selectivity with respect to the first insulating film (21). [13] A method of manufacturing a semiconductor device according to any one of claims 10 to 12, wherein etching of the first insulating film (21) is performed by wet etching in which selectivity with respect to the second insulating film (22) is obtained.

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