DATA GATING USING SAMPLE RELEASE PINS

Abstract

Integrated circuit (IC), comprising: a storage element; and a control switching logic that is configured to: in response to a sample enable control, selecting between a function data input and a sample data input to serve as the input for the memory element; in response to a clock enable control, selectively blocking the switching of an output of the memory element by suppressing a clock signal supplied to the memory element; and While the clock enable control specifies that the output of the memory element should be blocked for switching, select that the input of the memory element should be the sample data input.

Description

AREA OF REVELATION

[0001] The present disclosure relates generally to integrated circuits and more particularly to power reduction of gated clock circuits in an integrated circuit. BACKGROUND OF REVELATION

[0002] To simplify the testing process for integrated circuits (ICs) containing millions of transistors, a scan mode is often implemented, with flip-flops of the ICs connected in series, allowing simple scan series testing of otherwise complex state machines. For a summary of scan test techniques, see, for example, "Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic," IEEE Transactions on Computers, C-22(1), 46-60; M. Williams and J. Angell (doi:10.1109 / tc.1973.223600).

[0003] Clock gating is often used to reduce the dynamic power consumption of ICs with millions of transistors. In "Clock Gating - A Power Optimization Technique for VLSI Circuits" (J. Shinde et al., 2011 Annual IEEE India Conference, December 16-18, 2011; DOI 10.1109 / INDCON.2011.6139440), the authors investigate the various clock gating techniques that can be used to optimize power in VLSI circuits at the RTL level and discuss various problems that arise when applying these power optimization techniques at the RTL level. US 2008 / 0 307 280 A1 describes an integrated circuit comprising: a scan chain having a plurality of scan cells, at least one of the scan cells operating in one of normal, capture, and shift modes selected only in response to a clock signal and a scan enable signal, the at least one of the scan cells comprising: a data input and a shift input; a flip-flop for storing a bit representing a state of the clock signal at an edge of the sample enable signal; Selection circuit for selecting between the data input and the shift input in response to the bit stored in the flip-flop, the selection circuit being operable to: in normal mode, selects the data input in response to a first state of the scan enable signal; in the acquisition mode, selects the data input in response to a bit stored in the first storage element representing a first state of the clock signal at the edge of the scan enable signal; and in shift mode, selecting the shift input in response to a bit stored in the first storage element representing a second state of the clock signal control on the edge of the sample enable signal; a register for storing data present at the selected data and shift input in response to the first state of the clock signal. SUMMARY OF REVELATION

[0004] It is an object of the present invention to provide an improved integrated circuit, an improved method in an integrated circuit or an improved device.

[0005] The object is achieved by an integrated circuit having the features of claim 1, by a method having the features of claim 8 or by a device having the features of claim 15. Preferred embodiments and developments of the invention can be found in the dependent claims.

[0006] An embodiment described herein provides an integrated circuit (IC) including a memory element and control circuitry. The control circuitry is configured to select, in response to a scan enable control, between a functional data input and a scan data input to serve as an input to the memory element, to selectively disable switching of an output of the memory element in response to a clock enable control by suppressing a clock signal provided to the memory element, and to select, while the clock enable control indicates that the output of the memory element is to be disabled from switching, that the input of the memory element is to be the scan data input.

[0007] In some embodiments, the storage element includes one or more latches, and upon selecting the sample data input, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether the functional data input is toggled. In an exemplary embodiment, the control circuitry is configured to prevent the latches from toggling without adding latency to the functional data input.

[0008] In one disclosed embodiment, by selecting the scan data input while the clock enable control indicates that the output should be disabled for toggling, the control circuitry is configured to set the input for the memory element to a constant logic state regardless of whether the function data input toggles. In another embodiment, the control circuitry includes a logic gate configured to set the memory element to a scan mode in response to the clock enable control disabling the clock signal.

[0009] In yet another embodiment, the control circuitry includes a logic gate configured to set the input for the storage element to a constant logic state in response to the clock enable control disabling the clock signal. In yet another embodiment, the storage element includes a latch clocked by an inversion of the clock signal, and upon selecting the sample data input while the clock enable control indicates that the output should be disabled for toggling, the control circuitry is configured to set an input of the latch to a constant logic state.

[0010] Additionally, according to an embodiment described herein, a method is provided in an integrated circuit (IC) including at least one memory element. The method includes selecting, in response to a scan enable control, between a functional data input and a scan data input to serve as an input to the memory element. In response to a clock enable control, switching of an output of the memory element is selectively disabled by suppressing a clock signal provided to the memory element. While the clock enable control indicates that the output of the memory element is to be disabled for switching, the input of the memory element is selected as the scan data input.

[0011] According to an embodiment described herein, an apparatus is also provided that includes a processor including (i) fetch circuitry configured to fetch instructions and (ii) execution circuitry configured to execute instructions. One or both of the fetch circuitry and the execution circuitry includes a memory element and control circuitry.The control circuitry is configured to select, in response to a scan enable control, between a functional data input and a scan data input to serve as an input to the memory element, to selectively disable switching of an output of the memory element in response to a clock enable control by suppressing a clock signal provided to the memory element, and to select, while the clock enable control indicates that the output of the memory element is to be disabled from switching, that the input of the memory element is to be the scan data input.

[0012] The present disclosure will be more fully understood from the following detailed description of embodiments thereof taken in conjunction with the drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram schematically illustrating the structure of an integrated circuit (IC) according to an embodiment described herein; Fig. 2 is a block diagram schematically illustrating the structure of a D flip-flop (DFF) coupled to a sampling circuit and a clock gate according to an embodiment described herein; Fig. 3 is a block diagram schematically illustrating a structure of a computer according to an embodiment described herein; Fig. 4 is a flowchart schematically illustrating a method for reducing power consumption using data gating according to an embodiment described herein; Fig. 5 is a diagram schematically illustrating various types of systems that may include any of the circuits, devices, or systems discussed herein, according to embodiments described herein; and Fig. 6 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information, according to some embodiments. DETAILED DESCRIPTION OF EMBODIMENTSOverview

[0013] Typically, complex integrated circuits include memory elements, each configured to store a "logic 1" or "logic 0" value. As used herein, the term "memory element" refers to elements such as flip-flops, latches, and the like. The embodiments described herein refer to flip-flops by way of example, but the disclosed techniques are applicable to other suitable types of memory elements.

[0014] There are a variety of flip-flop types, including, for example, clocked and unclocked flip-flops, RS flip-flops, JK flip-flops, T flip-flops, and others. A common type of flip-flop widely used in today's integrated circuits is a D flip-flop (sometimes called a DFF), which includes a D input, a clock input, and an output. The DFF is configured to store the logical value present at its D input when the clock input transitions, e.g., from logic low to logic high. In the disclosure below, we sometimes use the terms "flip-flops" and "DFFs" interchangeably in examples.

[0015] To enable easy testing of digital integrated circuits, scan circuitry can be added to a group of DFFs in the integrated circuit. An external tester can specify a scan mode (or scan enable) to the scan circuitry, in which DFFs in the group should be scanned. The scan circuitry is configured to connect the DFFs in the group sequentially (e.g., in series) in response to the scan mode specification, so that a scan input from outside the group of DFFs is passed between the DFFs in the group, from a first DFF to a last DFF, and from the last DFF to a scan-out output of the group of DFFs. (We will refer to two modes of operation of integrated circuits below—the scan mode described above and a functional mode, in which the scan circuitry is not operating and the DFFs receive functional inputs instead of scan inputs.)

[0016] We will also refer to logic low and logic high as "low" and "high" below, respectively; we refer to a low-to-high transition as a rising edge (or "posedge") and a high-to-low transition as a falling edge (or "negedge"). It should be understood that low and high do not necessarily represent voltage levels; for example, in some logic families, low and high may refer to current directions; furthermore, in some logic families, low represents a voltage higher than the voltage level represented by high (e.g., in negative logic).

[0017] A DFF typically includes a primary latch and a secondary latch. In a posedge-triggered DFF, the primary latch passes the D input of the DFF to an input of the secondary latch when the clock input is low and holds the value of the D input on a rising clock edge; the secondary latch passes the output of the primary latch to the DFF output when the clock input is high and holds the value of the primary latch on a falling clock edge. Conversely, in a negedge-triggered DFF, the primary latch passes the input when the clock is high and holds on a negedge clock, while the secondary latch passes the output of the primary latch when the clock is low and holds the output on a rising clock edge. (It should be noted that the primary and secondary latches can operate in a manner that is also referred to by experts as "master" (i.e. primary) and "slave" (i.e. secondary).While the terminology "primary / secondary" is used herein, it is expressly intended that the terms "primary" and "secondary" be construed to include these equivalents.

[0018] High-density integrated circuits can include millions of DFFs, and switching the clock inputs of the DFFs is a significant contributing factor to the integrated circuit's power consumption. A common technique to reduce power consumption is clock gating, in which the clock signal is disabled in unused sections of the circuit. Clock gating saves power by pruning the clock tree, at the cost of adding more logic to a circuit.

[0019] When a DFF's clock is disabled, the DFF's clock input is typically set to a logic level at which the primary latch is transparent (i.e., it passes the D input to the secondary latch) but does not hold the logic value, while the secondary latch stores the last value output by the primary latch on the falling clock edge (e.g., the clock is set low for posed-triggered DFFs). Thus, when the secondary latch is not toggling, power dissipation is significantly reduced. (The secondary latch typically drives logic switching and charges and discharges additional nodes during toggling, resulting in significant power dissipation.)

[0020] However, if the primary latch is transparent, it will typically toggle when the D input toggles, even though the DFF's clock may be locked, and the changes at the D input will not be visible at the secondary latch's output. Thus, even though a DFF's clock is locked, toggling the primary latch can still result in significant power consumption.

[0021] Embodiments described herein provide devices and methods that use data gating in addition to clock gating of the clock-locked DFFs to further reduce the power consumption of clock-locked DFFs. In some embodiments, control circuitry is configured to, in response to a clock-lock input, drive the sample enable input, which is constant when no sampling is indicated, to the input of the corresponding DFF, setting the DFF input to a constant logic level. Thus, when the clock is locked, both the data input and the clock input are gated, which can result in a significant reduction in the power consumption of the integrated circuit.

[0022] Furthermore, the disclosed control logic does not add any logic in the functional data path, e.g., before the functional input of the flip-flop. Thus, the disclosed techniques do not introduce additional latency and do not degrade the achievable data throughput or clock speed. System description

[0023] Fig. 1 is a block diagram schematically illustrating the structure of an integrated circuit (IC) 100 according to an embodiment described herein. The IC 100 may include any suitable type of IC configured to perform any suitable function, e.g., a microprocessor, a video processor, or any other. The IC includes a group of dual-latch D-type flip-flops (DFFs) 102 that share a common clock input (referred to as "clock") and combinational logic circuitry 104 configured to generate function inputs to the DFFs 102 in response to the data stored in the DFFs (and possibly in response to other inputs). Each DFF includes a clock input ("CLK"), a D input, and a Q output (in embodiments, DFF 102 may include other inputs, e.g., reset).

[0024] It should be understood that integrated circuits according to some embodiments may include multiple clock inputs and multiple groups of DFFs, where the DFFs of each group share one of the multiple clock inputs. In some embodiments, IC 100 may include other logic, such as unclocked flip-flops, memories, analog circuits, and others. However, for clarity, we will refer below to an embodiment in which IC 100 includes a single clock, and we will ignore circuitry unrelated to the group of DFFs, such as memories, analog subsystems, and the like.

[0025] According to the Fig. 1, IC 100 includes sampling circuits 106, each sampling circuit coupled to a respective DFF 102 and configurable to provide either a functional input (output from combinational logic circuitry 104) or a sampling input to the D input of the DFF in response to a sampling enable input.

[0026] DFFs 102 are coupled together in a series fashion, such that the sample input of the sample circuit coupled to a first DFF is coupled to a SAMPLE-IN input of IC 100, the sample input of the sample circuit coupled to a second DFF is coupled to the Q output of the first DFF, and so on. The Q output of a last DFF is coupled to a SAMPLE-OUT output of the IC. (In some embodiments, SAMPLE-IN and / or SAMPLE-OUT are not inputs / outputs of IC 100; instead, SAMPLE-IN may be input from and / or SAMPLE-OUT may be output to a built-in self-test (BIST) circuit in IC 100.)

[0027] The IC 100 further includes clock disabling circuitry 108 configured to disable the clock inputs of the DFFs 102, which may be inactive. A clock gating circuit 110 is coupled to each DFF 102; the clock gating circuit is configured to disable the clock input of the DFF in response to a clock disabling control issued by the clock disabling circuitry 108, for example, by applying a constant logic low to the clock input of the DFF. As explained above, this prevents the secondary latch of the DFF 102 from toggling and thus reduces power consumption.

[0028] According to the Fig. 1, data gating is used in addition to clock gating to prevent the primary latch (in addition to the secondary latch) from toggling. (An exemplary internal structure of the dual-latch flip-flop 102 showing the primary and secondary latches is shown in Fig. 2 below.) Sampling circuit 106 is configured to send a constant logic level (e.g., low) to the D input of the corresponding DFF in response to the clock disable input. As a result, the primary latch does not toggle, and additional power reduction is achieved (in embodiments, the sampling circuit sends the sample enable input, which is constantly low in functional mode, to the D input of the DFF in response to the clock disable input).

[0029] It is understood that the structure of IC 100, which is Fig. 1 and described above is an exemplary embodiment provided for clarity. In some embodiments, alternative structures may be used. For example, the sampling circuits may also be used to set the DFFs to a known state; other types of flip-flops may be used; and more than one sampling chain may be implemented in the IC.

[0030] In the present context, the sampling circuit 106 and the clock gating circuit 110 are collectively referred to as “control circuitry” that carries out the disclosed technique, although in other embodiments, control circuitry for implementing the disclosed technique may be used using different circuitry or a different organization than in Fig. 1 can be implemented. In this context, the terms "clock enable input" and "clock disable input" are used interchangeably to refer to a signal that controls whether the clock is enabled or disabled.

[0031] Fig. Figure 2 is a block diagram schematically illustrating the structure of a DFF 102 coupled to a sampling circuit 106 and a clock gate 110, according to an embodiment described herein. DFF 102, sampling circuit 106, and clock gate 110, described with reference to Fig. 1 are hereby incorporated by reference in accordance with Fig. 2 will be described in more detail. As mentioned below, Fig. 2 illustrates the logical function of embodiments of sampling circuit 106 and clock gate 110 as AND and OR gates for ease of illustration. However, it should be understood that any suitable circuit structure may be used to implement the illustrated functionality.

[0032] The DFF 102 includes two latches—a primary latch 202 and a secondary latch 204. The primary latch passes the D input of the DFF to the input of the secondary latch when the clock input is low and holds the value of the D input on a rising clock edge. The secondary latch passes the output of the primary latch to the DFF output when the clock input is high and holds the value of the primary latch on a falling clock edge.

[0033] The clock input of the DFF 102, which is shared by the primary latch 202 and the secondary latch 204, is generated by the clock gate 110. According to the Fig. 2, the clock gate 110 is an AND gate that provides the clock input to the DFF clock input when a clock enable input is high and sets the clock input of the DFF low when the clock enable is low, thereby preventing the secondary latch from toggling.

[0034] The sampling circuit 106 includes a multiplexer 206 configured to select a source for the D input of the DFF 102, an AND gate 208 configured to gate the sample data, an inverter 209, and an OR gate 210 configured to indicate to which source the multiplexer 206 should send the D input of the DFF 102.

[0035] In sample mode, the sample enable input is high, the AND gate 208 outputs the sample data, the OR gate 210 outputs a logic high, which causes the multiplexer 206 to transfer the output of the AND gate 208 to the D input of the DFF 102. Thus, a sample path is configured, and the sample input passes through the DFF 102 to the Q output (and therefore to the sample input of the sampling circuit of the next DFF stage, as shown in Fig. 1). In function mode, the sample enable input is low, and when the clock enable input is high, multiplexer 206 transfers the function input to the D input of DFF 202.

[0036] However, when the clock enable is low in functional mode, OR gate 210 indicates that multiplexer 206 should transfer the output of AND gate 208 to the D input of DFF 102. Since the sample enable input is now low, inverter 209 outputs a high and AND gate 208 outputs a low, the D input of DFF 102 is low, and thus primary latch 202 does not toggle, regardless of any toggling at the functional input, resulting in a further reduction in power consumption.

[0037] It is understood that the structure of the DFF 102, the sampling circuit 106 and the clock gate 110, in Fig. 2 and described above. In alternative embodiments, various suitable structures may be used. For example, De Morgan equivalents of the illustrated gates may be used. In some embodiments, the sample enable and / or clock enable inputs may be active low. In embodiments, other types of DFFs may be used, and in some embodiments, some or all of the DFFs may be replaced with other types of flip-flops, e.g., T-flip-flops.

[0038] In this example, the various elements of Fig. 2 other than flip-flop 102 (sampling circuit 106 and clock gate 110) as control circuitry implementing the disclosed technique. In alternative embodiments, the control circuitry may have any other suitable configuration.

[0039] Fig. Figure 3 is a block diagram schematically illustrating the structure of a computer 300 according to an embodiment described herein. Computer 300 includes a central processing unit (CPU) 304 and a memory 306. The CPU includes an instruction fetch circuit 308 configured to fetch and decode instructions (e.g., from memory 306) and an instruction execution circuit 310 configured to execute the decoded instructions.

[0040] A user may interact with computer 300 via a display device and one or more input devices, in this example, a display / keyboard / mouse subsystem 312. It should be understood that computer 300 may include a variety of CPUs as well as numerous other components, including, for example, encryption / decryption units, graphics processors, network interface circuitry, analog circuitry, and wireless interface units.

[0041] An instruction fetch circuit 308 and an instruction execution circuit 310 include a plurality of flip-flops, such as the flip-flops 102 of Fig. 1 and Fig. 2. According to the Fig. 3, the CPU 304 includes a scan chain 316 that covers at least some of the flip-flops in the instruction fetch circuit 308 and the instruction execution circuit 310 (and / or additional logic circuits that the CPU 300 may include). The scan chain includes scan circuits (e.g., scan circuit 106, Fig. 2) configured to operate the respective flip-flops in a sampling mode and, when the clock is disabled to the corresponding flip-flops, to set the D input of the flip-flops to a constant logic level, for example, by conducting the sampling enable input to the D input of the flip-flop.

[0042] Fig. 4 is a flowchart schematically illustrating a method 400 for reducing power consumption using data gating according to an embodiment described herein. The flowchart is implemented by clock gates 110 and sampling circuits 106 ( Fig. 1). Each of the sampling circuits and clock gates executes the flow independently of the other sampling circuits and clock gates.

[0043] The flowchart begins at a scan enable check stage 402, where the scan circuit checks whether the scan enable is asserted. If so, the flowchart enters a scan to flip-flop conduct stage 404, where the scan circuit conducts the scan-in input to the D input of DFF 102, initiating the scan test of the DFFs, and ending the flowchart.

[0044] If no sampling enable is specified in stage 402, the clock gate and sampling circuit enter a clock enable check stage 406 and check whether the clock of the corresponding DFF is enabled. If so, the clock gate and sampling circuit enter a functional operation stage 408 where the sampling mode is disabled and the clock is not gated, and then the flowchart ends.

[0045] If the clock is not enabled in stage 406, the sampling circuit in a sample input-to-flip-flop route stage 410 routes the sample input (which is set low in functional mode) to the D input of DFF 102, preventing the DFF's primary latch from toggling. Next, in "force flip-flop clock low," clock gate 110 forces the flip-flop's clock input low, preventing the secondary latch from toggling.

[0046] Thus, according to the Fig. 4 and described above, a clock gate and sampling circuit are operable to, in response to a sampling mode indication (sample enable high), direct the sampling input to the D input of the corresponding flip-flop; and, in response to a clock disable indication (clock enable low), i) force a constant low level at the clock input of the flip-flop to prevent the secondary latch from toggling, and ii) direct the sample enable input, which is low in functional mode, to the D input of the flip-flop to prevent the primary latch from toggling.

[0047] Fig. 5 is a diagram 500 schematically illustrating various types of systems that may include any of the circuits, devices, or systems discussed above, according to embodiments described herein. The system or device 500, which may incorporate or otherwise utilize one or more of the techniques described herein, may be used in a wide range of fields. For example, the system or device 500 may be used as part of the hardware of systems such as a desktop computer 510, a laptop computer 520, a tablet computer 530, a cellular or mobile phone 540, or a television 550 (or a set-top box coupled to a television).

[0048] Similarly, the disclosed elements may be used in a wearable device 560, such as a smartwatch or a health monitoring device. Smartwatches, in many embodiments, may perform a variety of different functions, such as accessing email, cellular services, calendars, health monitoring, etc. A wearable device may also be designed to exclusively perform health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication with emergency medical services, etc.Other types of devices are also conceivable, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets that provide computer-generated reality experiences, such as those based on augmented and / or virtual reality, etc.

[0049] The system or device 500 may also be used in various other contexts. For example, the system or device 500 may be used in conjunction with a server computer system, such as a dedicated server or on shared hardware implementing a cloud-based service 570. Furthermore, the system or device 500 may be implemented in a wide range of specialized, everyday devices, including common household devices 580 such as refrigerators, thermostats, security cameras, etc. The networking of such devices is often referred to as the "Internet of Things" (IoT). The elements may also be implemented in various means of transportation. For example, the system or device 500 could be used in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles 590.

[0050] The Fig. The applications illustrated in Figure 5 are merely exemplary and are not intended to limit the possible future applications of the disclosed systems or devices. Other example applications include, without limitation, portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0051] In the present disclosure, various example circuits have been described in detail above. It is intended that the present disclosure cover not only embodiments that include such circuit logic, but also a computer-readable storage medium that includes design information specifying such circuit logic. Accordingly, the present disclosure is intended to support claims that cover not only a device that includes the disclosed circuit logic, but also a storage medium that specifies the circuit logic in a format recognized by a production system configured to manufacture hardware (e.g., an integrated circuit) that includes the disclosed circuit logic. Claims to such a storage medium are intended to cover, for example, an entity that creates a circuit design but does not itself produce the design.

[0052] Fig. 6 is a block diagram illustrating an exemplary non-transitory computer-readable storage medium storing circuit design information, according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 620 is configured to process the design information 615 stored on the non-transitory computer-readable medium 610 and to manufacture an integrated circuit 830 based on the design information 615.

[0053] The non-transitory computer-readable storage medium 610 may include any of various suitable types of storage devices or storage devices. The non-transitory computer-readable storage medium 610 may be an installation medium, e.g., a CD-ROM, floppy disks, or a tape device; computer system memory or random access memory, such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; non-volatile memory, such as flash memory; magnetic media, e.g., a hard disk or optical storage; registers or other similar types of storage elements, etc. The non-transitory computer-readable storage medium 610 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 610 may include two or more storage media that may be located in different locations, e.g.,in different computer systems connected via a network.

[0054] The design information 615 may be specified using any of various suitable computer languages, including hardware description languages ​​such as, without limitation, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 615 may be used by the semiconductor manufacturing system 620 to manufacture at least a portion of the integrated circuit 830. The format of the design information 615 may be recognized by at least one semiconductor manufacturing system 620. In some embodiments, the design information 615 may also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 830. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity.The design information 615 may, on its own, include sufficient information for the manufacture of a corresponding integrated circuit, but need not. For example, the design information 615 may specify the circuit elements to be manufactured, but not their physical layout. In this case, the design information 615 may need to be combined with layout information to actually manufacture the specified circuit logic.

[0055] The integrated circuit 830 may, in various embodiments, include one or more user-defined macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, the design information 615 may include information related to included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device- or transistor-level netlists. As used herein, mask design data may be formatted according to the Graphics Data System (GDSII) or any other suitable format.

[0056] The semiconductor manufacturing system 620 may include any of various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. The semiconductor manufacturing system 620 may also be configured to perform various tests of manufactured circuits for proper function.

[0057] In various embodiments, the integrated circuit 830 is configured to operate according to a circuit design specified by the design information 615, which may include performing any of the functionalities described herein. For example, the integrated circuit 830 may perform any of the various Fig. 1, Fig. 2, Fig. 3 and Fig. 5. Furthermore, integrated circuit 830 may be configured to perform various functions described herein in conjunction with other components. Furthermore, the functionality described herein may be performed by multiple connected integrated circuits.

[0058] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured to satisfy the element. Rather, this phrase indicates that the design information describes a circuit that, after manufacturing, is configured to perform the specified actions or include the specified components.

[0059] This disclosure includes references to "one" embodiment or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are various implementations or instances of the disclosed concepts. References to "embodiment," "an embodiment," "a particular embodiment," and the like do not necessarily refer to the same embodiment. A wide variety of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.

[0060] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all of the potential advantages. Whether an advantage is achieved for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are a number of reasons why an implementation that falls within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation might include different circuitry outside the scope of the disclosure that, when used in conjunction with one of the disclosed embodiments, negates or reduces one or more of the disclosed advantages. Furthermore, a suboptimal design of a particular implementation (e.g.,Implementation techniques or tools) may cancel out or diminish any benefits disclosed. Even assuming a qualified implementation, the achievement of benefits may still depend on other factors, such as the environmental circumstances in which the implementation is provided. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, thereby possibly failing to achieve the benefit of its solution. Due to the existence of possible factors external to this disclosure, it is expressly intended that any potential benefits described herein should not be construed as claim limitations that must be met to prove infringement.Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvement available to designers benefiting from this disclosure. The description of such benefits in a permissive sense (e.g., stating that a particular benefit "may occur") is not intended to cast doubt on whether such benefits can actually be achieved, but rather to acknowledge the technical reality that the achievement of such benefits often depends on additional factors.

[0061] Unless otherwise stated, embodiments are not restrictive. That is, the disclosed embodiments are not intended to limit the scope of any claims based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, unless otherwise stated in the disclosure. Thus, the application is intended to enable claims to cover disclosed embodiments, as well as the alternatives, modifications, and equivalents that would be obvious to one skilled in the art having the benefit of this disclosure.

[0062] For example, features in this application may be combined in any suitable manner. Accordingly, during the prosecution of this application (or an application claiming priority hereof), new claims may be drafted to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims that depend on other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

[0063] While the appended dependent claims may be drafted such that each depends on a single other claim, additional dependencies are contemplated accordingly. All combinations of features in the dependent claims that are consistent with this disclosure are contemplated and may be claimed in this or another application. In summary, combinations are not limited to those specifically enumerated in the appended claims.

[0064] Where appropriate, it is also contemplated that claims formulated in one format or statutory type (e.g., facility) should support corresponding claims of a different format or statutory type (e.g., method).

[0065] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and legal interpretation. Notice is hereby given that the following paragraphs, as well as definitions provided throughout this disclosure, should be used in determining how claims based on this disclosure are to be interpreted.

[0066] References to a singular form of an element (i.e., a noun or noun phrase preceded by "a" or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, a reference to "an element" in a claim, without an accompanying context, does not exclude additional instances of the element. A "plurality" of elements refers to a set of two or more of the elements.

[0067] The word “may” is used herein in a permissive sense (i.e., having the potential, being able to) and not in a mandatory sense (i.e., must).

[0068] The terms “comprehensive” and “including” and forms thereof are open-ended and mean “including, but not limited to.”

[0069] When the term "or" is used in this disclosure with reference to a list of options, it is generally understood to be used in the inclusive sense unless the context indicates otherwise. Thus, a statement of "x or y" is equivalent to "x or y or both," and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase such as "either x or y, but not both" makes it clear that "or" is used in the exclusive sense.

[0070] A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, for the set [w, x, y, z], these phrases cover any single element of the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "at least one of ... x, y, and z" thus refers to at least one element of the set [w, x, y, z], covering all possible combinations in this list of elements. This phrase should not be interpreted to require that at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z be present.

[0071] Various "labels" may precede nouns or noun phrases in this disclosure. Unless the context indicates otherwise, various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Additionally, the labels "first," "second," and "third," when applied to a feature, do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise noted.

[0072] The phrase "based on" or "upon the basis of" is used to describe one or more factors that influence a determination. This term does not preclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on stated factors or may be based on the stated factors as well as other, unstated factors. Consider the phrase "determine A based on B." This phrase specifies that B is a factor used to determine A or that influences the determination of A. This phrase does not preclude that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0073] The phrases "in response to" and "in reaction to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either jointly with the specified factors or independently of the specified factors. That is, an effect may occur solely in response to these factors, or it may occur in response to the specified factors as well as other, unspecified factors. Consider the phrase "doing A in response to B." This phrase specifies that B is a factor that triggers the performance of A or that triggers a particular result for A. This phrase does not exclude that doing A may also occur in response to another factor, such as C. Nor does this phrase exclude that doing A may occur in response to B and C together.This phrase is also intended to cover an embodiment in which A is performed solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on." Similarly, the phrase "in response to" is synonymous with the phrase "at least in part in response to."

[0074] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be referred to as being "configured to" perform a task even if the structure is not currently operating.Thus, an entity described or specified as being “configured to” perform a task refers to something physical, such as a device, a circuit, a system including a processing unit and memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to anything intangible.

[0075] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It is understood that these entities are "configured to" perform these tasks / operations, even if not specifically stated.

[0076] The term "configured to" is not intended to imply "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA can be "configurable to" perform that function. After appropriate programming, the FPGA can then be said to be "configured to" perform that specific function.

[0077] Various "circuits" may be described in this disclosure. These circuits or "circuitry" constitute hardware that includes various types of circuit elements, such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, and so on. Circuitry may be user-defined or taken from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., a decoding unit, an arithmetic logic unit (ALU), a functional unit, a memory management unit (MMU), etc.). Such units also refer to circuits or circuitry.

[0078] The disclosed circuits / units / components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode of an instruction and redirecting that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. This functional statement is sufficient for one skilled in the computer arts to further identify a set of possible structures for the circuit.

[0079] In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement and arrangement of such circuits / units / components with respect to one another and the manner in which they interact constitute a microarchitectural definition of the hardware that is ultimately fabricated on an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition will be recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitectural definition.This means that one skilled in the art, presented with the microarchitecture definition provided in accordance with this disclosure, can, without undue experimentation and by exercising ordinary skill, implement the structure by coding the description of the circuits / units / components in a Hardware Description Language (HDL), such as Verilog or VHDL. The HDL description is often expressed in a manner that may appear functional. However, to one skilled in the art, this HDL description is the manner used to transform the structure of a circuit, unit, or component to the next level of implementation detail. Such an HDL description may take the form of behavioral code (which is typically not synthesizable), Register Transfer Language (RTL) code (which, unlike behavioral code, is typically synthesizable), or structural code (e.g.,A netlist (i.e., a netlist specifying logic gates and their connectivity) can be used. The HDL description can then be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to result in a final design database that is submitted to a foundry to create masks and ultimately manufacture the integrated circuit. Some hardware circuits, or sections thereof, can also be customized in a schematic editor and incorporated into the integrated circuit design along with synthesized circuit logic. The integrated circuits can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and provide interconnection between the transistors and circuit elements.Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and may be implemented in the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits typically leads to the scenario where the circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuit is configured to do, since that process is performed at a different stage of the circuit implementation process.

[0080] The fact that many different low-level combinations of circuit elements can be used to implement the same circuit specification results in a large number of equivalent structures for that circuit. As noted, these low-level circuits can vary according to changes in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the selections made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0081] Furthermore, it is common for a single implementation of a particular functional specification of a circuit to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete specification of the low-level structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes a structure of circuits using the functional shorthand commonly employed in the industry.

Claims

[1] Integrated circuit (IC) comprising: a storage element; and a control logic configured to: in response to a scan enable control, selecting between a function data input and a scan data input to serve as an input to the memory element; in response to a clock enable control, selectively disabling the switching of an output of the memory element by suppressing a clock signal provided to the memory element; and while the clock enable control indicates that the output of the storage element should be disabled for toggling, selecting that the input of the storage element should be the sample data input. [2] The IC of claim 1, wherein the storage element comprises one or more latches, and wherein upon selecting the sample data input, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether the function data input toggles or not. [3] The IC of claim 2, wherein the control logic is configured to prevent switching of the latches without adding latency to the function data input. [4] The IC of any one of claims 1 to 3, wherein by selecting the sample data input while the clock enable control indicates that the output is to be disabled for toggling, the control circuitry is configured to set the input for the storage element to a constant logic state regardless of whether the function data input toggles or not. [5] The IC of any one of claims 1 to 3, wherein the control circuitry comprises a logic gate configured to set the memory element to a scan mode in response to the clock enable control disabling the clock signal. [6] The IC of any one of claims 1 to 3, wherein the control circuitry comprises a logic gate configured to set the input for the storage element to a constant logic state in response to the clock enable control disabling the clock signal. [7] The IC of any one of claims 1 to 3, wherein the storage element comprises a latch clocked by an inversion of the clock signal, and wherein upon selecting the sample data input while the clock enable control indicates that the output is to be disabled for toggling, the control circuitry is configured to set an input of the latch to a constant logic state. [8] A method in an integrated circuit (IC) including at least one memory element, the method comprising: in response to a scan enable control, selecting between a function data input and a scan data input to serve as an input to the memory element; in response to a clock enable control, selectively disabling switching of an output of the memory element by suppressing a clock signal provided to the memory element; and while the clock enable control indicates that the output of the storage element should be disabled for toggling, selecting that the input of the storage element should be the sample data input. [9] The method of claim 8, wherein the storage element comprises one or more latches, and wherein selecting the sample data input comprises preventing any of the latches from toggling while the output is disabled from toggling, regardless of whether the function data input toggles or not. [10] The method of claim 9, wherein preventing the switching of the latches is performed without adding latency to the function data input. [11] The method of any one of claims 8 to 10, wherein selecting the sample data input while the clock enable control indicates that the output is to be disabled from toggling comprises setting the input for the storage element to a constant logic state regardless of whether the function data input is toggling or not. [12] The method of any one of claims 8 to 10, wherein selecting the scan data input comprises setting the memory element to a scan mode using a logic gate in response to the clock enable controller disabling the clock signal. [13] The method of any one of claims 8 to 10, wherein selecting the sample data input comprises setting the input to the memory element to a constant logic state using a logic gate in response to the clock enable controller disabling the clock signal. [14] The method of any one of claims 8 to 10, wherein the storage element comprises a latch clocked by an inversion of the clock signal, and wherein selecting the sample data input while the clock enable control indicates that the output is to be disabled for toggling comprises setting an input of the latch to a constant logic state. [15] An apparatus comprising a processor comprising (i) fetch circuitry configured to fetch instructions and (ii) execution circuitry configured to execute instructions, wherein one or both of the fetch circuitry and the execution circuitry comprises: a storage element; and a control logic configured to: in response to a scan enable control, selecting between a function data input and a scan data input to serve as an input to the memory element; in response to a clock enable control, selectively disabling the switching of an output of the memory element by suppressing a clock signal provided to the memory element; and while the clock enable control indicates that the output of the storage element should be disabled for toggling, selecting that the input of the storage element should be the sample data input. [16] The apparatus of claim 15, further comprising a display device and one or more input devices. [17] The apparatus of claim 15, wherein the storage element comprises one or more latches, and wherein upon selecting the sample data input, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether the function data input toggles or not. [18] The apparatus of any one of claims 15 to 17, wherein by selecting the sample data input while the clock enable control indicates that the output is to be disabled for toggling, the control circuitry is configured to set the input for the storage element to a constant logic state regardless of whether the function data input toggles or not. [19] The apparatus of any of claims 15 to 17, wherein the control circuitry comprises a logic gate configured to set the memory element to a scan mode in response to the clock enable controller disabling the clock signal. [20] The apparatus of any of claims 15 to 17, wherein the control circuitry comprises a logic gate configured to set the input for the storage element to a constant logic state in response to the clock enable control disabling the clock signal.

Images