Solid-body imaging element, imaging device and method for controlling a solid-body imaging element

Abstract

The present invention reduces the circuit size in a solid-state imaging element that synthesizes multiple images. A pre-stage circuit generates an analog signal as a pixel signal. A sample-and-hold circuit holds a high-gain signal, obtained by amplifying the pixel signal according to a gain factor equal to the capacitance of any one of several capacitive elements, and generates a low-gain signal by amplifying the pixel signal according to a gain factor equal to the ratio of the resulting capacitance of the several capacitive elements to the capacitance. A post-stage circuit sequentially reads and outputs the high-gain and low-gain signals from the sample-and-hold circuit.

Description

TECHNICAL FIELD

[0001] The present technology relates to a solid-state imaging element. More particularly, the present technology relates to a solid-state imaging element that amplifies a signal, an imaging device, and a method for controlling a solid-state imaging element. BACKGROUND

[0002] In the prior art, to improve image quality, processing for combining multiple pieces of image data (in other words, frames) has been performed in an imaging device or the like. For example, a solid-state imaging element has been proposed that holds a frame in a frame memory, amplifies a signal of the frame with both a high gain and a low gain to generate two frames, and combines the frames (see, for example, Patent Document 1). CITATION LISTPATENT DOCUMENT

[0003] Patent Document 1: Japanese Patent Application Publication No. 2018-011162 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] In the above-described prior art, a dynamic range is expanded by combining a single image generated with a high gain and a single image generated with a low gain. However, the above-described solid-state imaging element requires a single image memory, causing a problem that a circuit scale increases accordingly.

[0005] The present technology was developed in consideration of such a situation, and an objective of the present technology is to reduce a circuit scale in a solid-state imaging element that combines multiple frames. SOLVING THE PROBLEMS

[0006] The present technology was developed to solve the problems described above, and a first aspect thereof relates to a solid-state imaging element and a method for controlling the same, the solid-state imaging element including: a pre-stage circuit that generates an analog signal as a pixel signal; a sample-and-hold circuit that holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain smaller than the high gain and corresponding to a combined capacitance of the plurality of capacitor elements;and a post-stage circuit that sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit. This achieves an effect of reducing circuit size.

[0007] Furthermore, in the first aspect, the plurality of capacitor elements may include a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element, and the sample-and-hold circuit may include: the first capacitor element; the second capacitor element; the third capacitor element; the fourth capacitor element; and a selection circuit that connects one or more of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element to the post-stage circuit. This brings about an effect of generating a low-gain signal by connecting a plurality of capacitor elements.

[0008] Furthermore, in the first aspect, the pre-stage circuit, the sample-and-hold circuit, and the post-stage circuit may be arranged in each of a plurality of pixels. A level of the pixel signal may include a reset level when a floating diffusion layer in the pre-stage circuit is initialized and a signal level when charge is transferred to the floating diffusion layer. The pre-stage circuit may generate the reset level immediately before a time point at which exposure of all of the plurality of pixels ends and generate the signal level at that time point. The selection circuit may connect the first capacitor element to the post-stage circuit immediately before the time point and connect the third capacitor element to the post-stage circuit at that time point. This brings about an effect of holding the reset level and signal level at the end of exposure using the global shutter method.

[0009] Furthermore, in the first aspect, the selection circuit may sequentially perform control for connecting the first capacitor element to the post-stage circuit, control for connecting the first capacitor element and the second capacitor element to the post-stage circuit, control for connecting the third capacitor element to the post-stage circuit, and control for connecting the third capacitor element and the fourth capacitor element to the post-stage circuit within one read period of the pixel signal. This results in an effect of generating high-gain and low-gain signals.

[0010] Furthermore, in the first aspect, the selection circuit may sequentially perform control for connecting the first capacitor element to the post-stage circuit, control for connecting the first capacitor element and the second capacitor element to the post-stage circuit, and control for connecting the third capacitor element to the post-stage circuit if it is determined that the signal level does not exceed a predetermined determination value, and for connecting the third capacitor element and the fourth capacitor element to the post-stage circuit if it is determined that the signal level is higher than the determination value, within one read period of the pixel signal. This brings about an effect of improving a read speed.

[0011] Furthermore, in the first aspect, a determination circuit may be further included that determines whether or not the signal level is higher than the determination value and provides a determination result to the sample-and-hold circuit. This brings about an effect of reducing a processing load on the post-stage circuit.

[0012] Furthermore, in the first aspect, the determination circuit may be arranged in each of the plurality of pixels. This brings about an effect of reducing the circuit scale in the subsequent stage of the pixel.

[0013] Furthermore, in the first aspect, the determination circuit may be arranged outside the plurality of pixels. This brings about an effect of reducing the circuit scale of the pixel.

[0014] Furthermore, in the first aspect, the determination circuit may compare a determination signal corresponding to the determination value with the high gain signal corresponding to the signal level to generate the determination result.

[0015] Furthermore, in the first aspect, an analog-to-digital converter may be further included that converts both the high-gain signal and the low-gain signal into a digital signal based on a predetermined ramp signal, and the determination circuit may compare the ramp signal with the high-gain signal corresponding to the signal level to generate the determination result. This achieves an effect of reducing the amount of wiring.

[0016] Furthermore, in the first aspect, a coupling circuit may be further included, the pre-stage circuit, the sample-and-hold circuit, and the post-stage circuit may be arranged in each of a plurality of pixels, and the coupling circuit may couple the sample-and-hold circuit of each of a pair of pixels among the plurality of pixels. This brings about an effect of improving resolution.

[0017] Furthermore, in the first aspect, the coupling circuit may select and connect one of the sample-and-hold circuit of each of a pair of pixels arranged in a predetermined direction and the sample-and-hold circuit of each of a pair of pixels arranged in a direction perpendicular to the predetermined direction. This brings about an effect of varying the direction in which resolution is improved.

[0018] Furthermore, in the first aspect, a logic circuit may be further included that combines a frame in which digital signals obtained by converting the high-gain signals are arranged and a frame in which digital signals obtained by converting the low-gain signals are arranged. This brings about an effect of expanding the dynamic range.

[0019] Furthermore, in the first aspect, a post-stage reset transistor may be further included that initializes a predetermined post-stage node when the plurality of capacitor elements are disconnected from the post-stage node, the plurality of capacitor elements may include a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element, the post-stage circuit may read the pixel signal via the post-stage node, and the sample-and-hold circuit may include: the first capacitor element; the second capacitor element; the third capacitor element; the fourth capacitor element;and a selection circuit that sequentially performs control for connecting the first capacitor element to the post-stage node, control for disconnecting the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element from the post-stage node, and control for connecting the third capacitor element to the post-stage node. This achieves a noise-reducing effect.

[0020] Furthermore, a second aspect of the present technology relates to an imaging device including: a front-end circuit that generates an analog signal as a pixel signal; a sample-and-hold circuit that holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements, and generates a low-gain signal obtained by amplifying the pixel signal with a low gain smaller than the high gain and corresponding to a combined capacitance of the plurality of capacitor elements; a back-end circuit that sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit;and a recording unit that records a single image generated from the high-gain signal and the low-gain signal. This achieves an effect of reducing the circuit scale of the imaging device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to a first embodiment of the present technology. Fig. 2 is a block diagram illustrating a configuration example of a solid-state imaging element according to the first embodiment of the present technology. Fig. 3 is a circuit diagram illustrating a configuration example of a pixel according to the first embodiment of the present technology. Fig. 4 is a block diagram illustrating a configuration example of a load MOS circuit block and a column signal processing circuit according to the first embodiment of the present technology. Fig. 5 is a block diagram illustrating a configuration example of a column circuit according to the first embodiment of the present technology. Fig. 6 is a block diagram illustrating a configuration example of a load MOS circuit block and a column signal processing circuit according to a comparative example. Fig. 7 is a timing chart illustrating an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. Fig. 8 is a timing diagram illustrating an example of a global shutter operation according to the first embodiment of the present technology. Fig. 9 is a timing diagram illustrating an example of a read operation according to the first embodiment of the present technology. Fig. 10 is a flowchart illustrating an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. Fig. 11 is a diagram illustrating an example of frame images before and after combination according to the first embodiment of the present technology. Fig. 12 is a circuit diagram illustrating a configuration example of a pixel when three or more gain factors are used according to the first embodiment of the present technology. Fig. 13 is a circuit diagram illustrating a configuration example of a pixel according to a modification example of the first embodiment of the present technology. Fig. 14 is a circuit diagram illustrating another example of a pixel according to a modification example of the first embodiment of the present technology. Fig. 15 is a circuit diagram illustrating a configuration example of a pixel in which the number of transistors is reduced in a modification example of the first embodiment of the present technology. Fig. 16 is a circuit diagram illustrating a configuration example of a pixel according to a second embodiment of the present technology. Fig. 17 is a timing chart illustrating an example of an operation of a solid-state imaging element according to the second embodiment of the present technology. Fig. 18 is a timing chart illustrating an example of a read operation according to the second embodiment of the present technology. Fig. 19 is a timing chart illustrating another example of the read operation according to the second embodiment of the present technology. Fig. 20 is a circuit diagram illustrating a configuration example of a pixel according to a third embodiment of the present technology. Fig. 21 is a block diagram illustrating a configuration example of a column circuit according to the third embodiment of the present technology. Fig. 22 is a timing chart illustrating an example of a read operation according to the third embodiment of the present technology. Fig. 23 is a timing chart illustrating another example of the read operation according to the third embodiment of the present technology. Fig. 24 is a block diagram illustrating a configuration example of a column circuit according to a fourth embodiment of the present technology. Fig. 25 is a timing chart illustrating an example of a read operation according to the fourth embodiment of the present technology. Fig. 26 is a timing chart illustrating another example of the read operation according to the fourth embodiment of the present technology. Fig. 27 is a block diagram illustrating a configuration example of a pixel array unit according to a fifth embodiment of the present technology. Fig. 28 is a circuit diagram illustrating a configuration example of a pixel according to the fifth embodiment of the present technology. Fig. 29 is a circuit diagram illustrating a configuration example of a reduced element pixel according to the fifth embodiment of the present technology. Fig. 30 is a timing chart illustrating an example of an operation of a solid-state imaging element according to the fifth embodiment of the present technology. Fig. 31 is a diagram illustrating an example of frame images before and after pixel interpolation according to the fifth embodiment of the present technology. Fig. 32 is a block diagram illustrating a configuration example of a pixel array unit according to a sixth embodiment of the present technology. Fig. 33 is a circuit diagram illustrating a configuration example of a pixel according to the sixth embodiment of the present technology. Fig. 34 is a diagram illustrating an example of frame images before and after pixel interpolation in a vertical direction according to the sixth embodiment of the present technology. Fig. 35 is a diagram illustrating an example of frame images before and after pixel interpolation in a horizontal direction and the vertical direction according to the sixth embodiment of the present technology. Fig. 36 is a timing diagram illustrating an example of a read operation according to a seventh embodiment of the present technology. Fig. 37 is a circuit diagram illustrating a configuration example of a pixel according to a first modification example of the seventh embodiment of the present technology. Fig. 38 is a timing chart illustrating an example of a global shutter operation according to the first modification example of the seventh embodiment of the present technology. Fig. 39 is a timing chart illustrating an example of a read operation according to the first modification example of the seventh embodiment of the present technology. Fig. 40 is a view illustrating an example of a stacked structure of a solid-state imaging element according to a second modification example of the seventh embodiment of the present technology. Fig. 41 is a circuit diagram illustrating a configuration example of a pixel according to the second modification example of the seventh embodiment of the present technology. Fig. 42 is a view illustrating an example of a stacked structure of a solid-state imaging element according to a third modification example of the seventh embodiment of the present technology. Fig. 43 is a circuit diagram illustrating a configuration example of a pixel according to an eighth embodiment of the present technology. Fig. 44 is a timing diagram illustrating an example of a global shutter operation according to the eighth embodiment of the present technology. Fig. 45 is a circuit diagram illustrating a configuration example of a pixel according to a ninth embodiment of the present technology. Fig. 46 is a diagram for describing a reset execution according to the ninth embodiment of the present technology. Fig. 47 is a diagram for describing level variations caused by a reset execution according to the ninth embodiment of the present technology. Fig. 48 is a timing chart illustrating an example of voltage control according to the ninth embodiment of the present technology. Fig. 49 is a timing diagram illustrating an example of a global shutter operation for odd frames according to a tenth embodiment of the present technology. Fig. 50 is a timing chart illustrating an example of an odd-frame read operation according to the tenth embodiment of the present technology. Fig. 51 is a timing chart illustrating an example of a global shutter operation for even frames according to the tenth embodiment of the present technology. Fig. 52 is a timing chart illustrating an example of an even frame read operation according to the tenth embodiment of the present technology. Fig. 53 is a circuit diagram illustrating a configuration example of a column signal processing circuit according to an eleventh embodiment of the present technology. Fig. 54 is a timing diagram illustrating an example of a global shutter operation according to the eleventh embodiment of the present technology. Fig. 55 is a timing chart illustrating an example of a read operation according to the eleventh embodiment of the present technology. Fig. 56 is a timing chart illustrating an example of a rolling shutter operation according to a twelfth embodiment of the present technology. Fig. 57 is a block diagram illustrating a configuration example of a solid-state imaging element according to a thirteenth embodiment of the present technology. Fig. 58 is a circuit diagram illustrating a configuration example of a dummy pixel, a regulator, and a switching unit according to the thirteenth embodiment of the present technology. Fig. 59 is a timing chart illustrating an example of an operation of the dummy pixel and the controller according to the thirteenth embodiment of the present technology. Fig. 60 is a circuit diagram illustrating a configuration example of an effective pixel according to the thirteenth embodiment of the present technology. Fig. 61 is a timing diagram illustrating an example of a global shutter operation according to the thirteenth embodiment of the present technology. Fig. 62 is a timing chart illustrating an example of a read operation according to the thirteenth embodiment of the present technology. Fig. 63 is a diagram for describing effects according to the thirteenth embodiment of the present technology. Fig. 64 is a block diagram illustrating a schematic configuration example of a vehicle control system. Fig. 65 is an explanatory view illustrating an example of an installation position of an imaging section. METHOD FOR CARRYING OUT THE INVENTION

[0021] Modes for implementing the present technology (hereinafter referred to as embodiments) are described below. The description will be given in the following order. 1. First embodiment (example of connecting multiple capacitor elements) 2. Second Embodiment (Example of connecting multiple capacitor elements according to a determination result within one pixel) 3. Third Embodiment (Example of connecting multiple capacitor elements according to a determination result outside a pixel) 4. Fourth Embodiment (Example of Connecting Multiple Capacitor Elements According to a Determination Result Outside a Pixel Using a Ramp Signal) 5. Fifth Embodiment (Example of connecting respective capacitor elements of a plurality of adjacent pixels) 6. Sixth Embodiment (Example of connecting respective capacitor elements of a plurality of pixels adjacent in a horizontal direction or horizontal direction) 7. Seventh Embodiment (Example of Initializing a Post-Stage Node When a Capacitor Element is Disconnected) 8. Eighth embodiment (example of adding a discharge transistor) 9. Ninth Embodiment (Example of Controlling a Reset Power Supply Voltage) 10. Tenth Embodiment (Example of switching a level held for each frame) 11. Eleventh Embodiment (Example of Suppressing a Black Spot Phenomenon) 12. Twelfth Embodiment (Example of the rolling closure operation) 13. Thirteenth Embodiment (Example in which a pre-stage source follower is turned off during reading) 14. Application example for mobile bodies <1. First Embodiment>[Configuration Example of the Imaging Device]

[0022] Fig. 1 is a block diagram illustrating a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that acquires image data (frames) and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 is assumed to be a digital camera or an electronic device (a smartphone, a PC, or the like) with an imaging function.

[0023] The solid-state imaging element 200 captures individual images under the control of the imaging control unit 130. The solid-state imaging element 200 supplies individual images to the recording unit 120 via a signal line 209.

[0024] The imaging lens 110 focuses light and directs the light to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture individual images. For example, the imaging control unit 130 supplies an imaging control signal including a vertical synchronization signal XVS to the solid-state imaging element 200 via a signal line 139. The recording unit 120 records individual images.

[0025] Here, the vertical synchronization signal XVS is a signal indicating imaging timing, and a periodic signal having a constant frequency (60 Hertz or the like) is used as the vertical synchronization signal XVS.

[0026] Note that although the imaging device 100 records individual images, the individual images may be transmitted outside the imaging device 100. In this case, an external interface for transmitting individual images is further provided. Alternatively, the imaging device 100 may further display individual images. In this case, a display section is further provided. [Configuration example of the solid-state imaging element]

[0027] Fig. 2 is a block diagram illustrating a configuration example of the solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 220, a plurality of pixels 300 are arranged in a two-dimensional grid pattern. Furthermore, each circuit in the solid-state imaging element 200 is provided in, for example, a single semiconductor chip.

[0028] Hereinafter, a set of pixels 300 arranged in a horizontal direction is referred to as a "row" and a set of pixels 300 arranged in a direction perpendicular to the row is referred to as a "column".

[0029] The timing control circuit 212 controls operation timings of each of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal XVS from the imaging control unit 130.

[0030] The DAC 213 generates a sawtooth-shaped ramp signal through digital-to-analog (DA) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0031] The vertical scanning circuit 211 sequentially selects rows and controls them to output analog pixel signals. The pixel 300 photoelectrically converts incident light to generate the analog pixel signal. The pixel 300 supplies a pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0032] In the load MOS circuit block 250, a MOS transistor providing a constant current is provided for each column.

[0033] The column signal processing circuit 260 performs signal processing, such as analog-to-digital (AD) conversion and correlated double sampling (CDS), on the pixel signal for each column. The column signal processing circuit 260 supplies image data (frame) including the processed signals to the recording unit 120. [Pixel configuration example]

[0034] Fig. 3 is a circuit diagram illustrating a configuration example of pixel 300 according to the first embodiment of the present technology. Pixel 300 includes a pre-stage circuit 310, a sample-and-hold circuit 320, a post-stage reset transistor 341, and a post-stage circuit 350.

[0035] The pre-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a floating diffusion (FD) reset transistor 313, an FD 314, a pre-stage amplification transistor 315, and a current source transistor 316.

[0036] The photoelectric conversion element 311 generates charges through photoelectric conversion. The transfer transistor 312 transfers the charges from the photoelectric conversion element 311 to the FD 314 according to a transfer signal trg from the vertical scanning circuit 211.

[0037] The FD reset transistor 313 extracts charges from the FD 314 to initialize the FD 314 according to an FD reset signal rst from the vertical scanning circuit 211. The FD 314 accumulates charges and generates a voltage corresponding to a charge amount. The pre-stage amplification transistor 315 amplifies a voltage level of the FD 314 and outputs the amplified voltage to a pre-stage node 319.

[0038] Furthermore, the FD reset transistor 313 and the pre-stage amplification transistor 315 have their respective sources connected to a power supply voltage VDD. The current source transistor 316 is connected to a drain of the pre-stage amplification transistor 315. The current source transistor 316 provides the current id1 under the control of the vertical scanning circuit 211.

[0039] Sample-and-hold circuit 320 samples and holds a pixel signal. Sample-and-hold circuit 320 includes capacitor elements 321, 322, 323, and 324 and a selection circuit 330.

[0040] The capacitor elements 321 to 324 have their respective one ends commonly connected to the pre-stage node 319 and have their respective other ends connected to the selection circuit 330. Note that the capacitor elements 321, 322, 323, and 324 are examples of a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element described in the claims.

[0041] The selection circuit 330 includes selection transistors 331, 332, 333, and 334. The selection transistor 331 opens and closes a path between the capacitor element 321 and a post-stage node 340 according to a selection signal Φr1 from the vertical scanning circuit 211. The selection transistor 332 opens and closes a path between the capacitor element 322 and a post-stage node 340 according to a selection signal Φr2 from the vertical scanning circuit 211.

[0042] In addition, the selection transistor 333 opens and closes a path between the capacitor element 323 and the post-stage node 340 according to a selection signal Φs1 from the vertical scanning circuit 211. The selection transistor 334 opens and closes a path between the capacitor element 324 and the post-stage node 340 according to a selection signal Φs2 from the vertical scanning circuit 211.

[0043] The post-stage reset transistor 341 initializes a level of the post-stage node 340 to a predetermined potential Vreg according to a post-stage reset signal rstb from the vertical scanning circuit 211. A potential different from the power supply potential VDD (for example, a potential lower than VDD) is set as the potential Vreg.

[0044] The post-stage circuit 350 includes a post-stage amplification transistor 351 and a post-stage selection transistor 352. The post-stage amplification transistor 351 amplifies the level of the post-stage node 340. The post-stage selection transistor 352 outputs a signal having the level amplified by the post-stage amplification transistor 351 to a vertical signal line 309 as a pixel signal according to a post-stage selection signal selb from the vertical scanning circuit 211.

[0045] It is noted that, for example, n-channel metal oxide semiconductor (nMOS) transistors are used as various transistors (transfer transistor 312 and the like) in the pixel 300.

[0046] The vertical scanning circuit 211 supplies a high-level FD reset signal rst and a high-level transfer signal trg to all pixels at the start of an exposure. Accordingly, the photoelectric conversion element 311 is initialized. Hereinafter, this control is referred to as "PD reset."

[0047] Then, the vertical scanning circuit 211 provides a high-level FD reset signal rst for one pulse period, while setting the post-stage reset signal rstb and the selection signal Φr1 to the high level for all pixels immediately before the end of an exposure. Accordingly, the FD 314 is initialized, and a level corresponding to the level of the FD 314 at that time is held in the capacitor element 321. This control is hereinafter referred to as "FD reset." The level of the FD 314 at the time of FD reset is hereinafter referred to as a "P-phase" or "reset level."

[0048] At the end of the exposure, the vertical scanning circuit 211 provides a high-level transfer signal trg throughout the pulse period, while the post-stage reset signal rstb and the selection signal Φs1 are set to the high level for all pixels. Accordingly, signal charges corresponding to an exposure amount are transferred to the FD 314, and a level corresponding to the level of the FD 314 at that time is held in the capacitor element 323. The level of the FD 314 at the time of signal charge transfer is hereinafter referred to as a "D-phase" or a "signal level."

[0049] The exposure control of simultaneously starting and stopping exposure for all pixels in this way is called a global shutter method. Through this exposure control, the pre-stage circuit 310 sequentially generates a reset level and a signal level for all pixels. A level corresponding to the reset level is held in capacitor element 321, and a level corresponding to the signal level is held in capacitor element 323.

[0050] After the end of the exposure, the vertical scanning circuit 211 sequentially selects a line and sequentially outputs the reset level and the signal level of the line. If the reset level is output, the vertical scanning circuit 211 provides a high-level selection signal Φr1 for a predetermined period, while the FD reset signal rst and the post-stage selection signal selb of the selected line are set to the high level. Accordingly, the capacitor element 321 is connected to the post-stage node 340. The level held in the capacitor element 321 corresponds to a level obtained by amplifying the level (reset level) of the FD 314 at the time of FD reset by the pre-stage amplification transistor 315. The analog gain at this amplification is assumed to be G1.

[0051] Next, the vertical scanning circuit 211 provides high-level selection signals Φr1 and Φr2 for a predetermined period, while the FD reset signal rst and the post-stage selection signal selb of the selected row are set to the high level. Accordingly, the capacitor elements 321 and 322 are connected to the post-stage node 340. At this time, since the capacitor elements 321 and 322 are connected in parallel, their combined capacitance becomes larger than that of the capacitor element 321. Therefore, the level held in the coupled capacitor elements 321 and 322 is lower than in a case where only the capacitor element 321 is connected to the post-stage node 340.

[0052] If the capacitance value of capacitor element 321 is assumed to be C1 and the capacitance value of the combined capacitance is assumed to be Cr, the level held in capacitor elements 321 and 322 is a level obtained by amplifying the reset level with an analog gain of G1 × C1 / Cr. Since the combined capacitance Cr is larger than C1, the gain at the time of coupling capacitor elements 321 and 322 is smaller than G1.

[0053] Then, the vertical scanning circuit 211 provides a high-level selection signal Φs1 for a predetermined period, while the FD reset signal rst and the post-stage selection signal selb of the selected row are set to the high level. Accordingly, the capacitor element 323 is connected to the post-stage node 340. The level held in the capacitor element 323 corresponds to a level obtained by amplifying the level (signal level) of the FD 314 at the time of transfer by the pre-stage amplification transistor 315. The analog gain at this amplification is assumed to be G3.

[0054] Next, the vertical scanning circuit 211 provides high-level selection signals Φs1 and Φs2 for a predetermined period, while the FD reset signal rst and the post-stage selection signal selb of the selected row are set to the high level. Accordingly, capacitor elements 323 and 324 are connected to the post-stage node 340. The gain at the time of coupling the capacitor elements 323 and 324 is less than G3.

[0055] Hereinafter, the gain (G1 or G3) when capacitor elements 321 or 323 are connected will be referred to as "high gain." On the other hand, when two capacitor elements (such as capacitor elements 321 and 322) are coupled, the gain is smaller than the high gain and will be referred to as "low gain" hereinafter.

[0056] Furthermore, the pixel signal (reset level or signal level) amplified with a high gain is called a “high gain signal” and the pixel signal amplified with a low gain is called a “low gain signal”.

[0057] The post-stage circuit 350 of the selected row sequentially reads the high gain signal and the low gain signal via the post-stage node 340 and outputs the read high gain signal and low gain signal to the vertical signal line 309.

[0058] Through the control described above, the pre-stage circuit 310 generates an analog pixel signal (reset level or signal level). The sample-and-hold circuit 320 holds a high-gain signal, obtained by amplifying a pixel signal with a predetermined high gain (G1 or G3), in the capacitor elements 321 and 323. Then, the sample-and-hold circuit 320 generates a low-gain signal smaller than the high gain and obtained by amplifying the pixel signal with a low gain (G1 × C1 / Cr or the like) corresponding to the combined capacitance, such as the capacitors 321 and 322. [Configuration example of the column signal processing circuit]

[0059] Fig. 4 is a block diagram illustrating a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0060] In the load MOS circuit block 250, the vertical signal line 309 is wired for each column. If the number of columns is I (I is an integer), I vertical signal lines 309 are wired. Furthermore, a load MOS transistor 251, which provides a constant current id2, is connected to each of the vertical signal lines 309.

[0061] A plurality of column circuits 450 and a logic circuit 460 are arranged in the column signal processing circuit 260. The column circuits 450 are arranged for each column. If the number of columns is assumed to be 1, 1 column circuits 450 are arranged.

[0062] Column circuit 450 performs AD conversion and CDS processing on the analog signal from the corresponding column. Column circuit 450 supplies the processed digital signal to logic circuit 460.

[0063] The logic circuit 460 combines a single image in which digital signals obtained by converting high-gain signals are arranged, and a single image in which digital signals obtained by converting low-gain signals are arranged. The dynamic range can be expanded through this composition, and this composition is referred to as high dynamic range (HDR) composition. Furthermore, the logic circuit 460 performs various types of signal processing, such as white balance correction processing and demosaic processing, on the combined single image as needed. The logic circuit 460 then outputs the processed single image to the recording unit 120. [Column circuit configuration example]

[0064] Fig. Figure 5 is a block diagram illustrating a configuration example of the column circuit 450 according to the first embodiment of the present technology. The column circuit 450 includes an ADC 451, a selector 454, a P-phase latch 455, and a CDS circuit 456.

[0065] The ADC 451 converts an analog signal into a digital signal. This ADC 451 includes a comparator 452 and a counter 453. The analog high-gain signal and the low-gain signal from the corresponding column are input to the ADC 451. Among the high-gain signals, a signal corresponding to the reset level (P-phase level) is assumed to be Ain_P1, and a signal corresponding to the signal level (D-phase level) is assumed to be Ain_D1. Among the low-gain signals, a signal corresponding to the reset level is assumed to be Ain_P2, and a signal corresponding to the signal level is assumed to be Ain_D2.

[0066] Comparator 452 compares a ramp signal RMP from DAC 213 with an analog signal from the corresponding column. Comparator 452 provides a comparison result CMP to counter 453.

[0067] Counter 453 counts a count value over one period until the comparison result CMP is inverted. Counter 453 provides a digital signal indicating the count value to selector 454. Digital signals corresponding to the analog signals Ain_P1, Ain_P2, Ain_D1, and Ain_D2 are assumed to be Dout_P1, Dout_P2, Dout_D1, and Dout_D2.

[0068] The selector 454 switches the output destination of the digital signal under the control of the timing control circuit 212. The selector 454 outputs the digital signals Dout_P1 and Dout_P2 corresponding to the P-phase level to the P-phase latch 455 for latching. Furthermore, the selector 454 supplies the digital signals Dout_D1 and Dout_D2 corresponding to the D-phase level to the CDS circuit 456.

[0069] The P-phase latch 455 temporarily holds the digital signals Dout_P1 and Dout_P2. Since the P-phase latch 455 is provided for each column, the memory in which they are arranged is a line memory for two lines.

[0070] The CDS circuit 456 performs CDS processing to obtain a difference between the reset level and the signal level. The CDS circuit 456 reads the digital signal Dout_P1 from the P-phase latch 455 and obtains a difference from the digital signal Dout_D1. The digital signal of the difference is assumed to be Dout_CDS1. Furthermore, the CDS circuit 456 reads the digital signal Dout_P2 from the P-phase latch 455 and obtains a difference from the digital signal Dout_D2. The digital signal of the difference is assumed to be Dout_CDS2.

[0071] The digital signals Dout_CDS1 and Dout_CDS2 are provided to logic circuit 460. The frame in which the digital signal Dout_CDS1 is located is a frame corresponding to a high gain factor, and the frame in which the digital signal Dout_CDS2 is located is a frame corresponding to a low gain factor. These frames are subjected to HDR composition.

[0072] Here, a configuration in which the sample-and-hold circuit 320 is not provided within the pixel and a frame memory is added is assumed as a comparative example.

[0073] Fig. 6 is a block diagram illustrating a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the comparative example. The logic circuit 460 of the comparative example includes a frame memory 461, a multiplication circuit 462, and an HDR composition unit 463.

[0074] The frame memory 461 holds a frame in which digital signals are arranged after AD conversion and CDS processing.

[0075] The multiplication circuit 462 amplifies each of the digital signals in the frame held in the frame memory 461 with a digital high gain or low gain. Accordingly, two images with different gain factors are generated and supplied to the HDR composing unit 463. The HDR composing unit 463 combines two frames from the multiplication circuit 462.

[0076] In the comparative example where the sample-and-hold circuit 320 is not provided within the pixel, a high-gain signal and a low-gain signal cannot be generated within the pixel. Therefore, the multiplication circuit 462 is required to generate a high-gain signal and a low-gain signal by amplifying a frame with a digital high-gain and low-gain. In this case, the frame memory 461 must hold the digital signal to be amplified.

[0077] On the other hand, if the sample-and-hold circuit 320 is provided with a circuit configuration for each pixel as shown in Fig. As illustrated in Figure 3, each of the pixels can generate and hold a high-gain signal and a low-gain signal. Assuming that the number of pixels is N, a total of N sample-and-hold circuits 320 in all pixels can be considered analog memories capable of holding a single image. Therefore, it is not necessary to provide the frame memory 461 in the subsequent stage of the pixel. As described above, the line memory for holding the P-phase level is required, but the frame memory 461 is unnecessary, so the circuit scale can be reduced compared to the comparative example. [Operation example of the solid-state imaging element]

[0078] Fig. 7 is a timing chart illustrating an example of an operation of the solid-state imaging element 200 according to the first embodiment of the present technology. The vertical scanning circuit 211 exposes all pixels over the exposure period from time T0 to time T1. That is, the pixel array unit 220 is exposed by the global shutter method. At the end of the exposure, the sample-and-hold circuit 320 of each pixel holds a high-gain signal obtained by amplifying the P-phase level and the D-phase level with a high gain. A high-gain signal corresponding to the P-phase level is assumed to be P1, and a high-gain signal corresponding to the D-phase level is assumed to be D1.

[0079] After time T1, the pixel signals are read sequentially for each line. A read period of a certain line is assumed to be from time T2 to time T3.

[0080] During the read period, the sample-and-hold circuit 320 outputs a held high-gain signal P1 in the corresponding row and generates and outputs the low-gain signal P2 by coupling the capacitor elements 321 and 322. Then, the sample-and-hold circuit 320 outputs the held high-gain signal D1 and generates and outputs the low-gain signal D2 by coupling the capacitor elements 323 and 324.

[0081] The ADC 451 in the corresponding row converts each of the analog signals P1, P2, D1, and D2 into a digital signal. The CDS circuit 456 obtains a difference between the digital signal corresponding to P1 and the digital signal corresponding to D1 and supplies the difference to the logic circuit 460. Furthermore, the CDS circuit 456 obtains a difference between the digital signal corresponding to P2 and the digital signal corresponding to D2 and supplies the difference to the logic circuit 460. The logic circuit 460 performs HDR composition.

[0082] Fig. Figure 8 is a timing diagram illustrating an example of a global shutter operation according to the first embodiment of the present technology. This drawing illustrates details of exposure period control in Fig. 7. The vertical scanning circuit 211 sets the post-stage reset signal rstb and the selection signal Φr1 for all lines (in other words, all pixels) to the high level at a time T10 immediately before the start of exposure.

[0083] Furthermore, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and the high-level transfer signal trg to all lines for a period from time T10 to time T11 after the pulse period has elapsed. Accordingly, all pixels are Pd-reset, and exposure begins simultaneously in all lines.

[0084] Here, rst_[n], trg_[n], rstb_[n], Φr1_[n], Φr2_[n], Φs1_[n], and Φs2_[n] in the figure indicate signals for pixels in the nth row among N rows. N is an integer indicating the total number of rows, and n is an integer from 1 to N.

[0085] Then, at a time T12 immediately before the end of the exposure period, the vertical scanning circuit 211 provides a high-level FD reset signal rst throughout the pulse period, while setting the post-stage reset signal rstb and the selection signal Φr1 to the high level for all pixels. Accordingly, the pre-stage circuit 310 generates the reset level for all pixels, and the selection circuit 330 connects only the capacitor element 321 to the post-stage circuit 350. As a result, a signal obtained by amplifying the reset level with a high gain is sampled and held.

[0086] Within the pulse period from time T13 to time T14 at the end of exposure, vertical scanning circuit 211 provides a high-level transfer signal trg, while setting post-stage reset signal rstb and selection signal Φs1 to high levels for all pixels. Accordingly, pre-stage circuit 310 generates the signal level of all pixels, and selection circuit 330 connects only capacitor element 323 to post-stage circuit 350. As a result, the signal obtained by amplifying the signal level with a high gain is sampled and held. The level of pre-stage node 319 decreases by Vsig. Here, Vsig is a net signal level obtained by CDS processing.

[0087] At a time T15 after the time T14, the vertical scanning circuit 211 returns the selection signal Φs1 to the low level and returns the post-stage reset signal rstb to the low level at the later time T16.

[0088] Furthermore, the vertical scanning circuit 211 drives the current source transistors 316 of all rows (all pixels) to supply a current id1. Here, id1_[n] in the drawing indicates a current of pixels in the nth row. The larger the current id, the greater the IR drop, so the current id1 is required to be on the order of a few nanoamperes (nA) to several tens of nanoamperes (nA). On the other hand, the load MOS transistors 251 of all columns are in the off state, and the current id2 is not supplied to the vertical signal line 309.

[0089] Fig. Figure 9 is a timing diagram illustrating an example of a read operation according to the first embodiment of the present technology. This drawing illustrates details of a read period control for one line in Fig. 7.

[0090] During a read period of the nth line, from time T20 to time T26, the vertical scanning circuit 211 sets the FD reset signal rst and the post-stage select signal selb of the nth line to the high level. Furthermore, during the read period, the transfer signals trg of all lines are driven to the low level. Here, selb_[n] in the figure indicates signals to pixels in the nth line.

[0091] The vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb to the n-th row over a predetermined pulse period from a time T20. Accordingly, the level of the post-stage node 340 is initialized.

[0092] Then, within a period from time T21 to time T22, the vertical scanning circuit 211 supplies a high-level selection signal Φr1 to the n-th row, and the selection circuit 330 connects the capacitor element 321 to the post-stage circuit 350 according to this signal. Within this period, a high-gain signal P1 corresponding to the P-phase level is output and converted into a digital signal. Within a period from time T22 to time T23, the vertical scanning circuit 211 supplies high-level selection signals Φr1 and Φr2 to the n-th row, and the selection circuit 330 connects the capacitor elements 321 and 322 to the post-stage circuit 350 according to this signal. Within this period, a low-gain signal P2 corresponding to the P-phase level is generated and converted into a digital signal.

[0093] Next, the vertical scanning circuit 211 supplies a high-level selection signal Φs1 to the n-th row within a period from time T24 to time T25. The level of the post-stage node 340 changes by a net signal level. Within this period, a high-gain signal D1 corresponding to the D-phase level is output and converted into a digital signal. The vertical scanning circuit 211 supplies high-level selection signals Φs1 and Φs2 to the n-th row within a period from time T25 to time T26. Since the gain decreases due to the coupling of the capacitor elements, the level of the post-stage node 340 decreases. Within this period, a low-gain signal D2 corresponding to the D-phase level is generated and converted into a digital signal.

[0094] Furthermore, the vertical scanning circuit 211 controls the current source transistor 316 of the nth row to be read over the period from time T20 to time T26 to provide the current id1. Furthermore, the timing control circuit 212 controls the load MOS transistors 251 of all columns to provide the current id2 within the read period of all rows.

[0095] Fig. 10 is a flowchart illustrating an example of an operation of the solid-state imaging element 200 according to the first embodiment of the present technology. This operation is initiated, for example, if a predetermined application for capturing a single image is executed.

[0096] The vertical scanning circuit 211 in the solid-state imaging element 200 exposes all pixels within the exposure period (step S901) and causes all pixels to sample and hold the high-gain signal (step S902).

[0097] The vertical scanning circuit 211 selects a line to be read and outputs analog signals from P1, P2, D1, and D2 to the selected line. The ADC 451 performs AD conversion on these analog signals (step S903).

[0098] In addition, the CDS circuit 456 performs CDS processing on P1 and D1 and CDS processing on P2 and D2 (step S904). The logic circuit 460 performs HDR composition (step S905).

[0099] The vertical scanning circuit 211 determines whether all rows have been selected (step S906). If there is a row that has not been selected (step S906: No), the solid-state imaging element 200 repeatedly executes step S903 and subsequent steps. If all rows have been selected (step S906: Yes), the solid-state imaging element 200 ends the imaging operation.

[0100] It is noted that if a plurality of frames are continuously captured in synchronization with the vertical synchronization signal XVS, the processing of steps S901 to S906 is repeatedly executed in synchronization with the vertical synchronization signal XVS.

[0101] Fig. 11 is a diagram illustrating an example of frame images before and after combination according to the first embodiment of the present technology. In the drawing, a is an example of frame 501 in which high-gain signals are arranged. In the drawing, b is an example of frame 502 in which low-gain signals are arranged. In the drawing, c is an example of combined frame 503.

[0102] As illustrated in a of the figure, if the magnification factor is large, a phenomenon (so-called "overexposure") is likely to occur in which gradation in a bright part is lost. On the other hand, as illustrated in b of the figure, if the magnification factor is small, a phenomenon (so-called "underexposure") is likely to occur in which gradation in a dark part is lost.

[0103] As illustrated in c of the drawing, a single image 503 with a high dynamic range is obtained by combining the single images 501 and 502 with different gain factors. This prevents overexposure and underexposure from occurring.

[0104] It is noted that in the Fig. 3, amplification factors in two stages of a high gain and a low gain are used, but amplification factors in three or more stages can also be used. If the amplification factor is set to three stages, as in Fig. 12, capacitor elements 325 and 326 and selection transistors 335 and 336 are further provided in the sample and hold circuit 320.

[0105] Capacitor elements 325 and 326 are connected to the pre-stage node 319 in parallel with capacitor elements 321 to 324. Selection transistor 335 opens and closes a path between capacitor element 325 and the post-stage node 340, and selection transistor 336 opens and closes a path between capacitor element 326 and the post-stage node 340. It is sufficient if vertical scanning circuit 211 couples two capacitor elements between a high gain and a low gain when generating a medium gain signal, and couples three capacitor elements when generating a low gain signal. If the gain is set to four or more stages, one capacitor element and one selection transistor are further added according to the number of stages.

[0106] In this way, according to the first embodiment of the present technology, since the sample-and-hold circuit 320 holds the high-gain signal and generates the low-gain signal, a frame buffer is unnecessary when performing HDR composition. Accordingly, the circuit scale of the solid-state imaging element 200 can be reduced. [Modification example]

[0107] In the first embodiment described above, the pixels 300 are arranged with the Fig. 3, but the circuit configuration of the pixels 300 is not limited to those shown in Fig. 3. A solid-state imaging element 200 according to a modification example of the first embodiment differs from the solid-state imaging element 200 of the first embodiment in that a circuit configuration different from that in Fig. 3 is used.

[0108] Fig. 13 is a circuit diagram illustrating a configuration example of a pixel 300 according to a modification example of the first embodiment of the present technology. The pixel 300 according to the modification example of the first embodiment differs from the pixel 300 of the first embodiment in that the post-stage circuit has two systems.

[0109] Post-stage circuits 350-1 and 350-2 are arranged in pixel 300. A post-stage amplification transistor 351-1 and a post-stage selection transistor 352-1 are arranged in post-stage circuit 350-1, and a post-stage selection transistor 352-1 is connected to a vertical signal line 309-1. A post-stage amplification transistor 351-2 and a post-stage selection transistor 352-2 are arranged in post-stage circuit 350-2, and the post-stage selection transistor 352-2 is connected to a vertical signal line 309-2.

[0110] Furthermore, in the sample-and-hold circuit 320, one end of the capacitor element 322 is connected to ground. The selection transistor 332 opens and closes a path between a post-stage node 340-1 and the other end of the capacitor element 322. Furthermore, one end of the capacitor element 324 is connected to ground. The selection transistor 334 opens and closes a path between a post-stage node 340-2 and the other end of the capacitor element 324. With the circuit configuration illustrated in the drawing, it is possible to suppress fluctuations in the level of the post-stage node.

[0111] It is noted that, as in Fig. As illustrated in Figure 14, the selection transistors 331 and 332 can be connected in series between the pre-stage circuit 310 and the post-stage circuit 350. In this case, the capacitor element 321 is inserted between the post-stage node 340 and a ground terminal. The capacitor element 322 is inserted between a connection node of the selection transistors 331 and 332 and a ground terminal. In addition, the selection transistor 333 and the capacitor element 323 are inserted in series between the post-stage node 340 and a ground terminal. The selection transistor 334 and the capacitor element 324 are inserted in series between a connection node of the selection transistors 331 and 332 and a ground terminal.

[0112] Regarding the circuit illustrated in the drawing, reference can be made to the control described in, for example, “Chen Xu et al., A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single-Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications, ISSCC2019”.

[0113] Furthermore, as in Fig. 15 illustrates, a sampling transistor 337 may be disposed in place of the selecting transistors 331 and 333 in the sample-and-hold circuit 320. In this case, the sampling transistor 337 and the capacitor element 321 are connected in series between the pre-stage circuit 310 and the post-stage circuit 350. The capacitor element 322 and the selecting transistor 332 are connected in series between a connection node of the sampling transistor 337 and the capacitor element 321 and the post-stage node 340. The capacitor element 323 is inserted between a connection node of the sampling transistor 337 and the capacitor element 321 and a ground terminal. The capacitor element 324 and the selecting transistor 334 are inserted in series between a connection node of the sampling transistor 337 and the capacitor element 321 and a ground terminal. The number of transistors can be reduced by the circuit configuration illustrated in the drawing.

[0114] Regarding the circuit described in the drawing, reference can be made to the control described in For example, “Jae-kyu Lee, et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3 um-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020”.

[0115] In this way, according to the first modification example of the first embodiment of the present technology, it is possible to suppress the fluctuation of the level of the post-stage node because the post-stage circuit has two systems. <2. Second Embodiment>

[0116] In the first embodiment described above, the sample-and-hold circuit 320 outputs both the high-gain signal D1 and the low-gain signal D2 according to the signal level, but with this configuration, it is difficult to improve the reading speed. A pixel 300 of this second embodiment differs from the pixel 300 of the first embodiment in that one of the high-gain signal D1 and the low-gain signal D2 is output according to the signal level.

[0117] Fig. 16 is a circuit diagram illustrating a configuration example of the pixel 300 according to the second embodiment of the present technology. The pixel 300 of the second embodiment differs from the pixel 300 of the first embodiment in that a determination circuit 338 is further provided.

[0118] The determination circuit 338 determines whether the signal level exceeds a predetermined determination value or not. For example, a comparator is used as the determination circuit 338. A determination signal DC is input to one of two input terminals of the determination circuit 338, and the other is connected to the post-stage node 340. Since the level obtained by amplifying the signal level with the high gain is compared with the determination signal DC, a signal having a value obtained by multiplying the determination value by the high gain is provided as the determination signal DC by the vertical scanning circuit 211. Further, an output terminal of the determination circuit 338 is connected to a gate of the selection transistor 334.

[0119] The vertical scanning circuit 211 provides the determination signal DC at a time when the high-gain signal D1 corresponding to the signal level is output from the post-stage node 340. The determination circuit 338 compares the determination signal DC with the high-gain signal D1. If the high-gain signal D1 is higher than the determination signal DC, that is, if the signal level is higher than the determination value, the determination circuit 338 outputs a high level as the determination result. Accordingly, the low-gain signal D2 is generated by coupling the capacitor elements 323 and 324 and is AD-converted.

[0120] On the other hand, if the high-gain signal D1 is equal to or lower than the determination signal DC, that is, if the signal level is equal to or lower than the determination value, the determination circuit 338 outputs a low level as the determination result. Accordingly, the high-gain signal D1 is AD-converted.

[0121] Furthermore, a vertical signal line 308 is further wired for each column, and the determination result of the determination circuit 338 is supplied to the CDS circuit 456 via the vertical signal line 308.

[0122] Fig. 17 is a timing chart illustrating an example of an operation of a solid-state imaging element 200 according to the second embodiment of the present technology.

[0123] During the read period, the sample-and-hold circuit 320 sequentially outputs the high-gain signal P1 and the low-gain signal P2 in the corresponding row. Then, the sample-and-hold circuit 320 outputs either the high-gain signal D1 or the low-gain signal D2 based on the determination result of the determination circuit 338.

[0124] The ADC 451 in the corresponding row converts each of the analog P1 and P2 and D1 or D2 into a digital signal.

[0125] If it is determined that the signal level is higher than the determination value, the CDS circuit 456 obtains a difference between the digital signal corresponding to P2 and the digital signal corresponding to D2. On the other hand, if it is determined that the signal level is equal to or lower than the determination value, the CDS circuit 456 obtains a difference between the digital signal corresponding to P1 and the digital signal corresponding to D1.

[0126] A frame in which the digital signals subjected to CDS processing are arranged is a frame in which a dynamic range is expanded. Therefore, logic circuit 460 does not need to perform HDR composition.

[0127] Fig. Figure 18 is a timing chart illustrating an example of a read operation according to the second embodiment of the present technology. In the drawing, control until time T24, when the select signal Φs1 becomes high, is similar to that of the first embodiment.

[0128] During a pulse period from immediately after time T24 to time T25, the vertical scanning circuit 211 provides a high-level determination signal DC that is higher than the initial value. The initial value of the determination signal DC is equal to or lower than the level at the time of initialization of the post-stage node 340.

[0129] In the drawing, it is assumed that the determination circuit 338 determines that the high-gain signal D1 corresponding to the signal level is higher than the determination signal DC at time T25. In this case, at time T25, the determination circuit 338 changes the determination result from the low level to the high level, and the selection circuit 330 connects the capacitor elements 323 and 324 to the post-stage circuit 350. Accordingly, the capacitor elements 323 and 324 are coupled, and the low-gain signal D2 is generated and is AD-converted from time T25 to time T26.

[0130] Fig. Figure 19 is a timing diagram illustrating another example of the read operation according to the second embodiment of the present technology. In the drawing, the control up to time T24 is similar to that in Fig. 18.

[0131] In Fig. 19, it is assumed that the determination circuit 338 determines that the high-gain signal D1 corresponding to the signal level is equal to or lower than the determination signal DC at time T25. In this case, the determination result remains at the low level after time T25, and the selection circuit 330 connects only the capacitor element 323 to the post-stage circuit 350. Accordingly, the capacitor elements 323 and 324 are not coupled, and the high-gain signal D1 is output and is AD-converted from time T25 to time T26.

[0132] As in Fig. 18 and Fig. As illustrated in Figure 19, the sample-and-hold circuit 320 outputs either the high-gain signal D1 or the low-gain signal D2 according to the signal level. Therefore, the ADC 451 only needs to perform AD conversion on one of D1 and D2, and the reading speed can be improved compared to the first embodiment in which AD conversion is performed on both D1 and D2. Furthermore, since the logic circuit 460 does not need to perform HDR composition processing, the processing load of the logic circuit 460 can be reduced.

[0133] It is noted that a modification example of the first embodiment can be applied to the second embodiment.

[0134] In this way, according to the second embodiment of the present technology, the reading speed can be improved compared to the first embodiment because the sample-and-hold circuit 320 outputs either the high-gain signal D1 or the low-gain signal D2 according to the signal level. <3. Third Embodiment>

[0135] In the second embodiment described above, the determination circuit 338 is arranged in the pixel, but with this configuration, the circuit scale of the pixel increases compared to a case where the determination circuit 338 is not arranged in the pixel. A solid-state imaging element 200 of this third embodiment differs from the solid-state imaging element 200 of the second embodiment in that a determination circuit is arranged outside the pixel.

[0136] Fig. 20 is a circuit diagram illustrating a configuration example of a pixel 300 according to the third embodiment of the present technology. The pixel 300 of the third embodiment differs from the pixel 300 of the second embodiment in that the determination circuit 338 is not provided. Furthermore, a feedback signal FB is input from the vertical signal line 308 to the gate of the selection transistor 334 of the third embodiment.

[0137] Fig. 21 is a block diagram illustrating a configuration example of a column circuit 450 according to the third embodiment of the present technology. The column circuit 450 of the third embodiment differs from the column circuit 450 of the second embodiment in that a determination circuit 457 is further arranged. For example, a comparator is used as the determination circuit 457.

[0138] The determination circuit 457 determines whether the signal level is higher than a determination value. One of two input terminals of the determination circuit 457 is connected to the vertical signal line 309, and the determination signal DC from the timing control circuit 212 is input to the other. The determination signal DC is provided at a time when the analog signal Ain_D1 corresponding to the signal level is output from the vertical signal line 309.

[0139] The determination circuit 457 compares the analog signal Ain_D1 with the determination signal DC and determines whether the analog signal Ain_D1 is higher than the determination signal DC (i.e., the signal level is higher than the determination value). The determination circuit 457 outputs a signal indicating the determination result to the sample-and-hold circuit 320 via the vertical signal line 308 as a feedback signal FB. Furthermore, the determination circuit 457 also supplies the feedback signal FB to the CDS circuit 456.

[0140] Fig. 22 and Fig. 23 are timing diagrams illustrating an example of a read operation according to the third embodiment of the present technology. Fig. 22 is a timing chart in a case where it is determined that the signal level is higher than the determination value, and Fig. 23 is a timing chart in a case where the signal level is determined to be equal to or lower than the determination value.

[0141] As in Fig. 22 and Fig. 23, in the third embodiment, the pulse width of the determination signal DC is set to a value larger than that in the second embodiment.

[0142] In this way, according to the third embodiment of the present technology, because the determination circuit 457 is arranged outside the pixel, the circuit scale of the pixel can be reduced compared to the second embodiment in which the determination circuit 338 is arranged in the pixel. <4. Fourth Embodiment>

[0143] In the third embodiment described above, the determination circuit 457 compares the determination signal DC with the analog signal Ain_D1 according to the signal level, but in this configuration, it is necessary to wire a signal line for transmitting the determination signal DC. A solid-state imaging element 200 of this fourth embodiment differs from the solid-state imaging element 200 of the third embodiment in that a ramp signal RMP is input to the determination circuit 457 instead of the determination signal DC.

[0144] Fig. 24 is a block diagram illustrating a configuration example of a column circuit 450 according to the fourth embodiment of the present technology. The column circuit 450 of the fourth embodiment differs from the column circuit 450 of the third embodiment in that the ramp signal RMP from the DAC 213 is input to the determination circuit 457 instead of the determination signal DC. The maximum value of the ramp signal RMP is set to a value corresponding to the determination value.

[0145] The determination circuit 457 of the fourth embodiment compares the analog signal Ain_D1 with the ramp signal RMP and determines whether the analog signal Ain_D1 is higher than the ramp signal RMP (that is, the signal level is higher than the determination value). Since the determination circuit 457 compares the high gain signal (Ain_D1), which corresponds to the signal level, with the ramp signal RMP, the wiring for transmitting the determination signal DC becomes unnecessary, and the wiring can be reduced.

[0146] Fig. 25 and Fig. 26 are timing diagrams illustrating an example of a read operation according to the fourth embodiment of the present technology. Fig. 25 is a timing chart in a case where it is determined that the signal level is higher than the determination value, and Fig. 26 is a timing chart in a case where the signal level is determined to be equal to or lower than the determination value.

[0147] As in Fig. 25 and Fig. As illustrated in Figure 26, during the conversion period of the high-gain signal P1 and the low-gain signal P2, the DAC 213 changes the ramp signal RMP to a sawtooth waveform over time. Furthermore, even within the determination period from time T24 to time T25, the DAC 213 changes the ramp signal RMP over time.

[0148] In this way, according to the fourth embodiment of the present technology, since the determination circuit 457 compares the high gain signal corresponding to the signal level with the ramp signal RMP, the number of wires for transmitting the determination signal DC can be reduced. <5. Fifth Embodiment>

[0149] In the first embodiment described above, the solid-state imaging element 200 performs HDR composition processing using the high-gain signal and the low-gain signal. However, signal processing other than HDR composition processing may be performed using these signals. A solid-state imaging element 200 of this fifth embodiment differs from the solid-state imaging element 200 of the first embodiment in that processing for improving resolution is performed.

[0150] Fig. 27 is a block diagram illustrating a configuration example of a pixel array unit 220 according to the fifth embodiment of the present technology. In the pixel array unit 220, for example, red (R), green (G), and blue (B) pixels are arranged in a Bayer array. Further, two pixels of the same color that are adjacent in the horizontal direction are connected by two signal lines. For example, R pixels 300-1 and 300-2 that are adjacent in the horizontal direction are connected. R pixels 300-3 and 300-4 that are adjacent in the horizontal direction are also connected. Similarly, for B and G, two pixels of the same color that are adjacent in the horizontal direction are connected. In the drawing, signal lines connecting B and G pixels are omitted for ease of description.

[0151] Fig. 28 is a circuit diagram illustrating a configuration example of pixels 300-1 and 300-2 according to the fifth embodiment of the present technology. Pixel 300-1 includes a pre-stage circuit 310-1, a sample-and-hold circuit 320-1, a post-stage circuit 350-1, and a coupling circuit 470-1. Pixel 300-2 includes a pre-stage circuit 310-2, a sample-and-hold circuit 320-2, a post-stage circuit 350-2, and a coupling circuit 470-2. Furthermore, pixels 300-1 and 300-2 further include a post-stage reset transistor 341, but the post-stage reset transistor 341 is omitted from the drawing for ease of description.

[0152] The coupling circuits 470-1 and 470-2 couple the sample-and-hold circuit 320-1 and the sample-and-hold circuit 320-2 in parallel according to a selection signal SELh from the vertical scanning circuit 211.

[0153] Coupling circuit 470-1 includes selectors 471 and 472. Selector 471 opens and closes a path between post-stage node 340-1 of pixel 300-1 and coupling circuit 470-2 according to selection signal SELh. Selector 472 opens and closes a path between pre-stage node 319-1 of pixel 300-1 and coupling circuit 470-2 according to selection signal SELh. The circuit configuration of coupling circuit 470-2 is similar to that of coupling circuit 470-1.

[0154] When the low-gain signal is generated, the vertical scanning circuit 211 controls the coupling circuits 470-1 and 470-2 to couple the sample-and-hold circuit 320-1 and the sample-and-hold circuit 320-2 in parallel. Furthermore, at this time, the vertical scanning circuit 211 controls the two selection transistors (selection transistors 331 and 332, and the like) to be in a closed state as needed. Through these controls, the plurality of capacitor elements are connected in parallel, and a low-gain signal is generated.

[0155] It is noted that, as in Fig. As illustrated in Figure 29, in the fifth embodiment, the capacitor element and the selection transistor in the sample-and-hold circuit 320-1 can be reduced by half. Even in this case, a low-gain signal can be generated by coupling the sample-and-hold circuits 320-1 and 320-2.

[0156] In addition, two pixels adjacent in the horizontal direction are connected, but three or more pixels can be connected. Furthermore, pixels adjacent in the horizontal direction are not connected, and instead, multiple pixels adjacent in the vertical direction can be connected.

[0157] Fig. 30 is a timing diagram illustrating an example of an operation of a solid-state imaging element 200 according to the fifth embodiment of the present technology. The pixel array unit 220 is exposed using the global shutter method. At the end of the exposure, each sample-and-hold circuit 320 of the pixel holds a high-gain signal P1 corresponding to the P-phase level and a high-gain signal D1 corresponding to the D-phase level.

[0158] After time T1, the pixel signals are read sequentially for each row. A read period of a certain row is assumed to be from time T2 to time T3. During this read period, the sample-and-hold circuit 320 outputs the held high-gain signals P1 and D1 in the corresponding row. The ADC 451 performs AD conversion on these analog signals, and the CDS circuit 456 performs CDS processing.

[0159] Then, the vertical scanning circuit 211 couples the sample-and-hold circuits of the two pixels adjacent in the horizontal direction to generate low-gain signals P2 and D2. The sample-and-hold circuit 320 in the corresponding row outputs the generated low-gain signals P2 and D2. The ADC 451 performs AD conversion on these analog signals, and the CDS circuit 456 performs CDS processing.

[0160] The result of CDS processing on the high-gain signals P1 and D1 corresponds to each pixel signal of two adjacent pixels. The result of CDS processing on the low-gain signals P2 and D2 corresponds to the average value of the respective pixel signals of the two adjacent pixels. Logic circuit 460 performs pixel interpolation processing to interpolate a pixel signal between two adjacent pixels using the average value. This processing improves the resolution in the horizontal direction. This interpolation processing is also called super-resolution processing.

[0161] Fig. 31 is a diagram illustrating an example of frame images before and after pixel interpolation according to the fifth embodiment of the present technology. In the drawing, a illustrates an example of frame 504 before pixel interpolation. In the drawing, b illustrates an example of frame 505 after pixel interpolation. As illustrated in b of the drawing, the resolution in the horizontal direction is improved by pixel interpolation compared to a of the drawing.

[0162] In this way, according to the fifth embodiment of the present technology, since the coupling circuit 470-1 couples the sample-and-hold circuits of the two pixels adjacent in the horizontal direction, the resolution in the horizontal direction can be improved by the pixel interpolation processing. <6. Sixth Embodiment>

[0163] In the fifth embodiment described above, the sample-and-hold circuits of two pixels adjacent in the horizontal direction are coupled, but the coupling direction and the number of pixels can be made variable. A solid-state imaging element 200 of this sixth embodiment differs from the solid-state imaging element 200 of the fifth embodiment in that the coupling direction is variable.

[0164] Fig. 32 is a block diagram illustrating a configuration example of a pixel array unit 220 according to the sixth embodiment of the present technology. In the sixth embodiment, in addition to the horizontal direction, two pixels of the same color that are adjacent in the vertical direction are further connected.

[0165] For example, R pixels 300-1 and 300-2, which are adjacent in the horizontal direction, are connected, and R pixels 300-1 and 300-3, which are adjacent in the vertical direction, are connected. Similarly, for B and G, two pixels of the same color that are adjacent in the horizontal and vertical directions are connected. In the drawing, signal lines connecting B and G pixels are omitted for ease of explanation.

[0166] Fig. 33 is a circuit diagram illustrating a configuration example of pixels according to the sixth embodiment of the present technology. Pixel 300-3 includes a pre-stage circuit 310-3, a sample-and-hold circuit 320-3, a post-stage circuit 350-3, and a coupling circuit 470-3. Furthermore, the post-stage reset transistor 341 is omitted from the drawing for ease of description.

[0167] In the coupling circuit 470-1, the selector 471 connects the connection destination of the post-stage node 340-1 to one of the sample-and-hold circuit 320-1, the sample-and-hold circuit 320-3, and a predetermined node according to a selection signal SELhv. When connected to a predetermined node, the post-stage node 340-1 is disconnected from the sample-and-hold circuits 320-1 and 320-3. The selector 472 connects the connection destination of the front-stage node 319-1 to one of the sample-and-hold circuit 320-1, the sample-and-hold circuit 320-3, and a predetermined node according to the selection signal SELhv.

[0168] With the circuit configuration shown in the drawing, the vertical scanning circuit 211 can control the coupling direction to either the horizontal direction or the horizontal direction. In the case of coupling in the vertical direction, the resolution in the vertical direction can be improved through pixel interpolation. Furthermore, if both the horizontal and vertical directions are sequentially coupled, the resolution in both the horizontal and vertical directions can be improved through pixel interpolation.

[0169] It is noted that the number of pixels to be coupled is fixed to two pixels, but the number of pixels to be coupled can be made variable.

[0170] Fig. 34 is a diagram illustrating an example of frame images before and after pixel interpolation in the vertical direction according to the sixth embodiment of the present technology. In the drawing, a is a diagram illustrating an example of frame 504 before pixel interpolation. In the drawing, b is a diagram illustrating an example of frame 506 on which pixel interpolation processing in the vertical direction has been performed. As illustrated in b of the drawing, the resolution in the vertical direction is improved by pixel interpolation compared to a of the drawing.

[0171] Fig. 35 is a diagram illustrating an example of frame images before and after pixel interpolation in the horizontal direction and the vertical direction according to the sixth embodiment of the present technology. In the drawing, a is a diagram illustrating an example of a frame 504 before pixel interpolation. In the drawing, b is a diagram illustrating an example of a frame 507 on which pixel interpolation processing has been performed in the horizontal direction and the vertical direction. As illustrated in b of the drawing, the resolution in the horizontal direction and the vertical direction is improved by the pixel interpolation compared to a of the drawing.

[0172] In this way, according to the sixth embodiment of the present technology, since the coupling circuit 470-1 couples the sample-and-hold circuit 320-1 to one of the sample-and-hold circuits 320-2 and 320-3, it is possible to change the direction of improvement in resolution. <7. Seventh Embodiment>

[0173] In the first embodiment described above, the vertical scanning circuit 211 initializes the post-stage node 340 and then sets the selection signal Φr1 to a high level, but the control is not limited to this. A vertical scanning circuit 211 of this seventh embodiment differs from the vertical scanning circuit 211 of the first embodiment in that the selection signal Φr1 is set to a high level and then the post-stage node 340 is initialized.

[0174] Fig. 36 is a timing chart illustrating an example of a read operation according to the seventh embodiment of the present technology. During a read period of the nth row from time T10 to time T17, the vertical scanning circuit 211 sets the FD reset signal rst and the post-stage selection signal selb of the nth row to the high level. Furthermore, during the reset period, the post-stage reset signal rstb of all rows is driven to the low level.

[0175] The vertical scanning circuit 211 supplies a high-level selection signal Φr1 to the n-th line over a period from a time T11 immediately after the time T10 to a time T13.

[0176] The vertical scan circuit 211 supplies a high-level post-stage reset signal rstb to the n-th row over the pulse period from a time T14 immediately after the time T13. Accordingly, if a parasitic capacitance is present in the post-stage node 340, the history of the previous signal held in the parasitic capacitance can be erased. The vertical scan circuit 211 supplies a high-level selection signal Φs1 to the n-th row over a period from a time T15 immediately after the initialization of the post-stage node 340 to a time T17.

[0177] Through the control illustrated in the drawing, the selected row selection circuit 330 sequentially performs control for connecting the capacitor element 321 to the post-stage node 340, control for disconnecting the capacitor elements 321 to 324 from the post-stage node 340, and control for connecting the capacitor element 323 to the post-stage node 340. Furthermore, when the capacitor elements 321 to 324 are disconnected from the post-stage node 340, the post-stage reset transistor 341 of the selected row initializes the level of the post-stage node 340.

[0178] By disconnecting the capacitor elements 321 to 324 at the time of driving the post-stage reset transistor 341, kTC noise generated at that time can be reduced. This can improve the image quality of the frame.

[0179] It is noted that any of the first to sixth embodiments can be applied to the seventh embodiment.

[0180] In this way, according to the seventh embodiment of the present technology, since the post-stage reset transistor 341 initializes the post-stage node 340 when the capacitor elements 321 to 324 are disconnected from the post-stage node 340, kTC noise can be reduced. [First modification example]

[0181] In the seventh embodiment described above, the pre-stage circuit 310 reads a signal, and the pre-stage circuit 310 is connected to the pre-stage node 319, but this configuration cannot block noise from the pre-stage circuit 319 during reading. A pixel 300 of a first modification example of the seventh embodiment differs from the pixel 300 of the seventh embodiment in that a transistor is inserted between the pre-stage circuit 310 and the pre-stage node 319.

[0182] Fig. 37 is a circuit diagram illustrating a configuration example of the pixel 300 according to the first modification example of the seventh embodiment of the present technology. The pixel 300 of the first modification example of the seventh embodiment differs from the pixel 300 of the first embodiment in that a pre-stage reset transistor 327 and a pre-stage selection transistor 328 are further provided. Furthermore, the power supply voltage of the pre-stage circuit 310 and the post-stage circuit 350 of the first modification example of the seventh embodiment is denoted as VDD1.

[0183] The post-stage reset transistor 327 initializes the level of the pre-stage node 319 with a power supply voltage VDD2. It is desirable that the power supply voltage VDD2 be set to a value that satisfies the following expression. VDD2=VDD1−Vgs In the above expression, Vgs is a gate-source voltage of the pre-stage amplification transistor 315.

[0184] Setting the value that satisfies Expression 1 enables a reduction in the potential variations between the pre-stage node 319 and the post-stage node 340 in the dark. This makes it possible to improve photoresponse non-uniformity (PRNU).

[0185] The pre-stage selection transistor 328 opens and closes a path between the pre-stage circuit 310 and the pre-stage node 319 according to a pre-stage selection signal sel from the vertical scanning circuit 211.

[0186] Fig. 38 is a timing chart illustrating an example of a global shutter operation according to the first modification example of the seventh embodiment of the present technology. The timing chart of the first modification example of the seventh embodiment differs from the timing chart of the seventh embodiment in that the vertical scanning circuit 211 further provides a pre-stage reset signal rsta and the pre-stage selection signal sel. In the drawings, rsta_[n] and sel_[n] indicate signals to pixels in the nth row.

[0187] The vertical scanning circuit 211 supplies a high-level pre-stage selection signal sel to all pixels over a period from a time T2 immediately before the end of an exposure to a time T5. The pre-stage reset signal rsta is driven to a low level.

[0188] Fig. 39 is a timing diagram illustrating an example of a read operation according to the first modification example of the first embodiment of the present technology. During the reading of each line, the pre-stage selection signal sel is driven to a low level. With this control, the pre-stage selection transistor 328 becomes open, and the pre-stage node 319 is disconnected from the pre-stage circuit 310. This allows noise from the pre-stage node 319 to be blocked during reading.

[0189] Furthermore, the vertical scanning circuit 211 supplies a high-level pre-stage reset signal rsta to the n-th line during the read period of the n-th line from a time T10 to a time T17.

[0190] Furthermore, during reading, the vertical scanning circuit 211 controls the current source transistors 316 of all pixels to stop supplying current id1. Current id2 is supplied in a manner similar to the first embodiment. Thus, the control of current id1 is simplified compared to the first embodiment.

[0191] In this way, according to the first modification example of the seventh embodiment of the present technology, it is possible to block noise from the pre-stage circuit 310 because the pre-stage selection transistor 328 turns into the open state during reading to disconnect the pre-stage circuit 310 from the pre-stage node 319. [Second modification example]

[0192] In the seventh embodiment described above, the circuits in the solid-state imaging element 200 are provided in a single semiconductor chip, but there is a possibility that this configuration may prevent the elements from fitting into the semiconductor chip if the pixel 300 is miniaturized. A solid-state imaging element 200 of a second modification example of the seventh embodiment differs from the solid-state imaging element 200 of the first embodiment in that the circuits in the solid-state imaging element 200 are distributed among two semiconductor chips.

[0193] Fig. 40 is a view illustrating an example of a stacked structure of the solid-state imaging element 200 according to the second modification example of the seventh embodiment of the present technology. The solid-state imaging element 200 of the seventh modification example of the second embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that the connection may be performed using a via or a bump in addition to the Cu-Cu bonding.

[0194] An upper pixel array unit 221 is arranged in the upper pixel chip 201. A lower pixel array unit 222 and a column signal processing circuit 260 are arranged in the lower pixel chip 202. For each pixel in the pixel array unit 220, a portion of the pixel is arranged in the upper pixel array unit 221, and the remainder is arranged in the lower pixel array unit 222.

[0195] Furthermore, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are also arranged in the lower pixel chip 202. These circuits are omitted from the drawing.

[0196] Furthermore, the upper pixel chip 201 is manufactured, for example, by a pixel-dedicated process, and the lower pixel chip 202 is manufactured, for example, by a complementary MOS (CMOS) process.

[0197] Fig. 41 is a circuit diagram illustrating a configuration example of the pixel 300 according to the second modification example of the seventh embodiment of the present technology. In the pixel 300, the pre-stage circuit 310 is arranged in the upper pixel chip 201, and the other circuits and elements (such as the capacitor elements 321 and 322) are arranged in the lower pixel chip 202. Note that the current source transistor 316 may be further arranged in the lower pixel chip 202. As illustrated in the drawing, dispersing the elements in the pixel 300 in the upper pixel chip 201 and the lower pixel chip 202, which are stacked on top of each other, allows for a reduction in the pixel area, thereby enabling pixel miniaturization.

[0198] In this way, according to the second modification example of the seventh embodiment of the present technology, pixel miniaturization is enabled because the circuits and elements in the pixel 300 are distributed in the two semiconductor chips. [Third modification example]

[0199] In the second modification example of the seventh embodiment described above, part of the pixel 300 and the peripheral circuits (such as the column signal processing circuit 260) are provided in the lower pixel chip 202 on the lower side. However, with this configuration, the arrangement area of ​​the circuits and elements on the lower pixel chip 202 side due to the peripheral circuit is larger than the arrangement area of ​​the upper pixel chip 201, and there is a possibility that unnecessary space without circuits and elements is generated in the upper pixel chip 201. A solid-state imaging element 200 of a third modification example of the seventh embodiment differs from the solid-state imaging element 200 of the second modification example of the seventh embodiment in that the circuits in the solid-state imaging element 200 are distributed among three semiconductor chips.

[0200] Fig. 42 is a view illustrating an example of a stacked structure of the solid-state imaging element 200 according to the third modification example of the seventh embodiment of the present technology. The solid-state imaging element 200 of the third modification example of the seventh embodiment includes the upper pixel chip 201, the lower pixel chip 202, and a circuit chip 203. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. Note that the connection may be performed using a via or a bump in addition to the Cu-Cu bonding.

[0201] An upper pixel array unit 221 is arranged in the upper pixel chip 201. The lower pixel array unit 222 is arranged in the lower pixel chip 202. For each pixel in the pixel array unit 220, a portion of the pixel is arranged in the upper pixel array unit 221, and the remainder is arranged in the lower pixel array unit 222.

[0202] Furthermore, the column signal processing circuit 260, the vertical scanning circuit 211, the timing control circuit 212, the DAC 213, and the load MOS circuit block 250 are arranged in the circuit chip 203. Circuits other than the column signal processing circuit 260 are omitted from the drawing.

[0203] Using the three-layer configuration, as illustrated in the drawing, enables a reduction in unused space and further pixel miniaturization compared to the two-layer configuration. Furthermore, the lower pixel chip 202, which is the second layer, can be manufactured using a dedicated process for the capacitor and switch.

[0204] In this way, in the third modification example of the seventh embodiment of the present technology, since the circuits in the solid-state imaging element 200 are distributed in the three semiconductor chips, the pixel can be further miniaturized compared to a case where the circuits are distributed in the two semiconductor chips. <8. Eighth Embodiment>

[0205] In the seventh embodiment described above, the reset level is sampled and held during the exposure period, but this configuration prevents the exposure period from being shorter than the sample-and-hold period of the reset level. A solid-state imaging element 200 of this eighth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that a transistor that discharges charges from a photoelectric conversion element is added to shorten the exposure period.

[0206] Fig. 43 is a circuit diagram illustrating a configuration example of a pixel 300 according to the eighth embodiment of the present technology. The pixel 300 of the eighth embodiment differs from the pixel 300 of the seventh embodiment in that a discharge transistor 317 is further provided in the pre-stage circuit 310.

[0207] The discharge transistor 317 functions as an overflow drain that discharges charges from the photoelectric conversion element 311 according to a discharge signal ofg from the vertical scanning circuit 211. For example, nMOS transistors are used as the discharge transistor 317.

[0208] In a configuration where the discharge transistor 317 is not provided, as in the seventh embodiment, blooming may occur when charges are transferred from the photoelectric conversion element 311 for all pixels to the FD 314. Then, at the time of FD reset, the potential of the FD 314 and the potential of the pre-stage node 319 drop. In response to the potential drop, a charge and discharge current of the capacitor element 321 or the like continues to occur, and an IR drop of the power supply or the ground changes from a steady state without blooming.

[0209] On the other hand, at the time of sampling and holding the signal levels of all pixels, after the signal charges are transferred, the photoelectric conversion element 311 has no charge, so blooming does not occur. An IR drop from the power supply or ground will enter the steady state without blooming. Stripe noise occurs due to a difference in the IR drop between the reset level and the signal level at the time of sampling and holding.

[0210] On the other hand, in the eighth embodiment, in which the discharge transistor 317 is provided, the charges in the photoelectric conversion element 311 are discharged to the overflow drain. Therefore, IR drops at the time of sampling and holding the reset level and the signal level become almost identical, so it is possible to suppress streaking noise.

[0211] Fig. 44 is a timing chart illustrating an example of a global shutter operation according to the second embodiment of the present technology. At a time T0 before the start of an exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst to all pixels for the pulse period, while setting the discharge signal ofg to the high level for all pixels. Accordingly, PD reset and FD reset are performed for all pixels. Further, the reset level is sampled and held. Here, ofg_[n] in the drawing indicates signals to pixels in the nth row of the N rows.

[0212] Then, at time T1, which is the start of an exposure, the vertical scanning circuit 211 returns the discharge signal ofg for all pixels to the low level. Then, the vertical scanning circuit 211 supplies a high-level transfer signal trg to all pixels for a period from time T2 immediately before the end of an exposure to time T3 at the end of the exposure. Accordingly, the signal level is sampled and held.

[0213] In a configuration where the discharge transistor 317 is not provided, as in the seventh embodiment, both the transfer transistor 312 and the FD reset transistor 313 must be turned on at the beginning of an exposure (i.e., at the time of PD reset). With this control, at the time of PD reset, the FD 314 must also be reset at the same time. Therefore, it is necessary to perform the FD reset again within the exposure period and sample and hold the reset level, and the exposure period cannot be made shorter than the sample and hold period of the reset level. When sampling and holding the reset levels of all pixels, a certain waiting time is required until the voltage or current stabilizes, and a sample and hold period of, for example, several microseconds (µs) to several tens of microseconds (µs) is required.

[0214] On the other hand, in the eighth embodiment, in which the discharge transistor 317 is provided, the PD reset and the FD reset can be performed separately. Therefore, as illustrated in the drawing, it is possible to sample and hold the reset level by performing the FD reset before the PD reset is canceled (the start of an exposure). This makes it possible to make the exposure period shorter than the reset level holding period.

[0215] It is noted that the first to third modification examples of the seventh embodiment can also be applied to the eighth embodiment.

[0216] In this way, according to the eighth embodiment of the present technology, it is possible to sample and hold the reset level by performing FD reset before the start of an exposure because the discharge transistor 317 that discharges charges from the photoelectric conversion element 311 is provided. This allows the exposure period to be made shorter than the holding period of the reset level. <9. Ninth Embodiment>

[0217] In the seventh embodiment described above, the FD 314 is initialized with the power supply voltage VDD, but there is a possibility that this configuration may cause photoresponse non-uniformity (PRNU) deterioration due to variations in the capacitor elements 321 to 324 or parasitic capacitance. A solid-state imaging element 200 of this ninth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that the PRNU is improved by reducing the power supply to the FD reset transistor 313 during reading.

[0218] Fig. 45 is a circuit diagram illustrating a configuration example of a pixel 300 according to the ninth embodiment of the present technology. The pixel 300 of the ninth embodiment differs from the pixel 300 of the first embodiment in that the power supply of the FD reset transistor 313 is separated from the power supply voltage VDD of the pixel 300.

[0219] The FD reset transistor 313 of the ninth embodiment has a drain connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by, for example, the timing control circuit 212.

[0220] Here, deterioration of the PRNU in the pixel 300 of the seventh embodiment will be described with reference to Fig. 46 and Fig. 47. In the seventh embodiment, as shown in Fig. As illustrated in Figure 46, at a time T0 immediately before the start of an exposure, the potential of the FD 314 decreases due to a reset operation of the FD reset transistor 313. This variation is referred to as Vft.

[0221] In the seventh embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 at time T0 varies from VDD to VDD - Vft. Furthermore, the potential of the pre-stage node 319 during one exposure becomes VDD - Vft - Vsig.

[0222] Furthermore, in the first embodiment, as in Fig. As illustrated in Figure 47, the FD reset transistor 313 enters the on-state during reading to fix the FD 314 to the power supply voltage VDD. The potential of the pre-stage node 319 and the potential of the post-stage node 340 during reading are shifted upward by approximately the variation Vft of the FD 314. However, due to variations in the capacitance values ​​of the capacitor elements 321 and 322 or parasitic capacitance, the amount of shift voltage varies for each pixel, causing deterioration of the PRNU.

[0223] The transition amount of the post-stage node 340, if the pre-stage node 319 transitions by Vft, is expressed by, for example, the following expression. {(Cs+δCs) / (Cs+δCs+Cp)}∗Vft In the above expression, Cs is a capacitance value of the capacitor element 323 on the signal level side, and δCs is a variation of Cs. Cp is a capacitance value of the parasitic capacitance of the post-stage node 340.

[0224] Expression 2 can be approximated by the following expression. {1−(δCs / CS)∗(Cp / Cs)}∗Vft

[0225] From Expression 3, the variations of the post-stage node 340 can be expressed by the following expression. {(δCs / Cs)*(Cp / Cs)}*Vft

[0226] If (δCs / Cs) is set to 10 -2 is set, (Cp / Cs) to 10 -1 and Vft is set to 400 millivolts (mV), PRNU is 400 µVrms according to Expression 4, which is a relatively large value.

[0227] In particular, to reduce kTC noise during sample-and-hold of an input conversion capacitance, it is necessary to increase the charge-to-voltage conversion efficiency of the FD 314. To increase the charge-to-voltage conversion efficiency, it is necessary to increase the capacitance of the FD 314, but the smaller the capacitance of the FD 314, the larger the variation Vft, which may be several hundred millivolts (mV). In this case, a PRNU influence according to Expression 4 may not be negligible.

[0228] Fig. 48 is a timing chart illustrating an example of voltage control according to the ninth embodiment of the present technology.

[0229] The timing control circuit 212 performs control to cause the reset power supply voltage VRST for the row-by-row read period after a time T9 to be different from the reset power supply voltage VRST for the exposure period.

[0230] For example, during the exposure period, the timing control circuit 212 sets the reset power supply voltage VRST to be identical to the power supply voltage VDD. On the other hand, during the read period, the timing control circuit 212 decreases the reset power supply voltage VRST to VDD - Vft. That is, during the read period, the timing control circuit 212 decreases the reset power supply voltage VRST by an amount approximately equal to the variation in Vft caused by a reset execution. Through this control, the reset level of the FD 314 can be made the same during exposure and during read.

[0231] Controlling the reset power supply voltage VRST, as illustrated in the drawing, enables reduction of variations in the voltage of the FD 314 and the pre-stage node 319. Therefore, it is possible to suppress variations in the capacitor elements 321 and 322 and deterioration of the PRNU due to parasitic capacitance.

[0232] It is noted that the first to third modification examples of the seventh embodiment or the eighth embodiment can also be applied to the ninth embodiment.

[0233] In this way, according to the ninth embodiment of the present technology, since the timing control circuit 212 reduces the reset power supply voltage VRST by the variation Vft caused by a reset during reading, it is possible to make the reset level during exposure and the reset level during reading identical. Therefore, it is possible to suppress deterioration of photoresponse non-uniformity (PRNU). <10. Tenth Embodiment>

[0234] In the seventh embodiment described above, the reset level and the signal level are read in this order for each frame, but there is a possibility that this configuration may cause deterioration of photoresponse unevenness (PRNU) due to variations in the capacitor elements 321 to 324 or parasitic capacitance. A solid-state imaging element 200 of this tenth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that the PRNU is improved by switching between the level held in the capacitor element 321 and the level held in the capacitor element 323 for each frame.

[0235] The solid-state imaging element 200 of the tenth embodiment continuously captures multiple frames in synchronization with the vertical synchronization signal. An odd-numbered frame is referred to as an "odd frame," and an even-numbered frame is referred to as an "even frame."

[0236] Fig. 49 is a timing chart illustrating an example of a global shutter operation for odd frames according to the tenth embodiment. The pre-stage circuit 310 in the solid-state imaging element 200 sets the selection signal Φr1 and the selection signal Φs1 to the high level in this order within the exposure period of the odd frame, causing the capacitor element 321 to hold the reset level, and then causing the capacitor element 323 to hold the signal level.

[0237] Fig. 50 is a timing chart illustrating an example of an odd-frame read operation according to the tenth embodiment of the present technology. The post-stage circuit 350 in the solid-state imaging element 200 sets the selection signal Φr1 and the selection signal Φs1 to the high level in this order to read the reset level and the signal level in this order within the odd-frame read period.

[0238] Fig. 51 is a timing chart illustrating an example of a global shutter operation for even frames according to the tenth embodiment. Pre-stage circuit 310 in solid-state imaging element 200 sets selection signal Φs1 and selection signal Φr1 to the high level in this order within the exposure period of the even frame, causing capacitor element 323 to hold the reset level, and then causing capacitor element 321 to hold the signal level.

[0239] Fig. 52 is a timing chart illustrating an example of an even-frame read operation according to the tenth embodiment of the present technology. The post-stage circuit 350 in the solid-state imaging element 200 sets the selection signal Φs1 and the selection signal Φr1 to the high level in this order to read the reset level and the signal level in this order within the even-frame read period.

[0240] As in Fig. 49 and Fig. As illustrated in Figure 51, the levels held in capacitor elements 321 and 323 are reversed between the even frame and the odd frame. Accordingly, the polarity of the PRNU is also reversed between even and odd frames. The column signal processing circuit 260 in the subsequent stage obtains an arithmetic mean of the odd frame and the even frame. Accordingly, it is possible to cancel PRNUs with opposite polarities.

[0241] This control is effective for capturing a moving image or summing individual images. Furthermore, it does not require adding an element to pixel 300 and can be achieved by simply changing a control system.

[0242] It is noted that the first to third modification examples of the seventh embodiment or the eighth and ninth embodiments can also be applied to the tenth embodiment.

[0243] In this way, according to the tenth embodiment of the present technology, since the level held in capacitor element 321 and the level held in capacitor element 323 are reversed between the odd frame and the even frame, the polarity of the PRNU can be reversed between the odd frame and the even frame. The column signal processing circuit 260 adds the odd frame and the even frame, making it possible to suppress PRNU degradation. <11. Eleventh Embodiment>

[0244] In the seventh embodiment described above, the column signal processing circuit 260 obtains a difference between the reset level and the signal level for each column. However, this configuration may suffer from a block spot (black spot) phenomenon when very high-intensity light is incident on the pixel, in which a luminance increases due to overflow of charges from the photoelectric conversion element 311 and becomes black. A solid-state imaging element 200 of this eleventh embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that it is determined for each pixel whether the black spot phenomenon has occurred.

[0245] Fig. 53 is a circuit diagram illustrating a configuration example of a column signal processing circuit 260 according to the eleventh embodiment of the present technology. In the column signal processing circuit 260 of the first embodiment, an ADC 270 is disposed instead of the ADC 451, and a selector 292 is further disposed for each column.

[0246] ADC 270 further includes a comparator 280 and a counter 271. Comparator 280 compares the level of vertical signal line 309 with the ramp signal RMP from DAC 213 and outputs a comparison result VCO. The comparison result VCO is provided to counter 271 and timing control circuit 212. Comparator 280 includes a selector 281, capacitor elements 282 and 283, autozero switches 284 and 286, and a comparator element 285.

[0247] The selector 281 connects either the vertical signal line 309 of the corresponding column or a node of a predetermined reference voltage VREF via the capacitor element 282 to a non-inverting input terminal (+) of the comparator element 285 according to an input side selection signal selin. The input side selection signal selin is provided by the timing control circuit 212. Note that the selector 281 is an example of an input side selector described in the claims.

[0248] The comparator element 285 compares a level of the non-inverting input terminal (+) with a level of an inverting input terminal (-) and outputs the comparison result VCO to the counter 271. The ramp signal RMP is input to the inverting input terminal (-) via the capacitor element 283.

[0249] The autozero switch 284 shorts the non-inverting input terminal (+) and an output terminal of the comparison result VCO according to an autozero signal Az from the timing control circuit 212. The autozero switch 286 shorts the inverting input terminal (-) and the output terminal of the comparison result VCO according to the autozero signal Az.

[0250] The counter 271 counts a count value over one period until the comparison result VCO is inverted and outputs a digital signal indicating the count value.

[0251] The CDS circuit 456 calculates a difference between the digital signal corresponding to the reset level and the digital signal corresponding to the signal level and outputs the difference as CDS_out to the selector 292.

[0252] The selector 292 outputs either the digital signal CDS_out subjected to CDS processing or a digital full code signal FULL as pixel data of the corresponding column according to an output page selection signal selout from the timing control circuit 212.

[0253] Fig. 54 is a timing diagram illustrating an example of a global shutter operation according to the eleventh embodiment of the present technology. A method for controlling transistors at the time of a global shutter in the eleventh embodiment is similar to the method in the seventh embodiment.

[0254] Here, it is assumed that very high-intensity light is incident on the pixel 300. In this case, the photoelectric conversion element 311 becomes full of charges, and the charges overflow from the photoelectric conversion element 311 to the FD 314, causing a decrease in the potential of the FD 314, which undergoes FD resetting. A long-dashed line in the drawing indicates variations in the potential of the FD 314 when weak sunlight is incident, causing a relatively small amount of charges to overflow. A dotted line in the drawing indicates variations in the potential of the FD 314 when strong sunlight is incident, causing a relatively large amount of charges to overflow.

[0255] When weak sunlight is incident, the reset level drops at a time T3 when the FD reset is completed, but the level does not drop completely at this time.

[0256] On the other hand, when strong sunlight is incident, the reset level drops completely at time T3. In this case, the signal level becomes equal to the reset level, and the potential difference between the signal level and the reset level becomes "0," so the digital signal that has undergone CDS processing becomes like a digital signal in a dark state and fades to black. Thus, a phenomenon in which the pixel turns black despite very high-intensity light is called a black spot phenomenon or blooming.

[0257] Furthermore, if the level of the FD 314 of the pixel where the black spot phenomenon has occurred is too low, the operating point of the pre-stage circuit 310 cannot be ensured, and the current id1 of the current source transistor 316 varies accordingly. Since the current source transistor 316 of each pixel is connected to a common power supply or ground, when a certain pixel experiences current variations, variations in the IR drop in that pixel affect the sampling level of another pixel. A pixel experiencing the black spot phenomenon becomes an aggressor, and a pixel whose sampling level fluctuates due to the pixel becomes a victim. As a result, streaking noise occurs.

[0258] Note that if the discharge transistor 317 is provided as in the eighth embodiment, in a pixel experiencing a blooming, overflow charges are discharged to the discharge transistor 317, so the black spot phenomenon is less likely to occur. However, if the discharge transistor 317 is provided, some charges may flow to the FD 314, and the black spot phenomenon may be difficult to completely eliminate. Furthermore, there is also a drawback that a ratio of the effective area / charge amount for each pixel decreases due to the addition of the discharge transistor 317. Therefore, it is desirable to suppress the black spot phenomenon without using the discharge transistor 317.

[0259] As a method for suppressing the black spot phenomenon without using the discharge transistor 317, there are two possible methods. The first is to adjust a clipping level of the FD 314. The second is to determine whether the black spot phenomenon has occurred during reading, and if the black spot phenomenon has occurred, the output is replaced with the full code.

[0260] Regarding the first method, the high level of the FD reset signal rst (in other words, the gate of the FD reset transistor 313) in the drawing corresponds to the power supply voltage VDD, and the low level corresponds to the clipping level of the FD 314. In the seventh embodiment, a difference between the high level and the low level (i.e., the amplitude) is set to a value corresponding to a dynamic range. In contrast, in the eleventh embodiment, the value is adjusted to a value that further adds a margin to this value. Here, the value corresponding to the dynamic range corresponds to a difference between the power supply voltage VDD and the potential of the FD 314 when the digital signal becomes the full code.

[0261] Decreasing the gate voltage (the low level of the FD reset signal rst) when the FD reset transistor 313 is off makes it possible to prevent the FD 314 from being excessively decreased due to blooming and the operating point of the pre-stage amplification transistor 315 from being lost.

[0262] Note that the dynamic range varies depending on the analog gain of the ADC. When the analog gain is low, a large dynamic range is required; conversely, when the analog gain is high, a small dynamic range is required. Therefore, it is possible to change the gate voltage when the FD reset transistor 313 is off according to the analog gain.

[0263] Fig. 55 is a timing chart illustrating an example of a read operation according to the eleventh embodiment of the present technology. When the selection signal Φr1 becomes high at a time T11 immediately after a time T10, which is the start of reading, the potential of the vertical signal line 309 varies in the pixel to which sunlight is incident. A long-short dashed line in the drawing indicates variations in the potential of the vertical signal line 309 when weak sunlight is incident. A dotted line in the drawing indicates variations in the potential of the vertical signal line 309 when strong sunlight is incident.

[0264] For example, in an auto-zero period from time T10 to time T12, the timing control circuit 212 provides the input side selection signal selin of "0" to connect the comparator element 285 to the vertical signal line 309. Within this auto-zero period, the timing control circuit 212 performs auto-zeroing using the auto-zero signal Az.

[0265] Regarding the second method, for example, the timing control circuit 212 provides the input side selection signal selin of "1" within a determination period from time T12 to time T13. The input side selection signal selin disconnects the comparator element 285 from the vertical signal line 309 and connects the comparator element 285 to the reference voltage node VREF. The reference voltage VREF is set to an expected value of the level of the vertical signal line 309 when no blooming occurs. For example, if the gate-source voltage of the post-stage amplification transistor 351 is designated as Vgs2, Vrst corresponds to Vreg - Vgs2. Furthermore, the DAC 213 decreases the level of the ramp signal RMP from Vrmp_az to Vrmp_sun within the determination period.

[0266] Furthermore, if blooming does not occur within the determination period, the reset level Vrst of the vertical signal line 309 is almost equal to the reference voltage VREF and is not much different from when the potential of the inverting input terminal (+) of the comparator element 285 is autozero. On the other hand, since the non-inverting input terminal (-) is lowered from Vrmp_az to Vrmp_sun, the comparison result VCO becomes high.

[0267] In contrast, if blooming occurs, the reset level Vrst becomes sufficiently higher than the reference voltage VREF, and the comparison result VCO becomes the low level when the following expression is satisfied. Vrst−VREF>Vrmp_az−Vrmp_sun

[0268] That is, the timing control circuit 212 can determine whether blooming has occurred or not based on whether or not the comparison result VCO becomes the low level within the determination period.

[0269] It is noted that it is necessary to ensure a certain large margin for sun determination (the right side of Expression 5) so as to prevent erroneous determination due to variations in the threshold voltage of the post-stage amplification transistor 351, IR drop differences of the in-plane Vreg, or the like.

[0270] After a time T13 after the determination period has elapsed, the timing control circuit 212 connects the comparator element 285 to the vertical signal line 309.

[0271] If it is determined that no blooming has occurred during the determination period, the timing control circuit 212 controls the selector 292 according to the output side selection signal selout to output the digital signal CDS_out that has undergone the CDS processing as it is.

[0272] On the other hand, if it is determined that blooming has occurred during the determination period, the timing control circuit 212 controls the selector 292 according to the output page selection signal selout to output the full code FULL instead of the digital signal CDS_out that has undergone CDS processing. Therefore, it is possible to suppress the black spot phenomenon.

[0273] It is noted that the first to third modification examples of the seventh embodiment or the eighth to tenth embodiments can also be applied to the eleventh embodiment.

[0274] In this way, according to the eleventh embodiment of the present technology, it is possible to suppress the black spot phenomenon because the timing control circuit 212 determines whether the black spot phenomenon has occurred or not based on the comparison result VCO and outputs the full code when the black spot phenomenon has occurred. <12. Twelfth Embodiment>

[0275] In the seventh embodiment described above, the vertical scanning circuit 211 performs control for simultaneously exposing all lines (all pixels) (i.e., the global shutter operation). However, if simultaneity of exposure is not required but low noise is required, such as during a test or analysis, it is desirable to perform a rolling shutter operation. A solid-state imaging element 200 of this twelfth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that the rolling shutter operation is performed during a test or the like.

[0276] Fig. Figure 56 is a timing chart illustrating an example of a rolling shutter operation according to the twelfth embodiment of the present technology. The vertical scanning circuit 211 performs control to sequentially select a plurality of lines and start exposure. This drawing illustrates exposure control of the nth line.

[0277] During the period from time T0 to time T2, the vertical scanning circuit 211 supplies a high-level post-stage selection signal selb, the high-level selection signal Φr1, and the high-level selection signal Φs1 to the n-th line. Furthermore, at time T0, which is the start of an exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and the high-level post-stage reset signal rstb to the n-th line over the pulse period. The vertical scanning circuit 211 supplies the transfer signal trg to the n-th line at time T1 at the end of the exposure. The rolling shutter operation in the drawing enables the imaging element 200 to generate low-noise image data.

[0278] It is noted that during normal imaging, the solid-state imaging element 200 of the twelfth embodiment performs the global shutter operation in a manner similar to the seventh embodiment.

[0279] Furthermore, the first to third modification examples of the seventh embodiment or the eighth to eleventh embodiments can also be applied to the twelfth embodiment.

[0280] In this way, according to the twelfth embodiment of the present technology, it is possible to generate low-noise image data because the vertical scanning circuit 211 performs control for sequentially selecting a plurality of lines and starting an exposure (i.e., the rolling shutter operation). <13. Thirteenth Embodiment>

[0281] In the seventh embodiment described above, the source of the pre-stage source follower (pre-stage amplification transistor 315 and current source transistor 316) is connected to the power supply voltage VDD, and row-by-row reading is performed with the source follower in the on state. However, there is a possibility that this driving method causes circuit noise of the pre-stage source follower to propagate to the subsequent stages during row-by-row reading, and random noise increases accordingly. A solid-state imaging element 200 of this thirteenth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that the pre-stage source follower is turned off during reading to reduce noise.

[0282] Fig. 57 is a block diagram illustrating a configuration example of the solid-state imaging element 200 according to the thirteenth embodiment of the present technology. The solid-state imaging element 200 of the thirteenth embodiment differs from the solid-state imaging element 200 of the seventh embodiment in that a regulator 420 and a switching unit 440 are further provided. Furthermore, in the pixel array unit 220 of the thirteenth embodiment, a plurality of effective pixels 301 and a predetermined number of dummy pixels 430 are arranged. The dummy pixels 430 are arranged around an area where the effective pixels 301 are arranged.

[0283] Furthermore, the power supply voltage VDD is supplied to each of the dummy pixels 430, and the power supply voltage VDD and a source voltage Vs are supplied to each of the effective pixels 301. A signal line through which the power supply voltage VDD is supplied to the effective pixels 301 is omitted from the drawing. Furthermore, the power supply voltage VDD is supplied from a pad 410 located outside the solid-state imaging element 200.

[0284] The regulator 420 generates a constant voltage V gen based on an input potential Vi from the dummy pixel 430 and provides the generated voltage V gen to the switching unit 440. The switching unit 440 selects either the power supply voltage VDD from the pad 410 or the generated voltage V genfrom the regulator 420 and supplies the selected voltage as the source voltage Vs to each of the columns of the effective pixels 301.

[0285] Fig. 58 is a circuit diagram illustrating a configuration example of the dummy pixel 430, the regulator 420, and the switching unit 440 according to the thirteenth embodiment of the present technology. In the drawing, a indicates a circuit diagram of the dummy pixel 430 and the regulator 420, and b indicates a circuit diagram of the switching unit 440.

[0286] As illustrated in a of the drawing, the dummy pixel 430 includes a reset transistor 431, an FD 432, an amplification transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to a reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charges and generates a voltage corresponding to an amount of charge. The amplification transistor 433 amplifies a voltage level of the FD 432 and supplies the amplified voltage as the input voltage Vi to the regulator 420.

[0287] Furthermore, reset transistor 431 and amplification transistor 433 have their respective sources connected to the power supply voltage VDD. Current source transistor 434 is connected to a drain of amplification transistor 433. Current source transistor 434 provides current id1 under the control of vertical scanning circuit 211.

[0288] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor element 423. The low-pass filter 421 passes, as an output voltage Vj, a component in a low-frequency band below a predetermined frequency from a signal of the input voltage Vi.

[0289] The output voltage Vj is input to a non-inverting input terminal (+) of the buffer amplifier 422. An inverting input terminal (-) of the buffer amplifier 422 is connected to an output terminal of the buffer amplifier 422. The capacitor element 423 holds a voltage of the output terminal of the buffer amplifier 422 as V gen . This V gen is supplied to the switching unit 440.

[0290] As illustrated in b of the drawing, the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442. The switching circuits 442 are each arranged for a corresponding one of the columns of the effective pixels 301.

[0291] The inverter 441 inverts a switching signal SW sent from the timing control circuit 212. The inverter 441 supplies the inverted signal to each of the switching circuits 442.

[0292] The switching circuit 442 selects either the power supply voltage VDD or the generated voltage V genand supplies the selected voltage as the source voltage Vs to the corresponding column in the pixel array unit 220. The switching circuit 442 includes switches 443 and 444. The switch 443 opens and closes a path between the node of the power supply voltage VDD and the corresponding column according to the switching signal SW. The switch 444 opens and closes a path between the node of the generated voltage V gen and the corresponding column according to the inverted signal of the switching signal SW.

[0293] Fig. 59 is a timing diagram illustrating an example of how the dummy pixel 430 and the regulator 420 operate according to the thirteenth embodiment of the present technology. At a time T10 immediately before reading a certain line, the vertical scanning circuit 211 supplies a high-level reset signal RST (here, the power supply voltage VDD) to each of the dummy pixels 430. A potential Vfd of the FD 432 in the dummy pixel 430 is initialized to the power supply voltage VDD. When the reset signal RST becomes low, then a reset execution causes a change to VDD - Vft.

[0294] Furthermore, the input voltage Vi decreases to VDD - Vgs - Vsig after the reset. By passing through the low-pass filter 421, Vj and V gen to approximately constant voltages.

[0295] After a time T20 immediately before reading the next line, a similar control is performed for each line and the constant generated voltage V gen is provided.

[0296] Fig. 60 is a circuit diagram illustrating a configuration example of the effective pixel 301 according to the thirteenth embodiment of the present technology. The effective pixel 301 is similar in circuit configuration to the pixel 300 of the seventh embodiment, except that the source voltage Vs is supplied from the switching unit 440 to the source of the pre-stage amplification transistor 315.

[0297] Fig. 61 is a timing diagram illustrating an example of a global shutter operation according to the thirteenth embodiment of the present technology. In the thirteenth embodiment, when all pixels are exposed simultaneously, the switching unit 440 selects the power supply voltage VDD and provides the power supply voltage VDD as the source voltage Vs. Further, at time T4, the voltage of the pre-stage node decreases from VDD - Vgs - Vth to VDD - Vgs - Vsig. Here, Vth represents a threshold voltage of the transfer transistor 312.

[0298] Fig. Fig. 62 is a timing diagram illustrating an example of a read operation according to the thirteenth embodiment of the present technology. In the thirteenth embodiment, the switching unit 440 selects the generated voltage V during reading. gen and sets the generated voltage V genthan the source voltage Vs. The generated voltage V gen is adjusted to VDD - Vgs - Vft. Furthermore, in the thirteenth embodiment, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to stop supplying the current id1.

[0299] Fig. 63 is a diagram for describing effects according to the thirteenth embodiment of the present technology. In the first embodiment, the source follower (pre-stage amplification transistor 315 and current source transistor 316) of the pixel 300 to be read is turned on during row-by-row reading. However, there is a possibility that this driving method causes circuit noise of the pre-stage source follower to propagate to the subsequent stages (capacitor element and post-stage source follower and ADC), and read noise increases accordingly.

[0300] For example, in the seventh embodiment, as illustrated in the drawing, kTC noise generated in one pixel during the global shutter operation is 450 (µVrms). Furthermore, noise generated in the pre-stage source follower (the pre-stage amplification transistor 315 and the current source transistor 316) during row-by-row reading is 380 (µVrms). Noise generated in the post-stage source follower and subsequent stages is 160 (µVrms). Therefore, the total noise is 610 (µVrms). In this way, in the seventh embodiment, a proportion of the pre-stage source follower noise to the total noise becomes relatively large.

[0301] To reduce the noise of the pre-stage source follower in the thirteenth embodiment, the adjustable voltage (Vs) is supplied to the source of the pre-stage source follower, as described above. During the global shutter (exposure) operation, the switching unit 440 selects the power supply voltage VDD and provides the selected power supply voltage as the source voltage Vs. Then, after the end of the exposure, the switching unit 440 switches the source voltage Vs to VDD - Vgs - Vft. Furthermore, the timing control circuit 212 turns on the pre-stage current source transistor 316 during the global shutter (exposure) operation and turns off the pre-stage current source transistor 316 after the end of the exposure.

[0302] As in Fig. 61 and Fig. As illustrated in Figure 62, the previously described control makes the potential of the pre-stage node identical during the global shutter operation and the potential during row-by-row reading, thus enabling an improvement in the PRNU. Furthermore, since the pre-stage source follower is in the off state during row-by-row reading, no source follower circuit noise occurs and becomes zero (µVrms), as shown in Fig. 63. Note that in the pre-stage source follower, the pre-stage amplification transistor 315 is in the on state.

[0303] In this way, according to the thirteenth embodiment of the present technology, noise generated in the source follower can be reduced because the pre-stage source follower is brought into the off state during reading. <14. Application example for a mobile body>

[0304] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can also be implemented as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, and a robot.

[0305] Fig. 64 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0306] The vehicle control system 12000 includes several electronic control units that are interconnected via a communication network 12001. In the Fig. 64, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (SST) 12053 are illustrated.

[0307] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a drive motor, or the like, a driving force transmitting mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0308] The body system control unit 12020 controls the operation of various types of devices provided for a vehicle body according to various types of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various types of lights such as a headlight, a reversing light, a brake light, a turn signal, a fog light, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals from various types of switches can be input to the body system control unit 12020.The body system control unit 12020 receives these input radio waves or signals and controls a door locking device, the power window device, the lights or the like of the vehicle.

[0309] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging section 12031. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting an object such as a person, a vehicle, an obstacle, a sign, a symbol on a road surface, or the like, or processing for detecting a distance thereto.

[0310] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 12031 can output the electrical signal as an image or can output the electrical signal as information about a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light or can be non-visible light, such as infrared rays or the like.

[0311] The vehicle interior information detection unit 12040 detects information about the interior of the vehicle. The vehicle interior information detection unit 12040 is connected, for example, to a driver state detection section 12041 that detects the state of a driver. The driver state detection section 12041 includes, for example, a camera that records the driver. Based on detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate a driver's fatigue level or a driver's concentration level, or can determine whether the driver is dozing.

[0312] The microcomputer 12051 may calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010.For example, the microcomputer 12051 may perform cooperative control to implement functions of an Advanced Driver Assistance System (ADAS), which functions include collision avoidance or impact mitigation for the vehicle, following travel based on a following distance, speed maintenance travel, warning of a collision of the vehicle, warning of the vehicle leaving a lane, or the like.

[0313] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle drive automatically without depending on the driver's operation or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like based on the information about the exterior or interior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040.

[0314] Furthermore, the microcomputer 12051 may output a control command to the body system control unit 12020 based on the vehicle exterior information detected by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control to prevent glare by controlling the headlight to switch from, for example, a high beam to a low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0315] The audio / video output section 12052 transmits an audio and / or video output signal to an output device capable of visually or acoustically communicating information to a vehicle occupant or the vehicle exterior. In the example of Fig. 64, an audio speaker 12061, a display section 12062, and a dashboard 12063 are illustrated as the output device. The display section 12062 may include, for example, an onboard display and / or a head-up display.

[0316] Fig. 65 is a diagram illustrating an example of the installation position of the imaging section 12031.

[0317] In Fig. 65, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104 and 12105.

[0318] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on a front nose, side mirrors, a rear bumper, and a rear door of the vehicle 12100, as well as a position on an upper part of a windshield within the vehicle interior. The imaging section 12101 provided at the front nose and the imaging section 12105 provided at the upper part of the windshield within the vehicle interior mainly obtain an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the side mirrors mainly obtain an image of the sides of the vehicle 12100. The imaging section 12104 provided at the rear bumper or rear door mainly obtains an image of the rear of the vehicle 12100.The imaging section 12105 provided on the upper part of the windshield within the interior of the vehicle is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0319] It is noted that Fig. 65 illustrates an example of imaging areas of the imaging sections 12101 to 12104. An imaging area 12111 represents the imaging area of ​​the imaging section 12101 provided at the front nose. Imaging areas 12112 and 12113 represent the imaging areas of the imaging sections 12102 and 12103 provided at the side mirrors, respectively. An imaging area 12114 represents the imaging area of ​​the imaging section 12104 provided at the rear bumper or the tailgate. A bird's-eye view image of the vehicle 12100 as viewed from above is obtained, for example, by superimposing image data obtained by the imaging sections 12101 to 12104.

[0320] At least one of the imaging sections 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or may be an imaging element with pixels for phase difference detection.

[0321] For example, the microcomputer 12051 may determine a distance to each three-dimensional object within the imaging areas 12111 to 12114 and a temporal change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, specifically, a next three-dimensional object that exists in a moving path of the vehicle 12100 and that moves in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h).Furthermore, the microcomputer 12051 can set a following distance to be kept with a preceding vehicle in advance and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), or the like. Accordingly, it is possible to perform cooperative control intended for automated driving, which allows the vehicle to travel automatically without depending on the driver's operation or the like.

[0322] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-size vehicle, a large-size vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk that indicates a risk of collision with each obstacle.In a situation where the collision risk is equal to or higher than a set value and accordingly there is a possibility of a collision, the microcomputer 12051 issues a warning to the driver through the audio speaker 12061 or the display section 12062 and performs forced deceleration or evasive steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid a collision.

[0323] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may detect a pedestrian by determining whether or not there is a pedestrian in captured images of the imaging sections 12101 to 12104. Such detection of a pedestrian is performed, for example, by a process for extracting characteristic points in the captured images of the imaging sections 12101 to 12104 as infrared cameras and a process for determining whether or not the pedestrian exists by performing pattern matching processing on a series of characteristic points representing the outline of the object.When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging sections 12101 to 12104 and accordingly detects the pedestrian, the audio / video output section 12052 controls the display section 12062 to display a square outline for highlighting, superimposed on the detected pedestrian. The audio / video output section 12052 can also control the display section 12062 to display an icon or the like representing the pedestrian at a desired position.

[0324] An example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging section 12031 under the configurations described above. Specifically, for example, the imaging device 100 in Fig.1 to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, it is possible to obtain a captured image that is easier to view by expanding the dynamic range, etc., thereby making it possible to reduce driver fatigue.

[0325] It should be noted that the above-described embodiments are examples for implementing the present technology, and the items in the embodiments and the items used to specify the invention in the claims have a correspondence relationship. Likewise, there is a correspondence relationship between the items specifying the invention in the claims and the items in the embodiments of the present technology with the same names. However, the present technology is not limited to the embodiments and can be modified by applying various modifications to the embodiments without departing from the essence thereof.

[0326] It is noted that the effects described in this document are merely examples and are not limiting, and other effects may also be present.

[0327] It is noted that the present technology may also have the following configuration. (1) A solid-state imaging element comprising: a pre-stage circuit that generates an analog signal as a pixel signal; a sample-and-hold circuit that holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the high gain and corresponds to a combined capacitance of the plurality of capacitor elements; and a post-stage circuit that sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit. (2) The solid-state imaging element according to (1), wherein the plurality of capacitor elements include a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element, and the sample-and-hold circuit includes: the first capacitor element; the second capacitor element; the third capacitor element; the fourth capacitor element; and a selection circuit connecting one or more of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element to the post-stage circuit. (3) The solid-state imaging element according to (2), wherein the pre-stage circuit, the sample-and-hold circuit and the post-stage circuit are arranged in each of several pixels, a level of the pixel signal includes a reset level when a floating diffusion layer in the pre-stage circuit is initialized and a signal level when a charge is transferred to the floating diffusion layer, the pre-stage circuit generates the reset level immediately before a time at which an exposure of all of the plurality of pixels ends and generates the signal level at that time, and the selection circuit connects the first capacitor element to the post-stage circuit immediately before the time and connects the third capacitor element to the post-stage circuit at the time. (4) The solid-state imaging element according to (3), wherein the selection circuit sequentially performs control for connecting the first capacitor element to the post-stage circuit, control for connecting the first capacitor element and the second capacitor element to the post-stage circuit, control for connecting the third capacitor element to the post-stage circuit, and control for connecting the third capacitor element and the fourth capacitor element to the post-stage circuit within a read period of the pixel signal. (5) The solid-state imaging element according to (3), wherein the selection circuit sequentially performs control for connecting the first capacitor element to the post-stage circuit, control for connecting the first capacitor element and the second capacitor element to the post-stage circuit, and control for connecting the third capacitor element to the post-stage circuit if it is determined that the signal level does not exceed a predetermined determination value, and for connecting the third capacitor element and the fourth capacitor element to the post-stage circuit if it is determined that the signal level is higher than the determination value, within a read period of the pixel signal. (6) The solid-state imaging element according to (5), further comprising: a determination circuit that determines whether the signal level is higher than the determination value or not and supplies a determination result to the sample-and-hold circuit. (7) The solid-state imaging element according to (6), wherein the determination circuit is arranged in each of the plurality of pixels. (8) The solid-state imaging element according to (6), wherein the determination circuit is arranged outside the plurality of pixels. (9) The solid-state imaging element according to (8), wherein the determination circuit compares a determination signal corresponding to the determination value with the high gain signal corresponding to the signal level to generate the determination result. (10) The solid-state imaging element according to (8), further comprising: an analog-to-digital converter that converts both the high-gain signal and the low-gain signal into a digital signal based on a predetermined ramp signal, wherein the determination circuit compares the ramp signal with the high gain signal corresponding to the signal level to produce the determination result. (11) The solid-state imaging element according to (1), further comprising: a coupling circuit, where the pre-stage circuit, the sample-and-hold circuit and the post-stage circuit are arranged in each of several pixels, and the coupling circuit couples the sample-and-hold circuit of each of a pair of pixels among the plurality of pixels. (12) The solid-state imaging element according to (11), wherein the coupling circuit selects and connects one of the sample-and-hold circuit of each of a pair of pixels arranged in a predetermined direction and the sample-and-hold circuit of each of a pair of pixels arranged in a direction perpendicular to the predetermined direction. (13) The solid-state imaging element according to (1), further comprising: a logic circuit that combines a frame in which digital signals obtained by converting the high-gain signals are arranged and a frame in which digital signals obtained by converting the low-gain signals are arranged. (14) The solid-state imaging element according to (1), further comprising: a post-stage reset transistor that initializes a predetermined post-stage node when the plurality of capacitor elements are disconnected from the post-stage node, wherein the plurality of capacitor elements include a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element, the post-stage circuit reads the pixel signal via the post-stage node, and the sample-and-hold circuit includes: the first capacitor element; the second capacitor element; the third capacitor element; the fourth capacitor element; and a selection circuit that sequentially performs control for connecting the first capacitor element to the post-stage node, control for disconnecting the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element from the post-stage node, and control for connecting the third capacitor element to the post-stage node. (15) An imaging device comprising: a pre-stage circuit that generates an analog signal as a pixel signal; a sample-and-hold circuit that holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain smaller than the high gain and corresponding to a combined capacitance of the plurality of capacitor elements; a post-stage circuit that sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit; and a recording unit that records a single image generated from the high-gain signal and the low-gain signal. (16) A method of controlling a solid-state imaging element, the method comprising: a pre-stage procedure in which a pre-stage circuit generates an analog signal as a pixel signal; a sample-and-hold procedure in which a sample-and-hold circuit holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the high gain and corresponds to a combined capacitance of the plurality of capacitor elements; and a post-stage procedure in which a post-stage circuit sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit. LIST OF REFERENCE SYMBOLS 100 imaging device 110 imaging lens 120 recording unit 130 Imaging control unit 200 solid-state imaging elements 201 Upper pixel chip 202 Lower pixel chip 203 circuit chip 211 Vertical scan circuit 212 Timing control circuit 213 DAC 220 pixel array unit 221 Upper pixel array unit 222 Lower pixel array unit 250 load MOS circuit block 251 Load MOS transistor 260 column signal processing circuit 270, 451 ADC 271, 453 points 280, 452 Comparator 281, 292, 454, 471, 472 selector 282, 283, 321 to 326, 423 capacitor element 284, 286 Autozero switch 285 Comparator element 300, 300-1, 300-2, 300-3, 300-4 pixels 301 Effective Pixels 310, 310-1, 310-2, 310-3, 310-4 preamplifier circuit 311 Photoelectric conversion element 312 transfer transistor 313 FD reset transistor 314, 432 FD 315 Preamplifier transistor 316, 434 current source transistor 317 discharge transistor 320, 320-1, 320-2, 320-3, 320-4 sample-and-hold circuit 327 Pre-stage reset transistor 328 Pre-stage selection transistor 330 selection circuit 331 to 336 selection transistor 337 sampling transistor 338, 457 Determination circuit 341 Post-stage reset transistor 350, 350-1, 350-2, 350-3, 350-4 post-stage circuit 351, 351-1, 351-2 post-stage amplification transistor 352, 352-1, 352-2 post-stage selection transistor 420 controllers 421 Low-pass filter 422 buffer amplifier 430 dummy pixels 431 Reset transistor 433 amplification transistor 440 switching unit 441 Inverter 442 circuit 443, 444 switches 450 column circuit 455 P-phase latch 456 CDS circuit 460 logic circuit 461 frame buffers 462 Multiplication circuit 463 HDR Composition Unit 470-1, 470-2, 470-3, 470-4 coupling circuit 12031 Imaging Section QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2018-011162

[0003]

Claims

[1] Solid-state imaging element comprising: a pre-stage circuit that generates an analog signal as a pixel signal; a sample-and-hold circuit that holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the high gain and corresponds to a combined capacitance of the plurality of capacitor elements; and a post-stage circuit that sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit. [2] A solid-state imaging element according to claim 1, wherein the plurality of capacitor elements include a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element, and the sample-and-hold circuit includes: the first capacitor element; the second capacitor element; the third capacitor element; the fourth capacitor element; and a selection circuit connecting one or more of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element to the post-stage circuit. [3] A solid-state imaging element according to claim 2, wherein the pre-stage circuit, the sample-and-hold circuit and the post-stage circuit are arranged in each of several pixels, a level of the pixel signal includes a reset level when a floating diffusion layer in the pre-stage circuit is initialized and a signal level when a charge is transferred to the floating diffusion layer, the pre-stage circuit generates the reset level immediately before a time at which an exposure of all of the plurality of pixels ends and generates the signal level at that time, and the selection circuit connects the first capacitor element to the post-stage circuit immediately before the time and connects the third capacitor element to the post-stage circuit at the time. [4] A solid-state imaging element according to claim 3, wherein the selection circuit sequentially performs control for connecting the first capacitor element to the post-stage circuit, control for connecting the first capacitor element and the second capacitor element to the post-stage circuit, control for connecting the third capacitor element to the post-stage circuit, and control for connecting the third capacitor element and the fourth capacitor element to the post-stage circuit within a read period of the pixel signal. [5] The solid-state imaging element according to claim 3, wherein the selection circuit sequentially performs control for connecting the first capacitor element to the post-stage circuit, control for connecting the first capacitor element and the second capacitor element to the post-stage circuit, and control for connecting the third capacitor element to the post-stage circuit if it is determined that the signal level does not exceed a predetermined determination value, and for connecting the third capacitor element and the fourth capacitor element to the post-stage circuit if it is determined that the signal level is higher than the determination value, within one read period of the pixel signal. [6] A solid-state imaging element according to claim 5, further comprising: a determination circuit that determines whether the signal level is higher than the determination value or not and supplies a determination result to the sample-and-hold circuit. [7] A solid-state imaging element according to claim 6, wherein the determination circuit is arranged in each of the plurality of pixels. [8] The solid-state imaging element according to claim 6, wherein the determination circuit is arranged outside the plurality of pixels. [9] The solid-state imaging element according to claim 8, wherein the determination circuit compares a determination signal corresponding to the determination value with the high gain signal corresponding to the signal level to generate the determination result. [10] A solid-state imaging element according to claim 8, further comprising: an analog-to-digital converter that converts both the high-gain signal and the low-gain signal into a digital signal based on a predetermined ramp signal, wherein the determination circuit compares the ramp signal with the high gain signal corresponding to the signal level to produce the determination result. [11] The solid-state imaging element of claim 1, further comprising: a coupling circuit, where the pre-stage circuit, the sample-and-hold circuit and the post-stage circuit are arranged in each of several pixels, and the coupling circuit couples the sample-and-hold circuit of each of a pair of pixels among the plurality of pixels. [12] The solid-state imaging element according to claim 11, wherein the coupling circuit selects and connects one of the sample-and-hold circuit of each of a pair of pixels arranged in a predetermined direction and the sample-and-hold circuit of each of a pair of pixels arranged in a direction perpendicular to the predetermined direction. [13] The solid-state imaging element of claim 1, further comprising: a logic circuit that combines a frame in which digital signals obtained by converting the high-gain signals are arranged and a frame in which digital signals obtained by converting the low-gain signals are arranged. [14] The solid-state imaging element of claim 1, further comprising: a post-stage reset transistor that initializes a predetermined post-stage node when the plurality of capacitor elements are disconnected from the post-stage node, wherein the plurality of capacitor elements include a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element, the post-stage circuit reads the pixel signal via the post-stage node, and the sample-and-hold circuit includes: the first capacitor element; the second capacitor element; the third capacitor element; the fourth capacitor element; and a selection circuit that sequentially performs control for connecting the first capacitor element to the post-stage node, control for disconnecting the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element from the post-stage node, and control for connecting the third capacitor element to the post-stage node. [15] Imaging device comprising: a pre-stage circuit that generates an analog signal as a pixel signal; a sample-and-hold circuit that holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain smaller than the high gain and corresponding to a combined capacitance of the plurality of capacitor elements; a post-stage circuit that sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit; and a recording unit that records a single image generated from the high-gain signal and the low-gain signal. [16] A method of controlling a solid-state imaging element, the method comprising: a pre-stage procedure in which a pre-stage circuit generates an analog signal as a pixel signal; a sample-and-hold procedure in which a sample-and-hold circuit holds a high-gain signal obtained by amplifying the pixel signal with a predetermined high gain in any one of a plurality of capacitor elements and generates a low-gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the high gain and corresponds to a combined capacitance of the plurality of capacitor elements; and a post-stage procedure in which a post-stage circuit sequentially reads and outputs the high-gain signal and the low-gain signal from the sample-and-hold circuit.

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