Pixel driver circuit, display substrate and display device

Abstract

The present disclosure provides a pixel driver circuit, a display substrate, and a display device. The pixel driver circuit serves to drive light-emitting elements (Fl). In the pixel driver circuit, a first end of a driver sub-circuit (10) is coupled to a power supply line (VDD); a compensation sub-circuit (11) is coupled to a sampling line (GA), a control end of the driver sub-circuit (10), and a second end of the driver sub-circuit (10); a first end of a coupling sub-circuit (12) is coupled to the control end of the driver sub-circuit (10); a first end of a memory sub-circuit (13) is coupled to a second end of the coupling sub-circuit (12); a data write sub-circuit (14) is coupled to a second end of the memory sub-circuit (13), a data line (DA), and a reset line (Rst).A first reset circuit (15) is coupled to the reset line (Rst), an initialization signal line (Init), the control end of the driver circuit (10), and the second end of the coupling circuit (12); a first hold circuit (16) is coupled to the sampling line (GA), the second end of the coupling circuit (12), and the initialization signal line (Init); a second hold circuit (17) is coupled to a first control line (EM'), a reference signal line (Ref), and the second end of the memory circuit (13).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology and, more particularly, to a pixel driver circuit, a display substrate, and a display device. STATE OF THE ART

[0002] Organic light-emitting diode displays not only have good flexibility, but also the advantages of light and thin design, low power consumption, fast response speed, and wide viewing angle, and are widely used in various fields. Furthermore, with the development of display technology, the market demand for high-frame-rate and high-resolution display panels is increasing, and organic light-emitting diode displays are gradually moving toward high-frame-rate and high-resolution displays. DISCLOSURE OF THE INVENTION

[0003] The object of this disclosure is to provide a pixel driver circuit, a display substrate and a display device.

[0004] To achieve the above-mentioned object, the present disclosure provides the following technical solutions: In a first aspect of the present disclosure, a pixel driver circuit is provided for driving light-emitting elements, the pixel driver circuit comprising: a driver subcircuit having a first end coupled to a power supply line; a compensation subcircuit, each coupled to a scan line, a control end of the driver subcircuit, and a second end of the driver subcircuit, and configured to control, under the control of the scan line, the switching on and off of an electrical connection between the control end and the second end of the driver subcircuit; a coupling subcircuit, the first end of which is coupled to the control end of the driver subcircuit; a memory subcircuit, the first end of which is coupled to a second end of the coupling subcircuit; a data write subcircuit, each coupled to a second end of the memory subcircuit, a data line, and a reset line, and configured to control, under the control of the reset line, the switching on and off of an electrical connection between the second end of the memory subcircuit and the data line; a first reset subcircuit, which is coupled to the reset line, an initialization signal line, the control end of the driver subcircuit, and the second end of the coupling subcircuit, respectively, and which is provided to control, under the control of the reset line, the switching on and off of an electrical connection between the initialization signal line and the control end of the driver subcircuit and the switching on and off of an electrical connection between the initialization signal line and the second end of the coupling subcircuit; a first holding subcircuit, coupled to the scanning line, the second end of the coupling subcircuit, and the initialization signal line, respectively, and provided to control, under the control of the scanning line, the switching on and off of an electrical connection between the second end of the coupling subcircuit and the initialization signal line; a second holding subcircuit, each coupled to a first control line, a reference signal line and the second end of the memory subcircuit and arranged to control, under the control of the first control line, the switching on and off of an electrical connection between the reference signal line and the second end of the memory subcircuit.

[0005] Optionally, the pixel driver circuit further includes: a light emission control subcircuit coupled to each of the second end of the driver subcircuit, the light-emitting element, and a second control line, and configured to control, under the control of the second control line, the switching on and off of an electrical connection between the second end of the driver subcircuit and the light-emitting element.

[0006] Optionally, the pixel driver circuit further includes: a second reset subcircuit coupled to each of the scanning line, the light-emitting element, and the initialization signal line, and configured to control, under the control of the scanning line, the switching on and off of an electrical connection between the light-emitting element and the initialization signal line.

[0007] Optionally, the coupling subcircuit comprises a first capacitor, the memory subcircuit comprises a second capacitor, the data write subcircuit comprises a first transistor, the compensation subcircuit comprises a second transistor, the driver subcircuit comprises a third transistor, the first reset subcircuit comprises a fourth transistor and a fifth transistor, the second reset subcircuit comprises a sixth transistor, the first hold subcircuit comprises a seventh transistor, the light emission control subcircuit comprises an eighth transistor, the second hold subcircuit comprises a ninth transistor; a gate electrode of the first transistor is coupled to the reset line, a first terminal of the first transistor is coupled to the data line, a second terminal of the first transistor is coupled to a second end of the second capacitor; a gate electrode of the second transistor is coupled to the scan line, a first pole of the second transistor is coupled to a second pole of the third transistor, a second pole of the second transistor is coupled to a gate electrode of the third transistor; a first pole of the third transistor is coupled to the power supply line; a first end of the first capacitor is coupled to the gate electrode of the third transistor, a first end of the second capacitor is coupled to a second end of the first capacitor; a gate electrode of the fourth transistor is coupled to the reset line, a first pole of the fourth transistor is coupled to the initialization signal line, a second pole of the fourth transistor is coupled to the gate electrode of the third transistor; a gate electrode of the fifth transistor is coupled to the reset line, a first terminal of the fifth transistor is coupled to the initialization signal line, a second terminal of the fifth transistor is coupled to the second end of the first capacitor; a gate electrode of the sixth transistor is coupled to the scan line, a first terminal of the sixth transistor is coupled to the initialization signal line, a second terminal of the sixth transistor is coupled to the light-emitting element; a gate electrode of the seventh transistor is coupled to the scan line, a first terminal of the seventh transistor is coupled to the initialization signal line, a second terminal of the seventh transistor is coupled to the second end of the first capacitor; a gate electrode of the eighth transistor is coupled to the second control line, a first pole of the eighth transistor is coupled to the second pole of the third transistor, a second pole of the eighth transistor is coupled to the light-emitting element; a gate electrode of the ninth transistor is coupled to the first control line, a first pole of the ninth transistor is coupled to the reference signal line, a second pole of the ninth transistor is coupled to the second end of the second capacitor.

[0008] Based on the above technical solution of the pixel driving circuit, in a second aspect of the present disclosure, there is provided a display substrate comprising a plurality of the aforementioned pixel driving circuits, wherein the pixel driving circuit comprises a first capacitor and a third transistor, wherein the first capacitor comprises a first electrode plate and a second electrode plate arranged opposite to each other, wherein the first electrode plate is multiplexed as a gate electrode of the third transistor; wherein the display substrate comprises: a plurality of data lines comprising at least one part extending along a first direction, the orthographic projection of the data line on the substrate of the display substrate and the orthographic projection of the first electrode plate on the substrate are arranged along a second direction, the first direction and the second direction intersect; a plurality of first shielding patterns, wherein at least a portion of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first electrode plate on the substrate; and / or, at least a part of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the second electrode plate on the substrate.

[0009] Optionally, the pixel driver circuit further comprises a second capacitor, the second capacitor comprising a third electrode plate and a fourth electrode plate arranged opposite each other, the third electrode plate being coupled to the second electrode plate; the third electrode plate and the second electrode plate are arranged along the first direction; at least a part of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the third electrode plate on the substrate; and / or at least a part of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the fourth electrode plate on the substrate.

[0010] Optionally, the first shielding pattern comprises a first shielding part and a second shielding part coupled to each other, wherein the first shielding part and the second shielding part are arranged along the second direction, at least a part of the orthographic projection of the data line on the substrate is located between the orthographic projection of the first shielding part on the substrate and the orthographic projection of the second shielding part on the substrate; at least a part of the orthographic projection of the first shielding part on the substrate is located between the orthographic projection of at least one of the adjacent first and second capacitors on the substrate and the orthographic projection of the data line on the substrate; and / or, at least a part of the orthographic projection of the second shielding part on the substrate is located between the orthographic projection of at least one of the first and second capacitors adjacent to it on the substrate and the orthographic projection of the data line on the substrate.

[0011] Optionally, the display substrate further comprises a second electrically conductive connection part and a data line, wherein the pixel driver circuit further comprises a first transistor, wherein a first pole of the first transistor is coupled to a corresponding data line, a second pole of the first transistor is coupled to the fourth electrode plate via the corresponding second electrically conductive connection part; the second electrically conductive connection part is located between the first shielding patterns adjacent along the second direction.

[0012] Optionally, the display substrate further comprises a third electrically conductive connection part and a fifth electrically conductive connection part, wherein the pixel driver circuit further comprises a second transistor and a third transistor, wherein a second pole of the second transistor is coupled to a gate electrode of the third transistor via the third electrically conductive connection part, a second pole of the fifth transistor is coupled to the second electrode plate via the fifth electrically conductive connection part; the third electrically conductive connection part is located between the first shielding patterns adjacent along the second direction, the fifth electrically conductive connection part is located between the first shielding patterns adjacent along the second direction.

[0013] Optionally, the display substrate further comprises: a plurality of shielding lines including at least one part extending along the second direction; wherein the plurality of pixel driver circuits are divided into a plurality of rows of pixel driver circuits, the orthographic projection of the shield line on the substrate at least partially overlapping with the orthographic projection of an edge of a respective first electrode plate located near the fourth electrode plate in a pixel driver circuit of a corresponding row on the substrate.

[0014] Optionally, the plurality of first shielding patterns are divided into a plurality of rows of first shielding patterns, wherein the shielding lines are each coupled to first shielding patterns of a corresponding row.

[0015] Optionally, the display substrate comprises power supply lines, wherein the first shielding patterns are coupled to the power supply lines.

[0016] Optionally, the first shielding patterns, the shielding lines and the third electrically conductive connecting parts are arranged on a same layer.

[0017] Optionally, the display substrate further comprises reset lines, wherein the shield line and the reset line are arranged along the first direction, both the third electrically conductive connection part and the fifth electrically conductive connection part are located between the shield line and the reset line.

[0018] Optionally, the display substrate further comprises: a plurality of second shielding patterns comprising at least a portion extending along the first direction, wherein the orthographic projection of the second shielding pattern on the substrate at least partially overlaps the orthographic projection of the data line on the substrate.

[0019] Optionally, the display substrate further comprises a plurality of second control lines, wherein the second shield patterns located in a same row along the second direction are each coupled to a corresponding second control line.

[0020] Optionally, the second shielding patterns located in a same row along the second direction and a corresponding second control line are formed into an integrated structure.

[0021] Optionally, the display substrate further comprises power supply lines and initialization signal lines, wherein the second shield pattern is coupled to the power supply line or to the initialization signal line.

[0022] Optionally, the display substrate further comprises: a plurality of initialization signal lines arranged along the first direction, the initialization signal lines including at least one part extending along the second direction; a plurality of initial connection lines arranged along the second direction, the initial connection lines including at least a portion extending along the first direction, each initial connection line being respectively coupled to the plurality of initialization signal lines.

[0023] Optionally, the display substrate further comprises: a plurality of reference signal lines arranged along the first direction, the reference signal lines including at least one portion extending along the second direction; a plurality of reference connection lines arranged along the second direction, the reference connection lines comprising at least a portion extending along the first direction, each reference connection line being respectively coupled to the plurality of reference signal lines.

[0024] Optionally, the initial connecting lines and the reference connecting lines are arranged alternately along the second direction; wherein the plurality of pixel driver circuits are divided into a plurality of columns of pixel driver circuits, each column of pixel driver circuits corresponding to one of the initial connection lines or one of the reference connection lines; wherein the orthographic projection of the initial connection line on the substrate at least partially overlaps with the orthographic projection of a second electrode plate in a pixel driver circuit of a corresponding column on the substrate; and / or wherein the orthographic projection of the reference connection line on the substrate at least partially overlaps with the orthographic projection of a second electrode plate in a pixel driver circuit of a corresponding column on the substrate.

[0025] Optionally, the display substrate further comprises a plurality of reset lines comprising at least one part extending along a second direction, wherein the reset lines and the third electrically conductive connecting part are arranged on a same layer.

[0026] Optionally, the pixel driver circuit comprises a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor, wherein the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor use a dual-gate structure.

[0027] Due to the above technical solution of the display substrate, in a second aspect of the present disclosure, a display device is provided which includes the aforementioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are provided to further understand the present disclosure and form a part of the specification. The schematic embodiments and their explanations of the present disclosure are intended to explain the present disclosure and do not unduly limit the present disclosure. In the drawings, Fig. 1 is a circuit structure diagram of a pixel driver circuit according to an embodiment of the present disclosure; Fig. 2 is a timing diagram of driving a pixel driver circuit according to an embodiment of the present disclosure; Fig. 3 is a schematic diagram of the layout of a pixel driver circuit according to an embodiment of the present disclosure; Fig. 4 is a schematic diagram of the layout of an active layer and a first electrically conductive layer in Fig. 3; Fig. Figure 5 is a schematic diagram of the layout of a second electrically conductive layer in Fig. 3; Fig. Figure 6 is a schematic diagram of the layout of a third electrically conductive layer in Fig. 3; Fig. Figure 7 is a schematic diagram of the layout of a fourth electrically conductive layer in Fig. 3; Fig. Figure 8 is a schematic diagram of the layout of a first electrically conductive layer, a second electrically conductive layer and a third electrically conductive layer in Fig. 3; Fig. 9 is a schematic diagram of the layout of a first electrically conductive layer, a second electrically conductive layer and a fourth electrically conductive layer in Fig. 3; Fig. 10 is a schematic diagram of the layout of a first electrically conductive layer, a second electrically conductive layer, a third electrically conductive layer and a fourth electrically conductive layer in Fig. 3; Fig. 11 is a schematic diagram of the layout of a 2-row, 4-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 12 is a schematic diagram of the layout of active layers in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 13 is a schematic diagram of the layout of a first electrically conductive layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 14 is a schematic diagram of the layout of a second electrically conductive layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 15 is a schematic diagram of the positions of via holes formed on an interlayer insulating layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 16 is a schematic diagram of the layout of a third electrically conductive layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 17 is a schematic diagram of the positions of vias formed on a first planarization layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 18 is a schematic diagram of the positions of vias formed on a passivation layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 19 is a schematic diagram of the layout of a fourth electrically conductive layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 20 is a schematic diagram of the positions of vias formed on a second planarization layer in a 2-row, 6-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 21 shows a second electrically conductive layer, a third electrically conductive layer, and a fourth electrically conductive layer in a 1-row, 3-column pixel driver circuit according to an embodiment of the present disclosure; Fig. 22 is a schematic diagram of the layout of vias in a pixel driver circuit according to an embodiment of the present disclosure; Fig. 23 is a schematic diagram of via holes formed on the interlayer insulating layer in a pixel driver circuit according to an embodiment of the present disclosure; Fig. 24 is a schematic diagram of the positions of vias formed on a first planarization layer in a pixel driver circuit according to an embodiment of the present disclosure; Fig. 25 is a schematic diagram of the positions of vias formed on a second planarization layer in a pixel driver circuit according to an embodiment of the present disclosure. EMBODIMENTS OF THE INVENTION

[0029] In order to further explain the pixel driving circuit, the display substrate and the display device provided in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings of the specification.

[0030] As the resolution and frame rate of display products increase, the scanning line period becomes shorter, which limits the detection and compensation accuracy of the threshold voltage detection of the pixel driver circuit in display products.

[0031] With reference to the Fig. 1 and Fig. 2, an embodiment of the present disclosure provides a pixel driver circuit for driving light-emitting elements. The pixel driver circuit includes: a driver subcircuit 10, the first end of which is coupled to a power supply line VDD; a compensation subcircuit 11, which is coupled to a scanning line GA, a control end of the driver subcircuit 10 and a second end of the driver subcircuit 10, respectively, and which is provided to control the switching on and off of an electrical connection between the control end and the second end of the driver subcircuit 10 under the control of the scanning line GA; a coupling subcircuit 12, the first end of which is coupled to the control end of the driver subcircuit 10; a memory subcircuit 13, the first end of which is coupled to a second end of the coupling subcircuit 12; a data write subcircuit 14, each coupled to a second end of the memory subcircuit 13, a data line DA, and a reset line Rst, and configured to control, under the control of the reset line Rst, the switching on and off of an electrical connection between the second end of the memory subcircuit 13 and the data line DA; a first reset subcircuit 15, which is coupled to the reset line Rst, an initialization signal line Init, the control end of the driver subcircuit 10 and the second end of the coupling subcircuit 12, respectively, and which is provided to control, under the control of the reset line Rst, the switching on and off of an electrical connection between the initialization signal line Init and the control end of the driver subcircuit 10 and to control the switching on and off of an electrical connection between the initialization signal line Init and the second end of the coupling subcircuit 12; a first holding subcircuit 16, which is coupled to the scanning line GA, the second end of the coupling subcircuit 12 and the initialization signal line Init, respectively, and which is provided to control, under the control of the scanning line GA, the switching on and off of an electrical connection between the second end of the coupling subcircuit 12 and the initialization signal line Init; a second holding subcircuit 17, which is coupled to a first control line EM', a reference signal line Ref and the second end of the memory subcircuit 13, respectively, and which is provided to control, under the control of the first control line EM', the switching on and off of an electrical connection between the reference signal line Ref and the second end of the memory subcircuit 13.

[0032] With reference to Fig. 1 and Fig. 2, the pixel driver circuit in some embodiments further comprises: a light emission control subcircuit 18, which is coupled to the second end of the driver subcircuit 10, the light-emitting element F1, and a second control line EM, respectively, and which is provided to control the switching on and off of an electrical connection between the second end of the driver subcircuit 10 and the light-emitting element under the control of the second control line EM. The cathode of the light-emitting element F1 is coupled to a negative power supply line VSS.

[0033] With reference to Fig. 1 and Fig. 2, the pixel driver circuit in some embodiments further comprises: a second reset subcircuit 19 which is coupled to the scanning line GA, the light-emitting element and the initialization signal line Init, respectively, and which is provided to control the switching on and off of an electrical connection between the light-emitting element and the initialization signal line Init under the control of the scanning line GA.

[0034] A duty cycle of the pixel driver circuit includes: a reset write phase P1, a threshold voltage detection phase P2, and a light emission phase P3.

[0035] In the reset write phase P1: The reset signal written by the reset line Rst is at an active level (e.g., a low level). Under the action of the reset signal, the first reset subcircuit 15 controls the electrical connection between the initialization signal line Init and the control end (defined as the N1 node) of the driver subcircuit 10, and controls the electrical connection between the initialization signal line Init and the second end (defined as the N2 node) of the coupling subcircuit 12. The control end of the driver subcircuit 10 and the second end of the coupling subcircuit 12 are reset.Under the action of the reset signal, the data write subcircuit 14 controls the electrical connection between the second end (defined as the N3 node) of the memory subcircuit 13 and the data line DA and writes the data signal provided by the data line DA to the second end of the memory subcircuit 13. In the reset write phase P1, the potential of the N1 node is Vinit, the potential of the N2 node is Vinit, and the potential of the N3 node is Vdt. Vinit is the voltage value of the initial signal transmitted by the initialization signal line Init. Vdt is the voltage value of the data signal.

[0036] In the threshold voltage detection phase P2: The scanning signal written by the scanning line GA is at an active level (e.g., a low level). Under the action of the scanning signal, the compensation subcircuit 11 controls the electrical connection between the control end and the second end of the driver subcircuit 10. The first hold subcircuit 16 controls the electrical connection between the second end of the coupling subcircuit 12 and the initialization signal line Init. The second reset subcircuit 19 controls the electrical connection between the light-emitting element and the initialization signal line Init. In the threshold voltage detection phase P2, the potential of the N1 node is Vdd-|Vth|, the potential of the N2 node is Vinit, and the potential of the N3 node is Vdt. Vdd is the voltage value of the power supply signal transmitted from the power supply line VDD.Vth is the threshold voltage of the driver transistor included in the driver subcircuit 10.

[0037] In the light emission phase P3: The first light emission control signal written by the first control line EM' is at an active level (e.g., a low level). Under the action of the first light emission control signal, the second holding subcircuit 17 controls the electrical connection between the reference signal line Ref and the second end of the memory subcircuit 13 to be turned on. The second light emission control signal written by the second control line EM is at an active level (e.g., a low level). Under the action of the second light emission control signal, the light emission control subcircuit 18 controls the electrical connection between the second end of the driver subcircuit 10 and the light-emitting element to be turned on. In the light emission phase P3, the potential of the N1 node is Vdd-IVthl+Vref-Vdt, the potential of the N2 node is Vinit+Vref-Vdt, and the potential of the N3 node is Vref.Vref is the voltage value of the reference signal transmitted by the reference signal line Ref.

[0038] In the light emission phase P3, the driver circuit that drives the light-emitting element to emit light is: I = k(Vgs-Vth) 2 , where k is a constant, Vgs is the gate-source voltage of the driver transistor included in the driver subcircuit 10.

[0039] Finally we get: I=k(Vref-Vdt) 2 .

[0040] According to the specific structure of the above pixel driver circuit, it can be seen that in a pixel driver circuit provided in the embodiment of the present disclosure, writing of the data signal is performed in the reset write phase P1, and this operation is a refresh operation of data signals. In the threshold voltage detection phase P2, detection of the threshold voltage is performed.Therefore, in the pixel driving circuit provided in the embodiment of the present disclosure, the refresh operation of data signals and the detection operation of the threshold voltage are separated as two separate operations, so that the detection operation of the threshold voltage is not restricted by any sampling period, a relatively ideal charging rate for the storage subcircuit 13 and a relatively ideal threshold voltage detection accuracy are enabled by extending the time of the detection operation, while satisfying a high refresh rate (ie, a high frame rate) at the same time as ensuring a sufficient time for detection of the threshold voltage.

[0041] In the pixel driving circuit provided in the embodiment of the present disclosure, by controlling a relatively short refresh operation time, it can be facilitated that a display product in which the pixel driving circuit is applied achieves a high resolution and a high frame rate.

[0042] In the pixel driving circuit provided in the embodiment of the present disclosure, the driving current of the light-emitting element is made correlated only with the reference signal and the data signal, thereby avoiding the influence of the threshold voltage on the driving current.

[0043] With reference to Fig. 1, Fig. 2 and Fig. 4, in some embodiments, the coupling subcircuit 12 comprises a first capacitor C1, the memory subcircuit 13 comprises a second capacitor C2, the data write subcircuit 14 comprises a first transistor T1, the compensation subcircuit 11 comprises a second transistor T2, the driver subcircuit 10 comprises a third transistor T3, the first reset subcircuit 15 comprises a fourth transistor T4 and a fifth transistor T5, the second reset subcircuit 19 comprises a sixth transistor T6, the first hold subcircuit 16 comprises a seventh transistor T7, the light emission control subcircuit 18 comprises an eighth transistor T8, the second hold subcircuit 17 comprises a ninth transistor T9; wherein a gate electrode of the first transistor T1 is coupled to the reset line Rst, a first pole of the first transistor T1 is coupled to the data line DA, a second pole of the first transistor T1 is coupled to a second end of the second capacitor C2; wherein a gate electrode of the second transistor T2 is coupled to the scan line GA, a first pole of the second transistor T2 is coupled to a second pole of the third transistor T3, a second pole of the second transistor T2 is coupled to a gate electrode T3-g of the third transistor T3; wherein a first pole of the third transistor T3 is coupled to the power supply line VDD; wherein a first end of the first capacitor C1 is coupled to the gate electrode T3-g of the third transistor T3, a first end of the second capacitor C2 is coupled to a second end of the first capacitor C1; wherein a gate electrode of the fourth transistor T4 is coupled to the reset line Rst, a first pole of the fourth transistor T4 is coupled to the initialization signal line Init, a second pole of the fourth transistor T4 is coupled to the gate electrode T3-g of the third transistor T3; wherein a gate electrode of the fifth transistor T5 is coupled to the reset line Rst, a first pole of the fifth transistor T5 is coupled to the initialization signal line Init, a second pole of the fifth transistor T5 is coupled to the second end of the first capacitor C1; wherein a gate electrode of the sixth transistor T6 is coupled to the scanning line GA, a first pole of the sixth transistor T6 is coupled to the initialization signal line Init, a second pole of the sixth transistor T6 is coupled to the light-emitting element; wherein a gate electrode of the seventh transistor T7 is coupled to the scanning line GA, a first pole of the seventh transistor T7 is coupled to the initialization signal line Init, a second pole of the seventh transistor T7 is coupled to the second end of the first capacitor C1; wherein a gate electrode of the eighth transistor T8 is coupled to the second control line EM, a first pole of the eighth transistor T8 is coupled to the second pole of the third transistor T3, a second pole of the eighth transistor T8 is coupled to the light-emitting element; wherein a gate electrode of the ninth transistor T9 is coupled to the first control line EM', a first pole of the ninth transistor T9 is coupled to the reference signal line Ref, a second pole of the ninth transistor T9 is coupled to the second end of the second capacitor C2.

[0044] By way of example, the first transistor T1 to the ninth transistor T9 are all P-type transistors, but are not limited thereto.

[0045] In the reset write phase P1: The reset signal written by the reset line Rst is at an active level (e.g., a low level). Under the action of the reset signal, the fourth transistor T4 controls the electrical connection between the initialization signal line Init and the gate electrode T3-g (defined as the N1 node) of the third transistor T3 to be turned on. The fifth transistor T5 controls the electrical connection between the initialization signal line Init and the second end (defined as the N2 node) of the first capacitor C1 to be turned on. The gate electrode T3-g of the third transistor T3 and the second end of the first capacitor C1 are reset.Under the action of the reset signal, the first transistor T1 controls the electrical connection between the second end (defined as the N3 node) of the second capacitor C2 and the data line DA and writes the data signal provided by the data line DA to the second end of the second capacitor C2. In the reset write phase P1, the potential of the N1 node is Vinit, the potential of the N2 node is Vinit, and the potential of the N3 node is Vdt.

[0046] In the threshold voltage detection phase P2: The scanning signal written by the scanning line GA is at an active level (e.g., a low level). Under the action of the scanning signal, the second transistor T2 controls the turning on of the electrical connection between the gate electrode T3-g and the second terminal of the third transistor T3; the seventh transistor T7 controls the turning on of the electrical connection between the second end of the first capacitor C1 and the initialization signal line Init; and the sixth transistor T6 controls the turning on of the electrical connection between the light-emitting element and the initialization signal line Init. In the threshold voltage detection phase P2, the potential of the N1 node is Vdd-|Vth|, the potential of the N2 node is Vinit, and the potential of the N3 node is Vdt.

[0047] In the light emission phase P3: The first light emission control signal written by the first control line EM' is at an active level (e.g., a low level). Under the action of the first light emission control signal, the ninth transistor T9 controls the switching on of the electrical connection between the reference signal line Ref and the second end of the memory subcircuit 13. The second light emission control signal written by the second control line EM is at an active level (e.g., a low level). Under the action of the second light emission control signal, the eighth transistor T8 controls the switching on of the electrical connection between the second terminal of the third transistor T3 and the light-emitting element. In the light emission phase P3, the potential of the N1 node is Vdd-|Vth|+Vref-Vdt, the potential of the N2 node is Vinit+Vref-Vdt, and the potential of the N3 node is Vref.In the light emission phase P3, the driving circuit that drives the light-emitting element to emit light is: I = k(Vgs-Vth). 2 , finally we get: I=k(Vref-Vdt) 2 .

[0048] In a pixel driver circuit provided in the embodiment of the present disclosure, the writing of the data signal is performed in the reset write phase P1, and this operation is a refresh operation of data signals. In the threshold voltage detection phase P2, the detection of the threshold voltage is performed. Therefore, in the pixel driver circuit provided in the above embodiment of the present disclosure, the refresh operation of data signals and the detection operation of the threshold voltage are separated as two separate operations, so that the detection operation of the threshold voltage is not limited by any sampling period, by extending the detection time, a relatively ideal charging rate for the memory subcircuit 13 and a relatively ideal threshold voltage detection accuracy are enabled, while satisfying a high refresh rate (ie,a high frame rate) at the same time ensures sufficient time for recording the threshold voltage.

[0049] In the pixel driving circuit provided in the above embodiment of the present disclosure, by controlling a relatively short refresh operation time, it can be facilitated that a display product to which the pixel driving circuit is applied achieves a high resolution and a high frame rate.

[0050] In the pixel driving circuit provided in the above embodiment of the present disclosure, the driving current of the light-emitting element is made correlated only with the reference signal and the data signal, thereby avoiding the influence of the threshold voltage on the driving current.

[0051] As in Fig. 3 to Fig. 10 and Fig. 16, an embodiment of the present disclosure still provides a display substrate comprising a plurality of the pixel driving circuits provided in the above embodiment, wherein the pixel driving circuit comprises a first capacitor C1 and a third transistor T3, wherein the first capacitor C1 comprises a first electrode plate C11 and a second electrode plate C12 arranged opposite to each other, wherein the first electrode plate C11 is multiplexed as a gate electrode T3-g of the third transistor T3; the display substrate includes: a plurality of data lines DA including at least one part extending along a first direction, wherein the orthographic projection of the data line DA on the substrate of the display substrate and the orthographic projection of the first electrode plate C11 on the substrate are arranged along a second direction, wherein the first direction and the second direction intersect; a plurality of first shielding patterns 20, wherein at least a part of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the first electrode plate C11 on the substrate.

[0052] As in Fig. 11 to Fig. 20, the display substrate exemplarily includes a plurality of subpixels, and a plurality of pixel driver circuits 50 included in the plurality of subpixels are distributed in an array. The plurality of pixel driver circuits 50 are divided into a plurality of rows of pixel driver circuits and a plurality of columns of pixel driver circuits. The plurality of rows of pixel driver circuits are arranged along a first direction, each row of pixel driver circuits including a plurality of pixel driver circuits arranged along a second direction. The plurality of columns of pixel driver circuits are arranged along the second direction, each column of pixel driver circuits including a plurality of pixel driver circuits arranged along the first direction. By way of example, the first direction and the second direction intersect. For example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0053] By way of example, the subpixel comprises a pixel driver circuit and a light-emitting element. The pixel driver circuit is coupled to the anode of the light-emitting element and is provided to provide a drive signal for the light-emitting element and to drive the light-emitting element to emit light.

[0054] It is pointed out: Fig. Figure 15 is a schematic diagram of the positions of through holes formed on an interlayer insulating layer in Fig. 11 are formed; Fig. Figure 17 is a schematic diagram of the positions of through holes formed on a first planarization layer in Fig. 11 are formed; Fig. Figure 18 is a schematic diagram of the positions of through holes formed on a passivation layer in Fig. 11 are formed; Fig. Figure 20 is a schematic diagram of the positions of through holes formed on a second planarization layer in Fig. 11 are formed.

[0055] For example, the third transistor T3 serves as a driver transistor in the pixel driver circuit. The first electrode plate C11 is multiplexed as the gate electrode T3-g of the third transistor T3 and serves as the N1 node.

[0056] For example, the orthographic projection of the first electrode plate C11 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C12 on the substrate.

[0057] By way of example, the plurality of data lines DA are arranged along the second direction. The plurality of data lines DA correspond one-to-one to the plurality of columns of pixel driver circuits. The data lines DA are each electrically connected to the first poles of the respective first transistors T1 in pixel driver circuits of a corresponding column to provide data signals.

[0058] For example, the plurality of first shielding patterns 20 correspond one-to-one to the plurality of data lines DA, at least a part of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the first electrode plate C11 adjacent to the data line DA on the substrate.

[0059] As in Fig. For example, as shown in Figure 21, adjacent first shielding patterns 20 are spaced apart from each other along the second direction by at least one subpixel. Along the second direction, a first shielding pattern 20 is located between two adjacent second electrode plates C12 or two adjacent third electrode plates C21.

[0060] According to the specific structure of the above-mentioned display substrate, it can be seen that in the display substrate provided in the embodiment of the present disclosure, the first shield pattern 20 can shield the influence between the data line DA and the N1 node and reduce the crosstalk between the data line DA and the N1 node by arranging at least a part of the orthographic projection of the first shield pattern 20 on the substrate between the orthographic projection of the data line DA on the substrate and the orthographic projection of the first electrode plate C11 on the substrate, and / or by arranging at least a part of the orthographic projection of the first shield pattern on the substrate between the orthographic projection of the data line on the substrate and the orthographic projection of the second electrode plate on the substrate.

[0061] As in Fig. 3 to Fig. 10, Fig. 16 and Fig. 21, in some embodiments, at least a portion of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the second electrode plate C12 on the substrate.

[0062] For example, the orthographic projection of the first shielding pattern 20 on the substrate partially overlaps with the orthographic projection of the second electrode plate C12 on the substrate.

[0063] By way of example, the first transistor T1 comprises a first active layer, the orthographic projection of the first shielding pattern 20 on the substrate partially overlaps with the orthographic projection of the first active layer on the substrate.

[0064] By way of example, the first active layer forms a first channel part included in the first transistor T1, and the orthographic projection of the first shielding pattern 20 on the substrate partially overlaps with the orthographic projection of the first channel part on the substrate.

[0065] For example, the orthographic projection of the first shielding pattern 20 on the substrate partially overlaps with the orthographic projection of the gate electrode of the first transistor T1 on the substrate.

[0066] The second electrode plate C12 is the aforementioned N2 node. The first shielding pattern 20 can shield the influence between the data line DA and the N2 node, and crosstalk between the data line DA and the N2 node is reduced by providing, as above, that at least a portion of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the second electrode plate C12 on the substrate.

[0067] As in Fig. 3 to Fig. 10 and Fig. 16, in some embodiments, the pixel driver circuit further comprises a second capacitor C2, and the second capacitor C2 comprises a third electrode plate C21 and a fourth electrode plate C22 arranged opposite each other, the third electrode plate C21 being coupled to the second electrode plate C12; wherein the third electrode plate C21 and the second electrode plate C12 are arranged along the first direction; wherein at least a portion of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the third electrode plate C21 on the substrate; and / or at least a portion of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the fourth electrode plate C22 on the substrate.

[0068] For example, the orthographic projection of the third electrode plate C21 on the substrate overlaps at least partially with the orthographic projection of the fourth electrode plate C22 on the substrate.

[0069] For example, the third electrode plate C21 and the second electrode plate C12 are formed into an integrated structure. The second electrode plate C12 and the third electrode plate C21 serve as the N2 node.

[0070] For example, the fourth electrode plate C22 and the first electrode plate C11 are provided on the same layer and made of the same material. The fourth electrode plate C22 and the first electrode plate C11 are arranged along the first direction.

[0071] For example, the orthographic projection of the first shielding pattern 20 on the substrate partially overlaps with the orthographic projection of the third electrode plate C21 on the substrate. The orthographic projection of the first shielding pattern 20 on the substrate partially overlaps with the orthographic projection of the fourth electrode plate C22 on the substrate.

[0072] The first shielding pattern 20 can shield the influence between the data line DA and the N2 node, and the crosstalk between the data line DA and the N2 node is reduced by providing, as above, that at least a part of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the third electrode plate C21 on the substrate.

[0073] The fourth electrode plate C22 is the aforementioned N3 node. The first shielding pattern 20 can shield the influence between the data line DA and the N3 node, and crosstalk between the data line DA and the N3 node is reduced by providing, as above, that at least a portion of the orthographic projection of the first shielding pattern 20 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the fourth electrode plate C22 on the substrate.

[0074] As in Fig. 3 to Fig. 10, Fig. 16 and Fig. 21, in some embodiments, the first shielding pattern 20 includes a first shielding part 201 and a second shielding part 201 coupled to each other, wherein the first shielding part 201 and the second shielding part 202 are arranged along the second direction, at least a part of the orthographic projection of the data line DA on the substrate is located between the orthographic projection of the first shielding part 201 on the substrate and the orthographic projection of the second shielding part 202 on the substrate; wherein at least a portion of the orthographic projection of the first shielding part 201 on the substrate is located between the orthographic projection of at least one of the adjacent first capacitor C1 or second capacitor C2 on the substrate and the orthographic projection of the data line DA on the substrate; and / or, at least a portion of the orthographic projection of the second shielding part 202 on the substrate is located between the orthographic projection of at least one of the adjacent first capacitor C1 or second capacitor C2 on the substrate and the orthographic projection of the data line DA on the substrate.

[0075] It should be noted that the first capacitor C1 or second capacitor C2 adjacent to the first shielding part 201 refers to a first capacitor C1 or second capacitor C2 that is closest to the first shielding part 201 along the second direction; that the first capacitor C1 or second capacitor C2 adjacent to the second shielding part 202 refers to a first capacitor C1 or second capacitor C2 that is closest to the second shielding part 202 along the second direction.

[0076] For example, the first shielding part 201 and the second shielding part 202 are formed into an integrated structure.

[0077] For example, the first shielding part 201 and the second shielding part 202 are jointly formed into a structure similar to an n-shaped pattern. The orthographic projection of the first shielding pattern 20 on the substrate at least partially overlaps with the orthographic projection of the data line DA on the substrate.

[0078] For example, at least a part of the orthographic projection of the first shielding part 201 on the substrate is located between the orthographic projection of at least one of the first electrode plate C11, second electrode plate C12, third electrode plate C21 or fourth electrode plate C22 adjacent to it on the substrate and the orthographic projection of the data line DA on the substrate.

[0079] For example, at least a part of the orthographic projection of the second shielding part 202 on the substrate is located between the orthographic projection of at least one of the first electrode plate C11, second electrode plate C12, third electrode plate C21 or fourth electrode plate C22 adjacent to it on the substrate and the orthographic projection of the data line DA on the substrate.

[0080] In the display substrate provided in the above embodiment, the distance between the above data line DA and the N1 node, N2 node, or N3 node adjacent thereto can be increased.

[0081] In the display substrate provided by the above embodiment, the first shielding part 201 and the second shielding part 202 can be located on the two sides, ie, the left side and the right side, of the data line DA and both enable shielding of crosstalk between the data line DA and the N1 node, the N2 node, and the N3 node by providing the first shielding pattern 20 having a first shielding part 201 and a second shielding part 202.

[0082] As in Fig. 3, Fig. 4, Fig. 6 and Fig. 16, in some embodiments, the display substrate further comprises a second electrically conductive connection part 42 and a data line DA, wherein the pixel driver circuit further comprises a first transistor T1, wherein a first pole of the first transistor T1 is coupled to a corresponding data line DA, a second pole of the first transistor T1 is coupled to the fourth electrode plate C22 via the corresponding second electrically conductive connection part 42; the second electrically conductive connection part 42 is located between the first shielding patterns 20 adjacent along the second direction.

[0083] The above arrangement can facilitate better shielding from crosstalk between the data line DA and the N3 node.

[0084] As in Fig. 3, Fig. 4, Fig. 6 and Fig. 16, in some embodiments, the display substrate further comprises a third electrically conductive connection part 43 and a fifth electrically conductive connection part 45, wherein the pixel driver circuit further comprises a second transistor T2 and a third transistor T3, wherein a second pole of the second transistor T2 is coupled to a gate electrode of the third transistor T3 via the third electrically conductive connection part 43, a second pole of the fifth transistor T5 is coupled to the second electrode plate C12 via the fifth electrically conductive connection part 45; the third electrically conductive connection part 43 is located between the first shielding patterns 20 adjacent along the second direction, the fifth electrically conductive connection part 45 is located between the first shielding patterns 20 adjacent along the second direction.

[0085] By the above arrangement, better shielding from the crosstalk of the data line DA to the third electrically conductive connecting part 43 and the fifth electrically conductive connecting part 45 can be facilitated.

[0086] As in Fig. 3 to Fig. 10 and Fig. 16, in some embodiments, the display substrate further comprises: a plurality of shielding lines 21 including at least one part extending along the second direction; wherein the plurality of pixel driver circuits are divided into a plurality of rows of pixel driver circuits, the orthographic projection of the shield line 21 on the substrate at least partially overlaps with the orthographic projection of an edge of each first electrode plate C11 located near the fourth electrode plate C22 in pixel driver circuits of a corresponding row on the substrate.

[0087] For example, the plurality of shield lines 21 are arranged along the first direction. The plurality of shield lines 21 correspond one-to-one to the plurality of rows of pixel driver circuits.

[0088] For example, the orthographic projection of the shielding line 21 on the substrate overlaps at least partially with the orthographic projection of an edge of the respective second electrode plate C12 located near the third electrode plate C21 in pixel driver circuits of a corresponding row on the substrate.

[0089] By the above arrangement, effective shielding from crosstalk between the first capacitor C1 and the second capacitor C2 can be achieved.

[0090] As in Fig. 3, Fig. 4 and Fig. 6, in some embodiments, the display substrate further comprises a reset line Rst, wherein the shield line 21 and the reset line Rst are arranged along the first direction, both the third electrically conductive connecting part 43 and the fifth electrically conductive connecting part 45 are located between the shield line 21 and the reset line Rst.

[0091] The above layout method can ensure the shielding effect and at the same time reduce the layout difficulty of the pixel circuit.

[0092] As in Fig. 16, the first shielding pattern 20 further comprises a third shielding part 203. The orthographic projection of the third shielding part 203 on the substrate is located between the orthographic position of the data line DA on the substrate and the fifth electrically conductive connecting part 45.

[0093] By the above arrangement, better shielding from crosstalk of the data line DA to the fifth electrically conductive connecting part 45 can be facilitated.

[0094] Note that the shield lines 21 are each coupled to the first shield patterns 20 located in the same row along the second direction. The first shield patterns 20 are coupled to the power supply lines, so that the structure transmitting the power supply signals can be integrally formed as a lattice-like structure, promoting the reduction of the loading of the power supply signals and improving the display uniformity of the entire display substrate.

[0095] The connection positions of the shield line 21 and the first shield pattern 20 can be adjusted according to actual needs, as long as the correct operating performance of the pixel driver circuits can be ensured. The shield line 21 can be linear or wave-shaped, or even arranged in sections.

[0096] The shield line and the first shield pattern must not be switched on with a power supply signal. For example, the shield line and the first shield pattern can be coupled to the reset line Rst and switched on with the reset signal, so that the shielding effect can also be enabled.

[0097] As in Fig. 3 to Fig. 10 and Fig. 16, in some embodiments, the plurality of first shielding patterns 20 are divided into a plurality of rows of first shielding patterns 20, and the shielding lines 21 are each coupled to first shielding patterns 20 of a corresponding row.

[0098] For example, the plurality of rows of first shielding patterns 20 correspond one-to-one to the plurality of rows of pixel driving circuits.

[0099] For example, the shielding line 21 is coupled to the first shielding parts 201 and the second shielding parts 202 in the first shielding patterns 20 of a corresponding row, which are included in the respective first shielding patterns 20.

[0100] For example, the shielding line 21 is formed into an integrated structure with both the first shielding parts 201 and the second shielding parts 202 in the first shielding patterns 20 of a corresponding row, which are included in the respective first shielding patterns 20.

[0101] By way of example, in the first shielding patterns 20 of the same row, two surrounding structures are formed between adjacent first shielding patterns 20 and the shielding line 21 coupled to them. The orthographic projection of one surrounding structure on the substrate surrounds at least a portion of the orthographic projection of the first capacitor C1 on the substrate; the orthographic projection of another surrounding structure on the substrate surrounds at least a portion of the orthographic projection of the second capacitor C2 on the substrate.

[0102] By the above arrangement, effective shielding from crosstalk between the first capacitor C1 and the second capacitor C2 can be achieved.

[0103] As in Fig. 3 to Fig. 10, Fig. 16 and Fig. 19, in some embodiments, the display substrate includes power supply lines VDD, the first shield patterns 20 are coupled to the power supply lines VDD.

[0104] By way of example, the display substrate comprises a plurality of power supply lines VDD, the plurality of power supply lines VDD correspond one-to-one to the plurality of columns of pixel driver circuits, the power supply lines VDD are each coupled to the first poles of the driver transistors included in the respective pixel driver circuits of the pixel driver circuits of a corresponding column.

[0105] For example, the VDD power supply lines are used to transmit stable power supply signals.

[0106] For example, the orthographic projection of the second shielding part 202 on the substrate has an overlap region with the orthographic projection of the power supply line VDD on the substrate. The second shielding part 202 and the power supply line VDD are coupled in the overlap region.

[0107] For example, along the first direction, the adjacent second shielding parts 202 may be connected via an electrically conductive structure, the second shielding part 202 near the frame region of the display substrate may be coupled to the power supply bus located in the frame region to receive power supply signals.

[0108] The first shielding pattern 20 is coupled to the power supply line VDD, so that the first shielding pattern 20 has a stable power supply signal, which promotes the improvement of the shielding effect.

[0109] As in Fig. 3 to Fig. 10 and Fig. 16, in some embodiments, the first shielding patterns 20, the shielding lines 21 and the third electrically conductive connecting parts 43 are arranged on a same layer.

[0110] As in Fig. 3 to Fig. 10 and Fig. 16, in some embodiments, the first shielding pattern 20, the shielding line 21 and the third electrically conductive connecting part 43 are both made of a third electrically conductive layer in the display substrate.

[0111] The above arrangement contributes to reducing the resistance of the first shield pattern 20 and reducing the load on the power supply line VDD during power supply signal transmission. At the same time, it ensures that the first shield pattern 20 has sufficient layout space, reducing the layout difficulty of the first shield pattern 20.

[0112] As in Fig. 6, in some embodiments, the display substrate further includes a reset line Rst. The shield line 21 and the reset line Rst are arranged along the first direction; both the third electrically conductive connecting part 43 and the fifth electrically conductive connecting part 45 are located between the shield line 21 and the reset line Rst.

[0113] As in Fig. 3 to Fig. 10 and Fig. 13, in some embodiments, the display substrate further comprises: a plurality of second shielding patterns 22 comprising at least a portion extending along the first direction, wherein the orthographic projection of the second shielding pattern 22 on the substrate at least partially overlaps with the orthographic projection of the data line DA on the substrate.

[0114] For example, the plurality of second shielding patterns 22 correspond one-to-one to a plurality of pixel driver circuits in the display substrate. The orthographic projection of the second shielding pattern 22 on the substrate at least partially overlaps with the orthographic projection of the data line DA, which is coupled to its corresponding pixel driver circuit, on the substrate.

[0115] For example, at least a part of the orthographic projection of the second shielding pattern 22 on the substrate is located between the orthographic projection of the first shielding part 201 on the substrate and the orthographic projection of the second shielding part 202 on the substrate.

[0116] As provided above, the display substrate further includes the second shielding pattern 22 so that the second shielding pattern 22 can further shield the influences between the data line DA and the N1 node, between the N2 node and the N3 node.

[0117] As in Fig. 3 to Fig. 10 and Fig. 13, in some embodiments, the display substrate further comprises a plurality of second control lines EM; the second shield patterns 22 located in a same row along the second direction are each coupled to a corresponding second control line EM.

[0118] For example, the plurality of second control lines EM correspond one-to-one to the plurality of rows of pixel driver circuits, respectively, the second control lines EM are each coupled to the gate electrodes of the eighth transistors T8 included in the respective pixel driver circuits in the pixel driver circuits of a corresponding row.

[0119] By way of example, the second control line EM, which is coupled to the gate electrode of the eighth transistor T8 in the pixel driver circuit, is multiplexed as the first control line EM', which is coupled to the ninth transistor T9 in the pixel driver circuit adjacent along the first direction.

[0120] As provided above, the second shield patterns 22 located in the same row along the second direction are each coupled to a corresponding second control line EM so that the second shield pattern 22 has a same potential as the second control line EM, thereby preventing the second shield pattern 22 from being in a floating state and impairing the stability of the pixel driving circuit.

[0121] In some embodiments, the orthographic projection of the second shielding pattern 22 on the substrate is completely covered by the orthographic projection of the data line DA coupled to its corresponding pixel driver circuit on the substrate.

[0122] In some embodiments, the orthographic projection of the second shielding pattern 22 on the substrate does not overlap with the orthographic projection of the data line DA coupled to its corresponding pixel driver circuit on the substrate.

[0123] In some embodiments, the display substrate further includes a power supply line VDD and an initialization signal line Init, and the second shield pattern 22 is coupled to the power supply line VDD or the initialization signal line Init.

[0124] In some embodiments, the second shield pattern is coupled to the power supply line in the display substrate such that the second shield pattern has a same potential as the power supply signal, thereby preventing the second shield pattern from being in a floating state and affecting the stability of the pixel driver circuit.

[0125] In some embodiments, the second shield pattern is coupled to an initialization signal line in the display substrate such that the second shield pattern has a potential equal to the initialization signal, thereby preventing the second shield pattern from being in a floating state and affecting the stability of the pixel driver circuit.

[0126] As in Fig. 3 to Fig. 10 and Fig. 13, in some embodiments, the second shield patterns 22 located in a same row along the second direction and a corresponding second control line EM are formed into an integrated structure.

[0127] For example, the second shielding pattern 22 and the second control line EM are both made of the first electrically conductive layer in the display substrate.

[0128] The above arrangement enables the second shield pattern 22 and the second control lines EM to be simultaneously formed in a same patterning process, thereby facilitating the simplification of the manufacturing process of the display substrate.

[0129] As in Fig. 3 to Fig. 10, Fig. 11, Fig. 14, Fig. 19 and Fig. 21, in some embodiments, the display substrate further comprises: a plurality of initialization signal lines Init arranged along the first direction, the initialization signal lines Init comprising at least a part extending along the second direction; a plurality of initial connection lines 30 arranged along the second direction, wherein the initial connection lines 30 include at least one portion extending along the first direction, each of the initial connection lines 30 being coupled to the plurality of initialization signal lines Init. The A2 portion in Fig. 21 illustrates a connection point of the initialization signal line Init and the initial connection line 30.

[0130] For example, the multiple initialization signal lines Init correspond one-to-one to the multiple rows of pixel driver circuits. A fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor belonging to the same pixel driver circuit are coupled to one and the same corresponding initialization signal line Init.

[0131] As provided above, the display substrate includes the plurality of initialization signal lines Init and the plurality of initial connection lines 30, so that the plurality of initialization signal lines Init and the plurality of initial connection lines 30 are formed as a lattice-shaped structure, the loading and IR drop of the initialization signal lines Init during transmission of initialization signals are effectively reduced.

[0132] As in Fig. 3 to Fig. 10, Fig. 11, Fig. 14, Fig. 19 and Fig. 21, in some embodiments, the display substrate further comprises: a plurality of reference signal lines Ref arranged along the first direction, the reference signal lines Ref including at least a portion extending along the second direction; a plurality of reference connection lines 31 arranged along the second direction, wherein the reference connection lines 31 include at least one part extending along the first direction, each of the reference connection lines 31 being coupled to the plurality of reference signal lines Ref. The A1 part in Fig. 21 illustrates a connection point of the reference signal line Ref and the reference connection line 31.

[0133] For example, the plurality of reference signal lines Ref correspond one-to-one to the plurality of rows of pixel driver circuits, the reference signal lines Ref are each coupled to the ninth transistors T9 included in the respective pixel driver circuits in the pixel driver circuits of a corresponding row.

[0134] As provided above, the display substrate includes the plurality of reference signal lines Ref and the plurality of reference connection lines 31, so that the plurality of reference signal lines Ref and the plurality of reference connection lines 31 are formed into a lattice-like structure, effectively reducing the loading and IR drop of the reference signal lines Ref during the transmission of reference signals. The drive current of the light-emitting element of the pixel drive circuit is correlated with the reference signal, and the above effect of reducing the loading and IR drop facilitates the optimization of the data range of the data signal transmitted by the data line DA.

[0135] As in Fig. 3 to Fig. 10, FIG. Fig. 11, Fig. 14, Fig. 19 and Fig. 21, in some embodiments, the initial connection lines 30 and the reference connection lines 31 are arranged alternately along the second direction; wherein the plurality of pixel driver circuits are divided into a plurality of columns of pixel driver circuits, each column of pixel driver circuits corresponding to one of the initial connection lines 30 or one of the reference connection lines 31; the orthographic projection of the initial connection line 30 on the substrate at least partially overlaps with the orthographic projection of a second electrode plate C12 in a pixel driver circuit of a corresponding column on the substrate; and / or the orthographic projection of the reference connection line 31 on the substrate at least partially overlaps with the orthographic projection of a second electrode plate C12 in a pixel driver circuit of a corresponding column on the substrate.

[0136] For example, the orthographic projection of the initial connection line 30 on the substrate does not overlap with the orthographic projection of the first electrode plate C11 in a pixel driver circuit of a corresponding column on the substrate.

[0137] For example, the orthographic projection of the initial connection line 30 on the substrate overlaps at least partially with the orthographic projection of the third electrode plate C21 in a pixel driver circuit of a corresponding column on the substrate.

[0138] For example, the orthographic projection of the initial connection line 30 on the substrate overlaps at least partially with the orthographic projection of the fourth electrode plate C22 in a pixel driver circuit of a corresponding column on the substrate.

[0139] For example, the orthographic projection of the reference connection line 31 on the substrate does not overlap with the orthographic projection of the first electrode plate C11 in a pixel driver circuit of a corresponding column on the substrate.

[0140] For example, the orthographic projection of the reference connection line 31 on the substrate overlaps at least partially with the orthographic projection of the third electrode plate C21 in a pixel driver circuit of a corresponding column on the substrate.

[0141] For example, the orthographic projection of the reference connection line 31 on the substrate overlaps at least partially with the orthographic projection of the fourth electrode plate C22 in a pixel driver circuit of a corresponding column on the substrate.

[0142] By arranging the reference connecting lines 31 and the initial connecting lines 30 as above, the layout difficulties of the reference connecting lines 31 and the initial connecting lines 30 are effectively reduced.

[0143] As in Fig. 6, in some embodiments, the display substrate further comprises a plurality of reset lines Rst including at least one portion extending along a second direction, wherein the reset lines Rst and the third electrically conductive connecting portion 43 are arranged on a same layer.

[0144] As in Fig. 3 to Fig. 10 and Fig. 16, in some embodiments, the display substrate further comprises a plurality of reset lines Rst including at least a portion extending along a second direction, wherein the reset lines Rst are made from the third electrically conductive layer in the display substrate.

[0145] For example, the multiple reset lines Rst correspond one-to-one to the multiple rows of pixel driver circuits. A first transistor T1, a fourth transistor T4, and a fifth transistor T5, which belong to the same pixel driver circuit, are each coupled to the corresponding reset lines Rst.

[0146] The above provision of the reset lines Rst from the third electrically conductive layer in the display substrate results in the resistance of the reset lines Rst being effectively reduced, and the loading and the IR drop of the entirety of the first electrically conductive layer in the display substrate being reduced.

[0147] As in Fig. 3 to Fig. As shown in Figure 10, in some embodiments, the pixel driver circuit includes a second transistor T2, a fourth transistor T4, a fifth transistor T5, and a seventh transistor T7. A dual-gate structure is used for the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7.

[0148] The above use of a double-gate structure for the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 facilitates the improvement of the current leakage of the N1 node and the N2 node.

[0149] Specifically, the display substrate includes an active layer, a first gate insulating layer, a first electrically conductive layer, a second gate insulating layer, a second electrically conductive layer, an interlayer insulating layer, a third electrically conductive layer, a first planarization layer, a fourth electrically conductive layer, a second planarization layer, an anode layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer, which are sequentially stacked in a direction away from the substrate. The display substrate may further include a passivation layer located between the first planarization layer and the fourth electrically conductive layer.

[0150] By way of example, the first electrically conductive layer comprises a first gate metal layer, the second electrically conductive layer comprises a second gate metal layer, the third electrically conductive layer comprises a first source-drain metal layer, the fourth electrically conductive layer comprises a second source-drain metal layer.

[0151] The active layer is provided to form the following: a first active layer included in the first transistor T1, a second active layer included in the first transistor T1, a third active layer included in the third transistor T3, a fourth active layer included in the fourth transistor T4, a fifth active layer included in the fifth transistor T5, a sixth active layer included in the sixth transistor T6, a seventh active layer included in the seventh transistor T7, an eighth active layer included in the eighth transistor T8, and a ninth active layer included in the ninth transistor T9.

[0152] The first electrically conductive layer is provided to form the gate electrode of the first transistor T1, the gate electrode of the second transistor T2, the gate electrode T3-g of the third transistor T3 (i.e., the first electrode plate C11), the gate electrode of the fourth transistor T4, the gate electrode of the fifth transistor T5, the gate electrode of the sixth transistor T6, the gate electrode of the seventh transistor T7, the gate electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9, the scanning line GA, the second control line EM, the fourth electrode plate C22, and the second shield pattern 22.

[0153] The second electrically conductive layer is provided to form the initialization signal line Init, the reference signal line Ref, the second electrode plate C12 and the third electrode plate C21.

[0154] The third electrically conductive layer is provided to form the first electrically conductive connecting part 41, the second electrically conductive connecting part 42, the third electrically conductive connecting part 43, the fourth electrically conductive connecting part 44, the fifth electrically conductive connecting part 45, the sixth electrically conductive connecting part 46, the eighth electrically conductive connecting part 48, and the ninth electrically conductive connecting part 49.

[0155] The first pole of the first transistor T1 is coupled to the corresponding data line DA via the first electrically conductive connecting part 41. The second pole of the first transistor T1 is coupled to the fourth electrode plate C22 via the second electrically conductive connecting part 42. The second pole of the second transistor T2 is coupled to the gate electrode T3-g of the third transistor T3 via the third electrically conductive connecting part 43. The first pole of the third transistor T3 is coupled to the power supply line VDD via the second shielding part 202. The first pole of the fourth transistor T4, the first pole of the fifth transistor T5, the first pole of the sixth transistor T6, and the first pole of the seventh transistor T7 are formed into an integrated structure and coupled to the initialization signal line Init via the fourth electrically conductive connecting part 44.The second pole of the fifth transistor T5 is coupled to the second electrode plate C12 via the fifth electrically conductive connection part 45, and the second pole of the sixth transistor T6 is coupled sequentially to the anode of a corresponding light-emitting element via the sixth electrically conductive connection part 46 and the seventh electrically conductive connection part 47. The first pole of the eighth transistor T8 is coupled to the second pole of the third transistor T3 via the eighth electrically conductive connection part 48. The first pole of the ninth transistor T9 is coupled to the reference signal line Ref via the ninth electrically conductive connection part 49. The second pole of the ninth transistor T9 is coupled to the multiplexed second control line EM via the second electrically conductive connection part 42.

[0156] As in Fig. 6, the first electrically conductive connecting part 41 comprises a strip structure, wherein at least a part of the first electrically conductive connecting part 41 extends along the first direction and the width of the first electrically conductive connecting part 41 is uneven in the second direction, the width of an end of the first electrically conductive connecting part 41 connected to the data line DA in the second direction is greater than the width of an end of the first electrically conductive connecting part 41 connected to the first pole of the first transistor T1 in the second direction.

[0157] The second electrically conductive connecting part 42 comprises a stripe structure, at least a part of the second electrically conductive connecting part 42 extends along the first direction, and the width of the second electrically conductive connecting part 42 in the second direction is uniform.

[0158] The third electrically conductive connecting part 43 comprises a strip structure. The third electrically conductive connecting part 43 comprises a part extending along the first direction and a part extending along the third direction. The third direction intersects both the first direction and the second direction.

[0159] The fourth electrically conductive connecting part 44 comprises a strip structure, at least a part of the fourth electrically conductive connecting part 44 extends along the second direction, the width of the fourth electrically conductive connecting part 44 in the first direction is uniform.

[0160] The fifth electrically conductive connecting part 45 comprises a strip structure. The fifth electrically conductive connecting part 44 comprises a part extending along the first direction and a part extending along the fourth direction. The fourth direction intersects all of the first, second, and third directions.

[0161] The sixth electrically conductive connecting part 46 comprises a stripe structure, at least a part of the sixth electrically conductive connecting part 46 extends along the first direction, and the width of the sixth electrically conductive connecting part 46 in the second direction is uneven.

[0162] The eighth electrically conductive connecting part 48 comprises a stripe structure and at least a part of the eighth electrically conductive connecting part 48 extends along the first direction.

[0163] The ninth electrically conductive connecting part 49 comprises a stripe structure and at least a part of the ninth electrically conductive connecting part 49 extends along the second direction.

[0164] In the respective electrically conductive connecting parts having the above-mentioned strip structure, the width of the end used for connection with other electrically conductive structures is larger to ensure the reliability of the connection.

[0165] The fourth electrically conductive layer is provided to form the seventh electrically conductive connection part 47, the power supply line VDD, the data line DA, the initial connection line 30 and the reference connection line 31.

[0166] The seventh electrically conductive connecting part 47 comprises a stripe structure and at least a part of the seventh electrically conductive connecting part 47 extends along the first direction.

[0167] As in Fig. 23 is a schematic diagram of the positions of through holes formed on the interlayer insulating layer in Fig. 3 are formed. As in Fig. 3, Fig. 4, Fig. 22 and Fig. 23, the first through-hole Via is provided to connect the ninth electrically conductive connecting part 49 and the first pole of the ninth transistor T9. The second through-hole Via2 is provided to connect the second pole of the sixth transistor T6 (or the second pole of the eighth transistor T8) and the sixth electrically conductive connecting part 42. The third through-hole Via3 is provided to connect the first pole of the eighth transistor T8 and the eighth electrically conductive connecting part 48. The fourth through-hole Via4 is provided to connect the ninth electrically conductive connecting part 49 and the reference signal line Ref.The fifth through-hole Via5 is provided to connect the fourth electrically conductive connecting part 44 and the first pole of the seventh transistor T7 (or the first pole of the sixth transistor T6, or the first pole of the fifth transistor T5, or the first pole of the fourth transistor T4). The sixth through-hole Via6 is provided to connect the fourth electrically conductive connecting part 44 and the initialization signal line Init. The seventh through-hole Via7 is provided to connect the eighth electrically conductive connecting part 48 and the second pole of the third transistor T3 (or the second pole of the second transistor T2). The eighth through-hole Via8 is provided to connect the reset line Rst and the gate electrode of the first transistor T1 (or the gate electrode of the fourth transistor T4, or the gate electrode of the fifth transistor T5).The ninth through-hole Via9 is provided to connect the second pole of the fourth transistor T4 and the third electrically conductive connecting part 43. The tenth through-hole Via10 is provided to connect the second pole of the fifth transistor T5 and the fifth electrically conductive connecting part 45. The eleventh through-hole Via11 is provided to connect the fifth electrically conductive connecting part 45 and the second electrode plate C12. The twelfth through-hole Via12 is provided to connect the first pole of the first transistor T1 and the first electrically conductive connecting part 41. The thirteenth through-hole Via13 is provided to connect the third electrically conductive connecting part 43 and the first electrode plate C11. The fourteenth through-hole Via14 is provided to connect the second electrically conductive connecting part 42 and the second pole of the first transistor T1.The fifteenth through-hole Via15 is provided to connect the first terminal of the third transistor T3 and the second shielding part 202. The sixteenth through-hole Via16 is provided to connect the second electrically conductive connecting part 42 and the second terminal of the ninth transistor T9. The seventeenth through-hole Via17 is provided to connect the second electrically conductive connecting part 42 and the fourth electrode plate C22.

[0168] The orthographic projections of the first via Via, the second via Via2, the third via Via3, and the fourth via Via4 on the substrate are located between the orthographic projection of the second control line EM on the substrate and the orthographic projection of the reference signal line Ref on the substrate. The orthographic projections of the fifth via Via5, the sixth via Via6, and the seventh via Via7 on the substrate are located between the orthographic projection of the scan line GA on the substrate and the orthographic projection of the initialization signal line Init on the substrate.The orthographic projections of the ninth via Via9 and the tenth via Via10 on the substrate are located between the orthographic projection of the reset line Rst on the substrate and the orthographic projection of the gate electrode of the fourth transistor T4 (or the gate electrode of the fifth transistor T5) on the substrate. Note that the gate electrode of the fourth transistor T4, the gate electrode of the fifth transistor T5, and the gate electrode of the first transistor T1 are formed into an integrated structure, such as denoted by Tg.The orthographic projections of the eleventh via Via11 and the thirteenth via Via13 on the substrate are located between the orthographic projection of the gate electrode of the fourth transistor T4 (or the gate electrode of the fifth transistor T5) on the substrate and the orthographic projection of the shielding line 21 on the substrate. The orthographic projections of the fourteenth via Via14, the fifteenth via Via15, the sixteenth via Via16, and the seventeenth via Via17 on the substrate are located between the orthographic projection of the shielding line 21 on the substrate and the orthographic projection of the second control line EM, which is connected to subpixels in the next adjacent row along the first direction, on the substrate.

[0169] As in Fig. 24, this is a schematic diagram of the positions of through holes formed on the first planarization layer in Fig. 3 are formed. As in Fig. 3, Fig. 4, Fig. 22 and Fig. As shown in Figure 24, the eighteenth through-hole Via18 is provided to connect the seventh electrically conductive connecting part 47 and the sixth electrically conductive connecting part 46. The nineteenth through-hole Via19 is provided to connect the data line DA and the first electrically conductive connecting part 41. The twentieth through-hole Via20 is provided to connect the second shielding part 202 and the power supply line VDD.

[0170] The orthographic projection of the eighteenth via Via18 on the substrate is located between the orthographic projection of the second control line EM on the substrate and the orthographic projection of the reference signal line Ref on the substrate. The orthographic projection of the nineteenth via Via19 on the substrate is adjacent to the orthographic projection of the twelfth via Via12 on the substrate. The orthographic projection of the twentieth via Via20 on the substrate is located between the orthographic projection of the shield line 21 on the substrate and the orthographic projection of the second control line EM, which is connected to subpixels in the next adjacent row along the first direction, on the substrate.

[0171] As in Fig. 25, this is a schematic diagram of the positions of through holes formed on the passivation layer in Fig. 3 are formed. The orthographic projection of the twenty-first through-hole Via21 on the substrate at least partially overlaps with the orthographic projection of the eighteenth through-hole Via18 on the substrate. The orthographic projection of the twenty-second through-hole Via22 on the substrate at least partially overlaps with the orthographic projection of the nineteenth through-hole Via19 on the substrate. The orthographic projection of the twenty-third through-hole Via23 on the substrate at least partially overlaps with the orthographic projection of the twentieth through-hole Via20 on the substrate.

[0172] The twenty-first through-hole Via21 is provided to connect the seventh electrically conductive connecting part 47 and the sixth electrically conductive connecting part 46. The twenty-second through-hole Via22 is provided to connect the data line DA and the first electrically conductive connecting part 41. The twenty-third through-hole Via23 is provided to connect the second shielding part 202 and the power supply line VDD.

[0173] As in Fig. 20, this is a schematic diagram of the positions of through holes formed on the second planarization layer in Fig. 3 are formed. The twenty-fourth through-hole Via24 is provided to connect the seventh electrically conductive connecting part 47 and a corresponding anode pattern.

[0174] As in Fig. 21 and Fig. As shown in Figure 17, the twenty-fifth through-hole Via25 is located in the dashed frame at A2. The twenty-fifth through-hole Via25 is provided to connect the initial connection line 30 and the fourth electrically conductive connecting part 44. The twenty-sixth through-hole Via26 is located in the dashed frame at A1. The twenty-sixth through-hole Via26 is provided to connect the reference connection line 31 and the ninth electrically conductive connecting part 49.

[0175] As in Fig. As shown in Figure 18, the orthographic projection of the twenty-seventh via Via27 on the substrate at least partially overlaps with the orthographic projection of the twenty-fifth via Via25 on the substrate. The orthographic projection of the twenty-eighth via Via28 on the substrate at least partially overlaps with the orthographic projection of the twenty-sixth via Via26 on the substrate. The twenty-seventh via Via27 is provided to connect the initial connection line 30 and the fourth electrically conductive connection part 44. The twenty-eighth via Via28 is provided to connect the reference connection line 31 and the ninth electrically conductive connection part 49.

[0176] As in Fig. As shown in Figure 4, in some embodiments, the active layer included in the ninth transistor T9 is an independent active layer. The active layer included in the first transistor T1 is an independent active layer. The active layers included in the second transistor T2 through the eighth transistor T8 are all formed into an integrated structure.

[0177] As in Fig. As shown in Figure 4, in some embodiments, the shape of the channel portion contained in the third transistor T3 can be chosen to be I-shaped. Of course, it can also be provided in other shapes, such as S-shaped or JL-shaped, but is not limited thereto.

[0178] As in Fig. 4, in some embodiments, the active layer corresponding to the first transistor T1 comprises two parts, one part is located along the second direction on one side of the first electrode plate C11 and the orthographic projection of another part on the substrate is located between the orthographic projection of the first electrode plate C11 on the substrate and the orthographic projection of the fourth electrode plate C22 on the substrate.

[0179] As in Fig. 4, in some embodiments, the active layer corresponding to the first transistor T1 and the active layer corresponding to the third transistor T3 are arranged along the second direction.

[0180] As in Fig. 4, in some embodiments, the active layer corresponding to the second transistor T2 and the active layer corresponding to the fourth transistor T4 through the active layer corresponding to the ninth transistor T9 are all located along the first direction on the same side of the active layer corresponding to the third transistor T3.In the same pixel driving circuit, the active layer corresponding to the fourth transistor T4 and the active layer corresponding to the fifth transistor T5 are closest to the active layer corresponding to the third transistor T3; the active layer corresponding to the eighth transistor T8 is farthest from the active layer corresponding to the third transistor T3; the active layer corresponding to the second transistor T2 and the active layer corresponding to the sixth transistor T6 are both located between the active layer corresponding to the eighth transistor T8 and the active layer corresponding to the fourth transistor T4; the active layer corresponding to the seventh transistor T7, the active layer corresponding to the sixth transistor T6, and the active layer corresponding to the second transistor T2 are sequentially arranged along the second direction.

[0181] As in Fig. 3 and Fig. 4, in some embodiments, the gate electrode of the fourth transistor T4, the gate electrode of the fifth transistor T5, and the gate electrode of the first transistor T1 are formed into a gate pattern of an integrated structure. The gate pattern includes a portion extending along the first direction and a portion extending along the second direction. At least a portion of the portion extending along the first direction serves as the gate electrode of the first transistor T1, and the portion extending along the second direction serves as the gate electrode of the fourth transistor T4 and the gate electrode of the fifth transistor T5. The gate pattern is coupled to the reset line Rst.

[0182] As in Fig. 4, in some embodiments, in the same pixel driver circuit, the second control line EM, the scanning line GA, the gate pattern, the first electrode plate C11, and the fourth electrode plate C22 are arranged sequentially along the first direction.

[0183] As in Fig. 5, in some embodiments, in the same pixel driver circuit, the reference signal line Ref, the initialization signal line Init, the second electrode plate C12 and the third electrode plate C21 are arranged sequentially along the first direction.

[0184] An embodiment of the present disclosure also provides a display device comprising the display substrate provided in the above embodiments.

[0185] In the display substrate provided in the above embodiment of the present disclosure, the first shielding pattern can shield the influence between the data line and the N1 node, and the crosstalk between the data line and the N1 node is reduced by having at least a part of the orthographic projection of the first shielding pattern on the substrate located between the orthographic projection of the data line on the substrate and the orthographic projection of the first electrode plate on the substrate.

[0186] In the display substrate provided in the above embodiment of the present disclosure, the first shielding pattern can shield the influence between the data line and the N2 node, and the crosstalk between the data line and the N2 node is reduced by having at least a part of the orthographic projection of the first shielding pattern on the substrate located between the orthographic projection of the data line on the substrate and the orthographic projection of the second electrode plate on the substrate.

[0187] In the display substrate provided in the above embodiment of the present disclosure, the first shielding pattern can shield the influence between the data line and the N2 node, and the crosstalk between the data line and the N2 node is reduced by having at least a part of the orthographic projection of the first shielding pattern on the substrate located between the orthographic projection of the data line on the substrate and the orthographic projection of the third electrode plate on the substrate.

[0188] In the display substrate provided in the above embodiment of the present disclosure, the first shielding pattern can shield the influence between the data line and the N3 node, and the crosstalk between the data line and the N3 node is reduced by having at least a part of the orthographic projection of the first shielding pattern on the substrate located between the orthographic projection of the data line on the substrate and the orthographic projection of the fourth electrode plate on the substrate.

[0189] When the display device provided in the embodiments of the present disclosure includes the above display substrate, it also has the above advantageous effects, which will not be described repeatedly here.

[0190] It should be noted that the display device may be any product or component having a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, or the like, wherein the display device further comprises a flexible board, a printed circuit board, and a backplane, or the like.

[0191] It should be noted that the extension of a signal line along an X direction means that the signal line includes a main part and a sub-part connected to the main part, wherein the main part is a line, a line segment or a strip body, the main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the sub-part extending along other direction.

[0192] It should be noted that "a same layer" in the embodiments of the present disclosure may refer to film layers on a same structural layer. Or, for example, the film layers on a same layer may be a layered structure formed by forming film layers to form a specific pattern using one and the same film forming process and then patterning them with the same mask through a patterning process. Depending on different specific patterns, a patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layered structure may be continuous or discontinuous. These specific graphics may also be located at different heights or have different thicknesses.

[0193] In the various embodiments of the method of the present disclosure, the numbers of the respective steps may not be used to limit the order of the respective steps. For those generally skilled in the art, changes to the order of the respective steps also fall within the scope of the present disclosure, requiring no inventive step.

[0194] It should be noted that the various embodiments are described step by step in the description of the present disclosure, and reference may be made to the same and similar parts between the various embodiments. Each embodiment focuses on its differences from other embodiments. In particular, the method embodiments are described relatively simply because they are fundamentally similar to the product embodiments. For details, please refer to the explanations section of the product embodiments.

[0195] Unless otherwise defined, technical or scientific terms used in this disclosure are intended to have the common meaning understood by a person having ordinary skill in the art to which this disclosure relates. "First," "second," and similar words used in this disclosure do not indicate order, quantity, or meaning, but are used only to distinguish different components. Words like "comprise" or "include" mean that the elements or things that appear before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words like "connect," "coupled," or "connected" are not limited to physical or mechanical connections, but can also include electrical connections, whether direct or indirect."Top," "bottom," "left," "right," etc., are intended only to express relative positional relationships. If the absolute position of a described object changes, the relative positional relationship may also change accordingly.

[0196] It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or an intervening element may be present.

[0197] In the description of the above embodiments, specific features, structures, materials, or properties may be combined in any one or more embodiments or examples in any suitable manner.

[0198] In summary, these are merely specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto. Anyone skilled in the art who is familiar with the technical field can easily devise modifications or substitutions within the technical framework disclosed in this disclosure, which are intended to fall within the scope of the present disclosure. Therefore, the scope of the present disclosure is intended to be based on the scope of the claims.

Claims

[1] A pixel driver circuit intended for driving light-emitting elements, the pixel driver circuit comprising: a driver subcircuit having a first end coupled to a power supply line; a compensation subcircuit, each coupled to a scan line, a control end of the driver subcircuit, and a second end of the driver subcircuit, and configured to control, under the control of the scan line, the switching on and off of an electrical connection between the control end and the second end of the driver subcircuit; a coupling subcircuit whose first end is coupled to the control end of the driver subcircuit; a memory subcircuit having a first end coupled to a second end of the coupling subcircuit; a data write subcircuit, each coupled to a second end of the memory subcircuit, a data line, and a reset line, and configured to control, under the control of the reset line, the switching on and off of an electrical connection between the second end of the memory subcircuit and the data line; a first reset subcircuit, which is coupled to the reset line, an initialization signal line, the control end of the driver subcircuit, and the second end of the coupling subcircuit, respectively, and which is provided to control, under the control of the reset line, the switching on and off of an electrical connection between the initialization signal line and the control end of the driver subcircuit and the switching on and off of an electrical connection between the initialization signal line and the second end of the coupling subcircuit; a first holding subcircuit coupled to the scanning line, the second end of the coupling subcircuit, and the initialization signal line, respectively, and configured to control, under the control of the scanning line, the switching on and off of an electrical connection between the second end of the coupling subcircuit and the initialization signal line; a second holding subcircuit, each coupled to a first control line, a reference signal line and the second end of the memory subcircuit and arranged to control, under the control of the first control line, the switching on and off of an electrical connection between the reference signal line and the second end of the memory subcircuit. [2] The pixel driver circuit of claim 1, wherein the pixel driver circuit further comprises: a light emission control subcircuit coupled to each of the second end of the driver subcircuit, the light-emitting element, and a second control line, and configured to control, under the control of the second control line, the switching on and off of an electrical connection between the second end of the driver subcircuit and the light-emitting element. [3] The pixel driver circuit of claim 2, wherein the pixel driver circuit further comprises: a second reset subcircuit coupled to each of the scanning line, the light-emitting element, and the initialization signal line, and configured to control, under the control of the scanning line, the switching on and off of an electrical connection between the light-emitting element and the initialization signal line. [4] The pixel driving circuit according to claim 3, wherein the coupling subcircuit comprises a first capacitor, the storage subcircuit comprises a second capacitor, the data writing subcircuit comprises a first transistor, the compensation subcircuit comprises a second transistor, the driving subcircuit comprises a third transistor, the first reset subcircuit comprises a fourth transistor and a fifth transistor, the second reset subcircuit comprises a sixth transistor, the first holding subcircuit comprises a seventh transistor, the light emission control subcircuit comprises an eighth transistor, the second holding subcircuit comprises a ninth transistor; a gate electrode of the first transistor is coupled to the reset line, a first terminal of the first transistor is coupled to the data line, a second terminal of the first transistor is coupled to a second end of the second capacitor; a gate electrode of the second transistor is coupled to the scan line, a first pole of the second transistor is coupled to a second pole of the third transistor, a second pole of the second transistor is coupled to a gate electrode of the third transistor; a first pole of the third transistor is coupled to the power supply line; a first end of the first capacitor is coupled to the gate electrode of the third transistor, a first end of the second capacitor is coupled to a second end of the first capacitor; a gate electrode of the fourth transistor is coupled to the reset line, a first pole of the fourth transistor is coupled to the initialization signal line, a second pole of the fourth transistor is coupled to the gate electrode of the third transistor; a gate electrode of the fifth transistor is coupled to the reset line, a first terminal of the fifth transistor is coupled to the initialization signal line, a second terminal of the fifth transistor is coupled to the second end of the first capacitor; a gate electrode of the sixth transistor is coupled to the scan line, a first terminal of the sixth transistor is coupled to the initialization signal line, a second terminal of the sixth transistor is coupled to the light-emitting element; a gate electrode of the seventh transistor is coupled to the scan line, a first terminal of the seventh transistor is coupled to the initialization signal line, a second terminal of the seventh transistor is coupled to the second end of the first capacitor; a gate electrode of the eighth transistor is coupled to the second control line, a first pole of the eighth transistor is coupled to the second pole of the third transistor, a second pole of the eighth transistor is coupled to the light-emitting element; a gate electrode of the ninth transistor is coupled to the first control line, a first pole of the ninth transistor is coupled to the reference signal line, a second pole of the ninth transistor is coupled to the second end of the second capacitor. [5] A display substrate comprising a plurality of pixel driving circuits according to any one of claims 1 to 4, wherein the pixel driving circuit comprises a first capacitor and a third transistor, the first capacitor comprising a first electrode plate and a second electrode plate arranged opposite to each other, the first electrode plate being multiplexed as a gate electrode of the third transistor; the display substrate comprises: a plurality of data lines comprising at least one part extending along a first direction, the orthographic projection of the data line on the substrate of the display substrate and the orthographic projection of the first electrode plate on the substrate are arranged along a second direction, the first direction and the second direction intersect; a plurality of first shielding patterns, wherein at least a portion of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first electrode plate on the substrate; and / or, at least a part of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the second electrode plate on the substrate. [6] The display substrate according to claim 5, wherein the pixel driving circuit further comprises a second capacitor, the second capacitor comprising a third electrode plate and a fourth electrode plate arranged opposite to each other, the third electrode plate being coupled to the second electrode plate; the third electrode plate and the second electrode plate are arranged along the first direction; at least a part of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the third electrode plate on the substrate; and / or at least a part of the orthographic projection of the first shielding pattern on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the fourth electrode plate on the substrate. [7] The display substrate according to claim 6, wherein the first shielding pattern comprises a first shielding part and a second shielding part coupled to each other, the first shielding part and the second shielding part being arranged along the second direction, at least a part of the orthographic projection of the data line on the substrate is located between the orthographic projection of the first shielding part on the substrate and the orthographic projection of the second shielding part on the substrate; at least a part of the orthographic projection of the first shielding part on the substrate is located between the orthographic projection of at least one of the adjacent first and second capacitors on the substrate and the orthographic projection of the data line on the substrate; and / or, at least a part of the orthographic projection of the second shielding part on the substrate is located between the orthographic projection of at least one of the adjacent first and second capacitors on the substrate and the orthographic projection of the data line on the substrate. [8] The display substrate according to claim 7, wherein the display substrate further comprises second electrically conductive connecting parts and data lines, wherein the pixel driving circuit further comprises a first transistor, wherein a first terminal of the first transistor is coupled to a corresponding data line, a second terminal of the first transistor is coupled to the fourth electrode plate via the corresponding second electrically conductive connecting part; the second electrically conductive connecting part is located between the first shield patterns adjacent along the second direction. [9] The display substrate according to claim 7, wherein the display substrate further comprises third electrically conductive connecting parts and fifth electrically conductive connecting parts, the pixel driving circuit further comprises a second transistor and a third transistor, wherein a second terminal of the second transistor is coupled to a gate electrode of the third transistor via the third electrically conductive connecting part, a second terminal of the fifth transistor is coupled to the second electrode plate via the fifth electrically conductive connecting part; the third electrically conductive connecting part is located between the first shield patterns adjacent along the second direction, the fifth electrically conductive connecting part is located between the first shield patterns adjacent along the second direction. [10] The display substrate according to claim 9, wherein the display substrate further comprises: a plurality of shielding lines including at least one part extending along the second direction; wherein the plurality of pixel driver circuits are divided into a plurality of rows of pixel driver circuits, the orthographic projection of the shield line on the substrate at least partially overlapping with the orthographic projection of an edge of a respective first electrode plate located near the fourth electrode plate in a pixel driver circuit of a corresponding row on the substrate. [11] The display substrate according to claim 10, wherein the plurality of first shield patterns are divided into a plurality of rows of first shield patterns, the shield lines being respectively coupled to first shield patterns of a corresponding row. [12] The display substrate of claim 11, wherein the display substrate comprises power supply lines, wherein the first shield pattern is coupled to the power supply line. [13] The display substrate according to claim 11, wherein the first shielding patterns, the shielding lines and the third electrically conductive connecting parts are arranged on a same layer. [14] The display substrate according to claim 10, wherein the display substrate further comprises reset lines, the shield line and the reset line are arranged along the first direction, both the third electrically conductive connecting part and the fifth electrically conductive connecting part are located between the shield line and the reset line. [15] The display substrate according to claim 5, wherein the display substrate further comprises: a plurality of second shielding patterns comprising at least a portion extending along the first direction, wherein the orthographic projection of the second shielding pattern on the substrate at least partially overlaps the orthographic projection of the data line on the substrate. [16] The display substrate of claim 15, wherein the display substrate further comprises a plurality of second control lines, the second shield patterns located in a same row along the second direction being each coupled to a corresponding second control line. [17] The display substrate according to claim 16, wherein the second shield patterns located in a same row along the second direction and a corresponding second control line are formed into an integrated structure. [18] The display substrate of claim 15, wherein the display substrate further comprises power supply lines and initialization signal lines, wherein the second shield pattern is coupled to the power supply line or to the initialization signal line. [19] The display substrate according to claim 5, wherein the display substrate further comprises: a plurality of initialization signal lines arranged along the first direction, the initialization signal lines including at least one part extending along the second direction; a plurality of initial connection lines arranged along the second direction, the initial connection lines including at least a portion extending along the first direction, each initial connection line being respectively coupled to the plurality of initialization signal lines. [20] The display substrate according to claim 19, wherein the display substrate further comprises: a plurality of reference signal lines arranged along the first direction, the reference signal lines including at least one portion extending along the second direction; a plurality of reference connection lines arranged along the second direction, the reference connection lines comprising at least a portion extending along the first direction, each reference connection line being respectively coupled to the plurality of reference signal lines. [21] A display substrate according to claim 20, wherein the initial connection lines and the reference connection lines are arranged alternately along the second direction; the plurality of pixel driver circuits are divided into a plurality of columns of pixel driver circuits, each column of pixel driver circuits corresponding to one of the initial connection lines or one of the reference connection lines; the orthographic projection of the initial connection line on the substrate at least partially overlaps with the orthographic projection of a second electrode plate in a pixel driver circuit of a corresponding column on the substrate; and / or the orthographic projection of the reference connection line on the substrate at least partially overlaps with the orthographic projection of a second electrode plate in a pixel driver circuit of a corresponding column on the substrate. [22] The display substrate according to claim 9, wherein the display substrate further comprises a plurality of reset lines including at least one part extending along a second direction, wherein the reset lines and the third electrically conductive connecting parts are arranged on a same layer. [23] The display substrate according to claim 5, wherein the pixel driving circuit comprises a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor, wherein the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor use a double-gate structure. [24] A display device comprising a display substrate according to any one of claims 5 to 23.

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