Gate control device and gate control system

Abstract

A gate drive device operates on two sides, a high side and a low side, and drives a gate electrode of a power transistor. The gate drive device comprises: a control element, provided in pairs to form the two sides, configured to output a switching signal at three or more levels, including a high level, a low level, and one or more intermediate levels between the high and low levels, in response to a received control signal; and a switching element, provided in pairs corresponding to the control element, configured to output a voltage to the gate electrode of the power transistor corresponding to a level of the switching signal received from the control element.

Description

Technical area

[0001] The present invention relates to a gate drive device and a gate drive system. Background technology

[0002] A power transistor, such as an insulated-gate bipolar transistor (IGBT), is subjected to switching control by changing a gate voltage through a gate driver (also called a gate drive device). In recent years, a gate driver that changes a gate voltage using an improved control method has been developed to conserve power of a power transistor.

[0003] JP 2017-135589 A discloses a gate driver for variably controlling a gate driver of a power transistor at multiple levels. According to this gate driver, a drive loss of the power transistor is reduced by controlling the power transistor by dynamically changing a gate voltage at multiple levels. Brief description of the invention

[0004] A power transistor contains a capacitance between each terminal, and the capacitance must be charged and discharged to drive a gate. In recent years, efforts have been made to increase the power of the power transistor, and a current input to the gate terminal to charge the capacitance must be relatively large, for example, 40 A or more. To increase an output current in the gate driver with the configuration disclosed in JP 2017-135589 A, it is necessary to connect multiple transistors in parallel, which leads to a problem of increasing the area occupied by the gate driver.

[0005] The invention has been developed to solve such a problem, and it is an object of the invention to provide a gate drive device and a gate drive system capable of variably controlling an output signal at multiple levels with a simpler configuration.

[0006] A gate drive device according to one aspect of the invention operates on two sides, a high side and a low side, and drives a gate electrode of a power transistor. The gate drive device comprises: a control device provided in pairs to form the two sides and configured to output a switching signal at three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, according to a received control signal; and a switching element provided in pairs corresponding to the control device and configured to output a voltage corresponding to a level of the switching signal received from the control device to the gate electrode of the power transistor.

[0007] A gate drive system according to one aspect of the invention operates on two sides, a high side and a low side, and drives a gate of a power transistor. The gate drive system includes: a control unit configured to output a control signal variable to three or more levels, including a high level, a low level, and one or more intermediate levels; a control device provided in pairs to form the two sides and configured to output a switching signal corresponding to the control signal output from the control unit; and a switching element provided in pairs corresponding to the control device and configured to output a voltage corresponding to a level of the switching signal received from the control device to the gate electrode of the power transistor.

[0008] According to the gate drive device of the aspect of the invention, the control device can output the switching signal at three or more levels according to the received control signal. Then, the switching element that receives the switching signal outputs the voltage corresponding to the level of the switching signal to the gate electrode of the power transistor. With such a configuration, a gate voltage of the power transistor can be dynamically controlled at multiple levels, and power saving of the power transistor can be achieved. Furthermore, the gate drive device has a half-bridge configuration in which the control device and the switching element are provided in pairs, and the configuration is simplified, so that the gate drive device can be miniaturized.

[0009] According to the gate drive system of the aspect of the invention, the control device can output the switching signal corresponding to the control signal received from the control unit, which can be changed to three or more levels. Then, the switching element receiving the switching signal outputs the voltage corresponding to the level of the switching signal to the gate electrode of the power transistor. With such a configuration, a gate voltage of the power transistor is dynamically controlled, whereby power saving of the power transistor can be achieved. Furthermore, the gate drive system has a half-bridge configuration in which the control device and the switching element are provided in pairs, and the configuration is simplified, so that the gate drive device can be miniaturized. Short description of the drawings Fig. 1 shows a diagram of a circuit using a gate driver according to an embodiment of the invention; Fig. 2 shows a detailed configuration diagram of an IC in the gate driver; Fig. 3A shows a detailed circuit configuration diagram of a DAC in the gate driver; Fig. Figure 3B shows an equivalent circuit of the DAC; Fig. 3C shows an explanatory diagram of an output signal of the DAC; Fig. 4 shows a timing diagram illustrating an operation example of an active control of the gate driver; Fig. 5A is a timing chart showing an operation of a single gate driver control executed in characteristic evaluation; Fig. 5B shows a diagram showing a result of characteristic evaluation of a gate voltage V GSH ; Fig. 5C shows a diagram showing a result of a characteristic curve evaluation of a gate current I G ; Fig. 6A shows a circuit configuration diagram of a double pulse test of the gate driver; Fig. 6B is a diagram showing evaluation results of single drive and active drive in the double pulse test; Fig. Fig. 7 is a circuit diagram showing a gate driver according to a first modification; and Fig. 8 is a circuit diagram showing a gate driver according to a second modification. Description of the embodiments

[0010] An embodiment of the invention will be described below with reference to the drawings.

[0011] Fig. 1 shows a diagram of a circuit using a gate driver according to an embodiment of the invention.

[0012] An output terminal of a gate driver 10 is connected to a gate electrode and an emitter electrode of a power transistor 20 to control the power transistor 20. The power transistor 20 is, for example, an insulated-gate bipolar transistor (IGBT). Hereinafter, a potential of the gate electrode with respect to the emitter electrode in the power transistor 20 is referred to as the gate voltage V GE and a current supplied to the gate electrode as gate current I G The gate voltage V GE of the power transistor 20 changes according to an output signal of the gate driver 10, and the power transistor 20 is controlled. The gate current I G must exceed a specified value according to a standard of the power transistor 20.

[0013] Gate driver 10 has a half-bridge configuration and features a two-stage configuration, an upper stage (high side) and a lower stage (low side) in the figure. In the gate driver 10 with the half-bridge configuration, one side is controlled by the high side and the low side, while the other side is not.

[0014] As will be described later, the gate driver 10 controls the gate voltage V GE and the gate current I GDynamically variable at multiple levels according to an externally received digital control signal. Such control of the gate electrode can reduce the drive loss of the power transistor 20. The gate driver 10 is an example of a gate drive device, and a device capable of variably controlling a gate voltage can also be referred to as a digital gate driver. Dynamically variable control of the gate driver 10 at multiple levels is called active control. Control of the gate driver 10 at one level (ON / OFF) is called single-step control or single-step control.

[0015] The gate driver 10 includes a digital-to-analog converter (DAC) 1 and a metal-oxide-semiconductor field-effect transistor (MOSFET) 3 forming the high side, and a DAC 2 and a MOSFET 4 forming the low side. The two DACs 1 and 2, including a control circuit thereof, are integrated in an integrated circuit (IC) and implemented as IC 11.

[0016] In the following, a gate voltage with respect to a source electrode of the high-side MOSFET 3 is defined as V GSH and a gate voltage with respect to a source electrode of the low-side MOSFET 4 as V GSL The gate voltages V GSH and V GSL of MOSFETs 3 and 4 are controlled by DACs 1 and 2, and the gate voltages V output by DACs 1 and 2 GSH and V GSLare used to switch MOSFETs 3 and 4 and can therefore be referred to as switching signals. A freewheeling diode is connected between the drain and source electrodes of each of MOSFETs 3 and 4, with one source side connected as the anode, i.e., connected antiparallel to MOSFETs 3 and 4.

[0017] On the high side, an output terminal of DAC 1 is connected to a gate electrode of MOSFET 3. DAC 1 is supplied with a DC voltage V DD3 from a power supply 5. One end of the DAC 1 connected to a negative electrode side of the power supply 5 is electrically connected to the source electrode of the MOSFET 3. The DAC 1 converts the supplied voltage V DD3 according to an externally received control signal and outputs the converted voltage to the gate electrode of the MOSFET 3 at a desired level at a desired time. By controlling the DAC 1 in this way, the gate voltage V GSHcontrolled, and MOSFET 3 works.

[0018] In MOSFET 3, the source electrode is connected to the gate electrode of power transistor 20, and the drain electrode is connected to the emitter electrode of power transistor 20 via a power supply 7. Power supply 7 supplies a DC voltage V DD1 and is configured such that at the gate electrode of the power transistor 20 there is a high potential with respect to the emitter electrode, ie the gate voltage V GE has a positive potential. In a high-side control zone, the MOSFET 3 is controlled according to the gate voltage V GSH controlled, and as a result the gate voltage V GE of the power transistor 20 a positive voltage, which is achieved by stepping down the voltage V DD1 is received.

[0019] The low-side configuration is the same as the high-side configuration. An output terminal of DAC 2 is connected to a gate electrode of MOSFET 4. DAC 2 is supplied with a DC voltage V DD4 supplied by a power supply 6.

[0020] One end of the DAC 2, which is connected to a negative electrode side of the power supply 6, is electrically connected to the source electrode of the MOSFET 4. The DAC 2 converts the supplied voltage V DD4 according to a control signal received from the outside and outputs the converted voltage at a desired level to the gate electrode of the MOSFET 4 at a desired time. By controlling the DAC 2 in this way, the gate voltage V GSL controlled, and the MOSFET 4 works.

[0021] In MOSFET 4, the drain electrode is connected to the gate electrode of power transistor 20, and the source electrode is connected to the emitter electrode of power transistor 20 via a power supply 8. Power supply 8 supplies a DC voltage V DD2 and is configured so that the emitter electrode of the power transistor 20 has a high potential with respect to the gate electrode, ie the gate voltage V GE has a negative potential. In a low-side control zone, the MOSFET 4 is controlled according to the gate voltage V GSL controlled, and as a result the gate voltage V GE of the power transistor 20 a negative voltage, which is achieved by stepping down the voltage V DD2 is received.

[0022] In this way, the gate voltages V GSH and V GSL of MOSFETs 3 and 4 according to the control of DACs 1 and 2. The gate voltage V GE and the gate current I Gof the power transistor 20 are controlled according to changes in the gate voltages V GSH and V GSL In the high-side control zone, the gate voltage V GE of the power transistor 20 which corresponds to the gate voltage V GSH of the MOSFET 3 corresponding positive voltage, and in the low-side control zone the gate voltage V GE of the power transistor 20 which corresponds to the gate voltage V GSL of the MOSFET 4. The power transistor 20 is controlled by such alternating control of the high side and the low side.

[0023] Fig. Figure 2 shows a detailed configuration diagram of IC 11. IC 11 includes the control circuit for DACs 1 and 2. In this figure, power supplies 5 and 6 are shown on the right side with respect to DACs 1 and 2.

[0024] The IC 11 includes shift registers 12 and 13 and an edge decoder 14, which serve as the control circuit for DACs 1 and 2. The control circuit, which includes shift registers 12 and 13 and edge decoder 14, can be implemented by any type of control unit. The shift register 12 receives a serial input signal and outputs a parallel signal. The shift register 13 receives a parallel input signal and outputs a serial signal.

[0025] The IC 11 receives an input signal (IN) and an enable signal (Enable) used to control DACs 1 and 2, an input signal (Scan IN) and a clock signal (Scan CLK) used for a scan design, and a timing signal (Timing) that changes the timing of the output signals (gate voltages V GSH and V GSL) of DACs 1 and 2. The scan design is implemented using the shift register 12 or the like, but a description of a detailed configuration of the scan design is omitted.

[0026] In addition to the input signal (IN) and the enable signal (Enable), the shift register 13 receives the timing signal (Timing) from the edge decoder 14. The shift register 13 outputs 8-bit control signals H_n PMOS and H_n NMOS to DAC 1 and outputs 8-bit control signals L_n PMOS and L_n NMOS to DAC 2. This output signal is updated at the change time of the timing signal. In this way, DACs 1 and 2 operate based on a digital control signal using the four 8-bit signals, and the gate voltages V GSH and V GSL, which are the switching signals for MOSFETs 3 and 4, are output. Next, detailed configurations of DACs 1 and 2 are described with reference to the Fig. 3A to 3C.

[0027] Fig. Figure 3A shows a detailed circuit configuration diagram of DAC 1. Fig. Figure 3B shows an equivalent circuit of DAC 1. Fig. Figure 3C shows an explanatory diagram of the output signal of DAC 1. As shown in the Fig. 3A and Fig. 3B, the output of the DAC 1 can be variably controlled since the DAC 1 has a variable resistor 15 in the upper part of the figure and a variable resistor 16 in the lower part of the figure, as shown in Fig. 3C. The configuration of DAC 1 is described in detail below.

[0028] As in Fig. 3A, the variable resistor 15 is connected in parallel by switching elements W P , 2W P , 4W P , 8WP , 16W P , 32W P , 64W P and 128W P , each of which has a resistance component. In each of these switching elements W P the voltage V DD3 supplied from the power supply 5 and the other end is connected to the gate electrode of the MOSFET 3.

[0029] The switching element W P The number in front indicates the relative size of a region of the element. That is, the switching element 2W P has a resistance value that is half that of the switching element W P . The switching elements W P , 2W P , 4W P , 8W P , 16W P , 32W P , 64W P and 128W P are each represented by register H_n PMOS [0] to H_n PMOS [7] This allows the resistance value of the variable resistor 15 to be changed in 256 steps (0 to 255: 8 bits).

[0030] Similarly, the variable resistor 16 is connected in parallel with switching elements W N , 2W N , 4W N , 8W N , 16W N , 32W N , 64W N and 128W N , each of which has a resistance component. For each of these switching elements W N One end is connected to the gate electrode of MOSFET 3 and the other end to the source electrode of MOSFET 3. The switching elements W N , 2W N , 4W N , 8W N , 16W N , 32W N , 64W N and 128W N are each represented by register H_n NMOS [0] to H_n NMOS [7] This allows the resistance value of the variable resistor 16 to be changed in 256 steps (0 to 255: 8 bits).

[0031] As in Fig. 3B, the DAC 1 corresponds to a configuration in which the variable resistor 15, whose resistance value is controlled by the registers H_n PMOS [0] to H_n PMOS [7], and the variable resistor 16, whose resistance value is controlled by the registers H_n NMOS [0] to H_n NMOS [7] are connected in series. The voltage V DD3 supplied from the power supply 5. A connection point between the variable resistor 15 and the variable resistor 16 is connected to the gate electrode of the MOSFET 3, and the terminals of the variable resistors 15 and 16 connected to the negative electrode side of the power supply 5 are connected to the source electrode of the MOSFET 3.

[0032] Fig. 3C shows the gate voltage V GSH of MOSFET 3, which is controlled by DAC 1. The gate voltage V GSHis achieved by stepping down the voltage V DD3 of the power supply 5 according to the resistance values ​​of the variable resistors 15 and 16. In particular, if the resistance value of the variable resistor 15 R P and the resistance value of the variable resistor 16 R N , the gate voltage V GSH one by multiplying V DD3 with R N / (R P + R N ) value obtained.

[0033] Fig. 4 shows a timing chart for illustrating an operation example of actively driving the gate driver 10. One cycle is formed by combining a case where the IN signal supplied to the gate driver 10 is ON (high side) and a case where the IN signal is OFF (low side).

[0034] In the time periods t1 to t5 in which the IN signal is ON, the gate voltage V GSHof the high-side MOSFET 3 is variably controlled at several levels, and the gate voltage V GSL of the low-side MOSFET 4 becomes zero. At a change in the timing signal, the gate voltage V GSH of MOSFET 3 according to H_n pMOS [0] to H_n PMOS [7] and the gate current I G and the gate voltage V GE of the power transistor 20 are controlled.

[0035] In particular, the gate voltage V GSH in the time periods t1 to t4 to a variety of levels between 0 V and V DD3 and becomes V in the last time period t5 DD3 On the other hand, the gate voltage V GSL in the time periods t1 to t5 is zero. When the gate voltage V GSH changes, the gate current I G increases or decreases in a positive range and eventually becomes zero. At the same time, the gate voltage V GE gradually increases and finally reaches the specified value VDD1 .

[0036] On the other hand, in the time periods t6 to t 10 , in which the IN signal is OFF, the gate voltage V GSL of the low-side MOSFET 4 is variably controlled at several levels, and the high-side gate voltage V GSH becomes zero. Similarly, since a voltage level of the gate voltage V GSL according to the input of the timing signal, the gate current I G of the IGBT 2 in a negative range and the gate voltage V GE be controlled in a decreasing range.

[0037] In this example, the gate voltage V GSL of the low-side MOSFET 4 in the time periods t6 to t9 to a variety of levels between 0 V and V DD4 set and is in the last time period t 10 to V DD4 On the other hand, the gate voltage V GSH in the time periods t6 to t 10 Zero. When the gate voltage V GSLchanges, the gate current I G increases or decreases in a negative range and eventually becomes zero. At the same time, the gate voltage V GE gradually decreases and finally becomes -V DD2 .

[0038] By repeating such control in the time periods t1 to t 10 The gate driver 10 can control the gate current I G and the gate voltage V GE of the power transistor 20.

[0039] Next, a characteristic curve evaluation carried out with respect to the gate driver 10 is carried out with reference to the Fig. 5A to 5C. In this characteristic curve evaluation, the single-step control, which is a single control to a given level, was used instead of the Fig. 4 shown active control.

[0040] Fig. 5A shows a timing chart for illustrating an operation of the single-step control of the gate driver 10 in the characteristic evaluation. Fig. 5B shows a diagram showing a characteristic curve of the gate voltage V GSH . Fig. 5C shows a diagram illustrating a characteristic curve of the gate current I G . This characteristic evaluation was carried out in an environment in which a 100 µF film capacitor was connected to the gate driver 10 and the Fig. 5B and Fig. The evaluation results shown in Figure 5C were obtained by performing the Fig. 5A shown single step control.

[0041] As in Fig. As shown in Figure 5A, when the IN signal was switched from OFF to ON, H_n PMOS changed from 0 to n (predefined value from 0 to 255), and H_n NMOS was changed from 255 to 60. If H_n PMOS and H_n NMOS change, the gate voltage V GSH of the MOSFET 3 and the gate current I Gof the power transistor 20. By changing n in such a control from 0 to 255, the Fig. 5B and Fig. 5C shown characteristics of the gate voltage V GSH and the gate current I G receive.

[0042] The Fig. 5B and Fig. 5C show measurement results under two conditions (a) and (b). In (a), the respective characteristic curve results of the gate voltage V GSH and the gate current I G according to a change in n when V DD1 and V DD2 15 V and V DD3 and V DD4 4 V. In (b) the respective characteristic curve results of the gate voltage V GSH and the gate current I G according to a change in n when V DD1 15 V, V DD2 0 V and V DD3 and V DD4 3.5 V.

[0043] Fig. Figure 5B shows an essentially linear correlation where the gate voltage VGSH increases with gradually increasing n. Fig. Figure 5C shows a correlation where the gate current I G gradually increases from n = 70 to 100 when n is increased step by step. As in (a) of Fig. As shown in Figure 5C, the gate current I G to about 51 A. In general, the gate current I G When driving a large-capacity power transistor, the required current may be 40 A or more, but the gate driver 10 of the present embodiment exceeds the required value. From such evaluation results, it can be seen that the gate driver 10 of the present embodiment has a linear characteristic in the gate voltage V GSH and a large capacitance in the gate current I G has.

[0044] Next, the evaluation results of a driving performance of the gate driver 10 (digital gate driver (DGD)) obtained by a double pulse test are presented with reference to the Fig. 6A and Fig. 6B. Fig. 6A shows a circuit configuration diagram of an evaluation environment of the double pulse test. Fig. 6B is a diagram showing the driving performance of the gate driver 10 in the double pulse test.

[0045] Fig. Figure 6A shows the circuit configuration diagram of the 600 V / 200 A double pulse test. In this circuit, two power transistors 31 and 32 are connected in series. A gate electrode of power transistor 31 in the lower part of the figure receives an input signal from gate driver 10. An inductor 33 in the upper part of the figure is connected in parallel with power transistor 32. In this test environment, power transistors 31 and 32 were used, in which the maximum value of a voltage between the collector and emitter electrodes was 6500 V and the maximum value of a collector current was 1000 A. In gate driver 10, V DD1 15 V, V DD2 0 V and VDD3 and V DD4 3.5V

[0046] A power supply 34 is connected to both ends of the series-connected power transistors 31 and 32, and a capacitor 35 is connected in parallel to the power supply 34. The power supply 34 supplies a voltage of 600 V, and a current of 200 A flows through the inductor 33. In such an environment, the double-pulse test was performed by controlling the power transistor 31 using the gate driver 10.

[0047] Fig. Figure 6B is a diagram showing results of the double pulse test using the environment of Fig. 6A. In this figure, the result of the double pulse test is an overshoot current (I OVERSHOOT ) of the power transistor 31 on an X-axis (horizontal axis) and a power loss (E LOSS ) of the power transistor 31 on a Y-axis (vertical axis).

[0048] Circles indicate a correlation between the overshoot current and the power loss when n is changed from 94 to 255, in a case where the gate driver 10 is driven by the Fig. 5A. According to this figure, it can be seen that there is a trade-off relationship in which the overshoot current decreases as n decreases and the power loss decreases as n increases.

[0049] A star indicates a result when the gate driver 10 is actively controlled. With active control, as in Fig. As shown in Figure 4, the gate voltages V GSH and V GSL of the MOSFET 3 are controlled so that they pass through an intermediate level when transitioning from OFF (low level) to ON (high level). Fig. The evaluation result shown in Figure 6B is achieved by the active control with a pattern that differs from that of Fig. 4 differs.

[0050] When the result of the star is compared with that of the circle of n = 96, the power loss can be reduced by 51% from 0.37 J to 0.18 J with almost the same overshoot current. When the result of the star is compared with that of the circle of n = 105, the overshoot current can be reduced by 26% from 326 A to 242 A with almost the same power loss. Therefore, it can be seen that the power transistors 31 and 32 can be driven with higher efficiency by variably controlling the gate driver 10 of the present embodiment.

[0051] In the description of the present embodiment, MOSFETs 3 and 4 are used as switches controlled by DACs 1 and 2, but the invention is not limited thereto. A bipolar transistor can be used instead of the MOSFET. While the MOSFET is controlled according to the gate voltage, the bipolar transistor is controlled by the gate current. Therefore, the gate voltage of the power transistor 20 connected to the bipolar transistor can be variably and dynamically controlled by controlling the current output from DACs 1 and 2 at three or more levels, including an intermediate level.

[0052] DACs 1 and 2, which are digital-to-analog converters, are used as control devices for controlling the switching elements, but the invention is not limited thereto. Alternatively, a device capable of outputting a signal with three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, may also be used.

[0053] By replacing the MOSFETs 3 and 4 with MOSFETs with different rated currents, a maximum value of an output current, ie the gate current I output by the gate driver 10, can also be achieved. G of the power transistor 20. By changing the voltages V DD3 and V DD4 of the power supplies 5 and 6 that supply power to the DACs 1 and 2 by using power supplies with different voltages, the maximum value of the gate current I output by the gate driver 10 can be GSince MOSFETs 3 and 4 and power supplies 5 and 6 are modularized and easily replaceable, the performance of gate driver 10 can be changed by replacing these components.

[0054] In this way, the gate driver 10 of the present embodiment includes the two DACs 1 and 2 and the MOSFETs 3 and 4. The output signals of the DACs 1 and 2 are variably and dynamically controlled to three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, according to a digital control signal received from the shift register 13. The MOSFETs 3 and 4 can control the gate voltage V GE and the gate current I G of the power transistor 20 to be controlled can be dynamically (actively) controlled to several levels according to the levels of the output signals of the DACs 1 and 2. As shown in Fig. 6B, both the overshoot current and the power loss of the power transistor 20 can be reduced.

[0055] Furthermore, the control circuit of DACs 1 and 2 is implemented by IC 11, which includes shift register 13. IC 11 includes a control circuit (shift registers 12 and 13 and edge decoder 14) that outputs a control signal to both DACs 1 and 2. In this way, both DACs 1 and 2 are controlled using one control circuit, allowing IC 11 to be miniaturized. Gate driver 10 has a half-bridge configuration with two sides, the high side and the low side, and can therefore operate in both turn-on control and turn-off control modes.

[0056] According to the present embodiment, the output signals of DACs 1 and 2 are the gate voltages V GSH and V GSLof MOSFETs 3 and 4, and with such a configuration, the switching control of MOSFETs 3 and 4 can be performed directly. The switching control of MOSFETs 3 and 4 can also be performed indirectly by changing the gate voltages to the ground of MOSFETs 3 and 4 instead of changing the gate voltages V GSH and V GSL as in the present embodiment. On the other hand, in the present embodiment, control accuracy of MOSFETs 3 and 4 can be improved by changing the gate voltages directly instead of indirectly.

[0057] Next, a further modification of the gate driver 10 will be described with reference to the Fig. 7 and Fig. 8 described.

[0058] Fig. Figure 7 shows a diagram illustrating a gate driver 10A according to a first modification. In the gate driver 10A illustrated in this figure, the power supply 5 that supplies a voltage to the DAC 1, the power supply 6 that supplies a voltage to the DAC 2, and the power supply 8 that forms a low-side output are smaller than in the gate driver 10A shown in Figure 7. Fig. 1 is omitted. At the same time, a predetermined voltage is supplied to DACs 1 and 2 from power supply 7 by changing voltage converters 41 and 42 instead of power supplies 5 and 6.

[0059] With such a configuration, DACs 1 and 2 can be driven by converting and supplying the voltage of power supply 7 (second power supply) without providing power supplies 5 and 6 (first power supply). Furthermore, gate driver 10A can be implemented even if one power supply 7 (second power supply) is provided for both MOSFETs 3 and 4. According to such a configuration, the number of power supplies in gate driver 10A can be reduced, and configuration can be simplified.

[0060] Fig. Fig. 8 is a diagram illustrating a gate driver 10B according to a second modification. In the gate driver 10B shown in this figure, compared to the gate driver 10B shown in Fig.In the gate driver 10 of the first embodiment shown in Figure 1, a resistor 51 is provided between the DAC 1 and the MOSFET 3, and a resistor 52 is provided between the DAC 2 and the MOSFET 4. With this configuration, the output signals of the DACs 1 and 2 can be smoothed, thereby stabilizing the operation of the power transistor 20 driven by the gate driver 10B.

[0061] As shown in the first modification, the number of power supplies of the gate driver 10A can be reduced, and as shown in the second modification, the operation of the gate driver 10B can be stabilized by providing the resistors 51 and 52. In addition to the configurations shown in these modifications, the gate driver 10 can adopt various other modifications.

[0062] Various embodiments and modifications can be made within the scope of the invention. The above-described embodiment serves to describe the invention and does not limit the scope of the invention. That is, the scope of the invention is indicated by the claims, not by the embodiment. Various modifications that can be made within the scope of the claims and equivalent embodiments of the invention are considered to be within the scope of the invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2017-135589 A [0003, 0004]

Claims

[1] Gate drive device operating on two sides, a high side and a low side, and driving a gate of a power transistor, the gate drive device comprising: a control device provided in pairs to form the two sides and configured to output a switching signal having three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, according to a received control signal; and a switching element provided in pairs corresponding to the control device and configured to output a voltage corresponding to a level of the switching signal received from the control device to the gate electrode of the power transistor. [2] A gate drive device according to claim 1, wherein the switching element is a MOSFET, and the control device is configured to output the switching signal corresponding to the received control signal to a gate electrode of the switching element. [3] Gate drive device according to claim 1 or 2, wherein the switching element is a MOSFET, and the control device is configured to change a gate voltage of the switching element to three or more levels according to the received control signal. [4] A gate drive device according to claim 1 or 2, wherein the switching element is a bipolar transistor, and the control device is configured to change a gate current of the switching element to three or more levels according to the received control signal. [5] The gate drive device according to claim 1 or 2, wherein the control means is a digital-to-analog converter configured to convert a received voltage based on the control signal, which is a received digital signal, and output the converted voltage as the switching signal. [6] The gate drive device according to claim 1, wherein, when operating on at least one of the two sides, the control signal is at the intermediate level in at least one period among a period during which the control signal changes from the high level to the low level and a period during which the control signal changes from the low level to the high level. [7] A gate drive device according to claim 1, wherein a maximum current that can be output from the switching element to the gate electrode of the power transistor is determined according to a rated current of the switching element. [8] A gate drive device according to claim 1, wherein a maximum current that can be output from the switching element to the gate electrode of the power transistor is determined according to a voltage supplied to the control means. [9] The gate drive device according to claim 1, wherein a control unit is provided for the paired control device, which control unit is configured to generate the control signal for the control device. [10] The gate drive device according to claim 1, wherein the control device is configured to receive a power supplied from a first power supply and output the switching signal, and the switching element is configured to convert a voltage received from a second power supply according to the switching signal and output a voltage corresponding to a level of the switching signal obtained by the conversion to the gate electrode of the power transistor. [11] The gate drive device according to claim 10, wherein the first power supply is formed by converting the second power supply. [12] A gate drive device according to claim 10 or 11, wherein at least one of a pair of switching elements is provided with the second power supply. [13] A gate drive device according to claim 1, further comprising: a resistor provided between the control device and the switching element. [14] Gate drive system operating on two sides, a high side and a low side, and driving a gate electrode of a power transistor, the gate drive system comprising: a control unit configured to output a control signal changeable to three or more levels, including a high level, a low level, and one or more intermediate levels; a control device provided in pairs to form the two sides and configured to output a switching signal corresponding to the control signal output by the control unit; and a switching element provided in pairs corresponding to the control device and configured to output to the gate electrode of the power transistor a voltage corresponding to a level of the switching signal received from the control device.

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