Semiconductor device

Abstract

An increase in the size of a device is suppressed. A semiconductor device comprises: a P-electrode arranged to extend outward from a first lateral surface of the substrate; an AC-electrode arranged to extend outward from a second lateral surface opposite the first lateral surface; a first interconnecting electrode and a second interconnecting electrode, each arranged to extend outward from at least one third lateral surface intersecting with the first lateral surface and a fourth lateral surface opposite the third lateral surface, wherein the first interconnecting electrode does not overlap either the P-electrode or the AC-electrode above the substrate, and the second interconnecting electrode does not overlap either the P-electrode or the AC-electrode above the substrate.

Description

TECHNICAL FIELD

[0001] The technology disclosed herein relates to power semiconductor technology. BACKGROUND TECHNOLOGY

[0002] A conventional power device module includes a P-electrode, an N-electrode, and an AC electrode. Each of the electrodes is disposed on a first lateral surface outside a frame of the power device module or a second lateral surface opposite the first lateral surface.

[0003] When a plurality of power device modules are used in parallel, the AC electrodes of the parallel-connected power device modules are wired and the N electrodes of the parallel-connected power device modules are wired, so that an oscillation phenomenon can be suppressed.

[0004] When the plurality of power device modules are used in parallel, other power device modules are generally arranged to face a third lateral surface perpendicular to both the first lateral surface and the second lateral surface, and a fourth lateral surface opposite the third lateral surface.

[0005] The AC electrodes or the N electrodes are thus arranged on the third lateral surface and the fourth lateral surface opposite each other to facilitate wiring between the AC electrodes or between the N electrodes of the parallel-connected power device modules.

[0006] For example, as illustrated in Patent Document 1, power device modules each having an AC electrode and an N electrode arranged on a side surface perpendicular to a side surface where a P electrode and an N electrode are arranged are arranged so that the side surfaces where the AC electrodes and the N electrodes are arranged face each other. This facilitates wiring between the AC electrodes and between the N electrodes of adjacent power device modules to suppress oscillation phenomena. DOCUMENTS ACCORDING TO THE PRIOR ART PATENT DOCUMENT

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-169609 SUMMARY PROBLEM TO BE SOLVED BY THE INVENTION

[0008] In a structure shown in Patent Document 1, electrodes are wired in a sealing resin of a power device module while overlapping each other in plan view. The electrodes wired so as to overlap each other in plan view must be spaced apart to maintain insulation. This results in the problem of increasing the size of a device.

[0009] The technology disclosed herein has been conceived in view of a problem as described above, and is a technology for suppressing an increase in the size of a device while facilitating wiring when devices are used in parallel. MEANS TO SOLVE THE PROBLEM

[0010] A semiconductor device as a first aspect of the technology disclosed herein comprises: a substrate; at least one semiconductor element disposed over a top surface of the substrate; a P-electrode electrically connected to the semiconductor element and arranged to extend outward in plan view from a first lateral surface of the substrate; an AC electrode electrically connected to the semiconductor element and arranged to extend outward in plan view from a second lateral surface opposite the first lateral surface;a first connection electrode electrically connected to the semiconductor element and the AC electrode and arranged to extend outward in plan view from at least one of a third lateral surface intersecting the first lateral surface and a fourth lateral surface opposite the third lateral surface; and a second connection electrode electrically connected to the semiconductor element and arranged to extend outward in plan view from at least one of the third lateral surface and the fourth lateral surface, wherein the first connection electrode overlaps neither the P electrode nor the AC electrode in plan view above the substrate, and the second connection electrode overlaps neither the P electrode nor the AC electrode in plan view above the substrate. EFFECTS OF THE INVENTION

[0011] According to at least the first aspect of the technology disclosed herein, the connecting electrodes are arranged on the side surfaces that intersect with the side surfaces where the P-electrode and the AC electrode are arranged to facilitate wiring while suppressing oscillation when the components are used in parallel. The connecting electrodes are arranged so that they do not overlap the P-electrode or the AC electrode in the plan view above the substrate, enabling device miniaturization.

[0012] These and other objects, features, aspects and advantages related to the technology disclosed herein will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view illustrating an example of a configuration of a semiconductor device according to an embodiment. Fig. 2 is a plan view illustrating an example of a configuration of a semiconductor device according to an embodiment. Fig. 3 is a plan view illustrating an example of a configuration of semiconductor devices according to an embodiment. Fig. 4 is a perspective view illustrating an example of a configuration of a semiconductor device according to an embodiment. Fig. 5 is a perspective view illustrating an example of a configuration of a semiconductor device according to an embodiment. Fig. Figure 6 is a side view of the configuration illustrated in the figure. Fig. 7 is a perspective view illustrating an example of a configuration of a semiconductor device according to an embodiment. Fig. 8 is a side view illustrating an example of a configuration of a semiconductor device according to an embodiment. Fig. 9 is a side view illustrating an example of a configuration of semiconductor devices according to an embodiment. Fig. 10 is a plan view illustrating an example of a configuration of semiconductor devices according to an embodiment. Fig. 11 is a plan view illustrating an example of a configuration of a semiconductor device DESCRIPTION OF THE EMBODIMENTS

[0013] Embodiments will be described below with reference to the accompanying drawings. Although detailed features and the like in the embodiments below are presented to describe the technology, they are examples and are not necessary features for implementing the embodiments.

[0014] The drawings are schematically illustrated, and components are omitted or simplified as appropriate for the sake of convenience in description. The sizes and inter-positional relationships between components and the like illustrated in the various drawings are not necessarily exact and may be changed as appropriate. For easy understanding of the embodiments, hatching is sometimes used for drawings other than cross-sectional views, such as plan views.

[0015] Similar components bear the same reference numerals and have similar names and functions in the following description. Therefore, their detailed description is sometimes omitted to avoid redundancy.

[0016] In the description herein, an expression “comprising,” “containing,” or “having” a particular component is not an exclusive expression that excludes the presence of the other components unless otherwise specified.

[0017] In the description made herein, ordinal numbers such as "first" and "second" are used for convenience in easily understanding the embodiments, and the order is not limited to that which can be represented by the ordinal numbers.

[0018] In the description herein, terms may be used to represent specific positions or directions, such as "upper," "lower," "left," "right," "side," "bottom," "front," and "rear"; however, these terms are used for convenience in easily understanding the embodiments and do not refer to positions or directions in an actual implementation.

[0019] In the description herein, the expression "an upper surface of..." or "a lower surface of..." includes not only the upper surface or lower surface of a target component itself, but also a state where another component is formed on the upper surface or lower surface of the target component. That is, the expression "A disposed on an upper surface of B" does not preclude the possibility of another component "C" being disposed between A and B. <Erste Ausführungsform>

[0020] A semiconductor device according to the present embodiment will be described below. A configuration of a semiconductor device known to the inventors will be described first for convenience of description.

[0021] In the following description, an expression “A and B are electrically connected” means that a current can flow bidirectionally between components A and B.

[0022] Fig. 11 is a plan view illustrating an example of a configuration of a semiconductor device. Fig. The semiconductor device illustrated in Fig. 11 includes an N-electrode 161, a P-electrode 131, and an AC electrode 151 arranged to protrude outward from a frame of a substrate 100 while being partially covered with a resin 80.

[0023] Here, the N-electrode 161 and the P-electrode 131 are arranged outside a frame of a first lateral surface of the substrate 100. On the other hand, the AC electrode 151 is arranged outside a frame of a second lateral surface opposite the first lateral surface. <Konfiguration einer Halbleitervorrichtung>

[0024] Fig. 1 is a plan view illustrating an example of a configuration of a semiconductor device according to the present embodiment. As shown in Fig. 1, the semiconductor device includes a metal layer 11, a metal layer 12, and a metal layer 13 formed over an upper surface of the substrate 100 so as to be spaced apart from each other.

[0025] A P-electrode 31 is connected to an upper surface of the metal layer 11 via an interconnect 21. A semiconductor element 41 is connected to the upper surface of the metal layer 11. That is, the P-electrode 31 is electrically connected to the semiconductor element 41 via the metal layer 11. An AC electrode 53 is connected to an upper surface of the semiconductor element 41. The AC electrode 53 is wired (connected) to an AC electrode 52. The AC electrode 53 is connected to the metal layer 12 via an interconnect 22.

[0026] An AC electrode 51 is connected to an upper surface of the metal layer 12 via a connection 23. That is, the AC electrode 53 is electrically connected to the AC electrode 51 via the metal layer 12. A semiconductor element 42 is connected to the upper surface of the metal layer 12. That is, the AC electrode 51 is electrically connected to the semiconductor element 42 via the metal layer 12. An N-electrode 63 is connected to an upper surface of the semiconductor element 42. The N-electrode 63 is connected to the metal layer 13 via a connection 24.

[0027] An N-electrode 62 is connected to an upper surface of the metal layer 13 via a connection 25. An N-electrode 61 is connected to the upper surface of the metal layer 13 via a connection 26. The N-electrode 61 is electrically connected to the semiconductor element 42 via the metal layer 13 and the N-electrode 63.

[0028] The P-electrode, the N-electrode, and the AC-electrode (output terminals) herein are, for example, lead terminals for use in the semiconductor device. The lead terminals are generally provided as a lead frame stamped in a predetermined pattern from a strip-like thin metal plate and separated from the frame after undergoing necessary processing.

[0029] The P-electrode 31 and the N-electrode 61 are arranged outside a frame of a first lateral surface of the substrate 100. The AC electrode 51 is arranged outside a frame of a second lateral surface opposite the first lateral surface.

[0030] The AC electrode 52 and the N electrode 62 are arranged outside a frame of a third lateral surface perpendicular to the first lateral surface. The AC electrode 53 and the N electrode 63 are arranged outside a frame of a fourth lateral surface opposite the third lateral surface.

[0031] According to such a configuration, the AC electrode 52 and the AC electrode 53 are electrically connected to the AC electrode 51 via the metal layer 12. Furthermore, the N electrode 62 and the N electrode 63 are electrically connected to the N electrode 61 via the metal layer 13.

[0032] Specifically, the AC electrode 52 and the AC electrode 53 are arranged so that, in plan view, they overlap the substrate 100 and do not overlap the P-electrode 31, the AC electrode 51, or the N-electrode 61 above the substrate 100. Similarly, the N-electrode 62 and the N-electrode 63 are arranged so that, in plan view, they overlap the substrate 100 and do not overlap the P-electrode 31, the AC electrode 51, or the N-electrode 61 above the substrate 100.

[0033] Consequently, the AC electrode 52 and the N electrode 62 may be arranged outside the frame of the third lateral surface, and the AC electrode 53 and the N electrode 63 may be arranged outside the frame of the fourth lateral surface, wherein within the frame of the substrate 100, the electrodes do not stereoscopically intersect (ie, do not overlap in plan view).

[0034] In other words, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are arranged at positions where they overlap the substrate 100 in plan view but do not overlap the P electrode 31 in plan view above the substrate 100. Furthermore, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are arranged at positions where they overlap the substrate 100 in plan view but do not overlap the AC electrode 51 in plan view above the substrate 100. Furthermore, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are arranged at positions where they overlap the substrate 100 in plan view but do not overlap the N electrode 61 in plan view above the substrate 100.

[0035] The number of semiconductor elements of the semiconductor device only needs to be at least one. <Zweite Ausführungsform>

[0036] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiment are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0037] Fig. 2 is a plan view illustrating an example of a configuration of the semiconductor device according to the present embodiment. As shown in Fig. 2, the semiconductor device includes the metal layer 11 and the metal layer 12 formed over an upper surface of a substrate 100A so as to be spaced apart from each other.

[0038] The P-electrode 31 is connected to the upper surface of the metal layer 11 via the interconnect 21. The semiconductor element 41 is connected to the upper surface of the metal layer 11. An AC electrode 53A is connected to the upper surface of the semiconductor element 41. The AC electrode 53A is wired (connected) to an AC electrode 52A. The AC electrode 53A is connected to the metal layer 12 via the interconnect 22.

[0039] The AC electrode 51 is connected to the upper surface of the metal layer 12 via the connection 23. The semiconductor element 42 is connected to the upper surface of the metal layer 12. An N-electrode 63A is connected to the upper surface of the semiconductor element 42. The N-electrode 63A is wired (connected) to an N-electrode 62A.

[0040] The P electrode 31 is arranged outside a frame of a first lateral surface of the substrate 100A. The AC electrode 51 is arranged outside a frame of a second lateral surface opposite the first lateral surface.

[0041] The AC electrode 52A and the N electrode 62A are arranged outside a frame of a third lateral surface perpendicular to the first lateral surface. The AC electrode 53A and the N electrode 63A are arranged outside a frame of a fourth lateral surface opposite the third lateral surface.

[0042] According to such a configuration, the AC electrode 52A and the AC electrode 53A are electrically connected to the AC electrode 51 via the metal layer 12.

[0043] Consequently, the AC electrode 52A and the N electrode 62A may be disposed outside the frame of the third lateral surface, and the AC electrode 53A and the N electrode 63A may be disposed outside the frame of the fourth lateral surface, with the electrodes not stereoscopically intersecting (i.e., not overlapping in plan view) within the frame of the substrate 100A. To enable miniaturization of the device, the N electrode is not disposed on the first lateral surface. <Dritte Ausführungsform>

[0044] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0045] Fig. 3 is a plan view illustrating an example of a configuration of semiconductor devices according to the present embodiment. Fig. 3 corresponds to a configuration in which a plurality of substrates 100, each having the Fig. 1, are arranged adjacent to each other such that the third lateral surface and the fourth lateral surface are opposed to each other, the configuration above the upper surface of the substrate 100 being partially covered with a resin 80; specifically, the semiconductor element 41, the semiconductor element 42, a portion of the P-electrode 31, a portion of the N-electrode 61, a portion of the AC electrode 52, a portion of the AC electrode 53, a portion of the N-electrode 62, a portion of the N-electrode 63, and a portion of the AC electrode 51 corresponding to each of the substrates 100 are covered with the resin 80.

[0046] In the Fig. In the configuration illustrated in Figure 3, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are arranged at positions where they do not overlap the P electrode 31 in the resin 80 when viewed from above. Furthermore, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are arranged at positions where they do not overlap the AC electrode 51 in the resin 80 when viewed from above. Furthermore, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are arranged at positions where they do not overlap the N electrode 61 in the resin 80 when viewed from above.

[0047] As in Fig. As illustrated in Fig. 3, the AC electrode 52 on the third lateral surface and the AC electrode 53 on the fourth lateral surface of the substrates 100, which are arranged adjacent to each other (opposite each other), are connected (i.e., the AC electrodes on the opposite lateral surfaces are connected), and the N electrode 62 on the third lateral surface and the N electrode 63 on the fourth lateral surface of the substrates 100, which are arranged adjacent to each other (opposite each other), are connected (i.e., the N electrodes on the opposite lateral surfaces are connected). These electrodes are connected, for example, by welding, screwing, or soldering.

[0048] According to such a configuration, oscillation of semiconductor elements of a plurality of parallel-connected power device modules can be suppressed. <Vierte Ausführungsform>

[0049] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0050] Fig. 4 is a perspective view illustrating an example of a configuration of the semiconductor device according to the present embodiment. Fig. 4 is a structure in which the resin 80 is above the Fig. 2, and further an N-bus bar 70 is disposed over an upper surface of the resin 80.

[0051] As in Fig. As illustrated in Figure 4, the N-type bus bar 70 is connected to both the N-type electrode 62 and the N-type electrode 63. The N-type bus bar 70 is formed to extend to a position adjacent to the P-type electrode 31, which is located outside the frame of the first lateral surface of the substrate 100A.

[0052] According to such a configuration, the N-type bus bar 70 is located at a top surface of the semiconductor device, so that the N-type bus bar 70 is a flat plate parallel to the wiring in the resin 80 above the top surface of the resin 80. This can suppress inductance. <Fünfte Ausführungsform>

[0053] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0054] Fig. 5 is a perspective view illustrating an example of a configuration of the semiconductor device according to the present embodiment. Fig. 5 is a structure in which the resin 80 is above the Fig. 2 (although a shape of a P-electrode 31A has been deformed), and further an N-bus bar 72 is arranged over the upper surface of the resin 80. Fig. 6 is a side view of the Fig. 5 illustrated configuration.

[0055] As in Fig. 5 and Fig. As illustrated in FIG. 6, the N bus bar 72 is connected to both the N electrode 62 and the N electrode 63. The N bus bar 72 is formed to extend as a flat plate parallel to the P electrode 31A outside the frame of the first lateral surface of the substrate 100A. That is, the N bus bar 72 is arranged to overlap the P electrode 31A outside the frame of the first lateral surface in plan view.

[0056] According to such a configuration, the inductance can be effectively suppressed. The N-electrode 61 and the P-electrode 31, which are Fig. 1 may be arranged so as to overlap each other in plan view outside the frame of the first lateral surface. <Sechste Ausführungsform>

[0057] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0058] Fig. Fig. 7 is a perspective view illustrating an example of a configuration of the semiconductor device according to the present embodiment. Fig. 7 is a structure in which a resin 80A is applied above the Fig. 2, and further an N-bus bar 70A is arranged over an upper surface of the resin 80.

[0059] As in Fig. As illustrated in Figure 7, the N-type bus bar 70A is connected to both the N-type electrode 62 and the N-type electrode 63. The N-type bus bar 70A is formed to extend to a position adjacent to the P-type electrode 31 located outside the frame of the first lateral surface of the substrate 100A.

[0060] The N busbar 70A has a plurality of holes 70B. The relative positions of the N busbar 70A and the resin 80A are determined such that a plurality of protrusions 82 formed on the upper surface of the resin 80A fit into the holes 70B (ie, the protrusions 82 overlap the holes 70B in plan view). The number of protrusions 82 and the number of holes 70B may each be one.

[0061] According to such a configuration, the relative positions of the N bus bar 70A and the resin 80A are determined by the holes 70B and the protrusions 82, so that misalignment in mounting the semiconductor device can be suppressed. <Siebte Ausführungsform>

[0062] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0063] Fig. 8 is a side view illustrating an example of a configuration of the semiconductor device according to the present embodiment. Fig. The structure illustrated in Figure 8 is a structure in which a form of the resin in the Fig. 4 illustrated structure has been deformed.

[0064] As in Fig. 8, a resin 80B has guides 84 on its upper surface. The guides 84 are protruding or raised portions on the upper surface of the resin 80B. An N-bus bar 74 is connected to both the N-electrode 62 and the N-electrode 63. Here, the N-bus bar 74 is arranged above the upper surface of the resin 80B adjacent to the guides 84 at a position where the N-bus bar 74 is sandwiched between the guides 84 in plan view. Specifically, the N-bus bar 74 is arranged above the upper surface of the resin 80B while being sandwiched between the two guides 84 for fixation. The N-bus bar 74 may be surrounded by a circumferentially continuous guide 84. Both the Fig. 7 illustrated elevations 82 as well as the guides 84 may be provided.

[0065] According to such a configuration, the N-type busbar 74 is positioned by fitting it between the guides 84, so that misalignment during assembly of the semiconductor device can be suppressed. Insulation strength can be improved by maintaining a long creepage distance between the N-type busbar 74 and the AC electrode by forming the guides 84. <Achte Ausführungsform>

[0066] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0067] Fig. 9 is a side view illustrating an example of a configuration of semiconductor devices according to the present embodiment. Fig. 9 is a structure in which a shape of at least one of the AC electrode and the N electrode is in the Fig. 1 illustrated structure has been deformed.

[0068] As in Fig. As illustrated in Figure 9, the N-electrode 63A has a bend 63B so that the height of an end connected to the N-electrode 62 of an adjacent power device module can be reduced. The bend 63B bends (offsets) the end of the N-electrode 63A by, for example, a thickness of the N-electrode 63A toward one side of the upper surface of the substrate 100.

[0069] According to such a configuration, good insulation can be maintained between a part installed on a top surface of the semiconductor device and the N-electrode 63A by ensuring a sufficient insulation distance. The part installed on the surface of the semiconductor device includes a bus bar, a control board, and the like.

[0070] While the above description illustrates a case where the N electrode 63A has the bend 63B, an electrode having a bend may include the N electrode 62, the AC electrode 52, the AC electrode 53, and the like. Both an electrode located outside the frame of the third lateral surface and an electrode located outside the frame of the fourth lateral surface may have a bend. <Neunte Ausführungsform>

[0071] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0072] Fig. 10 is a plan view illustrating an example of a configuration of semiconductor devices according to the present embodiment. Fig. 10 is a structure in which the Fig. 3 illustrated structure electrodes that are not connected to their counterparts of an adjacent power device module, that is, a non-connected AC electrode 52 on the third lateral surface, a non-connected AC electrode 53 on the fourth lateral surface, a non-connected N-electrode 62 on the third lateral surface and a non-connected N-electrode 63 on the fourth lateral surface in Fig. 3, are not arranged outside the frames of the side surfaces at the respective positions. At least one electrode not connected to its counterpart of an adjacent power device module need only be unconnected, and the configuration is not limited to a configuration in which all the electrodes not connected to their counterparts of the adjacent power device module are unconnected, as in Fig. 10 is illustrated.

[0073] According to such a configuration, good insulation can be maintained on surfaces where the N-electrode and the AC electrode are not arranged. Even if another device is arranged to face a surface where the N-electrode and the AC electrode are not arranged, the insulation distance does not need to be considered separately, so an increase in the size of the device can be suppressed. <Zehnte Ausführungsform>

[0074] A semiconductor device according to the present embodiment will be described below. In the following description, similar components to those described in the above-described embodiments are given the same reference numerals as those of the similar components, and detailed descriptions thereof will be omitted as appropriate. <Konfiguration der Halbleitervorrichtung>

[0075] In each of the embodiments described above, the semiconductor element may contain SiC. <Durch die oben beschriebenen Ausführungsformen erzielte Effekt>

[0076] Examples of effects achieved by the above-described embodiments will be presented next. In the description given below, the effects will be described based on a specific configuration, examples of which are illustrated in the above-described embodiments, but the specific configuration may be replaced with another specific configuration, examples of which are illustrated herein, to the extent that similar effects are achieved. That is, only one of respective specific configurations is sometimes described as representative hereinafter for convenience; however, the specific configuration described as the representative may be replaced with another corresponding specific configuration.

[0077] The replacement may encompass a variety of embodiments. That is, configurations exemplified in different embodiments may be combined to achieve similar effects.

[0078] According to the embodiments described above, the semiconductor device includes: the substrate 100 (or the substrate 100A); the at least one semiconductor element 41 (or semiconductor element 42); the P-electrode 31 (or the P-electrode 31A); the AC electrode 51; the first connection electrode; and the second connection electrode. The first connection electrode herein corresponds, for example, to at least one of the AC electrode 52, the AC electrode 52A, the AC electrode 53, the AC electrode 53A, and the like. The second connection electrode corresponds, for example, to at least one of the N-electrode 62, the N-electrode 62A, the N-electrode 63, the N-electrode 63A, and the like. The semiconductor element 41 is disposed above the upper surface of the substrate 100. The P-electrode 31 is electrically connected to the semiconductor element 41. The P-electrode 31 is arranged so as to extend outwardly from the first lateral surface of the substrate 100 in plan view.The AC electrode 51 is electrically connected to the semiconductor element 41. The AC electrode 51 is arranged so that, in plan view, it extends outward from the second lateral surface opposite the first lateral surface. The AC electrode 52 is electrically connected to the semiconductor element 41 and the AC electrode 51. The AC electrode 52 is arranged so that, in plan view, it extends outward from the third lateral surface intersecting the first lateral surface and / or the fourth lateral surface opposite the third lateral surface. The N-electrode 62 is electrically connected to the semiconductor element 41. The N-electrode 62 is arranged so that, in plan view, it extends outward from the third lateral surface and / or the fourth lateral surface. The AC electrode 52 does not overlap the P-electrode 31 or the AC electrode 51 in plan view above the substrate 100.In the plan view above the substrate 100, the N-electrode 62 overlaps neither the P-electrode 31 nor the AC-electrode 51.

[0079] According to such a configuration, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63, each constituting the connection electrode, are arranged on the side surfaces that intersect with the side surfaces where the P electrode 31 and the AC electrode 51 are arranged. This facilitates wiring while suppressing oscillation when the components are used in parallel. Furthermore, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63, which constitute the connection electrodes, do not overlap the P electrode 31 or the AC electrode 51 in the plan view above the substrate 100. This enables miniaturization of the device.

[0080] Similar effects can be achieved when another configuration, an example of which is shown herein, is added to the above-mentioned configuration as appropriate, that is, when another configuration not referred to herein as the above-mentioned configuration is added to the above-mentioned configuration as appropriate.

[0081] According to the embodiments described above, the semiconductor device includes the resin 80 (or the resin 80A and the resin 80B). The resin 80 is disposed over the upper surface of the substrate 100 so as to cover the semiconductor element 41, a portion of the P electrode 31, a portion of the AC electrode 51, a portion of the AC electrode 52, and a portion of the N electrode 62. The AC electrode 52 overlaps neither the P electrode 31 nor the AC electrode 51 in the resin 80 when viewed from a top view. The N electrode 62 overlaps neither the P electrode 31 nor the AC electrode 51 in the resin 80 when viewed from a top view. According to such a configuration, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are each arranged so that they do not overlap either the P electrode 31 or the AC electrode 51 in the resin 80 when viewed from a top view. This enables miniaturization of the device.

[0082] According to the embodiments described above, the semiconductor device includes the N-electrode 61 (or the N-bus bar 70, the N-bus bar 70A, the N-bus bar 72, and the N-bus bar 74) electrically connected to the semiconductor element 41 and arranged to extend outward from the first lateral surface in plan view. The N-electrode 62 is electrically connected to the N-electrode 61. According to such a configuration, the AC electrode 52, the AC electrode 53, the N-electrode 62, and the N-electrode 63 are each arranged so as not to overlap the P-electrode 31, the AC electrode 51, or the N-electrode 61 in plan view above the substrate 100. This enables miniaturization of the device.

[0083] According to the embodiments described above, the resin 80 is arranged to cover a partial area of ​​the N electrode 61. The AC electrode 52 does not overlap the N electrode 61 in the resin 80 when viewed from above. The N electrode 62 does not overlap the N electrode 61 in the resin 80 when viewed from above. According to such a configuration, the AC electrode 52, the AC electrode 53, the N electrode 62, and the N electrode 63 are each arranged so that they do not overlap the P electrode 31, the AC electrode 51, or the N electrode 61 in the resin 80 when viewed from above. This enables miniaturization of the device.

[0084] According to the embodiments described above, the N-type bus bar 70 is arranged above the upper surface of the resin 80. According to such a configuration, the N-type bus bar 70 is located at the top of the semiconductor device, so that the N-type bus bar 70 above the upper surface of the resin 80 is the flat plate parallel to the wiring in the resin 80. This can suppress inductance.

[0085] According to the embodiments described above, the resin 80A has at least one protrusion 82 on its upper surface. The N-type bus bar 70A has at least one hole 70B, into which the protrusion 82 is fitted, at a position where the N-type bus bar 70A overlaps the protrusion 82 in plan view. According to such a configuration, the relative positions of the N-type bus bar 70A and the resin 80A are easily determined by the holes 70B and the protrusions 82, so that misalignment during assembly of the semiconductor device can be suppressed.

[0086] According to the embodiments described above, the resin 80B has at least one guide 84 on its upper surface. The N-type bus bar 74 above the upper surface of the resin 80B is arranged adjacent to the guide 84 in plan view. According to such a configuration, the N-type bus bar 74 is easily positioned by being fitted between the guides 84, so that misalignment during assembly of the semiconductor device can be suppressed. The insulation strength can be improved by maintaining a long creepage distance between the N-type bus bar 74 and the AC electrode by forming the guides 84.

[0087] According to the embodiments described above, in plan view, the N bus bar 70, which is arranged to extend from the first lateral surface, is adjacent to the P electrode 31, which is arranged to extend from the first lateral surface. According to such a configuration, the N bus bar 70 is located at the top of the semiconductor device, so that the N bus bar 70 is above the top surface of the resin 80, the flat plate parallel to the wiring in the resin 80. This can suppress inductance.

[0088] According to the above-described embodiments, in plan view, the N bus bar 72, which is arranged to extend from the first lateral surface, overlaps the P electrode 31A, which is arranged to extend from the first lateral surface. According to such a configuration, inductance can be effectively suppressed. Furthermore, the P electrode 31A and the N bus bar 72 are arranged to overlap each other outside the frame of the first lateral surface, enabling device miniaturization.

[0089] According to the embodiments described above, the substrate 100 includes a plurality of substrates 100. The semiconductor element 41, the P-electrode 31, the AC electrode 51, the AC electrode 52, and the N-electrode 62 are arranged on each of the substrates 100. The plurality of substrates 100 includes a first substrate and a second substrate arranged adjacent to each other. The first substrate and the second substrate are arranged so that the fourth side surface of the first substrate and the third side surface of the second substrate face each other. The AC electrode 53, which is arranged to extend outward in plan view from the fourth side surface of the first substrate, and the AC electrode 52, which is arranged to extend outward in plan view from the third side surface of the second substrate, are connected.The N-electrode 63, which is arranged to extend outward from the fourth side surface of the first substrate in plan view, and the N-electrode 62, which is arranged to extend outward from the third side surface of the second substrate in plan view, are connected. According to such a configuration, the AC electrode 52 and the AC electrode 53 of the adjacent power device modules are connected, and the N-electrode 62 and the N-electrode 63 of the adjacent power device modules are connected to reduce a potential difference between semiconductor elements of the parallel-connected power device modules, so that oscillation of the semiconductor elements can be suppressed.

[0090] According to the embodiments described above, at least one of the AC electrode 52 and the N electrode 62 is not arranged to extend from the third side surface of the first substrate and / or the fourth side surface of the second substrate. According to such a configuration, the N electrode and the AC electrode are not arranged on a surface that does not face an adjacent power device module, so that good surface insulation can be maintained. Even if another device is arranged to face the surface on which the N electrode and the AC electrode are not arranged, the insulation distance does not need to be considered separately, so that an increase in the size of the device can be suppressed.

[0091] According to the embodiments described above, at least one of the AC electrode 53A and the N electrode 63A, which are arranged to extend outward from the fourth lateral surface in plan view, has the bend 63B outside the resin 80. The bend 63B bends the end extending outward from the fourth lateral surface in plan view toward a side of the upper surface of the substrate 100. According to such a configuration, when semiconductor devices are arranged adjacent to each other, a height of a connection between electrodes of the adjacent semiconductor devices can be reduced. Thus, good insulation between the part installed on the upper surface of the semiconductor device and the N electrode 63A can be maintained by ensuring a sufficient insulation distance.

[0092] According to the embodiments described above, a semiconductor of the semiconductor element 41 comprises SiC. According to such a configuration, SiC is used for the semiconductor of the semiconductor element to reduce the size of the element compared to a case where a Si element is used. The size of the semiconductor device can thereby be reduced. When the size of the semiconductor device is reduced, a wiring distance between the semiconductor elements for use in a parallel circuit is reduced to reduce a potential difference between the semiconductor elements. <Modifikationen der oben beschriebenen Ausführungsformen>

[0093] In the embodiments described above, material properties, materials, dimensions, shapes, a relative positional relationship therebetween, or conditions for their performance are sometimes described for the components; but they are each an example in all aspects and are not restrictive.

[0094] Numerous modifications and equivalents, examples of which are not illustrated, are thus conceived within the scope of the technology described herein. For example, a case where at least one component is modified, added, or omitted, and further a case where at least one component is extracted in at least one embodiment to be combined with components in another embodiment, are included.

[0095] In the above-described embodiments, if a name of a material and the like are described without being particularly specified, an alloy and the like containing an additive in addition to the material may be included unless there is a contradiction.

[0096] "A" component in the embodiments described above may include "one or more" components, unless otherwise stated.

[0097] Moreover, each component in the embodiments described above is a conceptual unit, and a case where one component includes a plurality of structures, a case where one component corresponds to a portion of a structure, and a case where a plurality of components are included in one structure are included within the scope of the technology disclosed herein.

[0098] Each component in the embodiments described above includes a structure that has a different structure or shape as long as the same function is performed.

[0099] The description made herein is incorporated by reference for all purposes with respect to the present technology and is not admitted as prior art. EXPLANATION OF REFERENCE SYMBOLS

[0100] 31 P-electrode, 31A P-electrode, 41 semiconductor element, 42 semiconductor element, 51 AC electrode, 52 AC electrode, 52A AC electrode, 53 AC electrode, 53A AC electrode, 61 N-electrode, 62 N-electrode, 62A N-electrode, 63 N-electrode, 63A N-electrode, 70B hole, 80 resin, 80A resin, 80B resin, 82 bump, 84 guide, 100 substrate, 100A substrate, 131 P-electrode, 151 AC electrode, 161 N-electrode.

Claims

[1] A semiconductor device comprising: a substrate; at least one semiconductor element disposed over an upper surface of the substrate; a P-electrode electrically connected to the semiconductor element and arranged to extend outwardly from a first lateral surface of the substrate in plan view; an AC electrode electrically connected to the semiconductor element and arranged to extend outwardly in plan view from a second lateral surface opposite the first lateral surface; a first connection electrode electrically connected to the semiconductor element and the AC electrode and arranged to extend outwardly in plan view from at least one of a third lateral surface intersecting the first lateral surface and a fourth lateral surface opposite the third lateral surface; and a second connection electrode electrically connected to the semiconductor element and arranged to extend outwardly in plan view from at least one of the third lateral surface and the fourth lateral surface, wherein the first connection electrode in the plan view above the substrate does not overlap the P-electrode or the AC electrode and the second connection electrode in the plan view above the substrate does not overlap either the P-electrode or the AC electrode. [2] A semiconductor device according to claim 1, further comprising: a resin disposed over the upper surface of the substrate so as to cover the semiconductor element, a portion of the P-electrode, a portion of the AC electrode, a portion of the first connection electrode, and a portion of the second connection electrode, wherein the first connecting electrode in plan view in the resin does not overlap the P-electrode or the AC-electrode and the second connecting electrode in plan view in the resin does not overlap either the P-electrode or the AC-electrode. [3] The semiconductor device according to claim 2, further comprising an N-electrode electrically connected to the semiconductor element and arranged to extend outwardly from the first lateral surface in plan view, wherein the second connection electrode is electrically connected to the N-electrode. [4] A semiconductor device according to claim 3, wherein the resin is arranged so that it covers a portion of the N-electrode, the first connection electrode in plan view in the resin does not overlap the N-electrode and the second connection electrode in plan view in the resin does not overlap the N-electrode. [5] The semiconductor device according to claim 3, wherein the N-electrode is disposed over an upper surface of the resin. [6] A semiconductor device according to claim 5, wherein the resin has at least one elevation on its upper surface and the N-electrode has at least one hole into which the protrusion is fitted, at a position where the N-electrode overlaps the protrusion in plan view. [7] A semiconductor device according to claim 5 or 6, wherein the resin has at least one guide on its upper surface and the N-electrode is arranged above the upper surface of the resin in plan view adjacent to the guide. [8] A semiconductor device according to any one of claims 3 to 7, wherein the N-electrode arranged to extend from the first lateral surface is adjacent in plan view to the P-electrode arranged to extend from the first lateral surface. [9] The semiconductor device according to any one of claims 3 to 7, wherein the N electrode arranged to extend from the first lateral surface overlaps, in plan view, the P electrode arranged to extend from the first lateral surface. [10] A semiconductor device according to any one of claims 1 to 9, wherein the substrate comprises a plurality of substrates, the semiconductor element, the P-electrode, the AC electrode, the first connection electrode and the second connection electrode are arranged on each of the substrates, the plurality of substrates comprises a first substrate and a second substrate arranged adjacent to each other, the first substrate and the second substrate are arranged such that the fourth lateral surface of the first substrate and the third lateral surface of the second substrate are opposite each other, the first connection electrode, which is arranged to extend outward in plan view from the fourth lateral surface of the first substrate, and the first connection electrode, which is arranged to extend outward in plan view from the third lateral surface of the second substrate, are connected, and the second connection electrode arranged to extend outward in plan view from the fourth lateral surface of the first substrate and the second connection electrode arranged to extend outward in plan view from the third lateral surface of the second substrate are connected. [11] The semiconductor device according to claim 10, wherein at least one of the first connection electrode and the second connection electrode is not arranged to extend from at least one of the third side surface of the first substrate and the fourth side surface of the second substrate. [12] A semiconductor device according to any one of claims 1 to 11, wherein at least one of the first connection electrode and the second connection electrode, which are arranged to extend outwardly from the fourth lateral surface in plan view, has a bend outside the resin and the bend bends an end extending outwardly in plan view from the fourth lateral surface to one side of the upper surface of the substrate. [13] A semiconductor device according to any one of claims 1 to 12, wherein a semiconductor of the semiconductor element comprises SiC.

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