SEMICONDUCTOR DEVICE

Abstract

A semiconductor device (100) comprises an insulating layer (4) and a first electrode pattern (1). The first electrode pattern (1) comprises a first housing section (21) and a first step section (31). The first housing section (21) has a first surface (11), a second surface (12), and a first side face (41). The first surface (11) faces the insulating layer (4). The second surface (12) is opposite the first surface (11). The first step section (31) has a third surface (13) and a first step face (25). The third surface (13) faces the insulating layer (4). The first step face (25) is opposite the third surface (13). A boundary between the second surface (12) and the first side face (41) is defined as a first boundary (91).A boundary between the first side surface (41) and the first step surface (25) is defined as a second boundary (92). In a cross-section perpendicular to the second surface (12), a length of the first side surface (41) is longer than a length of a conductor segment connecting the first boundary (91) and the second boundary (92).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] A semiconductor element that can handle high voltages or large currents is generally called a power semiconductor element. The current path of a power semiconductor element is usually in the thickness direction of the element. Examples of power semiconductor elements include an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a bipolar transistor, and a diode. A device in which a power semiconductor element is mounted on an insulating substrate and packaged with a sealing member is called a semiconductor device.

[0003] Semiconductor devices are used in a wide range of fields, including industrial equipment, automobiles, and railways. In recent years, as the performance of devices incorporating semiconductor devices has improved, the rated voltage and rated current of semiconductor devices have increased, and the operating temperature range of semiconductor devices has expanded (higher and lower temperatures). In other words, there is a growing demand for higher performance and higher reliability of semiconductor devices. To meet this demand, insulating substrates on which semiconductor elements are mounted must have high heat dissipation and high reliability.

[0004] Japanese Patent Laid-Open Publication No. 2004-296619 (Patent Document 1) discloses a method for manufacturing an insulating substrate in which an electrode pattern having a step portion on the side surface is formed by milling at least a part of a metal layer.

[0005] Japanese Patent Application Laid-Open No. 2004-296619

[0006] However, in an insulating substrate manufactured using the manufacturing method disclosed in Patent Document 1, the side surfaces of the electrode patterns are linear. Therefore, although the step portion can suppress peeling between the electrode patterns and the insulating substrate when subjected to a thermal cycle, peeling may occur between the sealing member and the insulating substrate. This may result in a deterioration of the insulating performance of the semiconductor device.

[0007] The present disclosure has been made in view of the above, and has an object to provide a semiconductor device capable of suppressing deterioration of insulation performance due to thermal cycles.

[0008] The semiconductor device according to the present disclosure includes an insulating substrate, a semiconductor element, a case, and a sealing member. The insulating substrate includes an insulating layer and a first electrode pattern. The first electrode pattern is provided on the insulating layer. The semiconductor element is provided on the first electrode pattern. The case surrounds the insulating substrate. The sealing member covers the insulating substrate and the semiconductor element. The first electrode pattern includes a first main body portion and a first step portion. The first step portion protrudes from the first main body portion. The first main body portion includes a first surface, a second surface, and a first side surface. The first surface faces the insulating layer. The second surface is located opposite the first surface. The second surface faces the semiconductor element. The first side surface is continuous with the second surface. The first step portion includes a third surface and a first step surface. The third surface is continuous with the first surface. The third surface faces the insulating layer. The first step surface is located opposite the third surface. The first step surface is continuous with the first side surface. In a cross section perpendicular to the second surface, the first side surface is curved. In a cross section perpendicular to the second surface, the boundary between the second surface and the first side surface is defined as a first boundary. In a cross section perpendicular to the second surface, the boundary between the first side surface and the first step surface is defined as a second boundary. The length of the line segment connecting the first boundary and the second boundary in the cross section perpendicular to the second surface is defined as a first length. The length of the first side surface in the cross section perpendicular to the second surface is longer than the first length.

[0009] According to the present disclosure, the first step portion of the first electrode pattern improves the bonding strength between the first electrode pattern and the insulating layer, while the anchor effect between the first side surface and the sealing member suppresses peeling between the sealing member and the insulating substrate, thereby providing a semiconductor device that can suppress deterioration of insulation performance due to thermal cycles.

[0010] 8 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. FIG. 9 is an enlarged schematic cross-sectional view of a region II in FIG. 1. For convenience of explanation, a sealing member is not shown in FIG. 2. FIG. 10 is an enlarged schematic cross-sectional view showing a step of bonding a metal plate to an insulating layer. FIG. 11 is an enlarged schematic cross-sectional view showing a step of cutting the metal plate. FIG. 12 is an enlarged schematic cross-sectional view showing a step of printing an etching resist on the metal plate. FIG. 13 is an enlarged schematic cross-sectional view showing the configuration of a semiconductor device according to a modified example of the first embodiment. FIG. 14 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. FIG. 15 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. FIG. 16 is an enlarged schematic cross-sectional view of a region IX in FIG. 1. FIG. 17 is an enlarged schematic cross-sectional view showing the configuration of a semiconductor device according to a modified example of the third embodiment.

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0012] Embodiment 1 (Configuration of Semiconductor Device) The configuration of a semiconductor device 100 will be described with reference to Figures 1 and 2. As shown in Figure 1, the semiconductor device 100 mainly includes a base plate 5, an insulating substrate 10, a first bonding portion 51, a semiconductor element 9, a second bonding portion 52, wiring 8, terminals 7, a case 6, a lid 70, and a sealing member 60.

[0013] The base plate 5 forms the bottom surface of the semiconductor device 100. In other words, the base plate 5 is the bottom plate of the semiconductor device 100. The insulating substrate 10 is on the base plate 5. The insulating substrate 10 and the base plate 5 are joined, for example, by a first joint 51. The semiconductor element 9 is on the insulating substrate 10. The semiconductor element 9 and the insulating substrate 10 are joined, for example, by a second joint 52. The case 6 is combined with the base plate 5. The case 6 forms the side surface of the semiconductor device 100. The terminals 7 are on the case 6. The lid 70 is on the case 6. The lid 70 and the case 6 are bonded, for example, by an adhesive (not shown). The sealing member 60 is filled in the area surrounded by the base plate 5, the case 6, and the lid 70. The wiring 8 is a portion for electrically connecting the semiconductor element 9 to an external device (not shown) of the semiconductor device 100.

[0014] The base plate 5 is, for example, flat. The base plate 5 has a seventh surface 17 and an eighth surface 18. The seventh surface 17 is the bottom surface of the semiconductor device 100. The eighth surface 18 is opposite to the seventh surface 17. The base plate 5 is made of, for example, copper. The insulating substrate 10 faces the eighth surface 18 of the base plate 5. The insulating substrate 10 has an insulating layer 4, a first electrode pattern 1, a second electrode pattern 2, and a third electrode pattern 3.

[0015] The third electrode pattern 3 faces the eighth surface 18 of the base plate 5. The third electrode pattern 3 is made of, for example, copper. The third electrode pattern 3 and the base plate 5 are joined by, for example, a first joint 51. The first joint 51 is, for example, solder. The first joint 51 may be made of, for example, silver or a silver alloy.

[0016] The insulating layer 4 is on the third electrode pattern 3. The insulating layer 4 has a ninth surface 19 and a tenth surface 20. The ninth surface 19 faces the third electrode pattern 3. At the ninth surface 19, the insulating layer 4 is in contact with the third electrode pattern 3. The third electrode pattern 3 is provided on the ninth surface 19 of the insulating layer 4 using, for example, a direct bonding method, a brazing bonding method, a molten metal bonding method, or a plating method. The tenth surface 20 is on the opposite side of the ninth surface 19.

[0017] The insulating layer 4 insulates the semiconductor element 9 from the base plate 5. It is desirable that the insulating layer 4 have heat dissipation properties. The insulating layer 4 is made of ceramic such as aluminum oxide (Al2O3), silicon dioxide (SiO2), aluminum nitride (AlN), boron nitride (BN), silicon nitride (Si3N4), or the like.

[0018] The first electrode pattern 1 is provided on the insulating layer 4. The first electrode pattern 1 is provided on the insulating layer 4 using, for example, a direct bonding method, a brazing material bonding method, a molten metal bonding method, or a plating method. The first electrode pattern 1 faces the insulating layer 4. The first electrode pattern 1 is made of, for example, copper. The first electrode pattern 1 has a first surface 11 and a second surface 12.

[0019] The first surface 11 faces the insulating layer 4. On the first surface 11, the first electrode pattern 1 is in contact with, for example, the insulating layer 4. On the first surface 11, the first electrode pattern 1 may be bonded to the insulating layer 4 via a bonding material (not shown). The second surface 12 is on the opposite side of the first surface 11.

[0020] The second electrode pattern 2 is provided on the insulating layer 4. The second electrode pattern 2 faces a tenth surface 20 of the insulating layer 4. The second electrode pattern 2 is provided on the insulating layer 4 using, for example, a direct bonding method, a brazing bonding method, a molten metal bonding method, or a plating method. The second electrode pattern 2 is spaced apart from the first electrode pattern 1. The second electrode pattern 2 is made of, for example, copper. The second electrode pattern 2 has a fourth surface 14 and a fifth surface 15.

[0021] The fourth surface 14 faces the insulating layer 4. On the fourth surface 14, the second electrode pattern 2 is in contact with the insulating layer 4, for example. On the fourth surface 14, the second electrode pattern 2 may be bonded to the insulating layer 4 via a bonding material (not shown). The fifth surface 15 is on the opposite side of the fourth surface 14. Note that the cross section shown in FIG. 1 is a cross section perpendicular to the second surface 12. Specifically, the cross section shown in FIG. 1 is a cross section perpendicular to the second surface 12 and intersecting with each of the first electrode pattern 1 and the second electrode pattern 2.

[0022] The semiconductor element 9 is provided on the first electrode pattern 1. The semiconductor element 9 faces the second surface 12 of the first electrode pattern 1. The semiconductor element 9 and the first electrode pattern 1 are joined by a second bonding portion 52. From another perspective, the semiconductor element 9 and the first electrode pattern 1 are each in contact with the second bonding portion 52. The second surface 12 is spaced apart from the semiconductor element 9. The second bonding portion 52 is, for example, solder. The second bonding portion 52 may be made of, for example, silver or a silver alloy. The number of semiconductor elements 9 is, for example, two. The two semiconductor elements 9 are electrically connected to each other by wiring 8.

[0023] The semiconductor element 9 is a wide bandgap semiconductor made of, for example, silicon carbide (SiC), gallium nitride (GaN)-based material, diamond, or the like. A wide bandgap semiconductor is a semiconductor with a wider bandgap than silicon (Si). The semiconductor element 9 is, for example, a power semiconductor element whose operating temperature reaches 150°C or higher. Specifically, the semiconductor element 9 is, for example, a semiconductor element that controls a large current, such as a MOSFET. The semiconductor element 9 may also be a freewheeling diode.

[0024] The case 6 has an annular shape. The case 6 surrounds the insulating substrate 10. The case 6 is preferably made of a material that does not thermally deform within the operating temperature range of the semiconductor device 100. The case 6 is preferably made of a material that has insulating properties. Specifically, the case 6 is preferably made of a resin material with a high thermal softening point. More specifically, the case 6 is made of, for example, polyphenylene sulfide (PPS) resin.

[0025] The lid 70 separates the inside of the semiconductor device 100 from the outside of the semiconductor device 100. The lid 70 is a part that prevents dust and the like from entering the inside of the semiconductor device 100. The terminal 7 is located between the lid 70 and the case 6. The terminal 7 may be sandwiched between the case 6 and the lid 70. A part of the terminal 7 is exposed to the outside of the semiconductor device 100. The terminal 7 is made of, for example, copper.

[0026] The wiring 8 electrically connects the terminal 7 and the semiconductor element 9. The wiring 8 electrically connects the semiconductor element 9 and the second electrode pattern 2. The wiring 8 electrically connects the second electrode pattern 2 and the terminal 7. The wiring 8 has a linear shape. The cross section of the wiring 8 is, for example, circular. The wiring 8 is made of, for example, gold or aluminum.

[0027] The sealing member 60 covers the insulating substrate 10, the semiconductor element 9, and the wiring 8. The sealing member 60 insulates the insulating substrate 10, the semiconductor element 9, and the wiring 8. The sealing member 60 contacts the terminals 7, the case 6, and the base plate 5. The sealing member 60 is spaced apart from the lid 70. The sealing member 60 is made of a resin having a predetermined elastic modulus and heat resistance. Specifically, the sealing member 60 is made of, for example, epoxy resin. The sealing member 60 may also be made of a resin having insulating and adhesive properties. Specifically, the sealing member 60 may also be made of, for example, silicone resin.

[0028] 2 , the first electrode pattern 1 has a first main body portion 21 and a first step portion 31. The first step portion 31 protrudes from the first main body portion 21. Specifically, the first step portion 31 protrudes from the first main body portion 21 in a direction parallel to the first surface 11.

[0029] The first body portion 21 constitutes each of the first surface 11 and the second surface 12 of the first electrode pattern 1. The first body portion 21 has a first side surface 41. The first side surface 41 is continuous with the second surface 12. The first side surface 41 faces the second electrode pattern 2. The first side surface 41 is spaced apart from the second electrode pattern 2. In a cross section perpendicular to the second surface 12, the first side surface 41 is curved. In a cross section perpendicular to the second surface 12, the first side surface 41 may be arc-shaped. In a cross section perpendicular to the second surface 12, the first side surface 41 is recessed, for example, toward the inside of the first body portion 21.

[0030] The first step portion 31 has a third surface 13, a first step surface 25, and a first step side surface 43. The third surface 13 is continuous with the first surface 11 of the first main body portion 21. The third surface 13 constitutes a part of the bottom surface of the first electrode pattern 1. The third surface 13 faces the insulating layer 4. On the third surface 13, the first electrode pattern 1 is in contact with the insulating layer 4, for example. On the third surface 13, the first electrode pattern 1 may be bonded to the insulating layer 4 via a bonding material (not shown). The third surface 13 extends in the direction in which the first surface 11 extends.

[0031] The first step surface 25 is located on the opposite side of the third surface 13. The first step surface 25 is continuous with the first side surface 41. The first step surface 25 is, for example, planar. The first step surface 25 extends, for example, along a direction parallel to the first surface 11. In the direction perpendicular to the second surface 12, the first step surface 25 is located between the first surface 11 and the second surface 12.

[0032] The first step side surface 43 is continuous with each of the third surface 13 and the first step surface 25. The first step side surface 43 faces the second electrode pattern 2. The first step side surface 43 is spaced apart from the second electrode pattern 2. The first step side surface 43 is located further outward from the first electrode pattern 1 than the first side surface 41. In a cross section perpendicular to the second surface 12, the first step side surface 43 is, for example, curved. In a cross section perpendicular to the second surface 12, the first step side surface 43 may be arc-shaped. In a cross section perpendicular to the second surface 12, the first step side surface 43 is, for example, recessed inward of the first main body portion 21.

[0033] As shown in FIG. 2 , in a cross section perpendicular to the second surface 12, the boundary between the second surface 12 and the first side surface 41 is defined as a first boundary 91. In a cross section perpendicular to the second surface 12, the boundary between the first side surface 41 and the first step surface 25 is defined as a second boundary 92. In a cross section perpendicular to the second surface 12, a line segment connecting the first boundary 91 and the second boundary 92 is defined as a first line segment 71. The first line segment 71 may extend along a direction perpendicular to the second surface 12. The length of the first line segment 71 is defined as a first length D1. The length of the first side surface 41 in a cross section perpendicular to the second surface 12 is longer than the first length D1. Note that, in a cross section perpendicular to the second surface 12, the length of the first side surface 41 is the distance along the first side surface 41 from the first boundary 91 to the second boundary 92.

[0034] The second electrode pattern 2 has a second main body portion 22 and a second step portion 32. The second step portion 32 protrudes from the second main body portion 22. Specifically, the second step portion 32 protrudes from the second main body portion 22 in a direction parallel to the fourth surface 14. The cross sections shown in FIGS. 1 and 2 are perpendicular to the second surface 12 and intersect with each of the first step portion 31 and the second step portion 32.

[0035] The second body portion 22 constitutes each of the fourth surface 14 and the fifth surface 15 of the second electrode pattern 2. The second body portion 22 has a second side surface 42. The second side surface 42 is continuous with the fifth surface 15. The second side surface 42 faces the first side surface 41 of the first electrode pattern 1. The second side surface 42 is spaced apart from the first side surface 41. In a cross section perpendicular to the second surface 12, the second side surface 42 is curved. In a cross section perpendicular to the second surface 12, the second side surface 42 may be arc-shaped. In a cross section perpendicular to the second surface 12, the second side surface 42 is recessed, for example, toward the inside of the second body portion 22.

[0036] The second step portion 32 has a sixth surface 16, a second step surface 26, and a second step side surface 44. The sixth surface 16 is continuous with the fourth surface 14 of the second main body portion 22. The sixth surface 16 constitutes a part of the bottom surface of the second electrode pattern 2. The sixth surface 16 faces the insulating layer 4. At the sixth surface 16, the second electrode pattern 2 is in contact with the insulating layer 4, for example. At the sixth surface 16, the second electrode pattern 2 may be bonded to the insulating layer 4 via a bonding material (not shown). The sixth surface 16 extends in the direction in which the fourth surface 14 extends.

[0037] The second step surface 26 is located on the opposite side of the sixth surface 16. The second step surface 26 is continuous with the second side surface 42. The second step surface 26 is, for example, planar. The second step surface 26 extends, for example, along a direction parallel to the fourth surface 14. In the direction perpendicular to the second surface 12, the second step surface 26 is located between the fourth surface 14 and the fifth surface 15.

[0038] The second step side surface 44 is continuous with each of the sixth surface 16 and the second step surface 26. The second step side surface 44 faces the first step side surface 43 of the first electrode pattern 1. The second step side surface 44 is spaced apart from the first step side surface 43. The second step side surface 44 is located further outward from the second electrode pattern 2 than the second side surface 42. In a cross section perpendicular to the second surface 12, the second step side surface 44 is, for example, curved. In a cross section perpendicular to the second surface 12, the second step side surface 44 may be arc-shaped. In a cross section perpendicular to the second surface 12, the second step side surface 44 is, for example, recessed inward of the second main body portion 22.

[0039] As shown in FIG. 2 , in a cross section perpendicular to the second surface 12, the boundary between the fifth surface 15 and the second side surface 42 is defined as a third boundary 93. In a cross section perpendicular to the second surface 12, the boundary between the second side surface 42 and the second step surface 26 is defined as a fourth boundary 94. In a cross section perpendicular to the second surface 12, a line segment connecting the third boundary 93 and the fourth boundary 94 is defined as a fifth line segment 75. The fifth line segment 75 may extend along a direction perpendicular to the second surface 12. The length of the fifth line segment 75 is defined as a fifth length D5. The length of the second side surface 42 in a cross section perpendicular to the second surface 12 is longer than the fifth length D5. Note that, in a cross section perpendicular to the second surface 12, the length of the second side surface 42 is the distance along the second side surface 42 from the third boundary 93 to the fourth boundary 94.

[0040] 2 , in a cross section perpendicular to the second surface 12, the line segment connecting the first boundary 91 and the third boundary 93 is defined as a second line segment 72. The second line segment 72 extends, for example, in the direction in which the second surface 12 extends and in the direction from the first electrode pattern 1 to the second electrode pattern 2. The length of the second line segment 72 is defined as a second length D2.

[0041] In a cross section perpendicular to the second surface 12, the line segment connecting the second boundary 92 and the fourth boundary 94 is defined as a third line segment 73. The third line segment 73 extends, for example, in a direction parallel to the second surface 12 and in a direction from the first electrode pattern 1 to the second electrode pattern 2. The third line segment 73 may be substantially parallel to the second line segment 72. The length of the third line segment 73 is defined as a third length D3. The third length D3 may be substantially the same as the second length D2. The third length D3 may be longer than the second length D2.

[0042] In a cross section perpendicular to the second surface 12, the midpoint of the first side surface 41 is defined as a first midpoint 81. In a direction perpendicular to the second surface 12, the distance between the first boundary 91 and the first midpoint 81 is equal to the distance between the second boundary 92 and the first midpoint 81. In a cross section perpendicular to the second surface 12, the midpoint of the second side surface 42 is defined as a second midpoint 82. In a direction perpendicular to the second surface 12, the distance between the third boundary 93 and the second midpoint 82 is equal to the distance between the fourth boundary 94 and the second midpoint 82.

[0043] In a cross section perpendicular to the second surface 12, the line segment connecting the first intermediate point 81 and the second intermediate point 82 is defined as a fourth line segment 74. The fourth line segment 74 may be substantially parallel to the second line segment 72. In the direction perpendicular to the second surface 12, the fourth line segment 74 is located between the second line segment 72 and the third line segment 73. The length of the fourth line segment 74 is defined as a fourth length D4. The fourth length D4 is longer than both the second length D2 and the third length D3.

[0044] 2 , the thickness of the first electrode pattern 1 in a direction perpendicular to the second surface 12 is defined as a first thickness H1. The first thickness H1 is the distance between the first surface 11 and the second surface 12 in the direction perpendicular to the second surface 12. The first thickness H1 is, for example, not less than 0.3 mm and not more than 5 mm. The first thickness H1 may be, for example, not less than 0.5 mm.

[0045] The thickness of the second electrode pattern 2 in a direction perpendicular to the second surface 12 is defined as a second thickness H2. The second thickness H2 is the distance between the fourth surface 14 and the fifth surface 15 in a direction perpendicular to the second surface 12. The second thickness H2 is, for example, not less than 0.3 mm and not more than 5 mm. The second thickness H2 may be, for example, not less than 0.5 mm. The second thickness H2 may be substantially the same as the first thickness H1.

[0046] The thickness of the first step portion 31 in a direction perpendicular to the second surface 12 is defined as a third thickness H3. The third thickness H3 is the distance between the third surface 13 and the first step surface 25 in a direction perpendicular to the second surface 12. The third thickness H3 is, for example, 0.2 mm. The third thickness H3 is smaller than the first thickness H1. The third thickness H3 is, for example, 0.1 to 0.8 times the first thickness H1.

[0047] The thickness of the second step portion 32 in a direction perpendicular to the second surface 12 is defined as a fourth thickness H4. The fourth thickness H4 is the distance between the sixth surface 16 and the second step surface 26 in a direction perpendicular to the second surface 12. The fourth thickness H4 is, for example, 0.2 mm. The fourth thickness H4 is smaller than the second thickness H2. The fourth thickness H4 is, for example, not less than 0.1 times and not more than 0.8 times the second thickness H2. The fourth thickness H4 may be substantially the same as the third thickness H3.

[0048] The thickness of the insulating layer 4 in a direction perpendicular to the second surface 12 is defined as a fifth thickness H5. The fifth thickness H5 is the distance between the ninth surface 19 and the tenth surface 20 in a direction perpendicular to the second surface 12. The fifth thickness H5 is, for example, 0.2 mm. The first thickness H1 is, for example, four times or more the fifth thickness H5. The lower limit of the first thickness H1 is not particularly limited, but may be, for example, six times or more the fifth thickness H5, or eight times or more the fifth thickness H5. The upper limit of the first thickness H1 is not particularly limited, but may be, for example, 20 times or less the fifth thickness H5, or 10 times or less the fifth thickness H5.

[0049] The second thickness H2 is, for example, four times or more the fifth thickness H5. The lower limit of the second thickness H2 is not particularly limited, but may be, for example, six times or more the fifth thickness H5, or eight times or more the fifth thickness H5. The upper limit of the second thickness H2 is not particularly limited, but may be, for example, 20 times or less the fifth thickness H5, or 10 times or less the fifth thickness H5.

[0050] The third thickness H3 is, for example, at least half the fifth thickness H5. The lower limit of the third thickness H3 is not particularly limited, but may be, for example, at least the fifth thickness H5 or at least twice the fifth thickness H5. The upper limit of the third thickness H3 is not particularly limited, but may be, for example, at most five times the fifth thickness H5 or at most four times the fifth thickness H5.

[0051] The fourth thickness H4 is, for example, at least half the fifth thickness H5. The lower limit of the fourth thickness H4 is not particularly limited, but may be, for example, at least the fifth thickness H5 or at least twice the fifth thickness H5. The upper limit of the fourth thickness H4 is not particularly limited, but may be, for example, at most five times the fifth thickness H5 or at most four times the fifth thickness H5.

[0052] 3 to 5, a method for forming the first electrode pattern 1 and the second electrode pattern 2 of the semiconductor device 100 according to the first embodiment will be described. Note that, hereinafter, the first electrode pattern 1 and the second electrode pattern 2 will collectively be referred to simply as the electrode pattern.

[0053] 3 , a metal plate 90 is bonded onto the tenth surface 20 of the insulating layer 4 by, for example, a direct bonding method. The metal plate 90 has an eleventh surface 86 and a twelfth surface 87. The eleventh surface 86 is in contact with the insulating layer 4, for example. The twelfth surface 87 is on the opposite side of the eleventh surface 86.

[0054] Next, as shown in Fig. 4, the metal plate 90 is cut using, for example, milling and blasting. As a result, a wall surface 98 and a bottom surface 97 are formed in the metal plate 90. The wall surface 98 is continuous with the twelfth surface 87. The wall surface 98 extends in a direction perpendicular to the twelfth surface 87. The bottom surface 97 is continuous with the wall surface 98. The wall surface 98 and the bottom surface 97 form a groove 99.

[0055] 5 , an etching resist 96 is printed on the metal plate 90. The etching resist 96 is printed on a portion of the bottom surface 97 and on the twelfth surface 87. From another perspective, the twelfth surface 87 is covered with the etching resist 96. A portion of the bottom surface 97 is exposed from the etching resist 96. A portion of the wall surface 98 is exposed from the etching resist 96.

[0056] The metal plate 90 is subjected to etching. For example, a ferric chloride solution or the like is used as an etching solution. The bottom surface 97 and wall surfaces 98 of the metal plate 90 are each etched. A portion of the insulating layer 4 is exposed from the metal plate 90. In this manner, the first electrode pattern 1 and the second electrode pattern 2 (see FIGS. 1 and 2) are formed.

[0057] When forming the electrode patterns on the insulating substrate 10 using only etching, the time required to form the electrode patterns increases compared to when forming the electrode patterns using milling and etching. This increases the time required for etching, particularly when the thickness of the metal plate 90 is, for example, 0.5 mm or greater. Therefore, if the etching solution is not applied uniformly to the metal plate 90, the dimensional variation of the electrode patterns increases. According to the method for forming electrode patterns on the semiconductor device 100 of the first embodiment, the electrode patterns are formed using milling and etching. This reduces the dimensional variation of the electrode patterns.

[0058] Furthermore, when forming the electrode pattern of the insulating substrate 10 using only etching, the amount of the electrode pattern removed by etching increases as one approaches the top surface from the bottom surface of the electrode pattern. In other words, as one approaches the top surface from the bottom surface of the electrode pattern, the side surface of the electrode pattern approaches the inside of the electrode pattern. Therefore, the second length D2 is longer than when forming the electrode pattern using both milling and etching. In other words, the ratio of the top surface area to the bottom surface area of ​​the electrode pattern is reduced. According to the method for forming the electrode pattern of the semiconductor device 100 of the first embodiment, the ratio of the top surface area to the bottom surface area of ​​the electrode pattern can be increased. In other words, the ratio of the top surface area of ​​the electrode pattern to the area of ​​the tenth surface 20 of the insulating layer 4 can be increased. Therefore, the insulating substrate 10 can be miniaturized without changing the number of semiconductor elements 9 in the semiconductor device 100. As a result, the semiconductor device 100 can be miniaturized.

[0059] If the electrode patterns are formed using only milling, there is a risk that the insulating layer 4 may be damaged when processing the electrode patterns near the insulating layer 4. This may result in a decrease in the reliability of the insulating substrate 10. According to the method for forming the electrode patterns of the semiconductor device 100 of the first embodiment, the electrode patterns near the insulating layer 4 are processed using etching. This makes it possible to suppress a decrease in the reliability of the insulating substrate 10.

[0060] Next, the effects of the semiconductor device 100 according to the first embodiment will be described. When the semiconductor device 100 is subjected to a thermal cycle, there is a risk of peeling between the components of the semiconductor device 100 due to differences in the thermal expansion coefficients between the components. Specifically, there is a risk of the first electrode pattern 1 peeling from the insulating layer 4 due to differences in the thermal expansion coefficients between the first electrode pattern 1 and the insulating layer 4.

[0061] According to the semiconductor device 100 of the first embodiment, the first electrode pattern 1 has a first body portion 21 and a first step portion 31. The first step portion 31 protrudes from the first body portion 21. The first step portion 31 has a third surface 13. The third surface 13 faces the insulating layer 4. This increases the bonding area between the first electrode pattern 1 and the insulating layer 4. Furthermore, compared to increasing the bonding area between the first electrode pattern 1 and the insulating layer 4 by increasing the size of the first body portion 21, this reduces the increase in thermal stress between the first electrode pattern 1 and the insulating layer 4. This reduces peeling between the first electrode pattern 1 and the insulating layer 4.

[0062] Furthermore, due to a difference in the thermal expansion coefficient between the sealing member 60 and the insulating substrate 10, the sealing member 60 may peel off from the insulating substrate 10. According to the semiconductor device 100 of the first embodiment, the first body portion 21 of the first electrode pattern 1 has a first side surface 41. In a cross section perpendicular to the second surface 12, the first side surface 41 is curved. In a cross section perpendicular to the second surface 12, the length of the first side surface 41 is longer than the length of the line segment connecting the first boundary 91 and the second boundary 92. Therefore, the sealing member 60 is disposed along the first side surface 41. This provides an anchor effect to the sealing member 60. The anchor effect is, for example, an effect in which the sealing member 60 penetrates into the irregularities of the first side surface 41, thereby biting into the first side surface 41 and improving the bonding strength between the sealing member 60 and the first electrode pattern 1.

[0063] Therefore, compared to when the first side surface 41 of the first electrode pattern 1 is linear, peeling between the sealing member 60 and the insulating substrate 10 can be suppressed. As a result, the semiconductor device 100 according to the first embodiment can suppress peeling between the sealing member 60 and the insulating substrate 10 while suppressing peeling between the first electrode pattern 1 and the insulating layer 4. As a result, deterioration of the insulating performance of the semiconductor device 100 due to thermal cycles can be suppressed.

[0064] The semiconductor device 100 according to the first embodiment may include a second electrode pattern 2. In a cross section perpendicular to the second surface 12, the length of the line segment connecting the first midpoint 81 and the second midpoint 82 (fourth length D4) may be longer than the length of the line segment connecting the first boundary 91 and the third boundary 93 (second length D2) and the length of the line segment connecting the second boundary 92 and the fourth boundary 94 (third length D3). Therefore, the sealing member 60 is disposed so as to be embedded between the first side surface 41 and the second side surface 42. This enhances the anchoring effect between the sealing member 60 and the first side surface 41 and the second side surface 42. As a result, peeling of the sealing member 60 from the insulating substrate 10 can be suppressed.

[0065] The thickness of the electrode pattern may be increased to improve the thermal diffusion of the semiconductor device 100. As the thickness of the electrode pattern increases, thermal stress between the electrode pattern and the insulating layer 4 increases when a thermal cycle is applied. This increases the likelihood of peeling of the first electrode pattern 1. According to the semiconductor device 100 of the first embodiment, the thickness of the first electrode pattern 1 in the direction perpendicular to the second surface 12 may be four or more times the thickness of the insulating layer 4. According to the semiconductor device 100 of the first embodiment, even in an insulating substrate 10 having a thick first electrode pattern 1, peeling between the insulating layer 4 and the first electrode pattern 1 and peeling between the sealing member 60 and the insulating substrate 10 can be suppressed when a thermal cycle is applied. As a result, deterioration of the insulating performance of the semiconductor device 100 can be suppressed.

[0066] If the thickness of the step portion of the electrode pattern is excessively thin, the contribution of the step portion to the bonding strength between the electrode pattern and the insulating layer 4 decreases. This reduces the effect of suppressing peeling between the electrode pattern and the insulating layer 4. According to the semiconductor device 100 of the first embodiment, the thickness of the first step portion 31 may be half or more of the thickness of the insulating layer 4. This makes it possible to more reliably suppress peeling between the first electrode pattern 1 and the insulating layer 4.

[0067] If the thickness of the step portion of the electrode pattern is excessively thick, the amount of thermal expansion at the step portion increases excessively, which may cause peeling between the electrode pattern and the insulating layer 4. According to the semiconductor device 100 of the first embodiment, the thickness of the first step portion 31 may be five times or less the thickness of the insulating layer 4. This makes it possible to suppress peeling between the first electrode pattern 1 and the insulating layer 4.

[0068] Furthermore, if the ratio of the thickness of the step portion to the thickness of the electrode pattern is excessively large, the length of the side surface of the main body of the electrode pattern becomes excessively short, thereby reducing the anchor effect on the sealing member 60. This may cause peeling between the sealing member 60 and the insulating substrate 10. According to the semiconductor device 100 of the first embodiment, the thickness of the first step portion 31 may be 0.8 times or less the thickness of the first electrode pattern 1. This makes it possible to suppress peeling between the sealing member 60 and the insulating substrate 10.

[0069] (Modification of First Embodiment) Next, the configuration of a semiconductor device 100 according to a modification of the first embodiment will be described with reference to FIG. 6 . The cross-sectional view shown in FIG. 6 corresponds to the cross-sectional view shown in FIG. 2 . As shown in FIG. 6 , the second length D2 may be greater than the third length D3. In a cross section perpendicular to the second surface 12, the first boundary 91 may be located more inward of the first electrode pattern 1 than the second boundary 92. In a cross section perpendicular to the second surface 12, the third boundary 93 may be located more inward of the second electrode pattern 2 than the fourth boundary 94.

[0070] The second length D2 may be greater than the fourth length D4. In a cross section perpendicular to the second surface 12, the first boundary 91 may be located more inward of the first intermediate point 81 in the first electrode pattern 1. In a cross section perpendicular to the second surface 12, the third boundary 93 may be located more inward of the second intermediate point 82 in the second electrode pattern 2.

[0071] The above description deals with the case where the insulating layer 4 is made of ceramic. However, the configuration of the semiconductor device 100 is not limited to this. Specifically, the insulating layer 4 may be made of, for example, a cured resin with dispersed powder, and the powder may be made of ceramic, such as Al2O3, SiO2, AlN, BN, or Si3N4. The powder may be made of, for example, diamond, silicon carbide, or boron oxide (BO3), or may be made of a resin material, such as silicone resin or acrylic resin. The shape of the powder may be, for example, spherical. The shape of the powder may be crushed, granular, flaky, or aggregated. The powder filling amount may be any amount sufficient to provide the required heat dissipation and insulation properties. The insulating layer 4 may be made of a cured resin with a ceramic plate embedded therein.

[0072] The number of semiconductor elements 9 in the semiconductor device 100 is not limited to 2. The number of semiconductor elements 9 in the semiconductor device 100 may be any number required depending on the application of the semiconductor device 100.

[0073] The materials of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 are not particularly limited as long as they have the necessary heat dissipation characteristics. Specifically, the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 may each be made of, for example, an aluminum-iron composite material, aluminum, or iron. The first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 may each be made of a composite material such as copper / invar / copper clad material, or a composite material of aluminum and silicon carbide (AlSiC). The first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 may each be made of an alloy such as copper-molybdenum (CuMo).

[0074] The surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 are configured to supply the necessary current and voltage to the semiconductor element. Specifically, the surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 are each plated with nickel, for example. The surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 may also be plated with gold or tin. The surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7 may each have minute irregularities. This can improve the adhesion between the sealing member 60 and the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5, and the terminals 7.

[0075] The wiring 8 may be, for example, a strip-shaped copper plate. In other words, the cross section of the wiring 8 may be, for example, rectangular. The number of wirings 8 is, for example, four. The number of wirings 8 may be any number required depending on the current density of the semiconductor element 9, etc.

[0076] The joints between the wiring 8 and each of the semiconductor element 9, the second electrode pattern 2, and the terminals 7 are configured to be able to supply the necessary current and voltage to the semiconductor element 9. Specifically, for example, the semiconductor element 9, the second electrode pattern 2, and the terminals 7 may be joined to each of the wiring 8 using molten copper or tin, or may be joined using ultrasonic bonding.

[0077] Second Embodiment Next, the configuration of a semiconductor device 100 according to a second embodiment will be described with reference to FIG. 7. The configuration of the semiconductor device 100 according to the second embodiment differs from that of the semiconductor device 100 according to the first embodiment mainly in that the insulating layer 4 of the insulating substrate 10 is made of an organic material, but in other respects is substantially the same as that of the semiconductor device 100 according to the first embodiment. The following description will focus on the differences from the configuration of the semiconductor device 100 according to the first embodiment. The cross-sectional view shown in FIG. 7 corresponds to the cross-sectional view shown in FIG. 1.

[0078] 7 , the insulating layer 4 of the insulating substrate 10 may be bonded to the base plate 5. The ninth surface 19 of the insulating layer 4 is in contact with the eighth surface 18 of the base plate 5. The insulating layer 4 and the base plate 5 are bonded together using, for example, heat and pressure bonding (hot pressing). In other words, no bonding agent such as brazing material is used to bond the insulating layer 4 and the base plate 5. The area of ​​the ninth surface 19 of the insulating layer 4 may be substantially the same as the area of ​​the eighth surface 18 of the base plate 5.

[0079] The insulating layer 4 may be made of, for example, an organic material. Specifically, the insulating layer 4 may be made of, for example, an epoxy resin. The insulating layer 4 may be made of a thermosetting resin such as a polyimide resin, a silicone resin, or an acrylic resin. The insulating layer 4 may be made of, for example, an organic material in which ceramic powder is filled into an epoxy resin or the like.

[0080] Next, the effects of the semiconductor device 100 according to the second embodiment will be described. As the area of ​​the insulating layer 4 increases, the insulating layer 4 becomes more susceptible to warping of the semiconductor device 100 due to the load of thermal cycles. Therefore, if the area of ​​the insulating layer 4 is excessively large, cracks may occur in the insulating layer 4. In the semiconductor device according to the second embodiment, the insulating layer 4 is made of an organic material. Typically, organic materials are softer than ceramics. Therefore, even if the area of ​​the insulating layer 4 is excessively large, the occurrence of cracks in the insulating layer 4 can be suppressed.

[0081] When the insulating layer 4 is made of an organic material, it is more brittle and more susceptible to wear than when it is made of a ceramic material. Therefore, when processing an electrode pattern near the insulating layer 4 using a milling process or the like, the insulating layer 4 may be worn away. In the semiconductor device according to the present disclosure, an etching process is used to form the electrode pattern near the insulating layer 4. Therefore, wear of the insulating layer 4 can be suppressed. As a result, a decrease in the reliability of the semiconductor device 100 can be suppressed.

[0082] Third Embodiment Next, the configuration of a semiconductor device 100 according to a third embodiment will be described with reference to FIGS. 8 and 9. The configuration of the semiconductor device 100 according to the third embodiment differs from that of the semiconductor device 100 according to the second embodiment mainly in that the sealing member 60 has a first sealing portion 61 and a second sealing portion 62, but is otherwise substantially the same as that of the semiconductor device 100 according to the second embodiment. The following description will focus on the differences from the configuration of the semiconductor device 100 according to the second embodiment. The cross-sectional view shown in FIG. 8 corresponds to the cross-sectional view shown in FIG. 1.

[0083] 8 and 9 , the sealing member 60 has a first sealing portion 61 and a second sealing portion 62. The first sealing portion 61 is located between the first electrode pattern 1 and the second electrode pattern 2. The first sealing portion 61 is in contact with each of the insulating layer 4, the first step portion 31, the second step portion 32, the first main body portion 21, and the second main body portion 22.

[0084] The thickness of the first sealing portion 61 in a direction perpendicular to the second surface 12 is defined as a sixth thickness H6. The sixth thickness H6 is, for example, equal to or smaller than the first thickness H1. The first sealing portion 61 is made of, for example, an epoxy resin. The first sealing portion 61 may also be made of a thermosetting resin such as a silicone resin or a polyimide resin.

[0085] The second sealing portion 62 is located on the first sealing portion 61. The second sealing portion 62 is in contact with each of the insulating layer 4, the first sealing portion 61, the first step portion 31, the second step portion 32, the first main body portion 21, and the second main body portion 22. The second sealing portion 62 is made of, for example, a silicone resin. The second sealing portion 62 may also be made of a thermosetting resin such as an epoxy resin or a polyimide resin. The material making up the second sealing portion 62 may have higher adhesion than the material making up the first sealing portion 61.

[0086] The viscosity of the material constituting the first sealing portion 61 is lower than the viscosity of the material constituting the second sealing portion 62. Note that the viscosity of the material constituting the first sealing portion 61 is the viscosity of the material constituting the first sealing portion 61 in a liquid state. Similarly, the viscosity of the material constituting the second sealing portion 62 is the viscosity of the material constituting the second sealing portion 62 in a liquid state.

[0087] Although the above description has been given of a configuration in which the first sealing portion 61 is located between the first electrode pattern 1 and the second electrode pattern 2, the first sealing portion 61 may surround each of the first electrode pattern 1 and the second electrode pattern 2. From another perspective, the first sealing portion 61 may cover each of the first step portion 31 and the second step portion 32. The second sealing portion 62 may be spaced apart from each of the first step portion 31 and the second step portion 32. The second sealing portion 62 may be spaced apart from each of the first side surface 41 and the second side surface 42.

[0088] Next, the effects of the semiconductor device 100 according to the third embodiment will be described. If the electrode patterns are excessively thick, the sealing member 60 may not fill properly between the first electrode pattern 1 and the second electrode pattern 2, resulting in voids. This may result in a decrease in performance of the semiconductor device 100. According to the semiconductor device 100 according to the third embodiment, the sealing member 60 includes a first sealing portion 61 and a second sealing portion 62. The first sealing portion 61 contacts the insulating layer 4, the first step portion 31, and the second step portion 32. The viscosity of the material constituting the first sealing portion 61 is lower than the viscosity of the material constituting the second sealing portion 62. This allows the first sealing portion 61 to easily fill even the narrow spaces between the electrode patterns. This prevents voids from forming between the sealing member 60 and the insulating substrate 10. As a result, the insulation reliability of the semiconductor device 100 can be improved.

[0089] According to the semiconductor device 100 of the third embodiment, the first sealing portion 61 may be made of epoxy resin. The second sealing portion 62 may be made of silicone resin. Generally, epoxy resin has a lower moisture permeability than silicone resin. Therefore, moisture absorption by the insulating layer 4 can be suppressed. Furthermore, generally, silicone resin has a higher heat resistance than epoxy resin. Therefore, the heat resistance of the second sealing portion 62 can be improved. As a result, the heat resistance of the semiconductor device 100 can be improved.

[0090] When the insulating layer 4 is made of an organic material, it is more likely to absorb moisture than when the insulating layer 4 is made of ceramic. According to the semiconductor device 100 of the third embodiment, even when the insulating layer 4 is made of an organic material, it is possible to prevent the insulating layer 4 from absorbing moisture.

[0091] (Modification of Third Embodiment) Next, the configuration of a semiconductor device 100 according to a modification of the third embodiment will be described with reference to Fig. 10. The cross-sectional view shown in Fig. 10 corresponds to the cross-sectional view shown in Fig. 9.

[0092] 10 , the sixth thickness H6 may be, for example, equal to or less than the third thickness H3. The upper limit of the sixth thickness H6 is not particularly limited, but may be, for example, equal to or less than half the third thickness H3 or equal to or less than one-quarter of the third thickness H3. The lower limit of the sixth thickness H6 is not particularly limited, but may be, for example, equal to or more than one-tenth the third thickness H3 or equal to or more than one-eighth the third thickness H3.

[0093] The first sealing portion 61 contacts a portion of each of the first step side surface 43 and the second step side surface 44. The first sealing portion 61 is spaced apart from each of the first main body portion 21 and the second main body portion 22. The first sealing portion 61 is spaced apart from each of the first step surface 25 and the second step surface 26.

[0094] A portion of the second sealing portion 62 is located between the first electrode pattern 1 and the second electrode pattern 2. The second sealing portion 62 contacts each of the first side surface 41, the second side surface 42, the first step surface 25, and the second step surface 26. The second sealing portion 62 contacts each of a portion of the first step side surface 43 and the second step side surface 44.

[0095] Next, the effects of the semiconductor device 100 according to the modification of the third embodiment will be described. According to the semiconductor device 100 according to the modification of the third embodiment, the sixth thickness H6 may be, for example, equal to or less than the third thickness H3. Therefore, the second sealing portion 62 fills the spaces between the electrode patterns. This allows the first side surface 41 and the second side surface 42 to exert an anchoring effect on the second sealing portion 62. As a result, peeling between the second sealing portion 62 and the insulating substrate 10 due to thermal cycling can be suppressed.

[0096] (Sample Preparation) Next, a test using samples will be described. First, three semiconductor devices each corresponding to Sample 1 to Sample 10 were prepared. The semiconductor devices 100 corresponding to Sample 1 to Sample 5 are comparative examples. The semiconductor devices 100 corresponding to Sample 6 to Sample 10 are examples.

[0097] The semiconductor devices 100 according to Samples 1 to 10 correspond to the semiconductor device 100 according to the second embodiment. In the semiconductor devices 100 according to Samples 1 to 10, the size of the base plate 5 was 100 mm x 150 mm. The size of the semiconductor element 9 was 10 mm x 11 mm. The semiconductor element 9 and the insulating substrate 10 were joined using solder. The diameter of the wiring 8 was 0.4 mm or 0.2 mm. The material of the wiring 8 was aluminum. The base plate 5 and the case 6 were bonded using an adhesive.

[0098] The electrode patterns of the semiconductor devices 100 according to Samples 1 to 10 were fabricated according to the method for forming the electrode pattern of the semiconductor device 100 according to the first embodiment described above. The semiconductor devices 100 according to Samples 1 to 5 do not have the first step portion 31 or the second step portion 32. The semiconductor devices 100 according to Samples 6 to 10 have the first step portion 31 and the second step portion 32. The thickness of each of the first step portion 31 and the second step portion 32 of the semiconductor devices 100 according to Samples 6 to 10 was set to 0.2 mm.

[0099] The electrode thicknesses (first thickness H1 and second thickness H2) of the semiconductor devices according to Samples 1 and 6 were 0.3 mm. The electrode thicknesses of the semiconductor devices according to Samples 2 and 7 were 0.5 mm. The electrode thicknesses of the semiconductor devices according to Samples 3 and 8 were 0.8 mm. The electrode thicknesses of the semiconductor devices according to Samples 4 and 9 were 1 mm. The electrode thicknesses of the semiconductor devices according to Samples 5 and 10 were 2 mm.

[0100] (Experimental Method) A thermal cycle test was performed on the semiconductor devices 100 according to Samples 1 to 10. First, before the thermal cycle test, the dielectric strength of the semiconductor devices 100 was evaluated. In the dielectric strength test, a voltage of 4 kV root mean square was applied to the semiconductor devices 100. The number of semiconductor devices 100 that suffered dielectric breakdown among the three semiconductor devices 100 was counted.

[0101] Next, the semiconductor device 100 was placed in a temperature-controllable thermostatic chamber, and the temperature of the thermostatic chamber was repeatedly changed between -40°C and 180°C. One cycle consisted of holding the temperature of the thermostatic chamber at -40°C for 30 minutes and then holding it at 180°C for 30 minutes, and this cycle was repeated 1000 times. The dielectric strength voltage of the semiconductor device 100 was evaluated every 250 cycles.

[0102] (Experimental results)

[0103]

[0104] Table 1 shows the results of the dielectric strength evaluation of the semiconductor devices 100 according to Samples 1 to 10. In Table 1, A indicates that the number of semiconductor devices 100 that underwent dielectric breakdown was 0. B indicates that the number of semiconductor devices 100 that underwent dielectric breakdown was 1 or 2. C indicates that the number of semiconductor devices 100 that underwent dielectric breakdown was 3.

[0105] As shown in Table 1, in the semiconductor devices 100 according to Samples 2 to 5, dielectric breakdown was confirmed in the dielectric strength voltage evaluation after 1000 cycles. In other words, in the semiconductor device 100 of the comparative example, when the electrode thickness was 0.5 mm or more, the insulation performance deteriorated due to the thermal cycle test.

[0106] As shown in Table 1, in the semiconductor devices 100 according to Samples 6 to 9, no semiconductor devices 100 were found to have undergone dielectric breakdown in the dielectric strength evaluation after 1000 cycles. In other words, in the semiconductor devices 100 according to the example, when the electrode thickness was 1 mm or less, the insulation performance was not deteriorated by the thermal cycle test.

[0107] As shown in Table 1, in the semiconductor devices 100 according to Sample 5, all of the semiconductor devices 100 underwent dielectric breakdown in the dielectric strength voltage evaluation after 1000 cycles. On the other hand, in the semiconductor devices 100 according to Sample 10, only one semiconductor device 100 underwent dielectric breakdown in the dielectric strength voltage evaluation after 1000 cycles.

[0108] From the above results, it was confirmed that, compared to the semiconductor device 100 of the comparative example, the semiconductor device 100 of the example can suppress deterioration of the insulating performance of the semiconductor device 100 when subjected to a thermal cycle.

[0109] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0110] 1 First electrode pattern, 2 Second electrode pattern, 3 Third electrode pattern, 4 Insulating layer, 5 Base plate, 6 Case, 7 Terminal, 8 Wiring, 9 Semiconductor element, 10 Insulating substrate, 11 First surface, 12 Second surface, 13 Third surface, 14 Fourth surface, 15 Fifth surface, 16 Sixth surface, 17 Seventh surface, 18 Eighth surface, 19 Ninth surface, 20 Tenth surface, 21 First main body portion, 22 Second main body portion, 25 First step surface, 26 Second step surface, 31 First step portion, 32 Second step portion, 41 First side surface, 42 Second side surface, 43 First step side surface, 44 Second step side surface, 51 First bonding portion, 52 Second bonding portion, 60 Sealing member, 61 First sealing portion, 62 Second sealing portion, 70 Lid, 71 First line segment, 72 Second line segment, 73 Third line segment, 74 Fourth line segment, 75 Fifth line segment, 81 First intermediate point, 82 Second intermediate point, 86 Eleventh surface, 87 Twelfth surface, 90 Metal plate, 91 First boundary, 92 Second boundary, 93 Third boundary, 94 Fourth boundary, 96 Etching resist, 97 Bottom surface, 98 Wall surface, 99 Groove, 100 Semiconductor device, D1 First length, D2 Second length, D3 Third length, D4 Fourth length, D5 Fifth length, H1 First thickness, H2 Second thickness, H3 Third thickness, H4 Fourth thickness, H5 Fifth thickness, H6 Sixth thickness.

Claims

1. An insulating substrate having an insulating layer and a first electrode pattern provided on the insulating layer; a semiconductor element provided on the first electrode pattern; a case surrounding the insulating substrate; and a sealing member covering each of the insulating substrate and the semiconductor element, wherein the first electrode pattern has a first main body portion and a first step portion protruding from the first main body portion, the first main body portion having a first surface facing the insulating layer, a second surface opposite the first surface and facing the semiconductor element, and a first side surface continuing to the second surface, the first step portion having a third surface continuing to the first surface and facing the insulating layer, and a first step surface opposite the third surface and continuing to the first side surface, wherein in a cross section perpendicular to the second surface, the first side surface is curved, and in a cross section perpendicular to the second surface, a boundary between the second surface and the first side surface is defined as a first boundary, and a boundary between the first side surface and the first step surface is defined as a second boundary, A semiconductor device, wherein, when a length of a line segment connecting the first boundary and the second boundary is defined as a first length, a length of the first side surface in a cross section perpendicular to the second surface is longer than the first length.

2. The insulating substrate further has a second electrode pattern provided on the insulating layer and spaced apart from the first electrode pattern, the second electrode pattern having a second main body portion and a second step portion protruding from the second main body portion, the second main body portion having a fourth surface facing the insulating layer, a fifth surface opposite the fourth surface, and a second side surface continuing to the fifth surface and facing the first side surface, the second step portion having a sixth surface continuing to the fourth surface and facing the insulating layer, and a second step surface opposite the sixth surface and continuing to the second side surface, in a cross section perpendicular to the second surface, a boundary between the fifth surface and the second side surface is defined as a third boundary, a boundary between the second side surface and the second step surface is defined as a fourth boundary, a length of a line segment connecting the first boundary and the third boundary is defined as a second length, and a length of a line segment connecting the second boundary and the fourth boundary is defined as a third length, 2. The semiconductor device according to claim 1, wherein, when the length of a line segment connecting the midpoint of the first side surface and the midpoint of the second side surface is defined as a fourth length, the fourth length is longer than each of the second length and the third length.

3. The semiconductor device according to claim 2, wherein the sealing member has a first sealing portion in contact with each of the insulating layer, the first step portion and the second step portion, and a second sealing portion on the first sealing portion.

4. The semiconductor device according to claim 3, wherein the thickness of said first sealing portion in a direction perpendicular to said second surface is equal to or less than the thickness of said first step portion.

5. The semiconductor device according to claim 3 or 4, wherein the viscosity of the material constituting the first sealing portion is lower than the viscosity of the material constituting the second sealing portion.

6. The semiconductor device according to claim 3 or 4, wherein the first sealing portion is made of epoxy resin, and the second sealing portion is made of silicone resin.

7. The semiconductor device according to any one of claims 1 to 6, wherein the insulating layer is made of an organic material.

8. The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the first electrode pattern in a direction perpendicular to the second surface is four times or more the thickness of the insulating layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein the thickness of the first step portion in a direction perpendicular to the second surface is at least half the thickness of the insulating layer.

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