Display substrate and method for producing the same, as well as display device

Abstract

Embodiments of the present disclosure provide a display substrate and a method for producing the same, as well as a display device. The display substrate comprises: a base substrate; a metal layer located on the base substrate, the metal layer comprising a copper layer of a first thickness; an antioxidant layer located on a side of the metal layer facing away from the base substrate, the antioxidant layer having a second thickness; and a light-emitting diode located on a side of the antioxidant layer facing away from the base substrate, the light-emitting diode comprising at least one electrode, the at least one electrode of the light-emitting diode being electrically connected to the metal layer, the first thickness of the metal layer being greater than the second thickness of the antioxidant layer.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Light emitting diode (LED) technology has been developed for nearly three decades, and its application scope has been continuously expanding. For example, it can be applied to the display field and used as a backlight source for display devices or as an LED display screen. With the development of technology, sub-millimeter light emitting diode (Mini LED) display technology and micro LED (Micro LED) display technology have gradually become a hot topic in display devices. LED has the advantages of self-luminescence, wide viewing angle, fast response, simple structure, and long life. Moreover, Mini LED / Micro LED display screens can achieve large-size display by splicing, so they have good market prospects. At present, the structure of Mini LED / Micro LED display devices and their manufacturing process are one of the important topics of concern to researchers and developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.

[0006] In one aspect, a display substrate is provided, comprising: a base substrate; a metal layer located on the base substrate, the metal layer comprising a copper layer having a first thickness; an anti-oxidation layer located on a side of the metal layer away from the base substrate, the anti-oxidation layer having a second thickness; a light-emitting diode located on a side of the anti-oxidation layer away from the base substrate, the light-emitting diode comprising at least one electrode, the at least one electrode of the light-emitting diode being electrically connected to the metal layer, wherein the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.

[0007] According to some exemplary embodiments, the anti-oxidation layer includes a nickel-containing alloy.

[0008] According to some exemplary embodiments, the base substrate includes a display area and a marking area, and the display substrate includes: a first accompanying plating area located in the marking area; and a second accompanying plating area located in the display area; the first accompanying plating area and the second accompanying plating area both include a copper layer; and the area ratio of the first accompanying plating area to the marking area is greater than the area ratio of the second accompanying plating area to the display area.

[0009] According to some exemplary embodiments, the display substrate further includes: a mark located in the mark area; and a clearance area located in the mark area, wherein the first accompanying plating area surrounds the mark, and the clearance area is located between the mark and the first accompanying plating area and surrounds the mark.

[0010] According to some exemplary embodiments, an orthographic projection of the first accompanying plating area on the base substrate is a ring-shaped area surrounding the mark.

[0011] According to some exemplary embodiments, the anti-oxidation layer surrounds the metal layer, and at least one electrode of the light emitting diode is electrically connected to the metal layer through the anti-oxidation layer.

[0012] According to some exemplary embodiments, the display substrate further includes: a passivation layer located away from the base substrate and away from the anti-oxidation layer; and a first via hole located in the passivation layer; the first via hole exposes at least a portion of the anti-oxidation layer, and at least one electrode of the light-emitting diode is electrically connected to the metal layer through the first via hole.

[0013] According to some exemplary embodiments, the anti-oxidation layer surrounds the metal layer.

[0014] According to some exemplary embodiments, the display substrate further includes: a passivation layer located away from the base substrate at the anti-oxidation layer; and a third via located in the passivation layer; the third via is located at a pad position of the display area, the third via exposes at least a portion of the metal layer, and at least one electrode of the light-emitting diode is electrically connected to the metal layer through the third via.

[0015] According to some exemplary embodiments, the display substrate further includes: a fourth via hole located in the passivation layer; the fourth via hole is located at a binding position, the fourth via hole exposes at least a portion of the anti-oxidation layer, and at least one electrode of the light-emitting diode is electrically connected to the metal layer through the exposed portion of the anti-oxidation layer.

[0016] According to some exemplary embodiments, the anti-oxidation layer includes an opening portion, the opening portion exposing at least a portion of the metal layer, and an orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the opening portion on the base substrate.

[0017] In another aspect, a method for preparing a display substrate is provided, comprising:

[0018] depositing a copper seed layer on the substrate;

[0019] forming a photoresist layer on a side of the copper seed layer away from the substrate;

[0020] patterning the photoresist layer through a patterning process to form a photoresist pattern;

[0021] forming a copper layer on the portion of the copper seed layer not covered by the photoresist pattern by an electroplating process;

[0022] removing the photoresist pattern and a portion of the copper seed layer not covered by the metal layer to form a metal layer including copper;

[0023] forming an anti-oxidation layer on a side of the metal layer away from the substrate;

[0024] A light emitting diode is mounted on a side of the anti-oxidation layer away from the substrate, wherein the light emitting diode includes at least one electrode, and the at least one electrode of the light emitting diode is electrically connected to the metal layer.

[0025] Wherein, the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.

[0026] According to some exemplary embodiments, the base substrate includes a display area and a marking area.

[0027] The forming of a copper layer on a portion of the copper seed layer not covered by the photoresist pattern by an electroplating process comprises:

[0028] In the marking area, a first accompanying plating area is formed;

[0029] forming a second accompanying plating area in the display area;

[0030] Wherein, the first accompanying plating area and the second accompanying plating area respectively include a portion of the copper layer;

[0031] An area ratio of the first accompanying plating area to the marking area is greater than an area ratio of the second accompanying plating area to the display area.

[0032] According to some exemplary embodiments, the method further includes: forming a mark in a region surrounded by the first accompanying plating region by an electroplating process.

[0033] According to some exemplary embodiments, forming an anti-oxidation layer on a side of the metal layer away from the substrate includes:

[0034] forming a passivation layer on a side of the metal layer away from the substrate;

[0035] forming a first via hole in the passivation layer, the first via hole exposing at least a portion of the metal layer;

[0036] forming the anti-oxidation layer in the first via hole,

[0037] Wherein, the anti-oxidation layer includes an organic solder protection film.

[0038] According to some exemplary embodiments, forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes: forming a nickel-containing alloy layer surrounding the metal layer on a side of the metal layer away from the base substrate.

[0039] According to some exemplary embodiments, forming an anti-oxidation layer on a side of the metal layer away from the substrate includes:

[0040] forming a nickel-containing alloy layer surrounding the metal layer on a side of the metal layer away from the base substrate;

[0041] forming a passivation layer on a side of the nickel-containing alloy layer away from the substrate;

[0042] A second via hole is formed in the passivation layer, the second via hole exposing at least a portion of the nickel-containing alloy layer.

[0043] According to some exemplary embodiments, forming an anti-oxidation layer on a side of the metal layer away from the substrate includes:

[0044] forming a nickel-containing alloy layer surrounding the metal layer on a side of the metal layer away from the base substrate;

[0045] An opening is formed in the nickel-containing alloy layer at a pad position in the display area, wherein the opening exposes at least a portion of the metal layer.

[0046] forming a passivation layer on a side of the nickel-containing alloy layer away from the substrate;

[0047] A third via hole is formed in the passivation layer at a pad position in the display area, wherein the third via hole exposes at least a portion of the metal layer.

[0048] The orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the opening on the base substrate.

[0049] According to some exemplary embodiments, forming an anti-oxidation layer on a side of the metal layer away from the substrate further comprises: forming a fourth via hole in the passivation layer at a binding position, the fourth via hole exposing at least a portion of the nickel-containing alloy layer.

[0050] In yet another aspect, a display device is provided, comprising the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0052] FIG1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure. It should be noted that, for the sake of illustration, FIG1 shows the display substrate and another substrate bound thereto in an unfolded state.

[0053] FIG. 2 is a cross-sectional view of a display substrate taken along line AA′ in FIG. 1 according to some exemplary embodiments of the present disclosure.

[0054] FIG3 is a flow chart of a method for forming a copper layer using a subtractive method in the related art.

[0055] FIG. 4 is a flowchart of a method of preparing a display substrate according to some exemplary embodiments of the present disclosure.

[0056] FIG5A is a partial schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a display area and a marking area.

[0057] FIG. 5B is a partially enlarged view of the marked area shown in FIG. 5A .

[0058] FIG. 5C is a partially enlarged view of the display area shown in FIG. 5A .

[0059] FIG. 6A is a schematic diagram of a mark formed by a method for preparing a display substrate according to some exemplary embodiments of the present disclosure.

[0060] FIG. 6B is a schematic diagram of a mark formed by a method for preparing a display substrate in the related art.

[0061] FIG. 7 is a partial cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a positional relationship between a metal layer and an anti-oxidation layer.

[0062] 8A and 8B are electron microscope images of regions I and II in FIG. 7 , respectively.

[0063] FIG9A is a partial cross-sectional view of a display substrate according to some other exemplary embodiments of the present disclosure, schematically illustrating the positional relationship between a metal layer and an anti-oxidation layer.

[0064] FIG9B is an electron microscope image of region III in FIG9A .

[0065] 10A and 10B are respectively a partial cross-sectional view and a partial plan view of a display substrate according to further exemplary embodiments of the present disclosure, which schematically illustrate the positional relationship between a metal layer and an anti-oxidation layer.

[0066] FIG. 11 is a partial cross-sectional view of a display substrate according to some other exemplary embodiments of the present disclosure, schematically illustrating the positional relationship between a metal layer and an anti-oxidation layer.

[0067] 12A and 12B are partial cross-sectional views of a display substrate at a first position and a second position according to other exemplary embodiments of the present disclosure, respectively, which schematically illustrate the positional relationship between a metal layer and an anti-oxidation layer.

[0068] FIG. 13 is a schematic diagram showing the arrangement of light-emitting units of the display substrate shown in FIG. 1 .

[0069] FIG. 14 is a schematic diagram of a light-emitting unit in the display substrate shown in FIG. 13 .

[0070] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0071] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0072] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0073] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0074] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0075] In this article, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED represents an inorganic light-emitting element that is different from OLED. Specifically, inorganic light-emitting elements may include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, abbreviated as Mini LED in English) and micro light-emitting diodes (Micro LED in English). Among them, micro light-emitting diodes (i.e., Micro LEDs) refer to ultra-small light-emitting diodes with a grain size of less than 100 microns, and sub-millimeter light-emitting diodes (i.e., Mini LEDs) refer to small light-emitting diodes with a grain size between Micro LEDs and traditional LEDs. For example, the grain size of Mini LEDs can be between 100 and 300 microns, and the grain size of Micro LEDs can be between 10 and 100 microns.

[0076] Wire bonding is a process that uses heat, pressure, or ultrasonic energy to tightly weld metal bonding wires to substrate pads. For example, in IC packaging, wire bonding can be used to connect semiconductor chip pads to I / O bonding wires on a microelectronic package or metal wiring pads on a substrate using thin metal filaments. Wire bonding works by using heat, pressure, or ultrasonic waves to break down oxide layers and contamination on the surface being bonded, causing plastic deformation. This allows the metal bonding wire to come into close contact with the surface being bonded, achieving the range of attraction between atoms and leading to atomic diffusion across the interface, forming a weld.

[0077] OSP stands for Organic Solderability Preservatives, also known as copper protectant. OSP chemically grows an organic film on the clean, bare copper surface. This film is resistant to oxidation, heat shock, and moisture, protecting the copper surface from further rust (oxidation or sulfide) in normal environments. During subsequent high soldering temperatures, this protective film can be easily removed by flux, allowing the exposed copper surface to quickly bond with molten solder, forming a strong solder joint.

[0078] Some exemplary embodiments of the present disclosure provide a display substrate, a method for preparing the same, and a display device comprising the display substrate. For example, some embodiments of the present disclosure provide a display substrate comprising: a base substrate; a metal layer located on the base substrate, the metal layer comprising a copper layer having a first thickness; an anti-oxidation layer located on a side of the metal layer away from the base substrate, the anti-oxidation layer having a second thickness; a light-emitting diode located on a side of the anti-oxidation layer away from the base substrate, the light-emitting diode comprising at least one electrode, the at least one electrode of the light-emitting diode being electrically connected to the metal layer, wherein the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer. In the embodiments of the present disclosure, a display substrate having a thick copper layer can be realized, and the copper layer can be prevented from being oxidized by the film design of the anti-oxidation layer.

[0079] Figure 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure. It should be noted that, for illustrative purposes, Figure 1 shows the display substrate and another substrate bound thereto in an unfolded state. Figure 2 is a cross-sectional view of the display substrate according to some exemplary embodiments of the present disclosure taken along line AA' in Figure 1.

[0080] 1 and 2 , a display substrate 100 may include a base substrate 1, and a plurality of first electrodes 2 and a plurality of first conductive pads 3 disposed on the base substrate 1. The plurality of first conductive pads 3 are located at the edge of the display substrate 100. For example, the plurality of first conductive pads 3 are located in a fan-out region (i.e., a fan-out region) of the display substrate 100 and are used to electrically connect signal lines (e.g., a portion of the signal lines 150 schematically shown in FIG. 1 ) located on the display substrate 100 to an external driving circuit.

[0081] For example, the material of the substrate 1 may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, etc. The first electrode 2 and the first conductive pad 3 may have a columnar structure. The material of the first electrode 2 and the first conductive pad 3 may include a conductive material, such as a metal material, etc. Specifically, it may be at least one or a combination of at least two selected from gold, silver, copper, aluminum, molybdenum, gold alloys, silver alloys, copper alloys, aluminum alloys, molybdenum alloys, etc., and the embodiments of the present disclosure are not limited to this.

[0082] For example, the display substrate 100 may further include a driving circuit 4 electrically connected to the plurality of first electrodes 2, and the driving circuit 4 is disposed on the base substrate 1. The driving circuit 4 can be used to provide electrical signals to the light-emitting diode chips 5 located on the plurality of first electrodes 2 to control their luminous brightness. For example, in some examples, the driving circuit 4 can be a plurality of pixel driving circuits connected one-to-one with each light-emitting diode chip, or a plurality of micro-integrated circuit chips connected one-to-one with each light-emitting diode chip, etc., which can control each light-emitting diode chip to emit different brightness grayscales. It should be noted that the specific circuit structure of the driving circuit 4 on the display substrate 100 can be set according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0083] In a specific preparation method, a plurality of light-emitting diodes 5 can be transferred and bonded onto the display substrate 100 .

[0084] 1 and 2 , the light emitting diode 5 includes an N electrode 5N and a P electrode 5P. The N electrode and the P electrode of the light emitting diode 5 are respectively connected to the corresponding first electrodes 2 , while the surfaces of the plurality of first conductive pads 3 are exposed.

[0085] Referring to Figure 1 , a plurality of light-emitting diodes are arranged in an array along a first direction X and a second direction Y. For example, the first direction X is the row direction, and the second direction Y is the column direction. Of course, the embodiments of the present disclosure are not limited to this. The first direction and the second direction can be any direction, as long as the first direction and the second direction intersect. Furthermore, the plurality of light-emitting diodes are not limited to being arranged along a straight line; they can also be arranged along a curve, in a ring, or in any other manner. This can be determined according to actual needs and is not limited in the embodiments of the present disclosure.

[0086] The plurality of first conductive pads 3 are arranged at the edge of the display substrate 100 along the first direction X, that is, the plurality of first conductive pads 3 form a first conductive pad row. For example, the plurality of first conductive pads 3 are arranged along the first direction X at equal intervals.

[0087] For example, the light emitting diode may include a micro light emitting diode (Micro-LED) or a sub-millimeter light emitting diode (Mini-LED).

[0088] For example, the second substrate 200 may be a circuit board, such as a PCB (Printed Circuit Board), an FPC (Flexible Printed Circuit), or a COF (Chip On Film).

[0089] The second substrate 200 may include a plurality of second conductive pads 7. For example, the plurality of second conductive pads 7 may be arranged along the first direction X, i.e., the plurality of second conductive pads 7 may constitute a second conductive pad row. For example, the plurality of second conductive pads 7 may correspond one-to-one with the plurality of first conductive pads 3. That is, the arrangement period of the second conductive pads 7 is the same as the arrangement period of the first conductive pads 3.

[0090] For example, a bonding wire 9 electrically connects the first conductive pad 3 and the second conductive pad 7. One end of the bonding wire 9 is connected to the first conductive pad 3, and the other end is connected to the second conductive pad 7. That is, one end of the bonding wire 9 is welded to the first conductive pad 3, and the other end is welded to the second conductive pad 7. The weld point welded to the first conductive pad 3 is referred to as a first weld point 911, and the weld point welded to the second conductive pad 7 is referred to as a second weld point 921. For example, the bonding wire 9 can be made of a metal such as Cu, Al, Au, Ag, or an alloy thereof.

[0091] Of course, the second substrate 200 may further include an external driving circuit, such as an integrated circuit chip, but the embodiments of the present disclosure are not limited thereto.

[0092] The display substrate 100 may be a backplane for a light emitting diode display panel, including but not limited to the following backplanes: a passive drive backplane, an active drive backplane including thin film transistors, or an active drive backplane driven by a micro IC.

[0093] Below, the display substrate 100 will be described using a specific example. However, the following specific example should not be regarded as limiting the embodiments of the present disclosure. The backplane according to the embodiments of the present disclosure may include driving backplanes of various types and structures known in the art.

[0094] FIG13 is a schematic diagram of the arrangement of light-emitting units of the display substrate shown in FIG1 , and FIG14 is a schematic diagram of a light-emitting unit in the display substrate shown in FIG13 . As shown in FIG1 , FIG13 , and FIG14 , the display substrate 100 may include a base substrate 1 and a plurality of light-emitting units 140 arrayed on the base substrate 1 . For example, the plurality of light-emitting units 140 are arranged in N rows and M columns, where N is an integer greater than 0 and M is an integer greater than 0. For example, the number of light-emitting units 140 can be determined based on actual needs, such as the size of the display substrate and the required brightness. Although FIG13 only shows three rows and five columns of light-emitting units 140, it should be understood that the number of light-emitting units 140 is not limited thereto.

[0095] For example, the light emitting units 140 in each row are arranged along the first direction X, and the light emitting units 140 in each column are arranged along the second direction Y.

[0096] Each light emitting unit 140 includes a driving circuit 4 , a plurality of light emitting diodes 5 and a driving voltage terminal Vled.

[0097] The driver circuit 4 includes a first input terminal Di, a second input terminal Pwr, an output terminal OT, and a common voltage terminal GND. The first input terminal Di receives a first input signal, such as an address signal, for selecting the driver circuit 4 with the corresponding address. For example, the addresses of different driver circuits 4 can be the same or different. The first input signal can be an 8-bit address signal, and the address to be transmitted can be obtained by parsing the address signal. The second input terminal Pwr receives a second input signal, such as a power line carrier communication signal. For example, the second input signal not only provides power to the driver circuit 4 but also transmits communication data to the driver circuit 4. This communication data can be used to control the lighting duration of the corresponding light-emitting unit 140, thereby controlling its visual brightness. The output terminal OT can output different signals in different time periods, such as a relay signal and a drive signal. For example, the relay signal is an address signal provided to other driver circuits 4. That is, the first input terminal Di of the other driver circuit 4 receives the relay signal as the first input signal to obtain the address signal. For example, the drive signal can be a drive current used to drive the light-emitting diode 5 to emit light. The common voltage terminal GND receives a common voltage signal, such as a ground signal.

[0098] The driver circuit 4 is configured to output a relay signal via the output terminal OT during a first time period based on a first input signal received at the first input terminal Di and a second input signal received at the second input terminal Pwr, and to provide a drive signal to a plurality of light-emitting diodes 5 connected in series via the output terminal OT during a second time period. During the first time period, the output terminal OT outputs a relay signal, which is provided to other driver circuits 4 so that they receive address signals. During the second time period, the output terminal OT outputs a drive signal, which is provided to the plurality of light-emitting diodes 5 connected in series, causing the light-emitting diodes 5 to emit light during the second time period. For example, the first and second time periods may be different time periods, and the first time period may precede the second time period. The first time period may be continuous with the second time period, with the end of the first time period coinciding with the start of the second time period. Alternatively, there may be another time period between the first and second time periods, which may be used to implement other desired functions or may simply be used to separate the first and second time periods to prevent interference between the signals at the output terminal OT during the first and second time periods.

[0099] For example, as shown in Figure 14, a plurality of light-emitting diodes 5 are connected in series in sequence and are connected in series between the driving voltage terminal Vled and the output terminal OT. For example, each light-emitting diode 5 includes a positive electrode (+) and a negative electrode (-) (or, it can be called an anode and a cathode, or, it can also be called a P electrode and an N electrode), and the positive electrodes and negative electrodes of the plurality of light-emitting diodes 5 are connected in series end to end in sequence, thereby forming a current path between the driving voltage terminal Vled and the output terminal OT. The driving voltage terminal Vled provides a driving voltage, for example, a high voltage during the period (second period) when the light-emitting diode 5 needs to emit light, and a low voltage during other periods. Thus, during the second period, the driving signal (such as the driving current) flows from the driving voltage terminal Vled through the plurality of light-emitting diodes 5 in sequence, and then flows into the output terminal OT of the driving circuit 4. The plurality of light-emitting diodes 5 emit light when the driving current flows through them. By controlling the duration of the driving current, the light-emitting duration of the light-emitting diodes 5 can be controlled, thereby controlling the visual brightness of the light.

[0100] It should be noted that in the embodiments of the present disclosure, the number of light-emitting diodes 5 in each light-emitting unit 140 is not limited and can be any number such as 4, 5, 7, 8, and is not limited to 6. The multiple light-emitting diodes 5 can be arranged in any manner, for example, according to a desired pattern, and are not limited to a matrix arrangement. The location of the drive circuit 4 is not limited and can be set in any gap between the light-emitting diodes 5. This can be determined according to actual needs and is not limited in the embodiments of the present disclosure.

[0101] For example, referring back to FIG. 1 , the driving circuit 4 in each light-emitting unit 140 may be connected to the first conductive pad 3 located in the fan-out region through the signal line 150 , and then connected to the external driving circuit through the bonding wire 9 and the second conductive pad 7 .

[0102] In an embodiment of the present disclosure, the driving circuit 4 may include a metal layer, for example, a conductive trace may be formed in the metal layer. Since the current load of the display substrate is large, which can reach tens of milliamperes, the resistance performance of the trace is high, and a metal with low resistance needs to be used, otherwise the trace will generate a lot of heat and cause the temperature to be too high; and copper has excellent conductivity, so copper is used as the main body of the conductive trace. Of course, the conductive trace is not limited to copper, and other metals such as silver and aluminum can also be used. As shown in Figure 2, the conductive trace includes a copper layer 32. The thickness of the copper layer 32 can be adjusted according to the size of the current load. The greater the current load, the thicker the copper layer 32. The thickness of the copper layer 32 can be 1 to 30 microns. In some embodiments, it can be 2 to 6 microns, 2 microns, 4 microns, 5 microns, 6 microns, etc. The copper layer 32 can be completed by electroplating.

[0103] In the related art, a subtractive method is usually used to form the copper layer 32. Figure 3 is a flow chart of a method for forming a copper layer using a subtractive method in the related art. In this method, a buffer layer is first formed on the base substrate. For example, the buffer layer may include one or more insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. The stress direction of the formed copper layer is opposite to that of the formed copper layer, so that the stress generated when the copper layer is formed can be offset and the base substrate can be prevented from breaking. Then, the copper layer is formed using a subtractive method. The so-called subtractive process is a method of selectively removing part of the copper foil on the surface of a copper-clad laminate to obtain a conductive pattern. For example, a thick copper layer can be formed on the buffer layer, and then a patterning process is used to selectively remove part of the copper to form a wiring pattern. Next, the copper layer is treated by a gold plating process to form a protective layer. The so-called gold plating process refers to a solderable surface coating process in which nickel is electrolessly plated on a bare copper surface and then gold is electrolessly immersed.

[0104] FIG4 is a flow chart of a method for preparing a display substrate according to some exemplary embodiments of the present disclosure. The method may form a metal layer through an additive process, and the method may include steps S410 to S470. It should be noted that some steps of the preparation method described below may be performed individually or in combination, and may be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figure.

[0105] In step S410 , a copper seed layer is deposited on a base substrate.

[0106] In step S420 , a photoresist layer is formed on a side of the copper seed layer away from the substrate.

[0107] In step S430 , the photoresist layer is patterned by a patterning process to form a photoresist pattern.

[0108] In step S440 , a copper layer is formed on the portion of the copper seed layer not covered by the photoresist pattern by an electroplating process.

[0109] In step S450 , the photoresist pattern and the portion of the copper seed layer not covered by the metal layer are removed to form a metal layer including copper.

[0110] In step S460 , an anti-oxidation layer is formed on a side of the metal layer away from the base substrate.

[0111] In step S470, a light emitting diode is mounted on a side of the anti-oxidation layer away from the base substrate, wherein the light emitting diode includes at least one electrode, and the at least one electrode of the light emitting diode is electrically connected to the metal layer.

[0112] In an embodiment of the present disclosure, the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer. For example, the thickness of the metal layer may be 5 to 30 microns, and in some embodiments, may be 5 to 10 microns, 5 microns, 6 microns, 7 microns, 8 microns, etc.

[0113] In the embodiments of the present disclosure, a thick metal layer can be formed on an LED display substrate by an additive process, which can save manufacturing costs.

[0114] Figure 5A is a partial schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a display area and a marking area. Figure 5B is a partial enlarged view of the marking area shown in Figure 5A. Figure 5C is a partial enlarged view of the display area shown in Figure 5A. Figure 6A is a schematic view of a marking formed by a method for preparing a display substrate according to some exemplary embodiments of the present disclosure. Figure 6B is a schematic view of a marking formed by a method for preparing a display substrate in the related art.

[0115] 1 to 5C , the base substrate may include a display area AA and a mark area MA. For example, the display area AA may be a region for display, such as where the light-emitting diodes (LEDs) may be located. The mark area MA may be a region for forming an alignment mark MK.

[0116] In step S440 , forming a copper layer on the portion of the copper seed layer not covered by the photoresist pattern by electroplating may include: forming a first accompanying plating area 51 in the mark area MA; and forming a second accompanying plating area 81 in the display area AA.

[0117] In the embodiment of the present disclosure, the first accompanying plating area 51 and the second accompanying plating area 81 each comprise a portion of the copper layer. The area ratio of the first accompanying plating area 51 to the marking area MA is greater than the area ratio of the second accompanying plating area 81 to the display area AA. In the embodiment of the present disclosure, by providing different accompanying plating areas for the display area and the marking area, excellent electroplating uniformity is achieved.

[0118] The area ratio of the first accompanying plating area 51 to the marking area MA represents the copper ratio in the marking area MA, and the area ratio of the second accompanying plating area 81 to the display area AA represents the copper ratio in the display area AA. In the embodiment of the present disclosure, the copper ratio in the marking area MA is greater than the copper ratio in the display area AA.

[0119] In the exemplary embodiments shown in Figures 5B and 5C, the areas of the first co-plating zone 51 and the second co-plating zone 81 can be represented by the areas of the annular regions, the shape enclosed by the outer contour of the first co-plating zone 51 is a square, the shape enclosed by the outer contour of the clearance zone 52 is a square, the shape enclosed by the outer contour of the second co-plating zone 81 is a square, and the shape enclosed by the outer contour of the clearance zone 82 is a square.

[0120] Accordingly, the copper ratio M1 in the marked area MA can be expressed by the following formula:

[0121] ,

[0122] The copper ratio M2 in the display area AA can be expressed by the following formula:

[0123] .

[0124] Those skilled in the art should understand that in the electroplating process, in the absence of a plating zone design, the concentration of electric field lines may cause a faster electroplating rate. As a result, when the metal layer is formed, the thickness of the metal exceeds the thickness of the photoresist pattern, thereby causing deformation of the formed component.

[0125] It can be seen from FIG6B that when the accompanying plating area is not set in the marking area, the formed mark will be deformed, thereby affecting the positioning accuracy; it can be seen from FIG6A that when the accompanying plating area is set in the marking area, the formed mark is more accurate, which is conducive to improving the positioning accuracy.

[0126] 5B and 6A , the method may further include forming a mark MK in the area surrounded by the first accompanying plating area 51 by an electroplating process.

[0127] Figure 7 is a partial cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows the positional relationship between the metal layer and the anti-oxidation layer. Figures 8A and 8B are electron microscope images of regions I and II in Figure 7, respectively. Figure 9A is a partial cross-sectional view of a display substrate according to some other exemplary embodiments of the present disclosure, which schematically shows the positional relationship between the metal layer and the anti-oxidation layer. Figure 9B is an electron microscope image of region III in Figure 9A. Figures 10A and 10B are a partial cross-sectional view and a partial plan view of a display substrate according to some further exemplary embodiments of the present disclosure, respectively, which schematically show the positional relationship between the metal layer and the anti-oxidation layer. Figure 11 is a partial cross-sectional view of a display substrate according to some other exemplary embodiments of the present disclosure, which schematically shows the positional relationship between the metal layer and the anti-oxidation layer. Figures 12A and 12B are partial cross-sectional views of a display substrate at a first position and a second position, respectively, according to some other exemplary embodiments of the present disclosure, which schematically show the positional relationship between the metal layer and the anti-oxidation layer.

[0128] 7 , in step S460 , forming an anti-oxidation layer on a side of the metal layer away from the base substrate may include: forming an OSP layer 61 on a side of the metal layer 32 away from the base substrate.

[0129] For example, the metal layer 32 can be a thick copper layer. After forming the thick copper layer 32, the surface is pickled to micro-etch the surface of the copper layer 32 to a depth of 1 to 2 microns. Then, it is immersed in OSP, and the OSP reacts with the surface of the copper layer. In this way, a layer of OSP is coated on the outer surface of the copper layer 32. For example, the middle thickness of the OSP layer 61 is between 0.2 and 0.4 microns, as shown in Figure 8A. As shown in Figure 8B, after the OSP process, there is a sloped portion at the edge, and the OSP layer is relatively thin, between 0 and 0.1 microns.

[0130] 9A , in step S460, forming an anti-oxidation layer on a side of the metal layer away from the base substrate may include: forming a passivation layer PVX on a side of the metal layer 32 away from the base substrate; forming a first via hole VH1 in the passivation layer, the first via hole exposing at least a portion of the metal layer; and forming the anti-oxidation layer in the first via hole VH1. For example, the anti-oxidation layer includes an organic solder paste (OSP) layer 61.

[0131] For example, the metal layer 32 can be a high-thickness copper layer. After forming the high-thickness copper layer 32, a passivation layer is coated on the outer surface of the copper layer 32 to achieve good coating and reliability and meet high temperature and high humidity requirements. The location where the first via VH1 is formed can be a pad and a binding location. Then, the surface is pickled so that the exposed surface of the copper layer 32 is micro-etched to a depth of 1 to 2 microns. Then, OSP immersion is performed, and OSP reacts with the surface of the copper layer. In this way, a layer of OSP is coated on the exposed outer surface of the copper layer 32.

[0132] In this embodiment, a passivation layer is first coated on the outer surface of the metal layer, which can prevent the OSP film layer from being thinner in some sloped parts on the edge after the OSP process, and is conducive to the uniform coating of the metal layer. As shown in FIG9B , the middle thickness of the passivation layer PVX is basically equal to the edge thickness, that is, the passivation layer PVX can improve the uniform coating of the metal layer and enhance the protection effect.

[0133] 10A , in step S460 , forming an anti-oxidation layer on a side of the metal layer away from the base substrate may include forming a nickel-containing alloy layer 71 surrounding the metal layer on a side of the metal layer 32 away from the base substrate.

[0134] The nickel-containing alloy layer 71 has oxidation resistance and good welding performance. For example, the nickel-containing alloy layer 71 can be CuNi, with a Ni mass percentage of 10 to 30%; or, the nickel-containing alloy layer 71 can be NiV, with a Ni mass percentage of 50 to 97%; or, the nickel-containing alloy layer 71 can be NiW, with a Ni mass percentage of 50 to 97%, etc.

[0135] For example, the nickel alloy layer 71 may have a thickness of 500 to 4000 angstroms. The nickel alloy layer 71 may be patterned by photolithography.

[0136] 11 , in step S460, forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes: forming a nickel-containing alloy layer 71 surrounding the metal layer on a side of the metal layer 32 away from the base substrate; forming a passivation layer PVX on a side of the nickel-containing alloy layer 71 away from the base substrate; and forming a second via hole VH2 in the passivation layer PVX, wherein the second via hole VH2 exposes at least a portion of the nickel-containing alloy layer 71.

[0137] For example, the metal layer 32 may be a thick copper layer. After forming the thick copper layer 32, the outer surface of the copper layer 32 is coated with a nickel-containing alloy layer 71 to achieve good coverage and reliability, meeting high temperature and high humidity requirements. The second via VH2 may be formed at a pad or a bonding location.

[0138] 12A and 12B , in step S460, forming an anti-oxidation layer on a side of the metal layer away from the base substrate includes: forming a nickel-containing alloy layer 71 surrounding the metal layer on a side of the metal layer 32 away from the base substrate; forming an opening 72 in the nickel-containing alloy layer at a pad position in the display area AA, the opening 72 exposing at least a portion of the metal layer 32; forming a passivation layer PVX at a side of the nickel-containing alloy layer 71 away from the base substrate; and forming a third via hole VH3 in the passivation layer PVX at a pad position in the display area, the third via hole VH3 exposing at least a portion of the metal layer 32.

[0139] In this embodiment, the orthographic projection of the third via hole VH3 on the base substrate is located within the orthographic projection of the opening 72 on the base substrate.

[0140] In step S460 , forming an anti-oxidation layer on a side of the metal layer away from the base substrate further includes: forming a fourth via hole VH4 in the passivation layer PVX at a binding position, wherein the fourth via hole VH4 exposes at least a portion of the nickel-containing alloy layer 71 .

[0141] In this embodiment, the compound used in the OSP process reacts only with copper to form the OSP layer and does not react with the nickel-containing alloy layer 71. Therefore, the pad area in the display area AA is well protected. No organic protective layer is formed in the bonding area, preventing poor contact or increased contact resistance between the bonding area and the external circuit.

[0142] In the embodiments disclosed herein, nickel-containing alloys and / or OSP are used as an anti-oxidation layer to address the issue of preventing oxidation of thick copper, resulting in a highly effective and cost-effective process. This nickel-containing alloy and / or OSP protection avoids the need for metallization, significantly reducing display substrate manufacturing costs.

[0143] Based on the above-mentioned preparation method provided in the embodiments of the present disclosure, some exemplary embodiments of the present disclosure further provide a display substrate. With reference to Figures 1, 2, and 9A-12B, the display substrate comprises: a base substrate 1; a metal layer located on the base substrate, the metal layer comprising a copper layer 32 having a first thickness; anti-oxidation layers 61 and 71 located on a side of the metal layer 32 away from the base substrate, the anti-oxidation layers having a second thickness; and a light-emitting diode 5 located on a side of the anti-oxidation layer away from the base substrate, the light-emitting diode 5 comprising at least one electrode, the at least one electrode of the light-emitting diode being electrically connected to the metal layer, wherein the first thickness of the metal layer 32 is greater than the second thickness of the anti-oxidation layers 61 and 71.

[0144] Referring to Figures 5A and 5B, the base substrate 1 includes a display area AA and a marking area MA. The display substrate includes a first accompanying plating area 51 located in the marking area MA and a second accompanying plating area located within the display area AA. Both the first accompanying plating area 51 and the second accompanying plating area include a copper layer. The area ratio of the first accompanying plating area 51 to the marking area MA is greater than the area ratio of the second accompanying plating area to the display area AA.

[0145] Specifically, the display substrate further includes: a mark MK located in the mark area; and a clearance area 52 located in the mark area. The first accompanying plating area 51 surrounds the mark MK, and the clearance area 52 is located between the mark MK and the first accompanying plating area 51 and surrounds the mark.

[0146] It should be noted that the clearance area refers to the area left under the alignment lens to prevent other graphics from affecting the alignment when the exposure machine is aligned. Only alignment graphics can be retained in this area.

[0147] For example, as shown in FIG5B , the orthographic projection of the first accompanying plating area 51 on the base substrate 1 is a ring-shaped area surrounding the mark MK.

[0148] As shown in FIG10A , the anti-oxidation layer 71 surrounds the metal layer 32 , and at least one electrode of the light emitting diode is electrically connected to the metal layer through the anti-oxidation layer.

[0149] As shown in FIG11 , the display substrate further includes: a passivation layer PVX located away from the base substrate 1 and away from the anti-oxidation layer 71; and a first via hole VH1 located in the passivation layer. The first via hole VH1 exposes at least a portion of the anti-oxidation layer 71, and at least one electrode of the light-emitting diode is electrically connected to the metal layer 32 through the first via hole 71.

[0150] For example, the anti-oxidation layer 71 surrounds the metal layer 32 .

[0151] As shown in FIG12A , the display substrate further includes: a passivation layer PVX located away from the base substrate from the anti-oxidation layer 71; and a third via hole VH3 located in the passivation layer. The third via hole VH3 is located at a pad position in the display area, exposing at least a portion of the metal layer 32. At least one electrode of the light-emitting diode is electrically connected to the metal layer through the third via hole.

[0152] The anti-oxidation layer includes an opening 72 , and the opening 72 exposes at least a portion of the metal layer 32 . The orthographic projection of the third via hole VH3 on the base substrate is located within the orthographic projection of the opening 72 on the base substrate.

[0153] As shown in FIG12B , the display substrate further includes a fourth via hole VH4 located in the passivation layer PVX. The fourth via hole VH4 is located at a binding position and exposes at least a portion of the anti-oxidation layer 71. At least one electrode of the light-emitting diode is electrically connected to the metal layer through the exposed portion of the anti-oxidation layer.

[0154] It should be noted that in the embodiments of the present disclosure, the thickness of the copper layer 32 is greater than the thickness of the passivation layer PVX, which is also greater than the thickness of the OSP layer 61 and the anti-oxidation layer 71. The thicknesses of the OSP layer 61 and the anti-oxidation layer 71 are substantially equal. For example, the copper layer 32 has a high thickness, such as 5 to 10 microns. The thickness of the passivation layer PVX can be 3000 to 5000 angstroms. When the thickness of the passivation layer PVX is greater than 5000 angstroms, the stress in the passivation layer PVX is greater. When the thickness of the passivation layer PVX is less than 2000 angstroms, the lateral coverage of the passivation layer PVX on the copper layer 32 is affected. The thicknesses of the OSP layer 61 and the anti-oxidation layer 71 are substantially equal, such as 2000 to 4000 angstroms.

[0155] Some exemplary embodiments of the present disclosure further provide a display device. Figures 11 and 12 are schematic diagrams of display devices according to some exemplary embodiments of the present disclosure. Referring to Figures 11 and 12, the display device includes at least two display substrates as described above.

[0156] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0157] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0158] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: include: substrate; a metal layer on the substrate, the metal layer comprising a copper layer having a first thickness; an anti-oxidation layer located on a side of the metal layer away from the substrate, the anti-oxidation layer having a second thickness; A light emitting diode located on a side of the anti-oxidation layer away from the substrate, the light emitting diode comprising at least one electrode, the at least one electrode of the light emitting diode being electrically connected to the metal layer, Wherein, the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.

2. The display substrate according to claim 1, wherein The anti-oxidation layer includes a nickel-containing alloy.

3. The display substrate according to claim 1, wherein The base substrate includes a display area and a marking area, and the display substrate includes: a first accompanying plating area located in the marking area; and a second accompanying plating area located in the display area; The first accompanying plating area and the second accompanying plating area both include a copper layer; An area ratio of the first accompanying plating area to the marking area is greater than an area ratio of the second accompanying plating area to the display area.

4. The display substrate according to claim 3, wherein: The display substrate further includes: a mark located in the mark area; and a clearance area located in the mark area, The first accompanying plating area surrounds the mark, and the clearance area is located between the mark and the first accompanying plating area and surrounds the mark.

5. The display substrate according to claim 4, wherein: The orthographic projection of the first accompanying plating area on the base substrate is an annular area surrounding the mark.

6. The display substrate according to claim 1 or 2, wherein: The anti-oxidation layer surrounds the metal layer, and at least one electrode of the light emitting diode is electrically connected to the metal layer through the anti-oxidation layer.

7. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises: a passivation layer located away from the base substrate from the anti-oxidation layer; and a first via hole located in the passivation layer; The first via hole exposes at least a portion of the anti-oxidation layer, and at least one electrode of the light emitting diode is electrically connected to the metal layer through the first via hole.

8. The display substrate according to claim 1 or 2, wherein: The anti-oxidation layer surrounds the metal layer.

9. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises: a passivation layer located away from the base substrate from the anti-oxidation layer; and a third via hole located in the passivation layer; The third via hole is located at a pad position of the display area, the third via hole exposes at least a portion of the metal layer, and at least one electrode of the light emitting diode is electrically connected to the metal layer through the third via hole.

10. The display substrate according to claim 9, wherein: The display substrate further includes: a fourth via hole located in the passivation layer; The fourth via hole is located at the binding position, and the fourth via hole exposes at least a portion of the anti-oxidation layer. At least one electrode of the light-emitting diode is electrically connected to the metal layer through the exposed portion of the anti-oxidation layer.

11. The display substrate according to claim 9 or 10, wherein: The anti-oxidation layer includes an opening portion, the opening portion exposing at least a portion of the metal layer, and an orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the opening portion on the base substrate.

12. A method for preparing a display substrate, characterized in that: include: depositing a copper seed layer on the substrate; forming a photoresist layer on a side of the copper seed layer away from the substrate; patterning the photoresist layer through a patterning process to form a photoresist pattern; forming a copper layer on the portion of the copper seed layer not covered by the photoresist pattern by an electroplating process; removing the photoresist pattern and a portion of the copper seed layer not covered by the metal layer to form a metal layer including copper; forming an anti-oxidation layer on a side of the metal layer away from the substrate; A light emitting diode is mounted on a side of the anti-oxidation layer away from the substrate, wherein the light emitting diode includes at least one electrode, and the at least one electrode of the light emitting diode is electrically connected to the metal layer. Wherein, the first thickness of the metal layer is greater than the second thickness of the anti-oxidation layer.

13. The method according to claim 12, wherein: The base substrate includes a display area and a marking area, The forming of a copper layer on a portion of the copper seed layer not covered by the photoresist pattern by an electroplating process comprises: In the marking area, a first accompanying plating area is formed; forming a second accompanying plating area in the display area; Wherein, the first accompanying plating area and the second accompanying plating area respectively include a portion of the copper layer; An area ratio of the first accompanying plating area to the marking area is greater than an area ratio of the second accompanying plating area to the display area.

14. The method according to claim 13, wherein The method further includes forming a mark in an area surrounded by the first accompanying plating area through an electroplating process.

15. The method according to claim 12, wherein: Forming an anti-oxidation layer on a side of the metal layer away from the substrate includes: forming a passivation layer on a side of the metal layer away from the substrate; forming a first via hole in the passivation layer, the first via hole exposing at least a portion of the metal layer; forming the anti-oxidation layer in the first via hole, Wherein, the anti-oxidation layer includes an organic solder protection film.

16. The method according to claim 12, wherein Forming an anti-oxidation layer on a side of the metal layer away from the substrate includes: A nickel-containing alloy layer is formed on a side of the metal layer away from the base substrate, surrounding the metal layer.

17. The method according to claim 12, wherein: Forming an anti-oxidation layer on a side of the metal layer away from the substrate includes: forming a nickel-containing alloy layer surrounding the metal layer on a side of the metal layer away from the base substrate; forming a passivation layer on a side of the nickel-containing alloy layer away from the substrate; A second via hole is formed in the passivation layer, the second via hole exposing at least a portion of the nickel-containing alloy layer.

18. The method according to claim 12, wherein: Forming an anti-oxidation layer on a side of the metal layer away from the substrate includes: forming a nickel-containing alloy layer surrounding the metal layer on a side of the metal layer away from the base substrate; An opening is formed in the nickel-containing alloy layer at a pad position in the display area, wherein the opening exposes at least a portion of the metal layer. forming a passivation layer on a side of the nickel-containing alloy layer away from the substrate; A third via hole is formed in the passivation layer at a pad position of the display area, wherein the third via hole exposes at least a portion of the metal layer. The orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the opening on the base substrate.

19. The method according to claim 18, wherein Forming an anti-oxidation layer on a side of the metal layer away from the substrate further comprises: At the bonding position, a fourth via hole is formed in the passivation layer, the fourth via hole exposing at least a portion of the nickel-containing alloy layer.

20. A display device comprising the display substrate according to any one of claims 1 to 11.

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