Semiconductor device and power converter device

Abstract

A maximum unipolar current density is increased while the electric field on a body diode is reduced in the off-state of a transistor. A semiconductor device includes a first separation region and a second separation region. The first separation region extends in a first direction and a second direction in plan view, the first separation region has at least a first fold region folded back in the second direction, the second separation region extends in at least the first direction in plan view, and the width of the second separation region in the second direction is equal to or greater than the width of the first separation region in either the first direction or the second direction.

Description

Technical area

[0001] The invention disclosed in the description of the present application relates to a semiconductor device. State of the art

[0002] A vertical metal-oxide-semiconductor field-effect transistor, i.e. a MOSFET, which uses silicon carbide, sometimes has a built-in unipolar diode as a backflow diode.

[0003] For example, Patent Document 1 proposes a method in which a Schottky diode (SBD) is included as a unipolar diode in a unit cell of a MOSFET and the Schottky diode is used.

[0004] Such a unipolar transistor having a built-in unipolar diode, i.e., a diode with electrical conductivity having only a large number of carriers in an active region, is designed so that the diffusion potential of the unipolar diode, i.e., the voltage at which conduction is started, is lower than the voltage at which conduction of a pn junction in a MOS structure (hereinafter occasionally referred to as a body diode) is started, so that forward current and defect extension in the body diode can be suppressed. State of the art documentPatent document

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. JP 2018-49951A SummaryProblem to be solved with the invention

[0006] For a MOSFET with a built-in Schottky diode, the following applies: When a current with a specific current density flows through the Schottky diode, the body diode begins to conduct electrically. This specific current density is defined as the maximum unipolar current density.

[0007] If the width or length, i.e., the area, of the Schottky diode is designed to be large, the maximum unipolar current density increases, and the current flowing in the body diode can be suppressed. Meanwhile, the electric field easily concentrates in the pn diode formed around the Schottky diode when the transistor is in the off state, causing leakage current to flow and heat to be generated. Consequently, in some cases, an element or circuit is destroyed.

[0008] For the reason described above, there is the circumstance in which the area of ​​the Schottky diode is preferably designed to be large so that the maximum unipolar current density is increased, and conversely, the circumstance in which the area of ​​the Schottky diode is preferably designed to be small so that breakdown of the element in the off state of the transistor is prevented.

[0009] The invention disclosed in the specification of the present application was conceived to solve the problems described above, and is a technique for increasing the maximum unipolar current density while reducing the electric field on a body diode in the off state of a transistor. Ways to solve the problem

[0010] A semiconductor device according to a first aspect of the invention disclosed in the specification of the present application comprises: a drift layer of a first conductivity type disposed on an upper surface of a semiconductor substrate of the first conductivity type; a plurality of well regions of a second conductivity type disposed separately from each other on a surface layer of the drift layer; a source region of the first conductivity type disposed on a surface layer of at least one of the well regions; a first separation region of the first conductivity type as a region between the plurality of well regions on the surface layer of the drift layer; a second separation region of the first conductivity type as a region different from the first separation region between the plurality of well regions of the surface layer of the drift layer;a gate insulating layer arranged to be in contact with at least one of the well regions sandwiched between the source region and the drift layer; a gate electrode arranged to be in contact with the gate insulating layer; a Schottky electrode arranged on an upper surface of the first separation region so as to have a Schottky junction with the first separation region; an ohmic electrode arranged on an upper surface of the source region;and a source electrode arranged to be in contact with the Schottky electrode and the ohmic electrode, wherein the first separation region extends in a first direction and a second direction as a direction different from the first direction in plan view, the first separation region having at least a first fold portion folded back in the second direction, the second separation region extending in at least the first direction in plan view, and the width of the second separation region in the second direction is equal to or greater than the width of the first separation region in the first direction or the second direction; Effects of the invention

[0011] According to at least the first aspect of the invention disclosed in the description of the present application, the first folding region is arranged at the first separation region. Consequently, the maximum unipolar current density can be increased. Meanwhile, the width of the first separation region is smaller than that of the second separation region. Consequently, the electric field at the PN junction region formed by the first separation region and the well region can be reduced.

[0012] These and other objects, features, aspects and advantages related to the invention disclosed in the specification of the present application will become more apparent from the following detailed description of the present invention when considered in conjunction with the accompanying diagrams. Short description of the drawings Fig. 1 A plan view of a MOSFET with a built-in Schottky diode as a semiconductor device according to an embodiment. Fig. 2 A schematic cross-sectional view along a cross section AA' in Fig. 1. Fig. 3 A schematic view showing a top view structure in Fig. 1, which is repeatedly and continuously arranged in a direction X and a direction Y. Fig. 4 A plan view of a terminal part of an active region in the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 5 A plan view of a modification example of the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 6 A plan view of a modification example of the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 7 A plan view of the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 8 A plan view of the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 9 A plan view of the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 10 A schematic view illustrating an example of a grid-type cell arrangement. Fig. 11 A block diagram showing a configuration of a power conversion system to which a power conversion device according to the embodiment is applied. Fig. 12 A plan view illustrating an example of a configuration of an active region of the MOSFET with the built-in Schottky diode as a semiconductor device according to the embodiment. Fig. 13 A schematic cross-sectional view along a cross section AA' in Fig. 12. Description of embodiments

[0013] An embodiment will be described below with reference to the accompanying diagrams. Detailed features will also be described below to explain the invention according to the embodiment. However, these are only an example and are therefore not always necessary to implement the embodiment.

[0014] The diagrams are presented schematically. Consequently, some omissions or simplifications have been made in the diagrams to simplify explanation. The interrelationship of sizes and positions of the configurations shown in the various diagrams is not necessarily depicted accurately, but may be appropriately modified. For example, hatching may be shown in the plan view as well as the cross-sectional view so that the contents of the embodiment can be easily understood.

[0015] In the following description, like reference numerals are assigned to similar elements in the illustration, as are their names and functions. Accordingly, in some cases, detailed descriptions may be omitted to avoid repetition.

[0016] In describing the present invention, when a description is made with "comprising," "comprising," or "including" or "having" a certain element, such description does not indicate an expression that excludes other elements unless otherwise explained.

[0017] In the description of the present invention, even if ordinal numbers such as "first" or "second" are used, these terms are used to facilitate understanding of the embodiments, and therefore the embodiments are not limited to the order indicated by the ordinal numbers.

[0018] In the description of the present invention, even if terms indicating a specific position or direction, such as "upper," "lower," "left," "right," "side," "bottom," "front," or "back," these terms are used to facilitate understanding of the embodiments and therefore are irrelevant to the positions or directions in the practical implementation of the embodiment.

[0019] Furthermore, when an "upper surface of..." or a "lower surface of..." is described in the description of the present invention, this also includes a state in which the other element is formed on an upper surface or a lower surface of a target element, in addition to the upper surface or the lower surface of the target element. That is, if the description reads, for example, "B is arranged on an upper surface of A," this does not prevent the interposition of another element "C" between A and B. First embodiment

[0020] A semiconductor device relating to the present embodiment will be described below.

[0021] In this specification, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may also be p-type, and the second conductivity type may be n-type. The "n-" type indicates that the "n-" type has a lower impurity concentration than the n-type, and the "n + “ type indicates that the “n + " type has a higher impurity concentration than the n-type. Similarly, the "p-" type indicates that the "p-" type has a lower impurity concentration than the p-type, and the "p + “ type indicates that the “p + “ -type has a higher impurity concentration than the p-type. Configuration of the semiconductor device

[0022] Fig. Figure 1 is a plan view of a Schottky diode-integrated MOSFET as a semiconductor device according to the present embodiment. The plan view is a diagram of a semiconductor substrate viewed from the top side in plan view, while omitting, for example, a source electrode, a gate wiring layer, or an insulating layer. Fig. 2 A schematic cross-sectional view along a cross section AA' in Fig. 1.

[0023] In Fig. 1, a separation region 21 is arranged, which runs in a direction X and a direction Y and has a folding region 221 which is folded back in the direction Y. The plurality of folding regions 221 are in Fig. 1. However, a case is also conceivable in which only one folding region 221 is present.

[0024] In Fig. 2, an n-type drift layer 20 is formed on an upper surface of a low-resistance n-type semiconductor substrate 10. A plurality of p-type well regions 30 are arranged on a surface layer portion of the drift layer 20.

[0025] An n-type source region 40 is formed at a position closer to the inside by a predetermined distance from the outer periphery of the well region 30 in a surface layer part of each well region 30.

[0026] A p-type contact region 35 with a low resistance is formed on the lateral side of the source region 40 in the surface layer portion of each well region 30. An n-type separation region 21 is formed between the well regions 30, which are formed separately from each other in the surface layer portion of the drift layer 20.

[0027] The n-type impurity concentration of the separation region 21 may be equal to, higher than, or lower than that of the drift layer 20.

[0028] A Schottky electrode 71, which is Schottky-connected to the separation region 21, is formed on an upper surface of the separation region 21. Here, it is preferable that the Schottky electrode 71 be formed so as to cover at least the separation region 21 in plan view, that is, the area of ​​the Schottky electrode 71 is larger than that of the separation region 21.

[0029] A region other than the separation region 21 between the well regions 30 formed separately from each other in the surface layer portion of the drift layer 20 is an n-type separation region 22. The separation region 22 has the same width as or greater than the width of the separation region 21. In other words, the separation region 21 has the same width as or smaller than the width of the separation region 22.

[0030] The n-type impurity concentration of the separation region 22 may be equal to, higher than, or lower than that of the drift layer 20.

[0031] A gate insulating layer 50 is formed on an upper surface of the well region 30, an upper surface of the separation region 22 between the well regions 30, and an upper surface of the source region 40 in each well region 30. The gate insulating layer 50 is arranged to make contact with the well region 30, which is sandwiched between the source region 40 and the drift layer 20.

[0032] A gate electrode 60 is formed in a region overlapping the source region 40 and the well region 30 in plan view, in an upper surface of the gate insulating film 50. The surface layer part of the well region 30 facing the gate electrode 60 with the gate insulating film 50 therebetween on the lower side of a position where the gate electrode 60 is formed is called a channel region.

[0033] An ohmic electrode 70 is formed on a part of the upper surface of the source region 40 and a part of an upper surface of the contact region 35. Then, a source electrode 80 is formed to cover the ohmic electrode 70 and the Schottky electrode 71.

[0034] The source region 40 can easily supply and receive electrons via the ohmic electrode 70. The well region 30 can easily supply and receive positive holes via the low-resistance contact region 35 and the ohmic electrode 70.

[0035] However, the ohmic electrode 70 does not need to be in contact with the separation region 21. According to such a configuration, the ohmic contact does not function as a bypass of the Schottky junction formed between the separation region 21 and the source electrode 80. More specifically, the separation region 21 and the ohmic electrode 70 are electrically separated from each other by the contact region 35 and the well region 30.

[0036] An interlayer insulating film 55 is formed to cover the gate electrode 60. A source electrode 80 is in contact with an upper surface of the ohmic electrode 70, an upper surface of the Schottky electrode 71, and an upper surface of the contact region 35 via a contact hole 90 formed to pass through the interlayer insulating film 55 and the gate insulating film 50.

[0037] Meanwhile, a drain electrode 84 is formed on a lower surface of the semiconductor substrate 10.

[0038] As in Fig. 1, the well region 30, the contact region 35, and the separation region 22 extend along the direction X, so that they are formed in a stripe shape. The gate electrode 60 in Fig. 2 is also designed to run along the direction X.

[0039] The separation region 21 extends along the X direction and the Y direction, which is the direction different from the X direction, and is arranged to be repeatedly folded back between the well regions 30 (the folding back occurs in the folding region 221). This configuration is defined as an accordion-like (zigzag) arrangement.

[0040] When the separation area 21 is arranged to have the accordion-like shape, the width of the separation area 21 is set to be equal to or smaller than that of the separation area 22.

[0041] In Fig. 1, the direction X is the direction parallel to a direction in which the well region 30, the contact region 35 and the separation region 22 extend, and the direction Y is the direction perpendicular to the direction X. Operation of the semiconductor device

[0042] Next, the operation of a MOSFET with a built-in SBD as a semiconductor device according to the present embodiment will be described. An example of a silicon carbide semiconductor device will be described below, in which the semiconductor material is 4H-type silicon carbide. In this case, the diffusion potential of the pn junction is approximately 2V.

[0043] First, the case of a backflow operation is described.

[0044] In reverse flow mode, the current tends to flow from the source electrode 80 to the drain electrode 84. In particular, when a turn-off voltage is applied to the gate electrode 60, there is no current path passing through a channel.

[0045] At this time, the Schottky diode, which is turned on at a lower voltage than the body diode formed by the well region 30 and the drift layer 20, is formed between the separation region 21 and the Schottky electrode 71. Therefore, when the current density is low, the reverse current flows entirely through the Schottky diode and does not flow to the body diode.

[0046] However, when the current density becomes high, a voltage greater than about 2 V occurs as a voltage breakdown occurring in a Schottky interface and the separation region 21, and it is applied to the pn junction arranged in parallel, and current conduction in the body diode starts.

[0047] To increase the current density at this time, that is, the maximum unipolar current density, it is effective to increase the n-type concentration of the separation region 21 or to increase the width of the separation region 21 so as to reduce the resistance of the separation region 21. However, in any method, the electric field intensity applied to the Schottky interface or the PN junction region increases in the off-state of the transistor.

[0048] Here, when the separation region 21 is arranged in a meander shape as in the present embodiment, the value of electrons flowing via the Schottky diode can be increased without increasing the n-type concentration and the width of the separation region 21, and the maximum unipolar current density can be increased.

[0049] As the meander cycle of separation region 21 becomes shorter, the amount of electrons flowing via the SBD can be increased. Consequently, the maximum unipolar current density can be further increased.

[0050] Next, a case is described where the transistor is in the off state.

[0051] When the transistor is in the off state, the electric field is easily concentrated in the PN junction region formed by the separation region 21 and the well region 30 and the PN junction region formed by the separation region 22 and the well region 30.

[0052] Reducing the width of the separation region 21 and the width of the separation region 22 is considered a method for reducing the electric field concentration in the PN junction region formed by the separation region 21 and the well region 30, and in the PN junction region formed by the separation region 22 and the well region 30. When the width of the separation region 21 and the width of the separation region 22 are reduced, the potential fluctuation in the separation region 21 and the separation region 22 in the off state of the transistor is reduced. Consequently, the electric field concentration in the PN junction region formed by the separation region 21 and the well region 30 and in the PN junction region formed by the separation region 22 and the well region 30 can be reduced.

[0053] As in Fig. As illustrated in Figure 2, the gate insulating layer 50 is formed on the upper surface of the separation region 22, and the gate insulating layer 50 divides the voltage applied to the entire device by applying the reverse voltage in the transistor's off state. Consequently, the electric field at the PN junction region formed by the separation region 22 and the well region 30 is reduced. Consequently, the electric field is easily concentrated in the PN junction region formed by the separation region 21 and the well region 30 without an electric field dividing layer on the upper surface.

[0054] Consequently, when the width of the separation region 21 is smaller than that of the separation region 22, the electric field on the PN junction region formed by the separation region 21 and the well region 30 can be reduced. Consequently, breakdown of an element in the off-state of the transistor can be suppressed.

[0055] For the above reason, if the width of the separation region 21 is set to be equal to or smaller than that of the separation region 22 when the separation region 21 is arranged in a meander shape, the electric field concentration in the body diode formed by the separation region 21 and the well region 30 is suppressed in the off state of the transistor, and breakdown of the element can be prevented.

[0056] As described above, according to the semiconductor device of the present embodiment, the operation of the body diode in the reverse flow mode is suppressed. Consequently, the maximum unipolar current density can be increased, and breakdown of the element in the off-state of the transistor can be suppressed, and the trade-off relationship between the two can be improved. Method for manufacturing the semiconductor device

[0057] Next, a method for manufacturing a MOSFET with a built-in Schottky diode as a semiconductor device according to the present embodiment will be described. An example of a silicon carbide semiconductor device in which the semiconductor material is 4H-type silicon carbide will be described below.

[0058] The n-type silicon carbide drift layer 20 is epitaxially grown on the upper surface of the semiconductor substrate 10 having the 4H polytype and formed of n-type low-resistance silicon carbide with a first main surface having a plane orientation that is a (0001) plane by a chemical vapor deposition (CVD) method, so that it has, for example, a thickness of 5 µm to 50 µm at an impurity concentration of 1 × 10 15 up to 1 × 10 17 cm -3 has.

[0059] Subsequently, an implantation mask is formed, for example, by photoresist, in a predetermined region on the upper surface of the drift layer 20, and aluminum (Al) is ion-implanted as a p-type impurity. At this time, the depth of Al ion implantation is set within a range of 0.5 µm to 3 µm so that it does not exceed the thickness of the drift layer 20.

[0060] The impurity concentration of ion-implanted Al has a maximum value at a depth away from the top surface of the drift layer 20, and it is within a range of 1 × 10 17 cm -3 up to 1 × 10 19 cm -3 so that it is higher than that of the drift layer 20. In contrast, the impurity concentration of the implanted Al in the upper surface of the drift layer 20 is low, and it is within a range of 1 × 10 15 cm -3 up to 1 × 10 18 cm -3 The implantation mask is then removed. The area where Al is ion-implanted in this process serves as the well region 30.

[0061] Next, an implantation mask is formed by photoresist on the upper surface of the drift layer 20, and Al with a p-type impurity concentration is ion implanted. At this time, the depth of Al ion implantation is set within a range of 0.5 μm to 3 μm so that it does not exceed the thickness of the drift layer 20. The depth of Al ion implantation is smaller than the well region 30, so that implantation defects or implantation impurities with a high concentration remain within the well region 30.

[0062] The impurity concentration of the ion-implanted Al is within a range of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3, so that it is higher than that of the drift layer 20 and lower than that of the well region 30. Then, the implantation mask is removed. The area where Al is ion-implanted in the present process serves as the contact region 35.

[0063] Next, an implantation mask is formed, for example, using photoresist, so that a predetermined position within the well region 30 is opened in the top surface of the drift layer 20 in plan view. Then, nitrogen (N) is ion-implanted as an n-type impurity. The ion implantation depth of N is smaller than the thickness of the well region 30. The impurity concentration of the ion-implanted N is within a range of 1 × 10 18 cm -3 up to 1 × 10 21 cm -3 so that it is higher than the p-type impurity concentration of the well region 30. The impurity concentration of N is preferably greater than 1 × 10 19 cm-3 , so that the sheet resistance or the contact resistance with the ohmic electrode 70 is reduced. A region exhibiting n-type conductivity in the area where N is implanted in the present process serves as the source region 40.

[0064] Next, a heat treatment or annealing treatment is performed at a temperature of 1300 °C to 1900 °C, for example, for 30 seconds to 1 hour in an inactive gas atmosphere, such as argon (Ar), in a heat treatment device (not shown here). This annealing electrically activates the ion-implanted N and Al.

[0065] Subsequently, a field insulating layer (not shown here) made of silicon oxide having a film thickness of 0.5 µm to 2 µm, greater than that of the gate oxide film, is formed on the upper surface of the drift layer 20 in a region different from the active region (ie, in a region substantially corresponding to the region where the well region 30 is formed), for example, using a CVD method or a photolithography technique.

[0066] Next, the upper surface of the drift layer 20 not covered by the field insulating layer is thermally oxidized to form a silicon oxide layer as the gate insulating layer 50 with a desired thickness. Essentially, a conductive polycrystalline silicon layer is formed by a decompression CVD method on an upper surface of the gate insulating layer 50 or an upper surface of the field insulating layer, and further, the polycrystalline silicon layer is patterned to form the gate electrode 60.

[0067] Next, the interlayer insulating layer 55 made of silicon oxide is formed using a decompression CVD method. Then, the contact hole 90 is formed, passing through the interlayer insulating layer 55 and the gate insulating layer 50, reaching the contact region 35 and the source region 40 in the active region.

[0068] After a metal layer containing Ni as a main component is formed by, for example, a sputtering method, a heat treatment is performed at a temperature of 600°C to 1100°C, and the metal layer containing Ni as the main component and a silicon carbide layer in the contact hole 90 react so that silicide is formed between the silicon carbide layer and the metal layer.

[0069] Subsequently, the remaining metal layer other than silicide formed in the above reaction is removed by wet etching. The ohmic electrode 70 is thereby formed.

[0070] Subsequently, a metal layer containing Ni as a main component is formed on the lower surface (second main surface) of the semiconductor substrate 10, and a heat treatment is further performed so that a back surface ohmic electrode (not shown here) is formed on one side of the lower surface of the semiconductor substrate 10.

[0071] Next, the interlayer insulating layer 55 and the gate insulating layer 50 on the upper surface of the separation region 21 are removed, for example, using patterning with a photoresist. The layer removal method used is wet etching, which does not damage the surface of the silicon carbide layer as the Schottky barrier. After wet etching, the photoresist is removed if photoresist is used.

[0072] Subsequently, a metal layer is deposited as a Schottky electrode, for example, using a sputtering method, and the Schottky electrode 71 is formed on the upper surface of the separation region 21 in the contact hole 90, for example, using photoresist patterning. For example, Ti or Mo can be used as the material of the Schottky electrode 71.

[0073] Next, a wiring metal such as Al is formed on the upper surface of the drift layer 20, in which the above-described Schottky electrode 71 is formed, using a sputtering method or a vapor deposition method. Then, the source-side ohmic electrode 70, the source electrode 80 in contact with the Schottky electrode 71, and a gate pad (not shown) and gate wiring (not shown) in contact with the gate electrode 60 are formed by processing the wiring metal into a predetermined shape using a photolithography technique.

[0074] When the drain electrode 84 is formed as a metal layer on a lower surface of the back surface ohmic electrode (not shown here) formed on the lower surface of the semiconductor substrate 10, the semiconductor device shown in Fig. 1 and Fig. 2 is shown.

[0075] The example of performing each ion implantation in a predetermined order is described in the present embodiment. However, the order of ion implantation can also be changed as appropriate. The order of forming the back surface ohmic electrode on the lower surface of the semiconductor substrate 10 and the ohmic electrode 70 and the Schottky electrode 71 on the upper surface of the semiconductor substrate 10 can be changed as appropriate.

[0076] In the present embodiment, an example of forming the Schottky electrode 71 only on the upper surface of the separation region 21 and the upper surface of the well region 30 is described. However, the Schottky electrode 71 may also be formed on the upper surface of the ohmic electrode 70 or the upper surface of the interlayer insulating film 55.

[0077] In the present embodiment, it is assumed that the channel or Schottky electrode 71 is a planar type formed parallel to the main surface of the semiconductor substrate 10. However, it is also conceivable that the channel or Schottky electrode 71 is a trench type formed obliquely or perpendicularly to the main surface of the semiconductor substrate 10. That is, it is also conceivable that a trench gate is provided in which a trench passing through the well region 30 and reaching the drift layer 20 is provided, and the gate insulating film 50 and the gate electrode 60 are formed on an inner side of the trench.

[0078] Fig. 12 is a plan view showing an example of an active region configuration of a SiC MOSFET having a built-in trench type Schottky diode as a semiconductor device according to the present embodiment. Fig. 13 A schematic cross-sectional view along a cross section AA' in Fig. 12.

[0079] In Fig. 12 and Fig. 13, the n-type silicon carbide drift layer 20 is formed on the upper surface of the semiconductor substrate 10. The drift layer 20 is formed of n-type silicon carbide with a low resistance. The p-type silicon carbide well region 30 is formed on the surface layer portion of the drift layer 20.

[0080] The n-type silicon carbide source region 40 is formed on the surface layer portion of a part of the well region 30. A p-type low-resistance contact region 35 is formed in a region adjacent to the source region 40 in the surface layer portion of the well region 30.

[0081] In the active region, a gate trench 302 is formed, which passes through the source region 40 and the well region 30 and reaches the drift layer 20.

[0082] A Schottky trench 303 passing through the source region 40 and the well region 30 and reaching the drift layer 20 is formed at a position different from the position where the gate trench 302 is formed.

[0083] The gate trench 302 and the Schottky barrier trench 303 are alternately arranged parallel to each other. The gate trench 302 and the Schottky barrier trench 303 may be formed to have the same width, or their widths may be different from each other.

[0084] A gate electrode 60A is formed in the gate trench 302 so as to be surrounded by a gate insulating layer 50A made of silicon carbide. The gate electrode 60A is formed of polycrystalline silicon, which has a high impurity concentration and low resistance. The interlayer insulating layer 55 made of silicon oxide is formed on an upper surface of the gate electrode 60A.

[0085] The source electrode 80 is formed in the Schottky trench 303 so as to be surrounded by a Schottky electrode 71A. The Schottky electrode 71A is formed to be in contact with the drift layer 20 and is Schottky-connected to the drift layer 20. A p-type protection region 32 is formed in the drift layer 20, which is in contact with a bottom surface of the gate trench 302. A p-type protection region 33 is formed in the drift layer 20, which is in contact with a bottom surface of the Schottky trench 303. The depth of the protection region 32 may be the same as or different from that of the protection region 33. The impurity concentration of the protection region 32 may be the same as or different from that of the protection region 33.

[0086] The ohmic electrode 70 is formed on a part of the upper surface of the source region 40 and a part of the upper surface of the contact region 35. Then, the source electrode 80 is formed to cover the ohmic electrode 70 and the Schottky electrode 71A.

[0087] Meanwhile, the drain electrode 84 is formed on the lower surface of the semiconductor substrate 10.

[0088] Next, the operation of the SiC MOSFET with the built-in trench-type Schottky diode as a semiconductor device according to the present embodiment will be described.

[0089] First, the case of a backflow operation is described.

[0090] In a similar way to the case of the SiC MOSFET with the built-in planar type Schottky diode, when the current density is low, the return current flows entirely to the Schottky diode and does not flow to the body diode, in return operation.

[0091] Meanwhile, when the current density is high, a voltage greater than about 2 V occurs as a voltage breakdown, which occurs in the Schottky interface and the separation region 34 as a region sandwiched by the Schottky trench 303 and the gate trench 302, and is applied to the parallel-arranged pn junction, and current conduction in the body diode starts.

[0092] In order to increase the current density in this case, ie, the maximum unipolar current density, it is effective to increase the n-type concentration of the separation region 34 or to increase the depth of the separation region 34 (ie, to increase the depth of the gate trench 302 and the Schottky trench 303) so that the resistance of the separation region 34 is reduced.

[0093] However, in any method, the electric field intensity applied to the Schottky interface or the PN junction region increases in the off state of the transistor.

[0094] Here, when the Schottky trench 303 is arranged in a meandering shape, as in the present embodiment, the separation region 34 is also arranged in a meandering shape, according to the meandering shape of the Schottky trench 303. Here, the region in which the Schottky trench 303, which is meandering so as to have a zigzag shape, is folded back in the direction Y is a folding region 304. In Fig. 12, the plurality of folding regions 304 are arranged at a regular spacing. However, the spacing of the folding regions 304 may not be constant.

[0095] In such a case, the amount of electrons flowing via the Schottky diode can be increased without increasing the n-type concentration and the depth of the separation region 34 (ie, without increasing the depths of the gate trench 302 and the Schottky trench 303), and the maximum unipolar current density can be increased.

[0096] Next, a case is described where the transistor is in the off state.

[0097] When the transistor is in the off state, the electric field is easily concentrated in the PN junction region formed by the protection region 32 and the drift layer 20 and in the PN junction region formed by the protection region 33 and the drift layer 20.

[0098] Reducing the depth of the isolation region 34 (i.e., reducing the depth of the gate trench 302 and the Schottky trench 303) is considered a method for reducing the electric field concentration in the PN junction region formed by the isolation region 32 and the drift layer 20, and in the PN junction region formed by the protection region 33 and the drift layer 20. As the depths of the gate trench 302 and the Schottky trench 303 are reduced, the potential fluctuation in the isolation region 34 decreases in the off-state of the transistor. Consequently, the electric field concentration in the PN junction region formed by the protection region 32 and the drift layer 20, and in the PN junction region formed by the protection region 33 and the drift layer 20 can be reduced.

[0099] As in Fig. As illustrated in Figure 13, the gate insulating layer 50A is formed on the upper surface of the protection region 32, and the gate insulating layer 50A divides the voltage applied to the entire device by applying the reverse voltage in the off-state of the transistor. Consequently, the electric field at the PN junction region formed by the protection region 32 and the drift layer 20 is reduced. Consequently, the electric field is easily concentrated in the PN junction region formed by the protection region 33 and the drift layer 20 without an electric field dividing layer at the upper part.

[0100] Consequently, when the depth of Schottky trench 303 is equal to or smaller than that of gate trench 302, the electric field on the PN junction region formed by protection region 33 and drift layer 20 can be reduced. Consequently, element breakdown in the off-state of the transistor can be suppressed.

[0101] In addition, when the depth of Schottky trench 303 is equal to or smaller than that of gate trench 302, the electric field on Schottky electrode 71 can also be reduced. Consequently, stray current can be suppressed in the case of the transistor's off state.

[0102] For the above reason, if the depth of the Schottky barrier trench 303 is set to be equal to or smaller than that of the gate trench 302, when the separation region 303 is arranged in a meandering shape, the electric field concentration in the body diode formed by the protection region 33 and the drift layer 20 is suppressed in the off-state of the transistor, and breakdown of the element can be prevented. Furthermore, the electric field on the Schottky barrier electrode 71 can be reduced, and stray current can be suppressed.

[0103] As described above, according to the semiconductor device of the present embodiment, the operation of the body diode in the reverse flow mode is suppressed. Consequently, the maximum unipolar current density can be increased, and breakdown of the element in the off-state of the transistor can be suppressed. Furthermore, the stray current can also be reduced, and the trade-off relationship between the two can be improved.

[0104] When Al ions are implanted to form the well region 30, the ion implantation is performed while the separation region 21 is covered with, for example, a photoresist. At this time, the photoresist may fall off in some cases. As the width of the separation region 21 decreases, the dimensions of the photoresist to be used also decrease. Consequently, the photoresist is prone to falling off.

[0105] Meanwhile, in the present embodiment, the separation region 21 is arranged in a meandering shape. Consequently, the photoresist used in the Al ion implantation is also formed in a meandering shape. In this case, the photoresist falls more difficult than in the case where the photoresist is formed in a straight line. Consequently, the occurrence of a pattern defect can be suppressed.

[0106] Fig. 3 is a schematic view showing a structure of the plan view in Fig. 1, which is repeatedly and continuously arranged in the X direction and the Y direction. Fig. For simplicity, Figure 3 illustrates only the separation region 21, the well region 30, and the separation region 22. In the following, the structure of the planar-type SiC MOSFET with the built-in Schottky diode is mainly assumed. However, a trench-type SiC MOSFET with the built-in Schottky diode can also be used as an alternative, as appropriate. Fig. 12 and Fig. 13, which are described above. In such a case, the meandering formation of the separation region 21 can be conveniently interpreted as the Schottky trench 303.

[0107] In Fig. 3, the p-type well regions 30, which substantially correspond to the MOSFET in plan view, are formed to sandwich the n-type separation region 21, which substantially corresponds to the Schottky diode in plan view, in the Y direction. Then, bands of the well regions 30, which sandwich the separation region 21 and extend in the X direction, are repeatedly arranged in a stripe shape in the Y direction. Such an arrangement is referred to as a "stripe type."

[0108] In the above stripe type, when the plane orientation of the upper surface (first principal surface) of the semiconductor substrate 10 is the (0001) plane having a skew angle in the <11-20> direction, the stripe-like well regions 30 extending in the X direction may be formed parallel to the <11-20> direction (ie, an off-direction), or they may also be formed parallel to a direction perpendicular to the off-direction.

[0109] If the area where the MOSFET is formed with the built-in Schottky diode, which is in Fig. 3, as an example, is referred to as the active region. In a case where the cycle is constant, in which the separation region 21 extends in the X direction and the Y direction, that is, when the cycle of the meandering formation is constant, the maximum unipolar current density in the active region in a semiconductor chip becomes uniform, and the performance of the element can be improved. However, the cycle of the meandering formation can be appropriately changed according to the formation position of the active region in the semiconductor chip.

[0110] Fig. 4 is a plan view of a terminal part of the active region in the MOSFET with the built-in Schottky diode as the semiconductor device according to the present embodiment. Fig. 4 illustrates an active region C in which the cycle of the meandering of the separation region 21 is constant, a near-end active region D in which the cycle of the meandering of the separation region 21 is not constant, and a terminal end region B (active region end) of the active region. The near-end active region D is arranged to surround the active region C. The terminal end region B of the active region is arranged to surround the near-end active region D.

[0111] The current density of the Schottky diode tends to be small in the terminal end region B of the active region. As shown in Fig. Therefore, as exemplified in Figure 4, the cycle of the meandering shape of the separation region 21 in the active region C is constant, and the number of meandering shapes of the separation region 21 is increased (i.e., the cycle of the meandering shape is shortened) in the vicinity of the active region end region D. Consequently, the current density of the Schottky diode in the vicinity of the active region end region D can be increased. Consequently, a reduction in the maximum unipolar current that may occur in the terminal end region B of the active region during the reflow operation can be suppressed, and the performance of the element can be improved.

[0112] Fig. 1 illustrates an example in which the separation region 21 includes the folding region 221, which has a part running along the X direction and a part running along the Y direction perpendicular to the X direction, thereby meandering. However, it is sufficient for the separation region 21 to have a component running along the X direction and a component running along the Y direction.

[0113] That is, as in Fig. 5, it is conceivable that the separation region 21A includes the folding region 221A having a portion extending in two directions inclined with respect to the X direction, arranged to be repeatedly bent. There is no limitation on the direction in which the separation region extends. Thus, the portion may extend in three or more directions. Fig. 5 is a plan view of a modification example of the MOSFET with the built-in Schottky diode as a semiconductor device according to the present embodiment. Modification example

[0114] Fig. 6 is a plan view of a modified example of the MOSFET with the built-in Schottky diode as a semiconductor device according to the present embodiment. When the separation region 21B is bent, the separation region 21B may be bent in a curved shape in the folding region 221B, as shown in Fig. 6 is exemplified. When the separation region 21B is bent in the curved shape in plan view, the change in the width of the separation region 21B upon bending (that is, the change in the width in the Y direction, the width in the direction inclined in the X direction and the Y direction, and the width in the X direction) decreases. Consequently, the electric field concentration in the PN junction region formed by the separation region 21B and the well region 30 in the off-state of the transistor is easily reduced.

[0115] When the separation region 21B is bent into a curved shape, there is no limitation on its curvature, and its width must be constant as long as the width is equal to or smaller than that of the separation region 22. When the width of the separation region 21B is constant, electric field concentration hardly occurs in the off state of the transistor. Consequently, the element is hardly damaged.

[0116] When the area where the separation region 21B is bent is formed into a curved shape, a corner region becomes a curved region. Consequently, the electric field concentration in the region is reduced. Second embodiment

[0117] A semiconductor device related to the present embodiment will be described. In the following description, the same reference numerals as those described in the above embodiment are assigned to similar elements in the diagrams, and detailed descriptions thereof will be omitted as appropriate. Configuration of the semiconductor device

[0118] Fig. 7 is a plan view of the MOSFET with the built-in Schottky diode as a semiconductor device according to the present embodiment.

[0119] A separation region 21C includes a folding region 221C having a part extending in two directions inclined with respect to the X direction (a direction inclined with respect to the Y direction). Thus, it is arranged to be repeatedly bent in a zigzag shape between the well regions 30. Unlike the separation region 21A, the separation region 21C does not include a part as a component only in the Y direction (i.e., a part between the folding regions 221A).

[0120] A pattern of the separation region 21C in the present embodiment is simple. Therefore, pattern breakdown hardly occurs when forming the pattern using a photoresist.

[0121] As the cycle for bending the separation region 21C into the zigzag shape becomes shorter, the area of ​​the Schottky diode increases. Consequently, the current-carrying capacity of the Schottky diode increases, and the maximum unipolar current density increases.

[0122] The cycle for bending the separation region 21C in the zigzag shape or the width of the separation region 21 need not be constant, but may also be applied to a stripe type or a lattice type (an arrangement in which the separation region 22 is arranged in a lattice shape in plan view).

[0123] When the separation region 21C is bent, the separation region 21C may be bent in a curved shape. There is also no limitation on the number of times the separation region 21C is bent. Modification example

[0124] Fig. 8 is a plan view of a modification example of the MOSFET with the built-in Schottky diode as a semiconductor device according to the present embodiment.

[0125] In Fig. 8, the separation region 22C has a folding region 222C with a portion extending in two directions inclined with respect to the X direction, in the same cycle as the cycle for bending the separation region 21C into the zigzag shape (i.e., the cycle for forming the folding region 221C). Thus, it is arranged to be repeatedly bent. The plan view shapes of the well region 30C, the contact region 35C, and the source region 40C also change according to the above configuration.

[0126] The separation region 22C is arranged to be bent in a zigzag shape so that the cycle for bending the separation region 22C (i.e., the cycle for forming the folding region 222C) coincides with the cycle for bending the separation region 21C (i.e., the cycle for forming the folding region 221C). Consequently, the separation region 21C and the separation region 22C are parallel to each other in the X direction, and the pitch of the cells in the Y direction in Fig. 8 can be reduced. Consequently, the semiconductor chip can be made smaller.

[0127] The cycle or width for bending the separation region 22C into the zigzag shape does not need to be constant. When the separation region 21C and the separation region 22C are bent, the separation region 21C and the separation region 22C can be bent in a curved shape. There is no limit to the number of times the separation region 21C is bent. Third embodiment

[0128] A semiconductor device related to the present embodiment will be described. In the following description, the same reference numerals as those described in the above embodiment are assigned to similar elements in the diagrams, and detailed descriptions thereof will be omitted as appropriate. Configuration of the semiconductor device

[0129] The cell structure is not limited to the stripe type. For example, the grid type is also applicable. Fig. 9 is a plan view of the MOSFET with the built-in Schottky diode as a semiconductor device according to the present embodiment. In the first embodiment and the second embodiment, the separation region 21, which is arranged to be bent, is repeatedly arranged side by side in one direction (Y direction) in the plan view. However, in the present embodiment, a lattice-like cell including the separation region 21 is repeatedly arranged separately from each other in each of the X direction and the Y direction. Such a structure is referred to as "the lattice type."

[0130] In Fig. 9, a separation region 21D having a folding region 221D with a part extending along the X direction and a part extending along the Y direction perpendicular to the X direction, so as to be bent, is arranged separately from each other in the X direction and the Y direction. Then, the well region 30D is repeatedly arranged separately from each other in the X direction and the Y direction while sandwiching the separation region 21D. Furthermore, the contact region 35D is repeatedly arranged separately from each other in the X direction and the Y direction while sandwiching the well region 30D.

[0131] Furthermore, the source region 40D is repeatedly arranged separately from each other in the X direction and the Y direction while sandwiching the contact region 35D. Furthermore, the well region 30D is repeatedly arranged separately from each other in the X direction and the Y direction while sandwiching the source region 40D. Furthermore, the separation region 22D is arranged to extend in the X direction and the Y direction while dividing the well region 30D in the lattice shape.

[0132] Fig. 10 is a schematic view illustrating an example of a grid-type cell arrangement. Fig. 10 illustrates only the separation region 21D, the well region 30D and the separation region 22D.

[0133] In the lattice type, a unit cell region formed of the n-type separation region 21D substantially corresponding to the Schottky diode and the p-type well region 30D substantially corresponding to the MOSFET is divided by the separation region 22D, and is repeatedly arranged in the direction and the Y direction in the plan view.

[0134] The separation region 21D is arranged to be repeatedly bent, as in the first and second embodiments. Then, the well region 30D is arranged to surround the separation region 21D. There is no limitation on the number of times the separation region 21D is bent in the unit cell region. Therefore, it can be bent multiple times. The cycle or the number of bends of the separation region 21D in each unit cell region can be appropriately changed according to the formation position in the semiconductor chip. Fourth embodiment

[0135] A power converter device related to the present embodiment will be described. In the following description, the same reference numerals as those described in the above embodiment are assigned to similar elements in the diagrams, and detailed descriptions thereof will be omitted as appropriate. Configuration of the power converter device

[0136] In the present embodiment, the semiconductor device relating to the first embodiment, the second embodiment, and the third embodiment is used with a power converter device. The present invention is not limited to a power converter device. However, the case where the present invention is used with a three-phase inverter will be described below as a fourth embodiment.

[0137] Fig. 11 is a block diagram illustrating a configuration of a power conversion system to which a power conversion device according to the present embodiment is applied.

[0138] The power converter system, which is exemplified in Fig. 11 includes a power source 100, a power converter device 200, and a load 300. The power source 100 is a direct current power source and supplies direct current power to the power converter device 200. The power source 100 may be formed from various components. Thus, for example, it may be formed from a direct current system, a solar battery, or a secondary battery, and it may also be formed from a rectifier circuit connected to an alternating current system or an AC / DC converter. The power source 100 may also be formed from a DC / DC converter that converts direct current power output from a direct current system into predetermined power.

[0139] The power converter device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 11, the power converter device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs the AC power, a drive circuit 202 that outputs a drive signal that drives each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal that controls the drive circuit 202 to the drive circuit 202.

[0140] The load 300 is a three-phase electric motor powered by the AC power supplied by the power converter device 200. The load 300 does not serve a specific purpose, but rather is an electric motor mounted on various types of electrical devices. Thus, it is used, for example, as an electric motor for a hybrid car, an electric car, a rail vehicle, an elevator, or an air conditioner.

[0141] Details of the power conversion device 200 will be described below. The main conversion circuit 201 includes a switching element and a flyback diode (not shown here). When the switching element is switched, the main conversion circuit 201 converts the DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201. The main conversion circuit 201 according to the present embodiment is a three-phase, two-level full-bridge circuit, and it may be formed of six switching elements and six flyback diodes, each connected in antiparallel to the switching elements.

[0142] The semiconductor device according to any one of the first embodiment, the second embodiment, and the third embodiment is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series two by two, forming upper and lower arms, and each pair of upper and lower arms forms each phase (U-phase, V-phase, and W-phase) of a full-bridge circuit. Then, the output terminals of each pair of upper and lower arms, i.e., three output terminals of the main conversion circuit 201, are connected to the load 300.

[0143] The driver circuit 202 generates the drive signal that drives the switching element of the main conversion circuit 201 and supplies the drive signal to a control electrode of the switching element of the main conversion circuit 201. Specifically, the driver circuit 202 outputs a drive signal that causes the switching element to enter an on-state and a drive signal that causes the switching element to enter an off-state to a control electrode of each switching element according to a control signal from the control circuit 203, as described below.

[0144] When the switching element is kept in the on state, the drive signal is a voltage signal (turn-on signal) equal to or greater than a threshold voltage of the switching element, and when the switching element is kept in the off state, the drive signal is a voltage signal (turn-off signal) equal to or less than the threshold voltage of the switching element.

[0145] The control circuit 203 controls the switching element of the main conversion circuit 201 so that a desired electrical power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on-time) at which each switching element of the main conversion circuit 201 should enter the on-state based on the electrical power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 using PWM control, which modulates the on-time of the switching element according to the voltage to be output.

[0146] Then, the control circuit 203 outputs a control command (a control signal) to the driver circuit 202 so that the turn-on signal is output to the switching element that is to enter the on state and the turn-off signal is output to the switching element that is to enter the off state at each time point. The driver circuit 202 outputs the turn-on signal or the turn-off signal as the drive signal to the control electrode of each switching element according to the control signal.

[0147] In the power converter device 200 concerning the present embodiment, the semiconductor device concerning the first embodiment, the second embodiment, and the third embodiment is used as the switching element of the main conversion circuit 201. Consequently, a power converter device 200 with low losses and increased reliability in high-speed switching can be achieved.

[0148] In the present embodiment, an example in which the present invention is applied to a three-phase, dual-level inverter is described. However, the present invention is not limited to this, and it can be applied to various power conversion devices. The dual-level power conversion device 200 is described in the present embodiment. However, a three-level or multi-level power conversion device can also be applied, and the present invention can be applied to a single-phase inverter when the electric power is supplied to a single-phase load. For example, when the electric power is supplied to a DC load, the present invention can also be applied to a DC / DC converter or an AC / DC converter.

[0149] The power converter device using the present invention can be used not only in the case where the above-mentioned load is the electric motor, but also as a power source device of an electric discharge machine, a laser beam machine, an induction heating cooking device, or a wireless charging system, and further, it can also be used as a power conditioner of a solar power system or an electricity storage system, for example. Effects produced by the embodiments described above

[0150] Examples of the effects produced by the above embodiments are described below. Note that in the following description, the effects are described based on the specific configurations exemplified in the above-described embodiments. However, other specific configurations may be used instead of the configurations exemplified in the description of the present invention, within the scope that produces similar effects. That is, in the following description, only one of the associated specific configurations is occasionally described as a representative. However, the specific configuration described as a representative may be replaced with the other associated specific configuration.

[0151] The exchange can also be carried out with a plurality of embodiments. That is, each of the configurations described by way of example in the various embodiments can be combined with another and produce the same effects.

[0152] According to the embodiments described above, the semiconductor device includes: the drift layer 20 of the first conductivity type (n-type); the plurality of well regions 30 (or the well region 30C and the well region 30D) of the second conductivity type (p-type), the n-type source region 40 (or the source region 40 and the source region 40D), the first n-type separation region, the second n-type separation region, the gate insulating layer 50, the gate electrode 60, the Schottky electrode 71, the ohmic electrode 70, and the source electrode 80.

[0153] Here, the first separation region corresponds, for example, to at least one of the separation region 21, the separation region 21A, the separation region 21B, the separation region 21C, and the separation region 21D. The second separation region corresponds, for example, to at least one of the separation region 22, the separation region 22C, and the separation region 22D. The drift layer 20 is arranged on the upper surface of the n-type semiconductor substrate 10. The well region 30 is arranged separately from each other on the surface layer of the drift layer 20. The source region 40 is arranged on the surface layer of the well region 30.

[0154] The separation region 21 is the region between the plurality of well regions in the surface layer of the drift layer 20. The separation region 22 is the region between the plurality of well regions in the surface layer of the drift layer 20, and it is the region different from the separation region 21. The gate insulating layer 50 is arranged to make contact with the well region 30 sandwiched between the source region 40 and the drift layer 20. The gate electrode 60 is arranged to make contact with the gate insulating layer 50. The Schottky electrode 71 is arranged on the upper surface of the separation region 21 to form a Schottky junction with the separation region 21.

[0155] The ohmic electrode 70 is arranged on the upper surface of the source region 40. The source electrode 80 is arranged to be in contact with the Schottky electrode 71 and the ohmic electrode 70. Then, the separation region 21 extends in the first direction and the second direction, which is different from the first direction in the plan view. Here, the first direction corresponds to, for example, the X direction. The second direction corresponds to, for example, the Y direction. The first separation region 21 has at least a first folding region folded back in the Y direction. Here, the first folding region corresponds to, for example, at least one of the folding region 221, the folding region 221A, the folding region 221B, the folding region 221C, and the folding region 221D. The separation region 22 extends in at least the X direction in the plan view.The width of the separation area 22 in the direction Y is equal to or greater than the width of the separation area 21 in the direction X or the direction Y.

[0156] According to such a configuration, the folding region 221 is arranged at the separation region 21. Consequently, the amount of electrons flowing to the Schottky diode can be increased without increasing the n-type concentration and the width of the separation region 21, and the maximum unipolar current density can be increased. Meanwhile, the width of the first separation region 21 is smaller than that of the second separation region 22. Consequently, the electric field at the PN junction region formed by the separation region 21 and the well region 30 can be reduced. Consequently, the maximum unipolar current density can be increased while reducing the electric field on the body diode in the off-state of the transistor.

[0157] Even in the case where the other configurations other than the configurations exemplified in the description of the present invention are appropriately added to the above-described configuration, that is, the other configurations other than the configurations in the description of the present invention that are not referred to as the above-described configurations are appropriately added, similar effects can be achieved.

[0158] According to the embodiment described above, a plurality of folding regions 221 are provided in the separation region 21. With such a configuration, the folding region 221 is repeatedly provided. Consequently, the separation region 21 can have a meandering shape. Consequently, the value of electrons flowing through the Schottky diode can be increased without increasing the n-type concentration and the width of the separation region 21, and the maximum unipolar current density can be increased.

[0159] According to the embodiment described above, the folding region 221 of the separation region 21 is arranged at a constant pitch interval. With such a configuration, the cycle (pitch interval) of the meandering of the separation region 21 is constant. Consequently, the maximum unipolar current density in the active region in the semiconductor chip becomes uniform, and the performance of the element can be improved. Various calculations confirm the effects of improving the maximum unipolar current density by the structure.

[0160] According to the above-described embodiment, the separation region 21 has a zigzag shape in plan view. According to such a configuration, the folding region 221 repeatedly arranged can make the separation region 21 into a zigzag shape. Consequently, the amount of electrons flowing via the Schottky diode can be increased without increasing the n-type concentration and the width of the separation region 21, and the maximum unipolar current density can be increased. The separation region 21 is formed in a meander shape to have a zigzag shape. Consequently, the photoresist used in the Al ion implantation is also formed in a meander shape. In this case, the photoresist falls more difficult than in the case where the photoresist is formed straight. Consequently, the occurrence of a pattern defect can be suppressed.

[0161] According to the embodiment described above, the separation region 22C extends in the Y direction in plan view. The separation region 22C has at least a first second folding region folded back in the Y direction. Here, the second folding region corresponds, for example, to the folding region 222C. The folding region 221C and the folding region 222C are arranged to correspond to each other. Consequently, the separation region 21C and the separation region 22C extend parallel to each other in the X direction. According to such a configuration, the separation region 21C and the separation region 22C extend parallel to each other in the X direction, and the pitch of the cells in the Y direction in Fig. 8 can be reduced. Consequently, the semiconductor chip can be made smaller.

[0162] According to the embodiments described above, the X direction is perpendicular to the Y direction. The well region 30 (or the well region 30C) and the gate electrode 60 have a stripe shape extending in the X direction in plan view. According to such a configuration, the meandering separation region 21 can be continuously arranged in the X direction. Consequently, the current density in the Schottky diode in the semiconductor chip can be more easily uniformed than in the case where the separation region 21 is intermittently arranged in the X direction. According to such a configuration, the meandering shape extends in mutually perpendicular directions. Consequently, layout can be easily performed.

[0163] According to the embodiment described above, the folding region 221B has a curved shape in plan view. According to such a configuration, the width of the separation region 21B is reduced when the separation region 21B is bent. Consequently, the electric field concentration in the PN junction region formed by the separation region 21B and the well region 30 in the off-state of the transistor is easily reduced.

[0164] According to the above-described embodiments, the semiconductor device includes the trench passing through the well region 30 and reaching the drift layer 20. Then, the gate insulating layer 50 is formed to cover the lateral surface of the well region 30, which is sandwiched between the source region 40 and the drift layer 20 in the trench. The gate electrode 60 is formed to be surrounded by the gate insulating layer 50 in the trench. According to such a configuration, the invention described in the above-described embodiment can be applied not only to the planar gate type MOSFET but also to the trench gate type MOSFET.

[0165] According to the above-described embodiments, the power conversion device includes the above-described semiconductor device, and further includes the main conversion circuit 201 that converts the input electrical power and outputs the converted electrical power, the drive circuit 202 that outputs the drive signal for driving the semiconductor device to the semiconductor device, and the control circuit 203 that outputs the control signal for controlling the drive circuit 202 to the drive circuit 202. According to such a configuration, the above-described semiconductor device is used. Consequently, the maximum unipolar current density can be increased while reducing the electric field on the body diode in the off-state of the transistor. Modification example of the above-described embodiments

[0166] In the above-described embodiments, the material properties, materials, dimensions, shapes, relative arrangement relationships, implementation conditions, etc. may be described for the respective elements. However, these are only an example in all aspects, and they are not limited to the description of the present invention.

[0167] Accordingly, it is understood that countless modification examples and equivalents not described by way of example can be used without departing from the scope of the invention described in the specification of the present application. For example, the following cases are involved, in which at least one of the elements is to be modified, added, or omitted, further extracting at least one of the elements of at least one of the embodiments and then combining it with the elements of the other embodiment.

[0168] In addition, in at least one of the embodiments described above, the following applies: When names of materials are mentioned, an alloy of the material and other additives, etc., are also included, as far as this is consistent with the embodiments, unless otherwise specified.

[0169] The "one" element described in the above-described embodiments may be "one or more" elements as long as this is consistent with the embodiments.

[0170] Furthermore, individual elements are conceptual units. Thus, within the scope of the invention described in the specification of the present invention, an element may have multiple structures, an element may correspond to a portion of any structure, and multiple elements may be contained within a single structure.

[0171] Each element has a structure having a different configuration or a different shape, as long as the structure of the different configuration or the different shape achieves the same function in each element in the embodiments described above.

[0172] What is described in the specification of the present application is incorporated by reference for all purposes with respect to the present invention. Accordingly, it is not admitted that any of the descriptions contained herein represent conventional techniques. List of reference symbols 10 Semiconductor substrate 20 Drift layer 21 Separation area 21A Separation area 21B Separation area 21C Separation area 21D separation area 22 Separation area 22C Separation area 22D separation area 30 Bath area 30C tub area 30D tub area 32 Protection area 33 Protection area 34 Separation area 40 Source area 40C source range 40D Source Area 50 Gate insulating layer 50A gate insulation layer 60 Gate electrode 60A gate electrode 70 ohm electrode 71 Schottky electrode 71A Schottky electrode 80 Source electrode 200 power converter device 201 Main conversion circuit 202 driver circuit 203 Control circuit 221 Folding area 221A Folding area 221B Folding area 221C folding area 221D folding area 222C folding area 302 Gate Trench 303 Schottky trench 304 Folding area QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2018- 49 951 A

[0005]

Claims

[1] Semiconductor device comprising: a drift layer of a first conductivity type disposed on an upper surface of a semiconductor substrate of the first conductivity type; a plurality of well regions of a second conductivity type arranged separately from each other on a surface layer of the drift layer; a source region of the first conductivity type arranged on a surface layer of at least one of the well regions; a first separation region of the first conductivity type as a region between the plurality of well regions on the surface layer of the drift layer; a second separation region of the first conductivity type as a region different from the first separation region between the plurality of well regions of the surface layer of the drift layer; a gate insulating layer arranged to be in contact with at least one of the well regions sandwiched between the source region and the drift layer; a gate electrode arranged to be in contact with the gate insulating layer; a Schottky electrode disposed on an upper surface of the first separation region so as to have a Schottky junction with the first separation region; an ohmic electrode disposed on an upper surface of the source region; and a source electrode arranged to be in contact with the Schottky electrode and the ohmic electrode, wherein the first separation region extends in a first direction and a second direction as a direction which is different from the first direction in plan view, the first separation region has at least one first folding region which is folded back in the second direction, the second separation region extends in at least the first direction in plan view, and the width of the second separation region in the second direction is equal to or greater than the width of the first separation region in the first direction or the second direction. [2] The semiconductor device according to claim 1, wherein there are a plurality of first folding regions of the first separation region. [3] The semiconductor device according to claim 2, wherein the first folding region of the first separation region is arranged at a regular pitch. [4] The semiconductor device according to claim 2 or 3, wherein the first separation region has a zigzag shape in plan view. [5] A semiconductor device according to any one of claims 1 to 4, wherein the second separation region extends in the second direction in plan view, the second separation region has at least one second folding region which is folded back in the second direction, and the first folding region and the second folding region are arranged so as to correspond to each other, and consequently the first separation region and the second separation region are parallel to each other in the first direction. [6] Semiconductor device comprising: a drift layer of a first conductivity type disposed on an upper surface of a semiconductor substrate of the first conductivity type; a plurality of well regions of a second conductivity type arranged separately from each other on a surface layer of the drift layer; a source region of the first conductivity type arranged on a surface layer of at least one of the well regions; a first trench arranged to extend into the interior of the drift layer from an upper surface of at least one of the well regions; a second trench disposed at a position different from the first trench so as to extend into the interior of the drift layer from an upper surface of at least one of the well regions; a separation region sandwiched between the first trench and the second trench; a gate insulating layer covering a lateral surface of at least one of the well regions sandwiched between the source region and the drift layer in the second trench; a gate electrode formed to be surrounded by the gate insulating layer in the second trench; a Schottky electrode having a Schottky junction with the separation region in the first trench; an ohmic electrode disposed on an upper surface of the source region; and a source electrode arranged to be in contact with the Schottky electrode and the ohmic electrode, where the first trench extends in a first direction and a second direction as a direction different from the first direction in plan view, the first trench has at least a first folding region, which is folded back in the second direction, the second trench runs in at least the first direction in plan view, and the depth of the second trench from an upper surface of at least one of the well regions is equal to or greater than the depth of the first trench from the upper surface of at least one of the well regions. [7] The semiconductor device according to claim 6, wherein there are a plurality of first folding regions of the first trench. [8] The semiconductor device according to claim 7, wherein the first folding region of the first trench is arranged at a regular pitch. [9] The semiconductor device according to claim 7 or 8, wherein the first trench has a zigzag shape in plan view. [10] A semiconductor device according to any one of claims 6 to 9, wherein the second trench extends in the second direction in plan view, the second trench has at least one second folding region folded back in the second direction, and the first folding region and the second folding region are arranged to correspond to each other, and consequently the first trench and the second trench are parallel to each other in the first direction. [11] A semiconductor device according to any one of claims 1 to 10, wherein the first direction is perpendicular to the second direction, and the gate electrode and at least one of the well regions have a stripe shape extending in the first direction in plan view. [12] The semiconductor device according to any one of claims 1 to 10, wherein the first folding region has a curved shape in plan view. [13] Power converter device comprising: a main conversion circuit comprising a semiconductor device according to any one of claims 1 to 12, converting input electrical energy and outputting the electrical energy; a driver circuit that outputs a driver signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the driver circuit to the driver circuit.

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