GATE DRIVE MODULE AND DISPLAY PANEL

Abstract

Gate drive module (10) comprising a frequency division signal line (FDL) and several cascaded gate driver circuits (20), wherein the frequency division signal line (FDL) is used to transmit frequency division control signals (FD) to the several gate driver circuits (20), and wherein the gate driver circuit (20) comprises the following: a cascade transmission unit (201) comprising a cascade transmission receiver unit (2011) and a cascade transmission output unit (2012), wherein the cascade transmission receiver unit (2011) is used to receive the cascade transmission signals generated by the gate driver circuit (20) of the upper stage, and wherein the cascade transmission output unit (2012) is electrically connected to the cascade transmission receiver unit (2011) via a first node (P) and a second node (Q) and is used to output the cascade transmission signals of the present stage to the gate driver circuit (20) of the lower stage in accordance with the signal of the first node (P) and the signal of the second node (Q); an output unit (202) which is electrically connected to the cascade transmission output unit (2012) by one of the first node (P) and the second node (Q) and a third node (S) and is used to output a gate control signal in accordance with the signal of one of the first node (P) and the second node (Q) and the signal of the third node (S);and a cascade transmission frequency division control unit (203) which is electrically connected to the cascade transmission receiving unit (2011) via the first node (P) or the second node (Q) and electrically connected to the cascade transmission output unit (2012) via a fourth node (R) and is used to control, in accordance with the frequency division control signal (FD), the signal of one of the first node (P) and the second node (Q) to drive the cascade transmission output unit (2012) to output the cascade transmission signal of the present stage; and ; an output frequency division control unit (204) which is connected between one of the first node (P) and the second node (Q) and the third node (S) and is used to control the signal of the third node (S) in accordance with the frequency division control signal (FD) in order to drive the output unit (202) to output the gate control signal of the present stage, the cascade transmission receiving unit (2011) comprises the following: a control unit (20111) for the fourth node (R) which is electrically connected to a clock signal line and the fourth node (R) to control the signal of the fourth node (R) in accordance with the clock signal transmitted by the clock signal line; a control unit (20112) for the second node (Q) which is electrically connected to a clock signal line and the second node (Q) to control the signal of the second node (Q) in accordance with the clock signal; an input unit (20114), wherein the input end of the input unit (20114) is electrically connected to the gate driver circuit (20) of the upper stage to load the cascade transfer signal generated by the gate driver circuit (20) of the upper stage, and wherein the output end of the input unit (20114) is electrically connected to the control unit (20111) for the fourth node (R) and the control unit (20112) for the second node (Q) or to the control unit (20111) for the fourth node (R) and a control unit (20113) for the first node (P), wherein the cascade transmission frequency division control unit (203) and the output frequency division control unit (204) are each electrically connected to the first node (P); and wherein the input unit (20114) comprises an input transistor (T3), and wherein the gate of the input transistor (T3) is loaded with the clock signal, and wherein the source of the input transistor (T3) is configured as the input end of the input unit (20114), and wherein the drain of the input transistor (T3) is configured as the output end of the input unit (20114); and wherein the control unit (20111) for the fourth node (R) comprises a first transistor (T4), a seventh transistor (T5), and a second transistor (T6) and third transistor (T7) connected in series, and wherein the gate of the seventh transistor (T5) is electrically connected to the drain of the input transistor (T3), and wherein the source of the seventh transistor (T5) is charged with the clock signal, and wherein the gate of the first transistor (T4) is charged with the clock signal, and wherein the source of the first transistor (T4) is charged with the second voltage, and wherein the drain of the first transistor (T4) is electrically connected to the gate of the second transistor (T6) and the drain of the seventh transistor (T5), and wherein the drain of the second transistor (T6) is electrically connected to the source of the third transistor (T7), and wherein the source of the second transistor (T6) and the gate of the third transistor (T7) are each charged with the clock signal,and wherein the drain of the third transistor (T7) is electrically connected to the fourth node (R); , and wherein the control unit (20112) for the second node (Q) comprises a fourth transistor (T13), a first capacitor (C1), and a fifth transistor (T1) and sixth transistor (T2) connected in series, and wherein the gate of the fourth transistor (T13) is charged with the control signal, and wherein the source of the fourth transistor (T13) is charged with the first voltage, and wherein the drain of the fourth transistor (T13) is electrically connected to the second node (Q), and wherein the gate of the fifth transistor (T1) is electrically connected to the drain of the first transistor (T4), and wherein the source of the fifth transistor (T1) is charged with the first voltage, and wherein the drain of the fifth transistor (T1) is electrically connected to the source of the sixth transistor (T2), and wherein the drain of the sixth transistor (T2) is charged with the clock signal,and wherein the gate of the sixth transistor (T2) is also charged with the cascade transfer signal generated by the gate driver circuit (20) of the upper stage, and wherein the first capacitor (C1) is electrically connected between the gate and the drain of the sixth transistor (T2).

Description

TECHNICAL AREA

[0001] The present application relates to the technical field of display technology, in particular a gate drive module and a display panel. STATE OF THE ART

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used because of their flexibility and other properties.

[0003] The gate driver circuit in the OLED display panel typically outputs stepwise effective pulses to turn on multiple rows of subpixels sequentially, and the refresh rate of the entire display area is the same, making it impossible to drive different areas with different refresh rates, resulting in limited application scenarios.

[0004] Therefore, a shortcoming of existing OLED display panels is that different refresh rates for different areas cannot be achieved, and there is an urgent need for improvements.

[0005] From US patent 2021 / 0201807 A1, a shift register unit, a gate driver circuit, a display device and a control method are known.

[0006] From US patent 2021 / 0335203 A1, a shift register unit is known which includes a first subunit with a first input circuit, which is connected via a first node to a first output circuit. The shift register unit additionally includes a second subunit with a second input circuit, which is connected via a second node to a second output circuit.

[0007] From US patent 2023 / 0142651 A1, a GOA (Gate-on-Array) unit circuit, a control method for it, a GOA circuit with cascaded multiple stages of GOA unit circuits and a display device are known. REVELATION OF THE INVENTION OVERVIEW OF THE INVENTION

[0008] The present application provides a gate drive module and a display panel to enable a drive with different update rates for different areas.

[0009] An embodiment of the present application provides a gate drive module comprising a frequency division signal line and several cascaded gate driver circuits, wherein the frequency division signal line is used to transmit the frequency division control signals to the several gate driver circuits, and wherein the gate driver circuit comprises the following: a cascade transmission unit comprising a cascade transmission receiver unit and a cascade transmission output unit, wherein the cascade transmission receiver unit is used to receive the cascade transmission signals generated by the gate driver circuit of the upper stage, and wherein the cascade transmission output unit is electrically connected to the cascade transmission receiver unit by a first node and a second node and is used to output the cascade transmission signals of the present stage to the gate driver circuit of the lower stage in accordance with the signal of the first node and the signal of the second node; an output unit which is electrically connected to the cascade transmission output unit via one of the first and second nodes and a third node, and which is used to output a gate control signal in accordance with the signal of one of the first and second nodes and the signal of the third node; and a cascade transmission frequency division control unit, which is electrically connected to the cascade transmission receiving unit via the first node or the second node and electrically connected to the cascade transmission output unit via a fourth node, and is used, in accordance with the frequency division control signal, to control the signal from one of the first and second nodes to drive the cascade transmission output unit to output the cascade transmission signal of the present stage; and an output frequency division control unit connected between one of the first nodes and the second node and the third node, and used to control the signal of the third node in accordance with the frequency division control signal in order to drive the output unit to output the gate control signal of the present stage. BENEFICIAL EFFECTS

[0010] The gate drive module and display panel provided by the present application comprise a frequency division signal line and several cascaded gate driver circuits, the gate driver circuit comprising a cascade transmission unit and output unit. A cascade transmission frequency division control unit is electrically connected to the cascade transmission receiving unit via the first or second node (and further electrically connected to the cascade transmission output unit via the fourth node), and an output frequency division control unit is arranged between the first and second nodes and the third node. The two are used to control, in accordance with the frequency division control signal, the signal of a gate connected to the first and second nodes.to control the cascade transmission output unit to output the cascade transmission signal of the present stage, and in accordance with the frequency division control signal, to control the signal of the third node to control the output unit to output the gate control signal of the present stage, so that the invalidity of the gate control signal does not affect the invalidity of the cascade transmission signal, and a sequential down-conversion mode of several areas of a display panel can be realized by setting whether the cascade transmission signal has an effective cascade transmission pulse, and by setting whether the gate control signal has an effective gate pulse (since the effective cascade transmission pulse can always be present), any inverter mode of several areas of a display panel is realized. PRESENTATION OF THE INVENTION

[0011] To clarify the technical solution in the embodiments of the present application, the figures to be used in the explanation of the embodiments are briefly introduced below. Obviously, the figures described below only show some embodiments of the present application. A person skilled in the art can derive other figures from these without any creative effort. Fig. Figure 1 shows a schematic structural view of a gate drive module provided by the embodiment of the present application. Fig. 2 and Fig. Figure 3 each shows a circuit diagram of two gate driver circuits provided by the embodiment of the present application. Fig. 4 and Fig. Figure 5 shows a schematic structural view of a display panel provided by the embodiment of the present application. Fig. 6 and Fig. Figure 7 shows a circuit diagram of a pixel driver circuit provided by the embodiment of the present application. Fig. 8 and Fig. 9 each show a waveform diagram of some of the signals in Fig. 6 and Fig. 7. Fig. Figure 10 shows a waveform diagram of some signals in a single-stage gate driver circuit provided by an embodiment of the present application. Fig. Figures 11 to 16 show a waveform diagram of some signals in a multi-stage gate driver circuit provided by an embodiment of the present application. Fig. Figure 17 shows a waveform diagram of a data signal transmitted over the same data line and two types of frequency division control signals corresponding to two types of gate driver circuits. SPECIFIC EXECUTION FORMS

[0012] In connection with the figures in the embodiments of the present application, the technical solutions in the embodiments of the present application are explained clearly and completely below. Obviously, the described embodiments do not represent all embodiments, but only a subset. All other embodiments that a person skilled in the art in this field could obtain from the embodiments in the present application without any creative work should be considered to be covered by the scope of protection of the present application.

[0013] In the explanatory notes to this application, "the first" and "the second" are used only to explain the objective and cannot be understood as indicating or implying relative importance or as implicitly referring to the number of technical features required. Therefore, the features defined by "the first" and "the second" may explicitly or implicitly include one or more of the features. In this document, no distinction is made between the source and the drain of a transistor, and the two may be interchangeable. The terms "low voltage" and "high voltage" denote two voltages with relatively small values ​​and two voltages with large values, respectively, and may refer to two voltage values ​​of the same signal at different times or to two voltages of different signals at the same time or at different times.It should also be noted that the accompanying drawings only show a structure that is more closely related to the present application, and some details that are not very relevant to the application have been omitted in order to simplify the accompanying drawings and to make the points of the application clear at a glance, rather than indicating that the device in practice is exactly the same as the accompanying drawings, and that the accompanying drawings should not be understood as a limitation of the device in practice.

[0014] The “embodiment” mentioned in the present description means that the specific features, structures, or properties explained in connection with the embodiment may be included in at least one embodiment of the present application. The occurrence of a phrase at different times and in different places in the description does not necessarily refer to the same embodiment or to an independent or alternative embodiment that is mutually exclusive with other embodiments. The person skilled in the art clearly and implicitly understands that the embodiment explained in the description may be combined with another embodiment.

[0015] The present application provides a gate drive module, wherein the gate drive module comprises, but is not limited to, the following embodiments and combinations thereof.

[0016] In one embodiment, the gate drive module 10 comprises a frequency division signal line FDL and several cascaded gate driver circuits 20, as shown in Fig. Figure 1 shows the frequency division signal line FDL being used to transmit the frequency division control signals FD to the multiple gate driver circuits 20, as shown in Fig. 2 and Fig. 3 shown, and wherein the gate driver circuit 20 comprises: a cascade transmission unit 201, comprising a cascade transmission receiver unit 2011 and a cascade transmission output unit 2012, wherein the cascade transmission receiver unit 2011 is used to receive the cascade transmission signals generated by the gate driver circuit 20 of the upper stage, and wherein the cascade transmission output unit 2012 is electrically connected to the cascade transmission receiver unit 2011 by a first node P and a second node Q and is used to output the cascade transmission signals of the present stage to the gate driver circuit 20 of the lower stage in accordance with the signal of the first node P and the signal of the second node Q;an output unit 202, which is electrically connected to the cascade transmission output unit 2012 via a signal from the first node P and the second node Q and a third node S, and is used to output a gate control signal of the present stage in accordance with the signal from a signal from a signal from a first node P and the second node Q and the signal from the third node; a cascade transmission frequency division control unit 203, which is electrically connected to the cascade transmission receiver unit 2011 via the first node P or the second node Q and is electrically connected to the cascade transmission output unit 2012 via a fourth node R, and is used to control the signal from a signal from a signal from a first node P and the second node Q in accordance with the frequency division control signal FD, in order to drive the cascade transmission output unit 2012 to output the cascade transmission signal of the present stage;and an output frequency division control unit 204, which is connected between one of the first node P and the second node Q and the third node S and is used to control the signal of the third node S in accordance with the frequency division control signal FD in order to drive the output unit 202 to output the gate control signal of the present stages.

[0017] In particular, this will be demonstrated using the example in Fig. Figure 1, with n (n≥2) gate driver circuits 20, explains that the gate driver circuit 20 of the first stage can use a first start signal STV1 or a second start signal STV2 (both in opposite phase) as a corresponding "upper stage gate control signal", output the gate control signal Scan(1) of the current stage based on this, and transmit this to the gate driver circuit 20 of the lower stage (stage 2), and so on. The gate driver circuit 20 of the nth stage can generate and output the gate control signal Scan(n) of the current stage (stage n) in accordance with the gate control signal Scan(n-1) of the (n-1)th stage. In Fig. 2 and Fig. Section 3 explains this using the example of the gate driver circuit 20 of the i-th stage. The gate driver circuit 20 of the i-th stage can generate and output the gate control signal Scan(i) of the current stage (stage i) in accordance with the gate control signal Scan(i-1) of the (i-1)-th stage.

[0018] It is understood that, on the basis that the signal of a node electrically connected to the cascade transmission output unit 2012 does not change between the first node P and the second node Q, a cascade transmission frequency division control unit 203 is arranged in the present embodiment, which is connected between the cascade transmission receiver unit 2011 and the cascade transmission output unit 2012, in order to control the signal of the other node from the first node P and the second node Q in accordance with the frequency division control signal FD (whether the fourth node R can influence it), so that the signal transmitted to the cascade transmission output unit 2012 can be controlled, in this way the specific situation of the cascade transmission signal output by the cascade transmission output unit 2012 of the present stage is determined (whether it has an effective cascade transmission pulse).to determine whether it acts as a driver for the gate driver circuit 20 of the next stage. If the cascade transmission signal has an effective cascade transmission pulse, it can be assumed that the cascade transmission receiving unit 20122 in the gate driver circuit 20 of the next stage can operate normally; analogously, in combination with the cascade transmission frequency division control unit 203 of this stage, the specific situation of the cascade transmission signal output by the cascade transmission output unit 2012 of this stage is determined; on the other hand, in the present embodiment, an output frequency division control unit 204 is further arranged, which is connected between the first node P and the second node Q and the third node S in order to control the signal of the third node S in accordance with the frequency division control signal FD.which allows the specific situation of the gate control signal output by the output unit 202 of the present stage to be controlled (i.e., the signal that is transmitted to the corresponding multiple subpixels Pi in the display panel to control whether the subpixels Pi are to be turned on) in order to decide whether the corresponding multiple subpixels Pi are to be turned on when the gate control signal has an effective gate pulse, it can be assumed that the corresponding multiple subpixels Pi can be updated for subsequent light emission.

[0019] It is to be understood that for the multiple gate driver circuits 20, which are cascaded sequentially, if in the multiple gate control signals output by the multiple gate driver circuits 20 of the first section outputs one frame of all n1 frames, in the multiple gate control signals output by the multiple gate driver circuits 20 of the second section outputs one frame of all n2 frames, and in the multiple gate control signals output by the multiple gate driver circuits 20 of the third section outputs one frame of all n3 frames, it can be assumed that three display areas, each formed by the three sections of subpixels Pi corresponding to the gate driver circuits 20 of the three sections, each have the three update rates of (1 / n1)*m, (1 / n2)*m and (1 / n3)*m.where m is the least common multiple of n1, n1, and n1.

[0020] In summary, if, in the present embodiment, the gate control signal used to determine the update rate of any display area of ​​the display panel is directly determined by the associated output frequency division unit and the frequency division control signal FD at that time, wherein one input end of the output frequency division unit is connected to either the first node P and the second node Q, and the other input end is connected to the third node S, and wherein the third node S is connected to either the first node P or the second node Q by a cascade transmission frequency division unit, then it can be assumed that the signal of the third node S is jointly determined by the cascade transmission frequency division unit and the frequency division control signal FD uploaded to the cascade transmission frequency division unit.Therefore, the gate control signal is jointly determined by the cascade transmission frequency division unit, the output frequency division unit, and the frequency division control signal FD uploaded to the cascade transmission frequency division unit and the output frequency division unit. By appropriately adjusting the three factors, the update rate of the assigned display area is determined. Furthermore, the three factors can be appropriately adjusted in the multiple gate driver circuits 20, each assigned to the different display areas of the display panel, in order to achieve different update rates.

[0021] In the present embodiment, it is not restricted whether the cascade transmission frequency division units in different gate driver circuits 20 are set differently, the output frequency division units are set differently, and the time periods in which the frequency division control signal FD is effective are set differently. To simplify the circuit design, the cascade transmission frequency division units and the output frequency division units in the multi-stage gate driver circuit 20 can each be set identically; similarly, the time periods in which the frequency division control signal FD is effective on different gate driver circuits 20 can be set differently in order to adjust the update rate of different display areas.

[0022] In one embodiment, as in Fig. As shown in Figures 1 to 3, the frequency division control signal FD comprises a first frequency division control signal FD1 and a second frequency division control signal FD2, wherein the frequency division signal line FDL comprises a first frequency division signal line FDL1 for transmitting the first frequency division control signal FD1 and a second frequency division signal line FDL2 for transmitting the second frequency division control signal FD2; and wherein the first frequency division signal line FDL is electrically connected to the output frequency division control unit 204 to control the signal of the third node S; and wherein the second frequency division signal line FDL is electrically connected to the cascade transmission frequency division control unit 203 to control the signal of one of the first node P and the second node Q.

[0023] It is understood that in the present embodiment, the frequency division signal line FDL is arranged in particular as an independent first frequency division signal line FDL and a first frequency division signal line, each of which can transmit an independent first frequency division control signal FD1 and second frequency division control signal FD2 (which need not be the same) in order to control the operating state of the output frequency division control unit 204 and the cascade transmission frequency division control unit 203 independently, thereby controlling the specific situation of the cascade transmission signal and gate signal generated by the gate driver circuit 20 of the present stage.

[0024] In particular, the time period in which the first frequency division control signal FD1 according to the gate driver circuit 20 of each stage is effective, and the time period in which the second frequency division control signal FD2 according to the gate driver circuit 20 of each stage is effective, can each be appropriately adjusted to adapt to different situations, and each stage of the gate driver circuits 20 can include, but is not limited to, the following situations: Situation 1: the second frequency division control signal FD2 is adjusted appropriately so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, thereby giving the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 an effective cascade transmission pulse to control the cascade transmission receiver unit 2011 in the next stage of the gate driver circuits 20 so that it can operate normally;

[0025] Based on situation 1, it may include, but is not limited to, the following situations: Situation 1.1: the first frequency division control signal FD1 is adjusted appropriately so that the gate control signal generated and output by the output frequency division unit has an effective gate pulse to control the corresponding multiple subpixels Pi so that they are turned on, namely, the corresponding multiple subpixels Pi are updated for later emission of light; Situation 1.2: the first frequency division control signal FD1 is adjusted appropriately so that the gate control signal generated and output by the output frequency division unit does not have an effective gate pulse to control the corresponding multiple subpixels Pi so that they are not turned on, namely, the corresponding multiple subpixels Pi are not updated for later emission of light.

[0026] If, in situation 1, the time period in which the second frequency division control signal FD2 effectively acts on each stage of the gate driver circuits 20 is arranged such that each stage of the cascade transfer signal has an effective cascade transfer pulse, i.e., each stage of the cascade transfer signal is not interrupted, it can now be controlled by adjusting the first frequency division control signal FD1 whether each stage of the gate control signal has an effective gate pulse.In conjunction with the above explanation, any frequency division of several display areas can be realized (compared to the previous display area, the update rate of the next display area can increase or decrease), namely, in a frame, the gate control signals of the several previous stages and the several next stages are each controlled in such a way that they successively have an effective gate pulse and no effective gate pulse, or successively have no effective gate pulse and an effective gate pulse.

[0027] Situation 2: The second frequency division control signal FD2 is adjusted appropriately so that the signal of the fourth node R cannot affect the signal of the first node P or the signal of the second node Q, thus preventing the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 from having an effective cascade transmission pulse (as determined by the signal of the first node P or the signal of the second node Q) to control the cascade transmission receiver unit 2011 in the next stage of the gate driver circuits 20 in such a way that it cannot operate normally, since the signal of the third node S connected to the source of the output unit 202 is also determined by the signal of the first node P or the signal of the second node Q, it can also be output from it, that the signal of the third node S can also lead toSince the gate control signal of the present stage has no effective gate pulse, it can be assumed that the gate control signals from the present stage to the last stage each have no effective gate pulse, and accordingly, the multiple subpixels Pi cannot be updated for subsequent light emission. In conjunction with the above explanation, only the downconversion of multiple display areas can be realized.

[0028] Situation 3: the first frequency division control signal FD1 is adjusted appropriately so that the output frequency division control unit 204 can control the third node S so that the first node P or the second node Q acts on it, so that the first node P or the second node Q can act on the output unit 202;

[0029] Based on situation 3, it can include, but is not limited to, the following situations: Situation 3.1: The second frequency division control signal FD2 is adjusted appropriately so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, thereby giving the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 an effective cascade transmission pulse to control the cascade transmission receiver unit 2011 in the next stage of the gate driver circuits 20 so that it can operate normally. Since the signal of the first node P or the signal of the second node Q can also act on the third node S to act on the output unit 202, the gate control signal now generated and output by the output frequency division unit also has an effective gate pulse to control the corresponding multiple subpixels Pi to be switched on.namely, the corresponding multiple subpixels Pi are updated for later emission of light; Situation 3.2: The second frequency division control signal FD2 is adjusted appropriately so that the signal of the fourth node R can affect the signal of the first node P or the signal of the second node Q, whereby the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 does not have an effective cascade transmission pulse, as can be seen in “Situation 2”. Now, the signal of the first node P or the signal of the second node Q cannot also render the signal of the third node S ineffective, namely, it also leads to the gate control signal of the present stage not having an effective gate pulse. Therefore, it can be assumed that the gate control signals from the present stage to the last stage each have no effective gate pulse, and accordingly, the several subpixels Pi cannot each be updated for subsequent emission of light.

[0030] If, in situation 3, the time period in which the first frequency division control signal FD1 effectively acts on each stage of the gate driver circuits 20 is arranged such that the first node P or the second node Q acts on the third node S of each stage, it can be controlled by setting the second frequency division control signal FD2 whether the signal of the fourth node R acts on the signal of the first node P or the signal of the second node Q, thereby controlling whether the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 of each stage has an effective cascade transmission pulse. In conjunction with the above explanation, the step-down conversion of multiple display ranges can be realized.

[0031] Situation 4: The first frequency division control signal FD1 is set appropriately so that the output frequency division control unit 204 cannot control the third node S in such a way that the first node P or the second node Q acts upon it, and thus the first node P or the second node Q cannot act upon the output unit 202; i.e., regardless of the signals of the first node P and the signals of the second node Q, the first frequency division control signal FD1 will act upon the output frequency division control unit 204, so that the signal of the third node S causes the gate control signal of the present stage to have no effective gate pulse, therefore it can be assumed that the gate control signals from the present stage to the last stage each have no effective gate pulse, and accordingly, the multiple subpixels Pi each cannot be updated for subsequent emission of light.In conjunction with the above explanation, only the downward conversion of multiple display areas can be implemented.

[0032] In one embodiment, as in Fig. As shown in Figures 1 to 3, the output frequency division control unit 204 comprises the following: a first frequency division transistor T18, wherein the gate of the first frequency division transistor T18 is connected to the first frequency division signal line FDL, and wherein the source of the first frequency division transistor T18 is electrically connected to the first node P or the second node Q, and wherein the drain of the control transistor is electrically connected to the third node S; and wherein the first frequency division control signal FD1 is used to control the third node S to be electrically connected to or disconnected from the first node P or the second node Q.

[0033] In conjunction with the above explanation, it can be seen that the first frequency division control signal FD1 can act on the output frequency division control unit 204 to control the third node S, whether the first node P or the second node Q acts on it; furthermore, in the present embodiment, the third node S can be controlled to be electrically connected to or disconnected from the first node P or the second node Q by the first frequency division control signal FD1 acting on the gate of the first frequency division transistor T18 in the output frequency division control unit 204.

[0034] When they are electrically connected, it can be assumed that the first node P or the second node Q can influence the third node S, namely, it can be controlled by the signal of the first node P or the signal of the second node Q whether the gate control signal generated and output by the output unit 202 has an effective gate pulse (namely situation 3 above); when they are separated, it can be assumed that the first node P or the second node Q cannot influence the third node S, since the first node P or the second node Q, which is used to control the generation of the cascade transmission signal, cannot each influence the output unit 202, it can be assumed that the gate control signal generated and output by the output unit 202 does not have an effective gate pulse (namely situation 4 above).

[0035] In one embodiment, as in Fig. As shown in Figures 1 to 3, the output frequency division control unit 204 further comprises: a second frequency division transistor T20, wherein the gate of the second frequency division transistor T20 is electrically connected to a fifth node of the cascade transmission unit 201, and wherein the source of the second frequency division transistor T20 is electrically connected to the first frequency division signal line FDL, and wherein the drain of the second frequency division transistor T20 is electrically connected to the gate of the first frequency division transistor T18; and wherein the first frequency division control signal FD1 and the signal of the fifth node are used to control the third node S to be electrically connected to or disconnected from the first node P or the second node Q;and wherein the signal of the fifth node is also used to control the cascade transfer signal and gate control signal output by the gate driver circuit 20 of the present stage.

[0036] It understands that in the present embodiment a second frequency division transistor T20 is further arranged, which is electrically connected to the gate of the first frequency division transistor T18, and that the switching on of the second frequency division transistor T20 is determined by the signal of the fifth node, and that the signal of the fifth node is also used to control the cascade transmission signal and gate control signal output by the present stage, namely, it can be assumed that the state of the signal of the fifth node can provide feedback to the state of the cascade transmission signal and gate control signal of the present stage, in this way it can be ensured that the switching on of the second frequency division transistor T20 is only controlled when the state of the cascade transmission signal and gate control signal generated by the present stage is appropriate.so that the first frequency division control signal FD1 is transmitted to the gate of the first frequency division transistor T18 of the present stage to control the switching on of the first frequency division transistor T18, in this way, provided that the cascade transmission signal and the gate control signal of each stage are output as a correct waveform, the differential setting of the update rate of different display areas is realized.

[0037] It should be noted that in the present embodiment, the specific connection relationship between the fifth node and the aforementioned module is not restricted, as long as the above restriction "the signal of the fifth node is also used to control the cascade transfer signal and gate control signal output by the gate driver circuit 20 of the present stage" is satisfied. For example, the fifth node can be electrically connected to the first node P or the second node Q; indeed, the fifth node can be the first node P or the second node Q. In the present application, this is explained by an example in which the fifth node is node D (the second frequency division transistor T20 according to Fig. 2 and Fig. 3 represents one P-type transistor and one N-type transistor, and for each of these two, reference can be made to the analysis via Fig. 10 in the following description).

[0038] In particular, it is relevant in connection with the analysis of Fig. 2 and Fig. 10. To see that the cascade transmission signal generated based on the present stage has an effective cascade transmission pulse (namely, the signal of the first node P and the signal of the second node Q are each an effective signal), if the gate control signal of the present stage must output the effective gate pulse, it can be assumed that it can be ensured in the signal of the fifth node that only the voltages after the time node of the complete output of the effective gate pulse of the present stage (e.g., endpoint of the fifth phase t5 in Fig. 10) can be used to control the transmission of the first frequency division control signal FD1 to the gate of the first frequency division transistor T18 of the present stage, if, for example, the second frequency division transistor T20 is a P-type transistor, it can be assumed that the voltages of the fifth node before and after the time node of the complete output of the effective gate pulse of the present stage are higher and lower voltages respectively, to ensure that the second frequency division transistor T20 can only be switched on after the complete output of the effective gate pulse of the present stage.

[0039] If, in particular, the gate control signal of the present stage does not need to output the effective gate pulse, it can be seen, in conjunction with the above explanation, that the starting point of the time period (voltage step) in which the first frequency division control signal FD1 effectively acts on the present stage is set before the time at which the voltage output by the effective gate pulse of the present stage occurs in the signal of the fifth node (such as the starting point of the third phase t3 in Fig. 10) to ensure that the electrical connection between the third node S and the first node P or the second node Q is broken before the output of the effective gate pulse of the present stage.

[0040] In one embodiment, as in Fig. As shown in Figures 1 to 3, the cascade transmission frequency division control unit 203 comprises the following: a third frequency division transistor T17, wherein the gate of the third frequency division transistor T17 is electrically connected to the second frequency division signal line FDL, and wherein the source of the first frequency division transistor T18 is electrically connected to the cascade transmission receiving unit 2011 via a fourth node R, and wherein the drain of the third frequency division transistor T17 is electrically connected to the first node P or the second node Q; and wherein the second frequency division control signal FD2 is used to control the fourth node R to be electrically connected to or disconnected from the first node P or the second node Q.

[0041] In conjunction with the above explanation, it can be seen that the second frequency division control signal FD2 can act on the cascade transmission frequency division control unit 203 to control the first node P or the second node Q, whether the fourth node R acts on it; furthermore, in the present embodiment, the fourth node R can be controlled to be electrically connected to or disconnected from the first node P or the second node Q by the second frequency division control signal FD2 acting on the gate of the third frequency division transistor T17 in the cascade transmission frequency division control unit 203.

[0042] If they are electrically connected, it can be assumed that the fourth node R can act on the first node P or the second node Q, namely, it can be controlled with the signal of the fourth node R whether the cascade transmission signal generated and output by the cascade transmission output unit 2012 has an effective cascade transmission pulse (namely the above situation 1);If they are separated, it can be assumed that the fourth node R cannot act on the first node P or the second node Q, since the fourth node R, which is used to control the cascade transmission signal generated by the present stage, cannot act on the cascade transmission output unit 2012, it can be assumed that the cascade transmission signal generated and output by the cascade transmission output unit 2012 does not have an effective cascade transmission pulse (namely, situation 2 above).

[0043] In one embodiment, as in Fig. 2 and Fig. As shown in Figure 3, the cascade transfer output unit 2012 comprises the following: a first-stage cascade transfer output transistor T10, wherein the gate of the first-stage cascade transfer output transistor T10 is electrically connected to the first node P, and wherein the source of the first-stage cascade transfer output transistor T10 is electrically connected to a first voltage line to charge a first voltage VGH, and wherein the drain of the first-stage cascade transfer output transistor T10 is electrically connected to the cascade transfer output end OUT in the gate driver circuit 20 to output the cascade transfer signal;a second-stage cascade transfer output transistor T9, wherein the gate of the second-stage cascade transfer output transistor T9 is electrically connected to the second node Q, and wherein the source of the second-stage cascade transfer output transistor T9 is electrically connected to a second voltage line to charge a second voltage VGL, and wherein the drain of the second-stage cascade transfer output transistor T9 is electrically connected to the cascade transfer output end OUT.

[0044] In particular, the first node P can control the switching on of the cascade transfer output transistor T10 of the first stage to control whether the first voltage can be transferred to the cascade transfer output end OUT, the second node Q can control the switching on of the cascade transfer output transistor T9 of the second stage to control whether the second voltage can be transferred to the cascade transfer output end OUT.In conjunction with the above explanation, it can be seen that in the present application, the arrangement of a third frequency division transistor T17 connected between the fourth node R and the first node P or the second node Q controls whether the first node P or the second node Q can receive the signal from the fourth node R to control the switching on of the first output transistor T22 or the switching on of the second output transistor T21; in this way, the specific situation of the cascade transmission signal generated and output by the cascade transmission output end OUT is controlled.

[0045] For example, if the first-stage cascade transfer output transistor T10 is switched on and the second-stage cascade transfer output transistor T9 is switched off, the gate control signal can be equal to the first voltage; if, for example, the first-stage cascade transfer output transistor T10 is switched off and the second-stage cascade transfer output transistor T9 is switched on, the generated cascade transfer signal can be equal to the second voltage; if, for example, both are switched off, the generated cascade transfer signal can be equal to the previous voltage; if, for example, both are switched on, the generated cascade transfer signal can lie between the first voltage and the second voltage.

[0046] In one embodiment, as in Fig. 2 and Fig. As shown in Figure 3, the output unit 202 comprises the following: a first output transistor T22, wherein the gate of the first output transistor T22 is electrically connected to the third node S, and wherein the source of the first output transistor T22 is electrically connected to a first voltage line, and wherein the drain of the first output transistor T22 is electrically connected to the gate output end OUTA in the gate driver circuit 20 for outputting the gate control signal; a second output transistor T21, wherein the gate of the second output transistor T21 is electrically connected to the first node P or the second node Q, and wherein the source of the second output transistor T21 is electrically connected to a second voltage line, and wherein the drain of the second output transistor T21 is electrically connected to the gate output end OUTA.

[0047] Similar to the explanation above, the third node S can control the switching on of the first cascade transfer output transistor T22 to control whether the first voltage can be transferred to the gate output end OUTA, the first node P or the second node Q can control the switching on of the second cascade transfer output transistor T21 to control whether the second voltage can be transferred to the gate output end OUTA.In conjunction with the above explanation, it can be seen that in the present application, the arrangement of a first frequency division transistor T18 connected between the third node S and the first node P or the second node Q controls whether the third node S can receive the signal from the first node P or the second node Q to control the switching on of the first output transistor T22 or the switching on of the second output transistor T21; in this way, the specific situation of the gate control signal generated and output by the gate output end OUTA is controlled.

[0048] In one embodiment, the gate driver circuit 20 is electrically connected to at least one corresponding pixel driver circuit 302, wherein the gate output end OUTA is electrically connected to the pixel transistor in each of the corresponding pixel driver circuits 302, and wherein the first voltage is greater than the second voltage; as shown in Fig. As shown in Figure 2, the pixel transistor is a P-type transistor, with the drain of the third frequency division transistor T17 and the source of the first frequency division control transistor each being electrically connected to the first node P (it can now be assumed that the gate driver circuit 20 is an i-th stage NScan circuit, the generated gate control signal is an NScano(i) signal, the cascade transfer signal is an NScan(i) signal, and the cascade transfer signal of the previous stage is an NScan(i-1) signal); or as in Fig. As shown in Figure 3, the pixel transistor is a P-type transistor, with the drain of the third frequency division transistor T17 and the source of the first frequency division control transistor each being electrically connected to the second node Q (it can now be assumed that the gate driver circuit 20 is a PScan circuit of the i-th stage, the generated gate control signal is a PScano(i) signal, the cascade transfer signal is a PScan(i) signal, and the cascade transfer signal of the previous stage is a PScan(i-1) signal).

[0049] Without restricting the architecture of the pixel driver circuit 302 in the present embodiment, it can be assumed that the pixel transistor, under control by the gate control signal output by the gate driver circuit 20, can control the activation of the corresponding subpixel Pi. In particular, in the present embodiment, based on the fact that the first voltage is greater than the second voltage, the drain of the third frequency division transistor T17 and the source of the first frequency division control transistor are each electrically connected to the first node P, assuming the pixel transistor is an N-type transistor, to control the activation of the first-stage cascade transfer output transistor T10 and the first output transistor T22, thereby controllingWhether the larger first voltage (which can be an effective voltage of the N-type transistor) can be transferred to the gate of the N-type pixel transistor, in this way it is controlled whether the corresponding subpixel Pi is switched on; if the pixel transistor is a P-type transistor, the drain of the third frequency division transistor T17 and the source of the first frequency division control transistor are each electrically connected to the second node Q to control the switching on of the second-stage cascade transmission output transistor T9 and the second output transistor T21, thereby controlling whether the smaller second voltage (which can be an effective voltage of the P-type transistor) can be transferred to the gate of the P-type pixel transistor, in this way it is controlled whether the corresponding subpixel Pi is switched on.

[0050] As explained above, if the effective voltages required to turn on the N-type or P-type pixel transistor are of the same duration, it can be assumed that, under the NScano signal and the PScano signal, respectively, output by the NScan circuit and the PScan circuit, the voltage value of the effective gate pulse of the former (e.g., without being limited to being equal to the first voltage) is greater than the voltage value of the effective gate pulse of the latter (e.g., without being limited to being equal to the second voltage), and the pulse widths of the effective gate pulses of the two can be equal.

[0051] Since the cascade transmission receiver unit 2011 can receive the cascade transmission signal generated by the upper stage, it is evident from the cascade transmission function of the cascade transmission signal that the first start signal STV1 and the second start signal STV2, which are applied to the NScan circuit of the first stage and the PScan circuit of the first stage respectively, can each be obtained such that the cascade transmission signal (NScan(1), PScan(1)) generated by the respective gate driver circuit 20 of the first stage is shifted by the same distance along the negative direction of the time axis, namely, the voltage values ​​of the effective cascade transmission pulses of the two can each be equal to the first voltage and the second voltage. The first start signal STV1, the second start signal STV2, the NScan signal, the PScan signal, the NScan signal, and the PScan signal can all be periodic signals.

[0052] In one embodiment, as in Fig. 2 and Fig. As shown in Figure 3, the cascade transmission receiving unit 2011 comprises the following: a control unit 20111 for the fourth node, which is electrically connected to a clock signal line (including, but not limited to, a first clock signal line CKL1 and a second clock signal line CKL2, and the first clock signals XCK with which the two are each loaded, and the second clock signal line CKL2CK can be symmetrical about a time axis; there is no restriction here on the voltage value at the intersection of the time axis and the voltage axis, which can both contain two different voltage values) and the fourth node R, in order to control the signal of the fourth node R in accordance with the clock signal transmitted by the clock signal line; a control unit 20112 for the second node (as shown in Figure 3). Fig. 2 shown) and a control unit 20113 for the first node (as shown in Fig. 3), wherein the control unit 20112 for the second node is electrically connected to a clock signal line and the second node Q to control the signal of the second node Q in accordance with the clock signal; and wherein the control unit 20113 for the first node is electrically connected to a clock signal line and the first node P to control the signal of the first node in accordance with the clock signal; an input unit 20114, wherein the input end of the input unit 20114 is electrically connected to the gate driver circuit 20 of the upper stage to load the cascade transfer signal generated by the gate driver circuit 20 of the upper stage, and wherein the output end of the input unit 20114 is electrically connected to the control unit for the fourth node 20111 and the control unit for the second node 20112 or to the control unit for the fourth node 20111 and the control unit for the first node 20113.

[0053] It should be noted that, for the sake of simplicity, the schematic diagram in the present application illustrates only the second cascade transfer output transistor T9 of the second stage, which is located below the cascade transfer output transistor T10 of the first stage (namely, the second node Q is located below the first node P), and the second output transistor T21, which is located below the first output transistor T22, as an example. In fact, the present application protects the interconnection relationship between several electronic devices without restricting the positional relationship. Based on the input unit 20114, the cascade transfer signals generated by the gate driver circuit 20 of the upper stage are loaded, as shown in Fig. As shown in Figure 2, it can be assumed that for the NScan circuit the fourth node R is also located in the upper part, since the cascade transmission frequency division control unit 203 is connected to the first node P in the upper part. It can now be assumed that it is also necessary to arrange the control unit 20111 for the fourth node in the upper part to control the voltage of the fourth node R (in combination with the cascade transmission frequency division control unit 203, the voltage of the first node P is controlled), and the voltage of the second node Q must be controlled by the arrangement of a control unit 20112 for the second node in the lower part; as shown in Figure 2. Fig. As shown in Figure 3, it can be assumed that for the PScan circuit the fourth node R is also located in the lower part, since the cascade transmission frequency division control unit 203 is connected to the second node Q in the lower part. Now it can be assumed that it is also necessary to arrange the control unit 20111 for the fourth node in the lower part in order to control the voltage of the fourth node R (in combination with the cascade transmission frequency division control unit 203, the voltage of the second node Q is controlled), and the voltage of the first node P must be controlled with the arrangement of a control unit 20113 for the first node in the upper part.

[0054] In one embodiment, as in Fig. As shown in Figure 2, the cascade transmission frequency division control unit 203 and the output frequency division control unit 204 are each electrically connected to the first node P (namely, at this point, the gate driver circuit 20 is shown as an example of an NScan circuit); and wherein the input unit 20114 comprises an input transistor T3, and wherein the gate of the input transistor T3 is loaded with the clock signal (for example, it is connected to the first clock signal line CKL1 to load the first clock signal), and wherein the source of the input transistor T3 is configured as the input end of the input unit 20114, and wherein the drain of the input transistor T3 is configured as the output end of the input unit 20114; and wherein the control unit 20111 for the fourth node comprises a first transistor T4, a seventh transistor T5, and a second transistor T6 and third transistor T7 connected in series.and wherein the gate of the seventh transistor T5 is electrically connected to the drain of the input transistor T3, and wherein the source of the seventh transistor T5 is charged with the clock signal (e.g., a first clock signal), and wherein the gate of the first transistor T4 is charged with the clock signal (e.g., a first clock signal), and wherein the source of the first transistor T4 is charged with the second voltage, and wherein the drain of the first transistor T4 is electrically connected to the gate of the second transistor T6 and the drain of the seventh transistor T5, and wherein the drain of the second transistor T6 is electrically connected to the source of the third transistor T7, and wherein the source of the second transistor T6 and the gate of the third transistor T7 are each charged with the clock signal, and wherein the drain of the third transistor T7 is electrically connected to the fourth node R; and wherein the control unit 20112 provides a fourth transistor T13 for the second node,comprising a first capacitor C1 and a fifth transistor T1 and sixth transistor T2 connected in series, wherein the gate of the fourth transistor T13 (electrically connected to the control line CL) is charged with the control signal, and wherein the source of the fourth transistor T13 is charged with the first voltage, and wherein the drain of the fourth transistor T13 is electrically connected to the second node Q, and wherein the gate of the fifth transistor T1 is electrically connected to the drain of the first transistor T4, and wherein the source of the fifth transistor T1 is charged with the first voltage, and wherein the drain of the fifth transistor T1 is electrically connected to the source of the sixth transistor T2, and wherein the drain of the sixth transistor T2 is charged with the clock signal, and wherein the gate of the sixth transistor T2 is also charged with the cascade transfer signal generated by the gate driver circuit 20 of the upper stage,and wherein the first capacitor C1 is electrically connected between the gate and the drain of the sixth transistor T2.

[0055] In the gate driver circuit 20, the transistors are all P-type transistors, as an example in the present application illustrates the operation of some of the signals in some of the states: at turn-on, the control signals transmitted by CL can drive the fourth transistor T13 to turn on, in order to transmit a first voltage to the second node Q; later, with a low voltage in the first clock signal and a low voltage in the gate control signal NScano(i-1) of the (i-1)th stage, the gate control signal NScano(i-1) drives the seventh transistor T5 and the second output transistor T21 to turn on, the second voltage is transmitted by the second output transistor T21 to the cascade transmission output end OUT, and the first clock signal drives the first transistor T4 to turn on, and the second voltage is transmitted to the gate of the second transistor T6 to drive it to turn on.At this point, the high voltage in the second clock signal controls the third transistor T7 to switch off; later, with a low voltage in the first clock signal, the input transistor T3, the second transistor T6 and the first transistor T4 are switched off, now it can be assumed that the second output transistor T21 remains switched on, the low voltage in the second clock signal still controls the third transistor T7 to switch on, the fourth node R is not yet charged with the voltage and the cascade transmission output end OUT is still outputting the second voltage.

[0056] It should be noted that the present application does not restrict the type of each transistor in the gate driver circuit 20; for example, all transistors may be P-type transistors, or some of the transistors may be N-type transistors and some of the transistors may be P-type transistors, and the corresponding signals may be adapted according to the type of transistors, as described in detail in the article “Transistors in the gate driver circuit 20 are all P-type transistors”.

[0057] Furthermore, the control unit 20111 for the fourth node can still include an eighth transistor T11 and a second capacitor C2, the control unit 20112 for the second node can still be a ninth transistor T12, the cascade transmission output unit 2012 can still include a third capacitor C3, which is electrically connected between the gate and the source of the first output transistor T22, the gate of the eighth transistor T11 and the gate of the ninth transistor T12 can each be charged with a second voltage so that they remain switched on, the source and drain of the eighth transistor T11 are each electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6, the second capacitor C2 is electrically connected between the gate and the drain of the second transistor T6.and the source and drain of the ninth transistor T12 are each electrically connected to the drain of the input transistor T3 and the second node Q.

[0058] The first capacitor C1, the second capacitor C2, and the third capacitor C3 can be used to maintain the voltage of the corresponding node and play a coupling role, and the eighth transistor T11 and the ninth transistor T12 can ensure that they are only switched on when the source voltage of the two is sufficiently low to keep the drain of the two at a lower voltage, which is beneficial for switching on the first output transistor T22 and the second output transistor T21, respectively.

[0059] In one embodiment, as in Fig. As shown in Figure 2, the control unit 20112 for the second node further comprises: a tenth transistor T14, wherein the source of the tenth transistor T14 is charged with the cascade transfer signal generated by the gate driver circuit 20 of the upper stage, and wherein the gate of the tenth transistor T14 is charged with the clock signal (first clock signal), and wherein the drain of the tenth transistor T14 is electrically connected to the gate of the sixth transistor T2; an eleventh transistor T16, wherein the gate and the source of the eleventh transistor T16 are each electrically connected to the gate of the sixth transistor T2, and wherein the drain of the eleventh transistor T16 is electrically connected to the second node Q.Similarly, a twelfth transistor T15 can be arranged to keep the gate of the sixth transistor T2 at a lower voltage, the gate of the twelfth transistor T15 being charged with a second voltage, and the source and drain of the twelfth transistor T15 being electrically connected to the drain of the tenth transistor T14 and the gate of the sixth transistor T2, respectively.

[0060] It is understood that the control unit 20112 for the second node in the present embodiment is further equipped with the above tenth transistor T14 and eleventh transistor T16, wherein the tenth transistor T14 can be used to control the voltage of the gate of the sixth transistor T2, with the arrangement of the eleventh transistor T16, which is connected between the second node Q and the gate of the sixth transistor T2, it is made possible that the second node Q is not directly electrically connected to the first capacitor C1 in order not to be subject to the coupling effect of the first capacitor C1, in this way the second node Q can be kept at a lower voltage.

[0061] It should be noted that when comparing Fig. 3 and Fig. Figure 2 shows that one of the differences between the PScan circuit and the NScan circuit lies in the difference between the second start signal STV2 and the first start signal STV1, and that the specific structures of the input unit 20114 and the output unit 202 of the two can be the same. Another difference is that the NScan circuit must include the control unit 20111 for the fourth node and the control unit 20112 for the second node, while the PScan circuit must include the control unit 20111 for the fourth node and the control unit 20113 for the first node. The specific structure of the control unit 20111 for the fourth node in the NScan circuit can be the same as the specific structure of the control unit 20113 for the first node in the PScan circuit.The difference is that the output end of the former is connected to the first node P via the cascade transmission frequency division control unit 203, while the output end of the latter is directly connected to the first node P. Similarly, the specific structure of the control unit 20112 for the second node in the NScan circuit can be the same as the specific structure of the control unit for the third node S in the PScan circuit. The difference is that the output end of the former is directly connected to the second node Q, while the output end of the latter is connected to the second node Q via the cascade transmission frequency division control unit 203.

[0062] Furthermore, the gate driver circuit 20 in the present application can also be an EM circuit, but is not limited to it, and the difference between the EM circuit and the NScan circuit is that the first start signal STV1 is replaced by a third start signal STV3, and the third start signal STV3 can be understood as being obtained by shifting the first start signal STV1 along the negative direction or the positive direction of the time axis by a certain distance and the two waveforms do not overlap, and similarly the third start signal STV3 can be a periodic signal.

[0063] The present application provides a display panel, wherein the display panel comprises, but is not limited to, the following embodiments and combinations thereof.

[0064] In one embodiment, as in Fig. As shown in Figures 4 to 7, the display panel 100 comprises the following: a gate drive module 10 as described in one of the preceding sections; a panel body 30 comprising several subpixels Pi and several scanning lines SL, wherein the several subpixels Pi comprise a light-emitting device 301 and a pixel driver circuit 302 for driving the light-emitting device 301 to emit light, and wherein the pixel driver circuit 302 comprises at least one transistor (namely, a pixel transistor as described above); and wherein the gate control signal output by the gate driver circuit 20 is transmitted through the corresponding scanning line to the gate of the several transistors in the corresponding several pixel driver circuits 302.

[0065] In Fig. 4 The display panel 100 includes, for example, 6 gate drive modules 10 (OA1, GOA2, 2 GOA3, GOA4, GOA5 are each electrically connected by a first scanning line ML1, a second scanning line NSL1, a third scanning line PSL, a fourth scanning line NSL2 and a fifth NML2 with the corresponding subpixels Pi): for example, the two GOA3 can be the same PScan circuit, i.e., the loaded signals (the second start signal STV2) and the output signals of both can be the same to improve the reliability of the PScan signals output by both; for example, GOA1 and GOA5 can be two different EM circuits, e.g., two third start signals STV3, corresponding to the two respectively, can each be different (e.g.,, but not limited to the fact that the values ​​of at least one of the two parameters of the pulse width and the starting moment of the effective pulses of the two may be different; for example, GOA2 and GOA4 may be two different NScan circuits, e.g., two first start signals STV1 corresponding to the two may each be different (e.g., but not limited to the fact that the values ​​of at least one of the two parameters of the pulse width and the starting moment of the effective pulses of the two may be different).

[0066] The difference between Fig. 5 and Fig. 4 consists in that the 6 gate drive modules comprise 10 2 GOA1', GOA2', 2 GOA3' and GOA4', each electrically connected to the corresponding subpixels Pi via a sixth sampling line EML', a seventh sampling line NSL1', an eighth sampling line PSL1' and a ninth sampling line NSL2', and similarly the 2 GOA1' can be the same EM circuit, but are not limited to it, and the GOA2', GOA4' can each be different two NScan circuits, e.g. the two first start signals STV1 corresponding to the two can be different, and the two GOA3 can be the same PScan circuit, without being limited to it.

[0067] It should be noted that Fig. 4 and Fig. 5 only show the connection relationship between the multiple gate driver circuits 20 in the same gate module and the connection relationship between each and multiple subpixel Pi, and for the signal line to which each gate driver circuit 20 is connected, reference can be made to Fig. 1 to 3 and the relevant textual descriptions above should be taken into account.

[0068] As in Fig. 4 and Fig. 6 shown, includes Fig. 6 a pixel driver circuit 302, which corresponds to the arrangement method of the gate drive module 10 in Fig. 4 corresponds to the pixel driver circuit 302, which can include a data transistor M2, the source of the data transistor M2 is loaded with the data signal Vdata, the drain of the data transistor is electrically connected to the source of the driver transistor M1, the gate of the data transistor M2 (e.g., the P-type transistor) can be electrically connected to the third scanning line PSL to load the PScan signal.

[0069] The pixel driver circuit 302 can further comprise a reset transistor M4 and a compensation transistor M3. The gate of the reset transistor M4 (e.g., an N-type transistor) can be electrically connected to the scanning line NSL1 to load the NScan1 signal. The reset transistor M4 is configured to cause the reset signal VI1 to be transferred to the gate of the driver transistor M1 to perform a reset. The compensation transistor M3 (e.g., an N-type transistor) can be electrically connected to the fourth scanning line NSL2 to load the NScan2 signal. The source and drain of the compensation transistor M3 are each electrically connected to the drain and gate of the driver transistor M1, respectively.

[0070] The pixel driver circuit 302 may further include an initialization transistor M7, wherein the gate of the initialization transistor M7 (e.g. a P-type transistor) is electrically connected to the fifth sampling line EML2 to charge the EM2 signal, and the drain of the initialization transistor M7 is electrically connected to one end of the light-emitting device 301 (the other end of the light-emitting device 301 may be charged with the low-voltage signal VSS), wherein the initialization transistor M7 is configured to cause the initialization signal VI2 to be transmitted to one end of the light-emitting device 301 for initialization.

[0071] The pixel driver circuit 302 further includes a reset transistor M8, a gate of the reset transistor M8 (e.g. a P-type transistor) can be electrically connected to the fifth sampling line EML2 to load the EM2 signal, a drain of the reset transistor M8 is electrically connected to the source of the driver transistor M1, and the reset transistor M8 is configured such that the reset signal VI3 is transferred to the source of the driver transistor M1 to perform a reset of a voltage thereon.

[0072] The pixel driver circuit 302 can further comprise a first light-emitting control transistor M5 and a second light-emitting control transistor M6, wherein the source of the first light-emitting control transistor M5 is charged with the first high voltage VDD, and wherein the drain of the first light-emitting control transistor M5 is electrically connected to the source of the driver transistor M1, and wherein the source and drain of the second light-emitting control transistor M6 are electrically connected to the drain of the driver transistor M1 and to one end of the light-emitting device 301, and wherein the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 (e.g.(both P-type transistors) are electrically connected to the first sampling line EML1 to load an EM1 signal, and the two are configured to control the timing of the light emission of the light-emitting device 301 based on the EM1 signal.

[0073] The pixel driver circuit 302 also includes a storage capacitor Cst, wherein the storage capacitor Cst is connected in series between the source of the first light-emitting control transistor M5 and the gate of the driver transistor M1.

[0074] The pixel driver circuit 302 also includes a boost capacitor Cboost, the boost capacitor Cboost being connected in series between the gate of the driver transistor M1 and the gate of the data transistor M2.

[0075] Based on the above explanation, the writing frame WF of the display panel can be, as in Fig. Figure 8 shows a timing diagram of the pixel driver circuit 302 in Fig. 7 corresponds to a first reset phase tim1, a second reset phase tim2, a data write phase tim3 and a light emission phase tim4, and the specific workflow is as follows: In the first reset phase tim1, the initial transistor M7 and the reset transistor M8 are switched on according to the corresponding EMo2 signal, and the compensation transistor M3 is switched on according to the corresponding NScano2 signal, which allows the anode of the light-emitting device 301 to be reset according to the initialization signal VI2 and the input end, output end and control end of the driver transistor M1 - the source, drain and gate - to be reset according to the reset signal VI3;

[0076] In the second reset phase tim2, the reset transistor M4 is switched on according to the corresponding NScano1 signal, and the compensation transistor M3 is switched on according to the corresponding NScano2 signal, which allows the gate and drain of the driver transistor M1 to be reset according to the initialization signal VI2;

[0077] During the data write phase tim3, the data transistor M2 is switched on according to the corresponding NScano signal, and the compensation transistor M3 is switched on according to the corresponding NScano2 signal, so that the gate of the driver transistor M1 can write the data signal Vdata;

[0078] During the light emission phase tim4, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are switched on according to the EMo1 signal, enabling the driver transistor M1 to generate a driver current to drive the corresponding light-emitting device 301 to emit light;

[0079] Furthermore, a third reset phase tin can be included between the light emission phase tim4 and the data write phase tim3, wherein in the third reset phase tin the initial transistor M7 and the reset transistor M8 are switched on according to the corresponding EMo2 signals, so that the anode of the light-emitting device 301 is able to be reset according to the initialization signal VI2, and the source and drain of the driver transistor M1 are able to be reset according to the reset signal VI3.

[0080] It should be noted that, as can be seen from the difference in the settings of the gate drive module 10 of Fig. 5 and Fig. 7, it is evident that Fig. 7 includes the pixel driver circuit 302, which corresponds to the setting method of the gate drive module 10 in Fig. 5 corresponds to, as in Fig. 5 and Fig. 7 shown, i.e. the pixel driver circuit in Fig. 7 can only be driven by the same EM circuit and can therefore only be electrically connected to the same sixth sampling line EML' and charged with the same signal (and not electrically connected to the first sampling line EML1 and the fifth sampling line EML2 to be charged with two different signals, as in Fig. 6 shown).

[0081] As in Fig. As shown in 7, the difference to Fig. 6 in particular, in that the reset transistor M8 is removed, the first sampling line EML1 is replaced by the sixth sampling line EML', the second sampling line NSL1 is replaced by the seventh sampling line NSL1', the third sampling line PSL is replaced by the eighth sampling line PSL1', and the fourth sampling line NSL2 is replaced by the ninth sampling line NSL2'. The fifth sampling line EML2 is also replaced by the eighth sampling line PSL1' of the previous level.

[0082] Based on the above explanation, the writing frame WF of the display panel can be, as in Fig. Figure 9 shows a timing diagram of the pixel driver circuit 302 in Fig. 7 corresponds to a first reset phase tim1', a second reset phase tim2', a data write phase tim3' and a light emission phase tim4', and with the gate driver circuit 20 of the i-th stage, the specific workflow is as follows: In the first reset phase tim1', the reset transistor M4 is switched on according to the corresponding NScano1'(i) signal, which allows the gate of the driver transistor M1 to be reset according to the initialization signal VI1; In the second reset phase tim2', the initial transistor M7 is switched on according to the corresponding PScano1'(i-1) signal, which allows the anode of the light-emitting device 301 to be reset according to the initialization signal VI2, and the compensation transistor M3 is switched on according to the corresponding NScano1'(2) signal; In the second reset phase tim3', the data transistor M2 is switched on according to the corresponding PScano1'(i) signal, and the compensation transistor M3 is switched on according to the corresponding NScano2'(i) signal, so that the gate of the driver transistor M1 can write the data signal Vdata; In the third reset phase tim4', the initial transistor M7 is switched on according to the corresponding PScano1'(i-1) signal, which allows the anode of the light-emitting device 301 to be reset again according to the initialization signal VI2; In the coupling stage tim5', the data transistor M2 is switched on according to the corresponding PScano1'(i) signal, and at this time, regardless of the data signal Vdata, since the compensation transistor M3 is switched off, the gate voltage of the driver transistor M1 is not affected, but since the gate voltage of the data transistor M2 is reduced, this also leads to an increase in the gate voltage of the driver transistor M1; In the light emission phase tim6', the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are switched on according to the EMo'(i) signal, which causes the driver transistor M1 to generate a driver current to drive the corresponding light-emitting device 301 to emit light, and since the gate voltage of the driver transistor M1 rises in the coupling phase tim5' until it is greater than the data voltage given by the data signal Vdata in the data write phase tim3', the light-emitting device 301 can have a greater brightness, and it can also be considered that the upper limit of the data voltage can be effectively reduced to lower the power consumption.

[0083] Based on the above analysis, it can be seen that in the writing frame WF, since normal light emission of the subpixel Pi in each row should be achieved, i.e., the gate driver circuit 20 of each stage (each from GOA1 to GOA5 and each from GOA1' to GOA4') must output a corresponding effective gate pulse in the corresponding time period to drive the corresponding transistor in the pixel driver circuit 302 to turn on and thus achieve a corresponding function to turn on the subpixel Pi, it can be assumed that the subpixel Pi of the corresponding row cannot emit light if the gate driver circuit 20 is not able to output a corresponding effective gate pulse in the corresponding time period.

[0084] As in Fig. 6 and Fig. As shown in Figure 7, the data transistor M2 cannot be turned on if the PScano signal and the PScano1'(i) signal do not have an effective (low-voltage) gate pulse; therefore, subpixel Pi cannot be turned on, which means that the data signal cannot be written to the source of the driver transistor M1 and subpixel Pi cannot be turned on; if the EM1 signal and the EMo'(i) signal do not have an effective (low-voltage) gate pulse, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 cannot be turned on, which means that the driver current cannot be generated and subpixel Pi cannot be turned on;The compensation transistor M3 cannot be switched on if the NScano2 signal and the NScano2'(i) signal do not have an effective (high-voltage) gate pulse. Therefore, the compensation transistor M3 cannot be switched on, which means that the data signal cannot be written to the gate of the driver transistor M1 and the subpixel Pi cannot be switched on. If the EMo2 signal, the NScano1 signal, and the NScano1'(i) signal do not have effective pulses, the light emission of the subpixel Pi will also be impaired to some extent.

[0085] Based on the in Fig. In the pixel driver circuit 302 shown in Figure 6, at least one of the three gate driver circuits 20, each used to generate the PScano signal, the EMo1 signal and the NScano2 signal in the present application, can be provided with a cascade transmission frequency division control unit 203 and output frequency division control unit 204 as described above; based on the Fig. In the pixel driver circuit 302 shown in Figure 7, at least one of the three gate driver circuits 20, each used to generate the PScano1'(i) signal, the EMo'(i) signal and the NScano2'(i) signal in the present application, can be provided with a cascade transmission frequency division control unit 203 and output frequency division control unit 204 as described above; based on the assumption that the start signal in the gate driver circuit 20 of the first stage (e.g., the first start signal STV1, the second start signal STV1 and the third start signal STV1) is already set, it can be controlled in each frame and in connection with the arrangement of the frequency division control signal FD (see the explanation in the text for situations 1 to 4) whether the first node P (according to Fig. 2) or the second node Q (according to Fig. 3) is electrically connected to the fourth node R and whether the third node S is connected to the first node P (according to Fig. 2) or the second node (according to Fig. 3) is electrically connected such that the output gate control signal has one or no effective gate pulse to control whether the subpixel Pi of the corresponding row is turned on (updated).

[0086] In one embodiment, as in Fig. 4 and Fig. As shown in Figure 5, the display panel is in a time-split down-conversion mode and an up-conversion mode, wherein the multiple gate driver circuits 20 comprise multiple cascaded first gate driver circuits 2001 and multiple cascaded second gate driver circuits 2002, which are cascaded after the multiple first gate driver circuits 2001; and wherein the multiple subpixels Pi comprise multiple first subpixels Pi1, which are electrically connected to the multiple first gate driver circuits 2001, and multiple second subpixels Pi2, which are electrically connected to the multiple second gate driver circuits 2002, and wherein the multiple first subpixels Pi form a first display area and the multiple second subpixels Pi form a second display area; and wherein in the down-conversion mode the update rate of the first display area is higher than that of the second display area;and wherein, in the upward conversion mode, the update rate of the first display area is lower than that of the second display area.

[0087] In conjunction with the above explanation, it can be seen that in the present application, the arrangement of the cascade transmission frequency division control unit 203 and the output frequency division control unit 204 in the drive unit allows control over whether the cascade transmission signal generated by the present stage has an effective cascade transmission pulse and whether the gate control signal has an effective gate pulse.

[0088] In particular, the NScan circuit of the i-th stage is described here according to Fig. 2 is used as an example. Based on the fact that the transistors in Fig. 2. Since all P-type transistors (i.e., low-voltage RMS) are switched on, the third frequency division transistor T17 is switched on for the time period (i.e., the second frequency division control signal FD2 is at a lower voltage), and the first clock signal line CKL1 and the second clock signal line CKL2 respectively transmit the first clock signal and the second clock signal, as in conjunction with the in Fig. The operating time sequence of the NScan circuit shown in Figure 9 can include the following six operating phases t1 to t6, but is not limited to them.

[0089] In the first phase t1, the first clock signal XCK is set low, the second clock signal line CK is set high, and the cascade transmission signal NScan(i-1) generated by the previous stage is set low: the third transistor T7 is in an off state according to the second clock signal line CK; the first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low cascade transmission signal NScan(i-2) is transmitted to node D, the second node Q, and node F, so that the seventh transistor T5, the thirteenth transistor T8, the output transistor of the second stage T9, the sixth transistor T2, and the eleventh transistor T16 are turned on according to NScan(i-1), the second voltage VGL is transmitted to node C and node B, and the high second clock signal line CK is transmitted to node E.The first voltage VGH is transmitted to node P (fourth node R), so that the second transistor T6 and the fifth transistor T1 are switched on according to the second voltage VGL. The high second clock signal line CK is transmitted to node A to charge the second capacitor C2 until it equals the voltage difference between node A and node B. The first voltage VGH is transmitted to node E (the voltage of node E can be between the first voltage VGH and the high voltage of the second clock signal line CK) to charge the first capacitor C1 until it equals the voltage difference between node E and node F. This charges the first capacitor C1, thus coupling the voltage of node F and increasing it. Since the first cascade transfer output transistor T10 is off and the second cascade transfer output transistor T9 is on,The generated gate control signal NScano(i) is of a low voltage;

[0090] In the second phase t2, the first clock signal XCK is set high, the second clock signal line CK is set low, and the cascade transmission signal NScan(i-1) generated by the previous stage is set low: the first transistor T4, the input transistor T3 and the tenth transistor T14 are in an off state according to the first clock signal XCK, and the gate of the seventh transistor T5, node D, the second node Q and node F are held at the previous voltages;The sixth transistor T2 is held in the on state, the low-level second clock signal line CK is transmitted to node E, the voltage of node F is further pulled down by the second clock signal CK being coupled downwards to the first capacitor C1, so that the eleventh transistor T16 is held in the on state, the voltage of node F is transmitted to node D, but the voltage of node D is also subject to the rising coupling of the first clock signal XCK transmitted by the first clock signal line CKL1 in the circuit layout and rises; the eleventh transistor T16 is turned off, and the voltage at the second node Q does not follow the voltage at node D due to the effect of the ninth transistor T12, and the second-stage cascade transmission output transistor T9 remains on;The seventh transistor T5 remains switched on, and the high first clock signal XCK is transmitted to nodes C and B; the fifth transistor T1 and the second transistor T6 are switched off; the thirteenth transistor T8 is switched on according to the voltage of node D, and the first voltage VGH is transmitted to the first node P (the fourth node R), so that the cascade transmission output transistor T10 of the first stage is switched off, and at the same time the low second clock signal line CK causes the third transistor T7 to be switched on, and the first voltage VGH is further transmitted to node A to charge the second capacitor C2 so that it is equal to the voltage difference between node A and node B;Since the cascade transfer output transistor T10 of the first stage is switched off and the cascade transfer output transistor T9 of the second stage is switched on, the generated gate control signal NScano(i) is of a low voltage;

[0091] In the third phase t3, the first clock signal XCK is set low, the second clock signal line CK is set high, and the cascade transmission signal NScan(i-1) generated by the previous stage is set high: the third transistor T7 is in an off state according to the second clock signal line CK; the first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the high cascade transmission signal NScan(i-1) is transmitted to node D, node Q, node F, and the gate of the seventh transistor T5; the second voltage VGL is transmitted to node C and node B; the cascade transmission output transistor T9 of the second stage is turned off, and the seventh transistor T5 is turned off according to the high cascade transmission signal NScan(i-1).The fifth transistor T1 and the second transistor T6 are switched on according to the second voltage VGL, the first voltage VGH is transmitted to node E to charge the first capacitor C1 until it equals the voltage difference between node E and node F, the high-level second clock signal line CK is transmitted to node A to charge the second capacitor C2 until it equals the voltage difference between node A and node B;The thirteenth transistor T8 is switched off according to the high cascade transfer signal NScan(i-1), and the first node P (the fourth node R) is held at the previous (high) voltage via the third capacitor C3, so that the first stage cascade transfer output transistor T10 is switched off, and since the first stage cascade transfer output transistor T10 and the second stage cascade transfer output transistor T9 are switched off, i.e., the cascade transfer output end OUT is suspended, the generated gate control signal NScano(i) is held at a low voltage;

[0092] In the fourth phase t4, the first clock signal XCK is set high, the second clock signal line CK is set low, and the cascade transmission signal NScan(i-1) generated by the previous stage is set high: the input transistor T3, the first transistor T4 and the tenth transistor T14 are in an off state according to the first clock signal XCK, and the gate of the seventh transistor T5, node D, the second node Q and node C are held at the previous voltages;The seventh transistor T5 is switched off according to the preceding high voltage, the second-stage cascade transmission output transistor T9 is switched off according to the high voltage before the second node Q, the thirteenth transistor T8 is switched off according to the high voltage at node D, the fifth transistor T1 and the second transistor T6 are switched on according to the low voltage before node C, and the sixth transistor T2 is switched off according to the high voltage before node F; the first voltage VGH is transferred to node E via the fifth transistor T1, i.e., the voltage at node E is essentially unchanged, and in combination with the coupling effect of the first capacitor C1, the voltage at node F can also be essentially unchanged;The low-level second clock signal CK is transmitted to node A via the second transistor T6, and in combination with the coupling effect of the second capacitor C2, the voltage at node B is reduced; the third transistor T7 is switched on according to the second clock signal CK, the low voltage at point A is transmitted via the third transistor T7 to node P (fourth node R), thereby switching on the first-stage cascade transfer output transistor T10, and since the first-stage cascade transfer output transistor T10 is switched on and the second-stage cascade transfer output transistor T9 is switched off, the generated gate control signal NScano(i) is of a high voltage;

[0093] In the fifth phase t5, the first clock signal XCK is set low, the second clock signal line CK is set high, and the cascade transmission signal NScan(i-1) generated by the previous stage is set low: the third transistor T7 is in an off state according to the second clock signal line CK; the first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low cascade transmission signal NScan(i-1) is passed via the input transistor T3 to node D, the second node Q, and the gate of the seventh transistor T5;The second stage's cascade transmission output transistor T9 is switched on according to the low voltage of the second node Q, the sixth transistor T2 is switched on according to the voltage of node F, so that the high second clock signal line CK is transferred to node E to charge the first capacitor C1 until it is equal to the voltage difference between node E and node F;The seventh transistor T5 is switched on to transmit the low-level first clock signal XCK to node C and node B. The fifth transistor T1 is switched on according to the low-level first clock signal XCK and the second voltage VGL, and the first voltage VGH is transmitted via the fifth transistor T1 to node E (the voltage of node E can be between the first voltage VGH and the high voltage of the second clock signal line CK). Based on the first voltage VGH and the high voltage of the second clock signal line CK being equal, the voltages of node E and node F remain almost unchanged. The eleventh transistor T16 is switched off to prevent the first capacitor C1 from affecting the rate of decrease of the voltage of the second node Q.The second transistor T6 is switched on according to the low voltage of node B, so that the high-level second clock signal line CK is transmitted to node A to charge the second capacitor C2 until it is equal to the voltage difference between node A and node B; the thirteenth transistor T8 is switched on according to the low voltage of node D, so that the first voltage VGH is transmitted to the first node P (fourth node R), thereby switching off the first-stage cascade transfer output transistor T10, and since the first-stage cascade transfer output transistor T10 is switched off and the second-stage cascade transfer output transistor T9 is switched on, the generated gate control signal NScano(i) is of a low voltage;

[0094] In the sixth phase t6, the cascade transmission signal NScan(i-1) generated by the previous stage is set low, and the first clock signal XCK and the second clock signal line CK are alternately set low and high, thus coupling the voltage of node F downwards. Each time the voltage of node F is coupled downwards, the voltage of node F gradually decreases, approaching -16V. Correspondingly, the voltage of the second node Q gradually decreases, approaching -20V. In the first few cycles after the seventh transistor T5 in the fifth phase, the voltage of node F is more pronouncedly coupled downwards, and the voltage of the second node Q is more strongly influenced by the voltage of node F. Later, the eleventh transistor T16 is switched off, and the voltages of the second node Q all tend to stabilize and are no longer affected by the voltage of node F.

[0095] It should be noted that the gate driver circuit provided in the present application can be a 16T3C structure or a 13T3C structure, but is not limited to either (only the former is shown as an example in the Fig. 2 and Fig. 3 shown), and the 16T3C structure is additionally provided with the tenth transistor T14, twelfth transistor T15 and eleventh transistor T16 described above compared to the 13T3C structure, so that, on the one hand, when the cascade transfer signal of the previous stage NScan(i-1) writes a low voltage to the second node Q and the node F, at that time the voltage of the second node Q can flow out simultaneously from the eleventh transistor T16 and the ninth transistor T12 and the second node Q is not directly connected to the first capacitor C1 (which is blocked by the eleventh transistor T16) to maintain the voltage, and therefore the voltage of the second node Q can decrease faster, which is conducive to the switching on of the cascade transfer output transistor T9 of the second stage.On the other hand, the second node Q is not directly connected to the first capacitor C1 (which is blocked by the eleventh transistor T16), so fluctuations in the voltage of node E do not cause changes in the voltage of the second node Q. Furthermore, the eleventh transistor T16 acts in a diode-like manner, so the voltage of the second node Q is not pulled up by node F.

[0096] In conjunction with the above explanation, it can be seen that, with reference to the Fig. 2 and Fig. 10. If the cascade transmission signal NScan(i-1) generated by the upper stage is kept low at all times (except for effective high-voltage pulses), it can be assumed that the second node and node D are kept at a low voltage at all times in order to keep the second stage's cascade transmission output transistor T9 and the thirteenth transistor T8 switched on at all times and the first stage's cascade transmission output transistor T10 switched off at all times. Thus, the transmission signal NScan(i) output by the present stage is at a low voltage at all times (except for effective high-voltage pulses).

[0097] In conjunction with the above explanation, it can be seen that, with reference to the Fig. 2 and Fig. 10, when the third frequency division transistor T17 is switched off for a certain time (i.e. the second frequency division control signal FD2 is at a higher voltage), i.e. the first node P and the fourth node R are separated, at this time the voltage of the first node P can only be determined by the switched-on state of the thirteenth transistor T8 and the coupling effect of the third capacitor C3.

[0098] In particular, in a first phase t1, the thirteenth transistor T8 is switched on, the first voltage VGH is transferred to the first node P, and the first-stage cascade transfer output transistor T10 is switched off; in a second phase t2, the thirteenth transistor T8 is switched on, the first voltage VGH is transferred to the first node P, and the first-stage cascade transfer output transistor T10 is switched off; in a third phase t3, the thirteenth transistor T8 is switched off, the first node P is held at the first voltage VGH, and the first-stage cascade transfer output transistor T10 is switched off; in a fourth phase t4, the thirteenth transistor T8 is switched off, the first node P is held at the first voltage VGH, and the first-stage cascade transfer output transistor T10 is switched off;In a fifth phase t5, the thirteenth transistor T8 is switched on, the first voltage VGH is transmitted to the first node P, and the first-stage cascade output transistor T10 is switched off; in a sixth phase t6, the thirteenth transistor T8 is switched on, the first voltage VGH is transmitted to the first node P, and the first-stage cascade output transistor T10 is switched off. Therefore, it can be assumed that in each phase, the first-stage cascade output transistor T10 is switched off, and the gate control signal is connected to the on state of the second-stage cascade output transistor T9 as follows: In a first phase t1, the cascade transfer output transistor T9 of the second stage is switched on, therefore the cascade transfer signal NScan(i) generated by the present stage is of a low voltage; In a second phase t2, the cascade transfer output transistor T9 of the second stage is switched on, therefore the cascade transfer signal NScan(i) generated by the present stage is of a low voltage; In a third phase t3, the cascade transmission output transistor T9 of the second stage is switched off, namely the cascade transmission output end OUT is suspended, therefore the cascade transmission signal NScano(i) generated by the present stage is kept at a low voltage; In a fourth phase t4, the cascade transmission output transistor T9 of the second stage is switched off, namely the cascade transmission output end OUT is suspended, therefore the cascade transmission signal NScano(i) generated by the present stage is kept at a low voltage; In a fifth phase t5, the cascade transmission output transistor T9 of the second stage is switched on, therefore the cascade transmission signal NScano(i) generated by the present stage is of a low voltage; In a sixth phase t6, the cascade transfer output transistor T9 of the second stage is switched on, therefore the cascade transfer signal NScano(i) generated by the present stage is of a low voltage.

[0099] In summary, if the third frequency division transistor T17 is switched off during the time period (i.e., the second frequency division control signal FD2 is at a higher voltage), the cascade transfer signals NScan(i) generated by the present stage are all at a low voltage; if the third frequency division transistor T17 is switched on during the time period (i.e., the second frequency division control signal FD2 is at a lower voltage), the cascade transfer signal NScan(i) generated by the present stage can, due to the fact that the cascade transfer signal NScan(i-1) generated by the previous stage, the first clock signal XCK, and the second clock signal CK alternately have high and low voltages, be at the corresponding time period (e.g., between the start point of the fourth phase t4 and the end point of the fifth phase according to Fig. 10) generate an effective cascade transfer pulse (e.g., a high-voltage pulse) that is applied to the corresponding transistor (e.g., the compensation transistor m3 in the Fig. 6 and Fig. 7) can act in the pixel driver circuit 302 of the corresponding row to switch on (update) the light-emitting device 301 of the corresponding row.

[0100] It is understood that the cascade transmission signal generated by the gate driver circuit 20 of the present stage is only transmitted in a cascade manner to the gate driver circuit 20 of the lower stage in the present application, and the generated gate control signal is only loaded into the subpixel Pi of the corresponding row of the present stage; in conjunction with the above analysis, it can be understood that in a frame, when the first node P (for Fig. 2) or the second node Q (for Fig. 3) in the gate driver circuit 20 of the present stage) is not electrically connected to the fourth node R, regardless of whether the third node S is electrically connected to the first node P or the second node Q, the gate control signals of the present stage have no valid pulses, which results in the subpixels Pi of the corresponding row of the present stage not being able to be turned on, at the same time the cascade transfer signal of the present stage has no effective cascade transfer pulse, therefore it cannot drive the gate driver circuit 20 of the lower stage to operation, which results in the cascade transfer signal of the lower stage and the gate control signal each having no effective cascade transfer pulse and no effective gate pulse (namely, the subpixels Pi of the corresponding row of the lower stage also cannot be turned on),Similarly, the subpixels Pi of the following lines can all be switched off; namely, only if the first node P (for , Fig. 2) or the second node Q (for Fig. 3) In the gate driver circuit 20, if each stage is electrically connected to the fourth node R, it can be controlled whether the subpixels Pi of each row are turned on by controlling whether the third node S is electrically connected to the first node P or the second node Q.

[0101] It can be understood that if the multiple first subpixels Pi have a larger number of turned-on frames in several successive frames compared to the multiple second subpixels Pi, this means that the first display area has a higher refresh rate compared to the second display area, and vice versa.

[0102] The following procedure can be used to implement a downward conversion mode (the update rate decreases from the first display area to the second display area): that in at least one of the preceding frames (e.g., frame 1 in Fig. 11) in the successive multiple frames it can be controlled that the cascade transmission signals and gate control signals (e.g. NScano(1) to NScano(6)) generated by all stages in Fig. 11) each have an effective cascade transmission pulse and an effective gate pulse pl; wherein in at least one of the following frames (e.g. frame 4 in Fig. 11) it is controlled so that the cascade transfer signals and gate control signals (e.g. NScano(1) to NScano(2)) generated by each of the first gate driver circuits in 2001 are in Fig. 11) each have an effective cascade transfer pulse and an effective gate pulse pl, and furthermore, it is controlled that the cascade transfer signals generated by each of the second gate driver circuits 2002 do not have an effective cascade transfer pulse, so that the corresponding gate control signals (e.g., NScano(3) to NScano(6) in Fig. 11) also do not exhibit an effective cascade transmission pulse, or only the generated gate control signals (e.g. NScano(3) to NScano(6) in Fig. 11) do not exhibit an effective gate pulse.

[0103] As shown here in connection with the Fig. 2 and Fig. As can be seen in Figure 3 and the accompanying explanation, there are in particular two implementation modes in the step-down conversion mode, where the first frequency division transistor T18 is an example of a P-type transistor: Mode 1: referring to Fig. 11, but not limited to, the first frequency division control signal FD1 (whose voltage is equal to a low voltage) is used to control the third node S in the gate driver circuit 20 of each stage so that it is in sync with the first node P (for Fig. 2) or the second node Q (for Fig. 3) is electrically connected; in one frame, the second frequency division control signal FD2 is used to control the first node P or the second node Q in the first gate driver circuit 2001 so that it is electrically connected to the fourth node R in order to control the output gate control signal so that it has an effective gate pulse pl, thereby turning on the corresponding light-emitting device 301; in the frame, the second frequency division control signal FD2 is further used to control the first node P or the second node Q in the second gate driver circuit 2002 so that it is disconnected from the fourth node R in order to control the output gate control signal so that it has no effective gate pulse pl, thereby not turning on the corresponding light-emitting device 301. Mode 2: the difference to Mode 1 is that the second frequency division control signal FD2 (whose voltage is equal to a low voltage) is used to control the fourth node R in the gate driver circuit 20 of each stage so that it is synchronized with the first node P (for Fig. 2) or the second node Q (for Fig. 3) is electrically connected; in one frame, the first frequency division control signal FD1 is used to control the third node S in the first gate driver circuit 2001 so that it is electrically connected to the first node P or the second node Q in order to control the output gate control signal so that it has an effective gate pulse pl, thereby turning on the corresponding light-emitting device 301; in the frame, the first frequency division control signal FD1 is further used to control the third node S in the second gate driver circuit 2002 so that it is disconnected from the first node P or the second node Q in order to control the output gate control signal so that it has no effective gate pulse pl, thereby not turning on the corresponding light-emitting device 301.

[0104] Regardless of whether Mode 1 or Mode 2 is selected, it is assumed for the gate driver circuit 20 of stage 1 to stage 6 that the gate driver circuits 20 of the first two stages (stages 1 to 2), the gate driver circuits 20 of the middle two stages (stages 3 to 4), and the gate driver circuits 20 of the last two stages (stages 5 to 6) each have an update rate of 120 Hz, 60 Hz, and 30 Hz, respectively. From the above, it is evident that in the 4 consecutive frames (frames 1 to 4), the setting can be as follows: NScano(1) to NScano(2) each have an effective gate pulse pl in frames 1 to 4, the gate control signals NScano(3) to NScano(4) each have an effective gate pulse pl in frames 1 and 3, and the gate control signals NScano(5) to NScano(6) only exhibit an effective gate pulse pl in frame 1; The frequency division control signal FD must be set as follows (mode 1 is used as an example below): The first frequency division control signal FD1 is of a low voltage in frames 1 to 4, so that the first 6 frequency division transistors T18, which correspond to the gate driver circuits 20 of stages 1 to 6, are switched on, thereby the gate control signal generated by each gate driver circuit can be equal to the corresponding cascade transfer signal; The second frequency division control signal FD2 is of a low voltage in frame 1 corresponding to each stage, so that the 6 third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 1 to 6, are switched on, thereby the 6 cascade transfer signals NScan(1) to NScan(6) and the 6 gate control signals NScano(1) to NScano(6) in frame 1 each have an effective gate pulse pl; The second frequency division control signal FD2 is a low voltage in frame 2 before tfl, so that the two third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 1 to 2, are switched on, so that NScano(1) to NScano(2) in frame 2 each have an effective gate pulse pl; and the second frequency division control signal is a high voltage after tfl, so that the four third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 3 to 6, are switched off, so that NScano(3) to NScano(6) in frame 2 each have no effective gate pulse pl; The second frequency division control signal FD2 is of a low voltage in frame 3 before tf2, so that the four third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 1 to 4, are switched on, so that NScan(1) to NScan(4) in frame 3 each have an effective gate pulse pl; and the second frequency division control signal is of a high voltage after tf2, so that the two third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 5 to 6, are switched off, so that NScan(5) to NScan(6) in frame 3 each have no effective gate pulse pl;

[0105] For the analysis of the second frequency division control signal FD2 in frame 4, reference can be made to the analysis in frame 2.

[0106] Of course, as analyzed above, it is in comparison to Fig. 11 It is also possible to bring the second frequency division control signal FD2 in frames 1 to 4 to a low voltage in order to turn on the 6 third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 1 to 6, so that each of the cascade transfer signals generated by each of them has an effective cascade transfer pulse,

[0107] Furthermore, in each frame the first frequency division control signal FD1 is controlled so that, in a time period in which it acts on the gate driver circuit of the corresponding stage, it has an effective gate pulse or no effective gate pulse in order to realize a corresponding frequency division setting.

[0108] In summary, the display panel can be divided into at least a first area, a second area, and a third area. Data is written to the first area (which is subject to an action by the gate driver circuits 20 of stages 1 to 2), i.e., four data updates are performed, by loading it into frames 1 to 4 with the effective pulse pl. Data is written to the second area (which is subject to an action by the gate driver circuits 20 of stages 3 to 4), i.e., two data updates are performed, by loading it into frames 1 and 3 with the effective gate pulse pl. Its update rate is half that of the first area. Similarly, data is written to the second area (which is subject to an action by the gate driver circuits 20 of stages 5 to 6), i.e.,(a data update is performed) by loading it with the effective pulse pl in frame 1, and its update rate is 1 / 4 that of the first frame. In the example above, the update rates of the first frame, second frame, and third frame can be a, (1 / 2)*a, and (1 / 4)*a, respectively, where a is an integer multiple of 4 and must be divided into 4 frames, e.g., the update rate is 120 Hz, 60 Hz, and 30 Hz, respectively.

[0109] For simplicity, the display panel is divided into three areas, each subject to the gate control signals of two stages. The refresh rate of each of the three can be a, (1 / 2)*a, and (1 / 4)*a, respectively. Those skilled in the art should understand that the number of subdivided areas of the display panel and the number of subpixel rows (Pi) contained in each area of ​​a stage can be changed, and the corresponding refresh rate can also be adjusted. Here, it is only shown that the degree of difference in the refresh rates of several areas leads to adjustments in the number of frames. If, in three areas, the refresh rate of each of the latter is 1 / 3 of the refresh rate of the first, then 9 frames must be represented. Thus, the number of updates for three areas has a 3-fold relationship: the three frames in the 9 areas are each updated 9 times, 3 times, and 3 times.and updated once.

[0110] In particular, the following procedure can be used to implement an upward conversion mode (the frequency increases from the first display area to the second display area): in at least one of the preceding frames (e.g., frame 1 in Fig. 12 to 16) in the successive multiple frames, it can be controlled that the cascade transmission signals and gate control signals generated by all stages each have an effective cascade transmission pulse and an effective gate pulse; wherein in at least one of the subsequent frames (e.g., frame 4 in Fig. 12 to 13, frame 3 in Fig. 14 to 15 and frame 4 in Fig. 16) it is controlled so that the cascade transfer signals generated by each of the first gate driver circuits 2001 have an effective cascade transfer pulse (the cascade transfer is continuous to act on the second gate driver circuit 2002), and the generated gate control signal does not have an effective gate pulse (e.g. NScan(1) to NScan(2) in Fig. 12 to 13, NScan(3) to NScan(4) in Fig. 14 to 15 and NScan(1) to NScan(4) in Fig. 16); and the cascade transfer signals and gate control signals generated by each of the second gate driver circuits 2002 each have an effective cascade transfer pulse and an effective gate pulse (e.g. NScan(3) to NScan(4) in Fig. 12 to 13, NScan(5) to NScan(6) in Fig. 14 to 15 and NScan(5) to NScan(6) in Fig. 16).

[0111] As shown here in connection with the Fig. 2 and Fig. 3 and the accompanying explanation show that in the upward conversion mode, referring to, but not limited to, Fig. 12 to 16, the first frequency division transistor T17 is, for example, a P-type transistor, namely the second frequency division control signal FD2 (whose voltage is equal to a low voltage) is used to control the fourth node R in the gate driver circuit 20 of each stage so that it is connected to the first node P (for Fig. 2) or the second node Q (for Fig. 3) is electrically connected; in a frame, the first frequency division control signal FD1 is used to control the third node S in the first gate driver circuit 2001 so that it is controlled by the first node P (for Fig. 2) or the second node Q (for Fig. 3) is separated to control the output gate control signal so that it has no effective gate pulse, thus preventing the corresponding light-emitting device 301 from being switched on; in this context, the first frequency division control signal FD1 is used to control the first node P (for Fig. 2) or the second node Q (for Fig. 3) in the second gate driver circuit 2002 to control it so that it is electrically connected to the fourth node R in order to control the output gate control signal so that it has an effective gate pulse, thereby turning on the corresponding light-emitting device 301.

[0112] As in Fig. As shown in Figure 12, the gate driver circuits 20 of the first 2 stages, the gate driver circuits 20 of the middle 2 stages, and the gate driver circuits 20 of the last 2 stages each have an update rate of 30 Hz, 120 Hz, and 60 Hz, respectively. From the above, it is evident that in frames 1 to 4, the setting can be as follows: NScano(1) to NScano(2) each have an effective gate pulse pl in frame 1, NScano(3) to NScano(4) each have an effective gate pulse pl in frames 1 to 4, and the gate control signals NScano(5) to NScano(6) have an effective gate pulse pl in frames 1 and 3. The frequency division control signal FD must be set as follows: The second frequency division control signal FD2 in frames 1 to 4 is each of a low voltage to turn on the 6 third frequency division transistors T17, which correspond to the gate driver circuits 20 of stages 1 to 6, so that each of the cascade transfer signals generated by each of them has an effective cascade transfer pulse; The first frequency division control signal FD1 in frame 1 is of a low voltage for each stage, so that the first 6 frequency division transistors T18, which correspond to the gate driver circuits 20 of stages 1 to 6, are switched on, and the third node S can be electrically connected to the first node P or the second node Q, so that the 6 gate control signals NScano(1) to NScano(6) in frame 1 also each have an effective gate pulse pl; The first frequency division control signal FD1 is of a high voltage in frame 2 before tf1 and after ft2, so that the first two frequency division transistors T18, corresponding to the gate driver circuits 20 of stages 1, 2, 5, 6, are switched off, thus NScano(1) to NScano(2) and NScano(5) to NScano(6) in frame 2 each have no effective gate pulse pl; and the first frequency division control signal is of a low voltage between tf1 and ft2, so that the first two frequency division transistors T18, corresponding to the gate driver circuits 20 of stages 1 and 3, are switched on, thus NScano(1) to NScano(3) in frame 2 each have no effective gate pulse pl; The first frequency division control signal FD1 is of a high voltage in frame 3 before tf3, so that the first two frequency division transistors T18, which correspond to the gate driver circuits 20 of stages 1 and 2, are switched off, thus NScano(1) to NScano(2) in frame 3 each have no effective gate pulse pl; and the first frequency division control signal after tf3 is of a low voltage, so that the first four frequency division transistors T18, which correspond to the gate driver circuits 20 of stages 3 to 6, are switched on, thus NScano(3) to NScano(6) in frame 3 each have an effective gate pulse pl;

[0113] For the analysis of the first frequency division control signal FD1 in frame 4, reference can be made to the analysis in frame 2.

[0114] As in Fig. As shown in Figure 13, the gate driver circuits 20 of the first 2 stages, the gate driver circuits 20 of the middle 2 stages, and the gate driver circuits 20 of the last 2 stages each have an update rate of 60 Hz, 120 Hz, and 30 Hz, respectively. From the above, it is evident that in frames 1 to 4, the setting can be as follows: NScano(1) to NScano(2) each have an effective gate pulse pl in frames 1 and 3, NScano(3) to NScano(4) each have an effective gate pulse pl in frames 1 to 4, and the gate control signals NScano(5) to NScano(6) only have an effective gate pulse pl in frame 1. The frequency division control signal FD must be set as follows: The second frequency division control signal FD2 is identical to that in Fig. 12 set to ensure that the cascade transfer signal generated by the gate driver circuit 20 of each stage has an effective cascade transfer pulse; The first frequency division control signal FD1 in frame 1 is of a low voltage for each stage, so that the 6 gate control signals NScano(1) to NScano(6) in frame 1 also each have an effective gate pulse pl; The first frequency division control signal FD1 is of a high voltage in frame 2 before tf1 and after ft2, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) in frame 2 each have no effective gate pulse pl; and the first frequency division control signal is of a low voltage between tf1 and ft2, so that NScano(3) to NScano(4) in frame 2 each have an effective gate pulse pl in a similar manner; The first frequency division control signal FD1 is of a low voltage in frame 3 before tf3, so that NScano(1) to NScano(4) in frame 3 each have an effective gate pulse pl in a similar manner; and the first frequency division control signal is of a high voltage after tf3, so that NScano(5) to NScano(6) in frame 3 each have no effective gate pulse pl;

[0115] For the analysis of the first frequency division control signal FD1 in frame 4, reference can be made to the analysis in frame 2.

[0116] As in Fig. As shown in Figure 14, the gate driver circuits 20 of the first 2 stages, the gate driver circuits 20 of the middle 2 stages, and the gate driver circuits 20 of the last 2 stages each have an update rate of 120 Hz, 30 Hz, and 60 Hz, respectively. From the above, it is evident that in frames 1 to 4, the setting can be as follows: NScano(1) to NScano(2) each have an effective gate pulse pl in frames 1 to 4, NScano(3) to NScano(4) only have an effective gate pulse pl in frame 1, and the gate control signals NScano(5) to NScano(6) have an effective gate pulse pl in frames 1 and 3. The frequency division control signal FD must be set as follows: The second frequency division control signal FD2 is identical to that in Fig. 12 set to ensure that the cascade transfer signal generated by the gate driver circuit 20 of each stage has an effective cascade transfer pulse; The first frequency division control signal FD1 in frame 1 is of a low voltage for each stage, so that the 6 gate control signals NScano(1) to NScano(6) in frame 1 also each have an effective gate pulse pl; The first frequency division control signal FD1 is of a low voltage in frame 2 before tf1, so that NScano(1) to NScano(2) in frame 2 each have an effective gate pulse pl in a similar manner; and the first frequency division control signal is of a high voltage after tf1, so that NScano(3) to NScano(6) in frame 2 each have no effective gate pulse pl; The first frequency division control signal FD1 is of a low voltage in frame 3 before tf2 and after ft3, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) each have an effective gate pulse pl in frame 3; and the first frequency division control signal is of a high voltage between tf2 and ft3, so that NScano(3) to NScano(4) in frame 3 similarly each have no effective gate pulse pl; For the analysis of the first frequency division control signal FD1 in frame 4, reference can be made to the analysis in frame 2.

[0117] As in Fig. As shown in Figure 15, the gate driver circuits 20 of the first 2 stages, the gate driver circuits 20 of the middle 2 stages, and the gate driver circuits 20 of the last 2 stages each have an update rate of 60 Hz, 30 Hz, and 120 Hz, respectively. From the above, it is evident that in frames 1 to 4, the setting can be as follows: NScano(1) to NScano(2) each have an effective gate pulse pl in frames 1 and 3, NScano(3) to NScano(4) each have an effective gate pulse pl only in frame 1, and the gate control signals NScano(5) to NScano(6) each have an effective gate pulse pl in frames 1 to 4. The frequency division control signal FD must be set as follows: The second frequency division control signal FD2 is identical to that in Fig. 12 set to ensure that the cascade transfer signal generated by the gate driver circuit 20 of each stage has an effective cascade transfer pulse; The first frequency division control signal FD1 in frame 1 is of a low voltage for each stage, so that the 6 gate control signals NScano(1) to NScano(6) in frame 1 also each have an effective gate pulse pl; The first frequency division control signal FD1 is of a high voltage in frame 2 before tf1, so that NScano(1) to NScano(4) in frame 2 similarly do not have an effective gate pulse pl; and the first frequency division control signal is of a low voltage after tf1, so that NScano(5) to NScano(6) in frame 2 each have an effective gate pulse pl; The first frequency division control signal FD1 is of a low voltage in frame 3 before tf2 and after ft3, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) each have an effective gate pulse pl in frame 3; and the first frequency division control signal is of a high voltage between tf2 and ft3, so that NScano(3) to NScano(4) in frame 3 similarly each have no effective gate pulse pl;

[0118] For the analysis of the first frequency division control signal FD1 in frame 4, reference can be made to the analysis in frame 2.

[0119] As in Fig. As shown in Figure 16, the gate driver circuits 20 of the first 2 stages, the gate driver circuits 20 of the middle 2 stages, and the gate driver circuits 20 of the last 2 stages each have an update rate of 30 Hz, 60 Hz, and 120 Hz, respectively. From the above content, it is evident that in frames 1 to 4 the setting can be as follows: NScano(1) to NScano(2) each have an effective gate pulse pl only in frame 1, NScano(3) to NScano(4) each have an effective gate pulse pl only in frames 1 and 3, and the gate control signals NScano(5) to NScano(6) each have an effective gate pulse pl in frames 1 to 4. The frequency division control signal FD must be set as follows: The second frequency division control signal FD2 is identical to that in Fig. 12 set to ensure that the cascade transfer signal generated by the gate driver circuit 20 of each stage has an effective cascade transfer pulse; The first frequency division control signal FD1 in frame 1 is of a low voltage for each stage, so that the 6 gate control signals NScano(1) to NScano(6) in frame 1 also each have an effective gate pulse pl; The first frequency division control signal FD1 is of a high voltage in frame 2 before tf1, so that NScano(1) to NScano(4) in frame 2 similarly do not have an effective gate pulse pl; and the first frequency division control signal is of a low voltage after tf1, so that NScano(5) to NScano(6) in frame 2 each have an effective gate pulse pl; The first frequency division control signal FD1 is of a high voltage in frame 3 before tf2, so that NScano(1) to NScano(2) in frame 3 similarly do not have an effective gate pulse pl; and the first frequency division control signal is of a low voltage after tf2, so that NScano(3) to NScano(6) in frame 3 each have an effective gate pulse pl;

[0120] For the analysis of the first frequency division control signal FD1 in frame 4, reference can be made to the analysis in frame 2.

[0121] In conjunction with the relevant explanation in Fig. From 11 to 16, the display panel can still be divided into m sections, which correspond to the m gate driver circuits connected in series 20, and the corresponding m update rates can be represented as a / (j1), a / (j2) to a / (jm), where j1 to jm are positive integers and the m update rates are positive integers, then the number of frames should be set to the least common multiple of the m numbers j1 to jm, e.g., if the two update rates of 120 Hz and 1 Hz are included, 120 frames should represent one cycle. Similarly, reference can be made to the corresponding explanation in the above explanation about "m is the least common multiple of n1, n1, n1".

[0122] In summary, based on the relationship of the refresh rates of the first area, the second area A2, and the third area, the first frequency division control signal FD1 and the second frequency division control signal FD2 can be appropriately controlled. For example, the first area A1, the second area A2, and the third area A3 are used for video playback, the commentary screen (which can be scrolled as needed), and the keyboard screen, respectively. The refresh rates of the three decrease sequentially. This can be achieved by keeping the first frequency division control signal FD1 at a low voltage for several frames and by the second frequency division control signal FD2 switching from an effective (low) voltage to an ineffective (high) voltage. It can also be achieved by...that the second frequency division control signal FD2 is maintained at a low voltage across several frames, and is realized based on the jump of the first frequency division control signal FD1 from an effective (low) voltage to an ineffective (high) voltage; another example is that the first area A1, the second area A2, and the third area A3 are each used for the date display, video playback, and commentary screen (which can be scrolled as needed), i.e., the update rate of the three tends to increase and then decrease; now, it is maintained that each stage can output an effective cascade transmission pulse by constantly maintaining the second frequency division control signal FD2 at a low voltage across several frames.and it is realized based on the jump of the first frequency division control signal FD1 from an effective (high) voltage to an effective (low) voltage, as well as the jump from an effective (low) voltage to an ineffective (high) voltage.

[0123] A frame in which the gate of the multi-stage gate control signal corresponding to any given area has an effective gate pulse can be called a write frame of the area to enable the subpixels Pi, so that at least one corresponding data string can be loaded into the corresponding at least one row of subpixels Pi. A frame in which the gate has no effective gate pulse is called a hold frame of the area, so that the corresponding at least one row of subpixels Pi is maintained on the corresponding at least one data string. For example, frame 1 in Fig. 11 to 16 simultaneously represent a write frame from the three areas corresponding to the gate driver circuits 20 of the first two stages, the middle two stages, and the last two stages; frames 2 and 4 in the Fig. Frames 12 to 13 simultaneously represent a write frame of a region corresponding to the gate driver circuits 20 of the middle two stages, and simultaneously a hold frame of a region corresponding to the gate driver circuits 20 of the first two stages and the last two stages; frame 3 in the Fig. Frames 14 to 15 simultaneously represent a holding frame of a region corresponding to the gate driver circuits 20 of the middle two stages, and simultaneously a writing frame of a region corresponding to the gate driver circuits 20 of the first two stages and the last two stages; frames 2 and 4 in the Fig. 15 to 16 simultaneously represent a holding frame of an area corresponding to the gate driver circuits 20 of the first two stages and the middle two stages, and simultaneously a writing frame of an area corresponding to the gate driver circuits 20 of the last two stages.

[0124] Continuing the explanation above, it can be assumed that in the write frame, the effective gate pulse in the gate control signal inputs the subpixel Pi of the corresponding row, so that several subdata values ​​in the corresponding data string are each transmitted to the corresponding subpixel Pi. Therefore, based on whether two data strings corresponding to two adjacent subpixel Pi change (namely, whether two voltage values ​​corresponding to the two adjacent subdata values ​​transmitted by a data line electrically connected to any row of subpixel Pi are equal, i.e., whether the data signal transmitted by the data line has a jump), it can be determined whether the frame is the write frame of the next row of subpixel Pi or the hold frame of the previous row of subpixel Pi.

[0125] As in Fig. Figure 17 shows that if the data signal source transmitted by the data line has a jump, the data signals transmitted by each data line will simultaneously have an effective jump hop1 due to the line-wise sampling (namely, the gate control signal of the corresponding stage needs an effective gate pulse to turn on the subpixel Pi of the corresponding line, so that the multiple subdata are loaded after the jump), and the frequency division control signal FD can be set to drive the corresponding effective gate pulse to be generated before the occurrence of the corresponding data string to ensure the turning on of the subpixel Pi of the corresponding line, based on the fact that the first frequency division transistor T18 and the second frequency division transistor T20 are each a P-line transistor.The first frequency division control signal FD1 and the second frequency division control signal FD1 are each set to a low voltage to turn on the first frequency division transistor and the second frequency division transistor, respectively.

[0126] In particular, as in Fig. Figure 6 shows the NScano2 signal and the NScano1 signal in Fig. 8 each represent the signals that are in M3 and M4 (each a P-type transistor) in Fig. 6 are loaded, the con(M3) signal and the con(M4) signal in Fig. 17 can each represent a total frequency division control signal FD in two NScan circuits to generate the NScano2 signal and the NScanol signal, “the total frequency division control signal FD” can be understood as a signal that is obtained by summing the first frequency division control signal FD1 and the second frequency division control signal FD2 in the NScan circuit, namely only if the two are at an effective (low) voltage, “the total frequency division control signal FD” can only be at an effective (low) voltage, otherwise it is at an ineffective (high) voltage.

[0127] Referring to the above explanation in Fig. 6 and Fig. 8. The NScano2 signal must be at an effective (high) voltage earlier than the NScano1 signal to ensure that the compensation transistor M3 is switched on in the first reset phase tim1, so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2. Then, in the second reset phase tim2, the reset transistor M4 is switched on, thereby resetting the gate of the driver transistor M1 according to the initialization signal VI2, as shown in Fig. As shown in Figure 17, the con(M3) signal and the con(M4) signal, each corresponding to two NScan circuits, can jump from an ineffective (high) voltage to an effective (low) voltage by 32 and 16 line cycles, respectively, before the "effective jump hop1 of the subdata" in order to switch on the compensation transistor and the reset transistor sequentially, as described in conjunction with the relevant explanation of Fig. 2 and Fig. 3 shown to complete the first reset phase tim1 and the second reset phase tim2 of the subpixel Pi of the corresponding row;

[0128] Referring to Fig. 6. The frequency division control signal FD (which may also be called the con(M2) signal) in the PScan circuit for generating a PScano signal can be controlled such that it jumps from an ineffective (high) voltage to an effective (low) voltage before the "effective jump hop1 of the subdata" (by less than 16 line cycles) or at the "effective jump hop1 of the subdata" (not shown in Fig. 17), to turn on the data transistor, and from the effective step hop1 to the ineffective step hop2 the data line continuously transmits the data signal to perform the data write phase tim3;

[0129] Referring to Fig. 6, after the “non-effective lead hop2 of the sub-data”, the frequency division control signal FD (which can also be called the con(M5 / 6) signal) in the EM circuit can be controlled to generate an EMo1 signal such that it jumps from a non-effective (high) voltage to an effective (low) voltage (not shown in Fig. 17), to turn on the first light emission control transistor and the second light emission control transistor, and from the effective step hop1 to the ineffective step hop2 the data line continuously transmits the data signal to perform the light emission phase tim4;

[0130] Referring to Fig. 6. Between the light emission phase tim4 and the data write phase tim3, the frequency division control signal FD (which can also be called the con (M7 / 8) signal) in the EM circuit can be controlled to generate an EMo2 signal such that it jumps from an ineffective (high) voltage to an effective (low) voltage (not shown in Fig. 17), to turn on the initial transistor and the reset transistor so that the third reset phase is carried out.

[0131] The above “row cycle” can be understood as the sum of the time period in which each row of the subpixel Pi is turned on and the time period in which the row is hidden, within a framework according to Fig. 17. The first 878 lines of subpixel Pi are in the holding frame (namely, the time span in which the corresponding con(M3) signal and con(M4) signal are at an ineffective (high) voltage is first maintained at 878 line cycles), and the con(M3) signal and the con(M4) signal each jump from an effective (low) voltage to an ineffective (high) voltage by 30 line cycles and 14 line cycles respectively before the "ineffective lead hop2 of the subdata", the following 878 lines of subpixel Pi are also in the holding frame (namely, the time span in which the corresponding con(M3) signal and con(M4) signal are at an ineffective (high) voltage is also maintained at 878 line cycles).

[0132] In summary, in the present embodiment, the waveform of the "total frequency division control signal FD" in at least one corresponding gate driver circuit 20 can be set according to the "effective step hop1 of the sub-data" and the "effective step hop1 of the sub-data" of the data signal transmitted by the data line. For example, in the low-frequency range, if the source signal is in the hold frame at a constant voltage signal, the "total frequency division control signal FD" can be equal to the ineffective (high) voltage, so that the effective gate pulse cannot be output. Conversely, in the high-frequency range, if the source signal occurs at the "effective step hop1 of the sub-data", the "total frequency division control signal FD" can be triggered so that it jumps to an effective (low) voltage, so that the effective gate pulse is output normally.In conjunction with the above analysis, it can be seen that the jump time of the “total frequency division control signal FD” in different gate driver circuits 20 of different transistors in the pixel driver circuit 302 can be at the “effective jump hop1 of the subdata” or before or after this in order to realize different operating phases.

[0133] In connection with the above explanation regarding the Fig. 2, Fig. 3 and Fig. 10. It should be noted that if, in the gate driver circuit 20, at least one of the first clock signal and the second clock signal is equal to the constant voltage at any stage, it will result in the corresponding cascade transfer signal and gate control signal each having no effective cascade transfer pulse and effective gate pulse, so that the subpixel Pi of the corresponding row cannot be updated (i.e., turned on).

[0134] Furthermore, the gate drive module comprises 10 successively cascaded n stages of the gate driver circuits 20, where n is a positive integer greater than or equal to 2, and where each of the n stages of the gate driver circuits 20 is loaded with the same clock signal (e.g., the gate driver circuits 20 are of the 6 stages according to Fig. 11 to 16 each loaded with a first clock signal and a second clock signal, and it can be assumed that the positions at which the first clock signal and the second clock signal are loaded in two adjacent stages are opposite each other); and wherein in a frame the clock signal in the time period in which it is effectively applied to the gate driver circuits 20 of the i-th to the (i+k)-th stage is alternately equal to a first clock voltage and a second clock voltage (they can each be a high voltage and a low voltage in the first clock signal and second clock signal, namely, several rows of subpixels Pi corresponding to the gate control signals of the i-th to the (i+k)-th stage can be driven to turn on), and wherein i, k are positive integers greater than or equal to 1;and wherein, when the gate control signal output by the gate driver circuits 20 of the (i+k+1)th to the nth stage does not have an effective gate pulse, the clock signal in the time period in which it is effectively applied to the gate driver circuits 20 of the (i+k+1)th to the nth stage is constant, equal to the first clock voltage or the second clock voltage (which also corresponds to the fact that the corresponding multiple subpixels Pi are not switched on).

[0135] It is understood that the gate control signals of the i-th to the (i+k)-th stage each have an effective gate pulse, and the gate control signals of the (i+k+1)-th to the n-th stage each have no effective gate pulse. Based on this, in the present embodiment, the clock signal is set to a constant voltage during the time period in which it is effectively applied to the gate driver circuits 20 of the (i+k+1)-th to the n-th stage. This not only fulfills the requirement that "the gate control signals of the (i+k+1)-th to the n-th stage each have no effective gate pulse" but can also save power.

[0136] To ensure that the effective gate pulse of the gate control signal of the (i+k)th stage is fully generated (to avoid interruption due to the conversion of the clock signal to a constant voltage signal), the clock signal can be adjusted to be equal to the constant voltage signal after the effective gate pulse has been fully generated.

[0137] It should be noted that the condition must be met that the gate control signals of the last several stages each have no effective gate pulse. If at least one of the last several stages of the gate control signals has an effective gate pulse, the voltage of the gate driver circuits 20 of the several stages, which correspond to the gate control signals of the several stages without an effective gate pulse to which the clock signal is effectively applied, cannot be set as a constant voltage, since this would simultaneously prevent the generation of a cascade transfer signal acting on the next stage, thus making it impossible to ensure that at least one subsequent stage of the gate control signals has an effective gate pulse.

[0138] As in Fig. As shown in Figure 11, in frames 2 and 4, after the time at which the effective gate pulse in NScano(2) ends, at least one of the first clock signal and the second clock signal (the two can be the same or different) can be adjusted to be equal to at least one of the high voltage and the low voltage, and in frame 3, after the time at which the effective gate pulse in NScano(4) ends, at least one of the first clock signal and the second clock signal can be adjusted to be equal to at least one of the high voltage and the low voltage.

[0139] As in Fig. As shown in Figure 12, in frames 2 and 4, after the time at which the effective gate pulse in NScano(4) ends, at least one of the first clock signal and the second clock signal can be adjusted in a similar way so that it is equal to at least one of the high voltage and the low voltage.

[0140] As in Fig. As shown in Figure 13, in frames 2 to 4, after the time at which the effective gate pulse in NScano(4) ends, at least one of the first clock signal and the second clock signal can be adjusted in a similar way so that it is equal to at least one of the high voltage and the low voltage.

[0141] As in Fig. As shown in Figure 14, in frames 2 and 4, after the time at which the effective gate pulse ends in NScano(2), at least one of the first clock signal and the second clock signal can be adjusted in a similar way so that it is equal to at least one of the high voltage and the low voltage.

[0142] As mentioned above, for example, as in Fig. 15 and Fig.As shown in Figure 16, in frames 1 and 4 the first clock signal and the second clock signal in each frame are alternately held at a first clock voltage and a second clock voltage at all times, since NScano(5) and NScano(6) (namely the gate driver circuits 20 of the last two stages) each have an effective gate pulse to ensure that the cascade transfer signal of each stage can be generated until the gate control signal of the sixth stage is generated.

[0143] The gate drive module and display panel provided by the present application comprise a frequency division signal line and several cascaded gate driver circuits, the gate driver circuit comprising a cascade transmission unit and output unit. A cascade transmission frequency division control unit is electrically connected to the cascade transmission receiving unit via the first or second node (and further electrically connected to the cascade transmission output unit via the fourth node), and an output frequency division control unit is arranged between the first and second nodes and the third node. The two are used to control, in accordance with the frequency division control signal, the signal of a gate connected to the first and second nodes.to control the cascade transmission output unit to output the cascade transmission signal of the present stage, and in accordance with the frequency division control signal, to control the signal of the third node to control the output unit to output the gate control signal of the present stage, so that the invalidity of the gate control signal does not affect the invalidity of the cascade transmission signal, and a sequential down-conversion mode of several areas of a display panel can be realized by setting whether the cascade transmission signal has an effective cascade transmission pulse, and by setting whether the gate control signal has an effective gate pulse (since the effective cascade transmission pulse can always be present), any inverter mode of several areas of a display panel is realized.

[0144] The principle and embodiment of the present application are explained in more detail with reference to examples. All explanations of the embodiments serve only to aid in understanding the method of the present application and its core ideas; according to the intent of the present application, a person skilled in the art in this field will make a modification with regard to the detailed embodiment and the scope of application; in summary, the content of this description should not be understood as limiting the present application.

Claims

[1] Gate drive module (10) comprising a frequency division signal line (FDL) and several cascaded gate driver circuits (20), wherein the frequency division signal line (FDL) is used to transmit frequency division control signals (FD) to the several gate driver circuits (20), and wherein the gate driver circuit (20) comprises: a cascade transmission unit (201) comprising a cascade transmission receiver unit (2011) and a cascade transmission output unit (2012), wherein the cascade transmission receiver unit (2011) is used to receive the cascade transmission signals generated by the gate driver circuit (20) of the upper stage, and wherein the cascade transmission output unit (2012) is electrically connected to the cascade transmission receiver unit (2011) via a first node (P) and a second node (Q) and is used to output the cascade transmission signals of the present stage to the gate driver circuit (20) of the lower stage in accordance with the signal of the first node (P) and the signal of the second node (Q); an output unit (202) which is electrically connected to the cascade transmission output unit (2012) by one of the first node (P) and the second node (Q) and a third node (S) and is used to output a gate control signal in accordance with the signal of one of the first node (P) and the second node (Q) and the signal of the third node (S);and a cascade transmission frequency division control unit (203) which is electrically connected to the cascade transmission receiving unit (2011) via the first node (P) or the second node (Q) and electrically connected to the cascade transmission output unit (2012) via a fourth node (R) and is used to control, in accordance with the frequency division control signal (FD), the signal from one of the first node (P) and the second node (Q) to drive the cascade transmission output unit (2012) to output the cascade transmission signal of the present stage; and; an output frequency division control unit (204) which is connected between one of the first node (P) and the second node (Q) and the third node (S) and is used to control the signal of the third node (S) in accordance with the frequency division control signal (FD) in order to drive the output unit (202) to output the gate control signal of the present stage, the cascade transmission receiving unit (2011) comprises the following: a control unit (20111) for the fourth node (R) which is electrically connected to a clock signal line and the fourth node (R) to control the signal of the fourth node (R) in accordance with the clock signal transmitted by the clock signal line; a control unit (20112) for the second node (Q) which is electrically connected to a clock signal line and the second node (Q) to control the signal of the second node (Q) in accordance with the clock signal; an input unit (20114), wherein the input end of the input unit (20114) is electrically connected to the gate driver circuit (20) of the upper stage to load the cascade transfer signal generated by the gate driver circuit (20) of the upper stage, and wherein the output end of the input unit (20114) is electrically connected to the control unit (20111) for the fourth node (R) and the control unit (20112) for the second node (Q) or to the control unit (20111) for the fourth node (R) and a control unit (20113) for the first node (P), wherein the cascade transmission frequency division control unit (203) and the output frequency division control unit (204) are each electrically connected to the first node (P); and wherein the input unit (20114) comprises an input transistor (T3), and wherein the gate of the input transistor (T3) is loaded with the clock signal, and wherein the source of the input transistor (T3) is configured as the input end of the input unit (20114), and wherein the drain of the input transistor (T3) is configured as the output end of the input unit (20114); and wherein the control unit (20111) for the fourth node (R) comprises a first transistor (T4), a seventh transistor (T5), and a second transistor (T6) and third transistor (T7) connected in series, and wherein the gate of the seventh transistor (T5) is electrically connected to the drain of the input transistor (T3), and wherein the source of the seventh transistor (T5) is charged with the clock signal, and wherein the gate of the first transistor (T4) is charged with the clock signal, and wherein the source of the first transistor (T4) is charged with the second voltage, and wherein the drain of the first transistor (T4) is electrically connected to the gate of the second transistor (T6) and the drain of the seventh transistor (T5), and wherein the drain of the second transistor (T6) is electrically connected to the source of the third transistor (T7), and wherein the source of the second transistor (T6) and the gate of the third transistor (T7) are each charged with the clock signal,and wherein the drain of the third transistor (T7) is electrically connected to the fourth node (R); and wherein the control unit (20112) for the second node (Q) comprises a fourth transistor (T13), a first capacitor (C1), and a fifth transistor (T1) and sixth transistor (T2) connected in series, and wherein the gate of the fourth transistor (T13) is charged with the control signal, and wherein the source of the fourth transistor (T13) is charged with the first voltage, and wherein the drain of the fourth transistor (T13) is electrically connected to the second node (Q), and wherein the gate of the fifth transistor (T1) is electrically connected to the drain of the first transistor (T4), and wherein the source of the fifth transistor (T1) is charged with the first voltage, and wherein the drain of the fifth transistor (T1) is electrically connected to the source of the sixth transistor (T2), and wherein the drain of the sixth transistor (T2) is charged with the clock signal,and wherein the gate of the sixth transistor (T2) is also charged with the cascade transfer signal generated by the gate driver circuit (20) of the upper stage, and wherein the first capacitor (C1) is electrically connected between the gate and the drain of the sixth transistor (T2). [2] Gate drive module (10) according to claim 1, wherein the frequency division control signal (FD) comprises a first frequency division control signal (FD1) and a second frequency division control signal (FD2), and wherein the frequency division signal line (FDL) comprises a first frequency division signal line (FDL1) for transmitting the first frequency division control signal (FD1) and a second frequency division signal line (FDL2) for transmitting the second frequency division control signal (FD2); and wherein the first frequency division signal line (FDL1) is electrically connected to the output frequency division control unit (204) to control the signal of the third node (S); and wherein the second frequency division signal line (FDL2) is electrically connected to the cascade transmission frequency division control unit (203) to control the signal of one of the first node (P) and the second node (Q). [3] Gate drive module (10) according to claim 2, wherein the output frequency division control unit (204) comprises: a first frequency division transistor (T18), wherein the gate of the first frequency division transistor (T18) is connected to the first frequency division signal line (FDL1), wherein the source of the first frequency division transistor (T18) is electrically connected to the first node (P) or the second node (Q), and wherein the drain of the control transistor is electrically connected to the third node; and wherein the first frequency division control signal (FD1) is used to control the third node (S) to electrically connect or disconnect it from the first node (P) or the second node (Q). [4] Gate drive module (10) according to claim 3, wherein the output frequency division control unit (204) further comprises: a second frequency division transistor (T20), wherein the gate of the second frequency division transistor (T20) is electrically connected to a fifth node of the cascade transmission unit (201), and wherein the source of the second frequency division transistor (T20) is electrically connected to the first frequency division signal line (FDL1), and wherein the drain of the second frequency division transistor (T20) is electrically connected to the gate of the first frequency division transistor (T18); and wherein the first frequency division control signal (FD1) and the signal of the fifth node are used to control the third node (S) to be electrically connected to or disconnected from the first node (P) or the second node (Q); and wherein the signal of the fifth node is also used to control the cascade transfer signal and gate control signal output by the gate driver circuit (20) of the present stage. [5] Gate drive module (10) according to claim 2, wherein the cascade transmission frequency division control unit (203) comprises: a third frequency division transistor (T17), wherein the gate of the third frequency division transistor (T17) is electrically connected to the second frequency division signal line (FDL2), wherein the source of the first frequency division transistor (T18) is electrically connected to the cascade transmission receiving unit (2011) via a fourth node (R), and wherein the drain of the third frequency division transistor (T17) is electrically connected to the first node (P) or the second node (Q); and wherein the second frequency division control signal (FD2) is used to control the fourth node (R) to connect or disconnect electrically from the first node (P) or the second node (Q). [6] Gate drive module (10) according to claim 3, wherein the cascade transmission frequency division control unit (203) comprises: a third frequency division transistor (T17), wherein the gate of the third frequency division transistor (T17) is electrically connected to the second frequency division signal line (FDL2), wherein the source of the first frequency division transistor (T18) is electrically connected to the cascade transmission receiving unit (2011) via a fourth node (R), and wherein the drain of the third frequency division transistor (T17) is electrically connected to the first node (P) or the second node (Q); and wherein the second frequency division control signal (FD2) is used to control the fourth node (R) to connect or disconnect electrically from the first node (P) or the second node (Q). [7] Gate drive module (10) according to claim 6, wherein the cascade transfer output unit (2012) comprises: a first-stage cascade transfer output transistor (T10), wherein the gate of the first-stage cascade transfer output transistor (T10) is electrically connected to the first node (P), and wherein the source of the first-stage cascade transfer output transistor (T10) is electrically connected to a first voltage line to charge a first voltage, and wherein the drain of the first-stage cascade transfer output transistor (T10) is electrically connected to the cascade transfer output end (OUT) in the gate driver circuit (20) to output the cascade transfer signal; a second-stage cascade transfer output transistor (T9), wherein the gate of the second-stage cascade transfer output transistor (T9) is electrically connected to the second node (Q), and wherein the source of the second-stage cascade transfer output transistor (T9) is electrically connected to a second voltage line to charge a second voltage, and wherein the drain of the second-stage cascade transfer output transistor (T9) is electrically connected to the cascade transfer output end (OUT). [8] Gate drive module (10) according to claim 7, wherein the output unit comprises: a first output transistor (T22), wherein the gate of the first output transistor (T22) is electrically connected to the third node (S), and wherein the source of the first output transistor (T22) is electrically connected to a first voltage line, and wherein the drain of the first output transistor (T22) is electrically connected to the gate output end (OUTA) in the gate driver circuit (20) for outputting the gate control signal; a second output transistor (T21), wherein the gate of the second output transistor (T21) is electrically connected to the first node (P) or the second node (Q), and wherein the source of the second output transistor (T21) is electrically connected to a second voltage line, and wherein the drain of the second output transistor (T21) is electrically connected to the gate output end (OUTA). [9] Gate drive module (10) according to claim 8, wherein the gate driver circuit (20) is electrically connected to at least one corresponding pixel driver circuit (302), and wherein the gate output end (OUTA) is electrically connected to the pixel transistor in each of the corresponding pixel driver circuits (302), and wherein the first voltage is greater than the second voltage; and wherein the pixel transistor is a P-type transistor, and wherein the drain of the third frequency division transistor (T17) and the source of the first frequency division control transistor are each electrically connected to the first node (P); or the pixel transistor is a P-type transistor, and wherein the drain of the third frequency division transistor (T17) and the source of the first frequency division control transistor are each electrically connected to the second node (Q). [10] Gate drive module (10) according to claim 1, wherein the control unit (20112) for the second node (Q) further comprises: a tenth transistor (T14), wherein the source of the tenth transistor (T14) is charged with the cascade transfer signal generated by the gate driver circuit (20) of the upper stage, and wherein the gate of the tenth transistor (T14) is charged with the clock signal, and wherein the drain of the tenth transistor (T14) is electrically connected to the gate of the sixth transistor (T2); an eleventh transistor (T16), wherein the gate and source of the eleventh transistor (T16) are each electrically connected to the gate of the sixth transistor (T2), and wherein the drain of the eleventh transistor (T16) is electrically connected to the second node (Q). [11] Display panel (100), comprising: a gate drive module (10) according to claim 2; a panel body (30) comprising multiple subpixels (Pi) and multiple scanning lines (SL), wherein the multiple subpixels (Pi) comprise a light-emitting device (301) and a pixel driver circuit (302) for driving the light-emitting device (301) to emit light, and wherein the pixel driver circuit (302) comprises at least one transistor; and wherein the gate control signal output by the gate driver circuit (20) is transmitted through the corresponding sampling line to the gate of the multiple transistors in the corresponding multiple pixel driver circuits (302). [12] Display panel (100) according to claim 11, wherein the output frequency division control unit (204) comprises: a first frequency division transistor (T18), wherein the gate of the first frequency division transistor (T18) is connected to the first frequency division signal line (FDL1), wherein the source of the first frequency division transistor (T18) is electrically connected to the first node (P) or the second node (Q), and wherein the drain of the control transistor is electrically connected to the third node (S); and wherein the first frequency division control signal (FD1) is used to control the third node (S) to electrically connect or disconnect it from the first node (P) or the second node (Q). [13] Display panel (100) according to claim 11, wherein the display panel (100) is in a down-conversion mode and an up-conversion mode at different times, and wherein the multiple gate driver circuits (20) comprise multiple cascaded first gate driver circuits (2001) and multiple cascaded second gate driver circuits (2002) which are cascaded after the multiple first gate driver circuits (2001); and wherein the multiple subpixels (Pi) comprise multiple first subpixels (Pi1) electrically connected to the multiple first gate driver circuits (2001) and multiple second subpixels (Pi2) electrically connected to the multiple second gate driver circuits (2002), and wherein the multiple first subpixels (Pi1) form a first display area and the multiple second subpixels (Pi2) form a second display area; and wherein, in the down-conversion mode, the update rate of the first display area is higher than that of the second display area; and wherein, in the upward conversion mode, the update rate of the first display area is lower than that of the second display area. [14] Display panel (100) according to claim 13, wherein in the step-down conversion mode the first frequency division control signal (FD1) is used to control the third node (S) in the gate driver circuit (20) of each stage so that it is electrically connected to the first node (P) or the second node (Q); and wherein in a first frame type the second frequency division control signal (FD2) is used to control the first node (P) or the second node (Q) in the first gate driver circuit (2001) so that it is electrically connected to the fourth node (R) to control the output gate control signal so that it has an effective gate pulse, thereby turning on the corresponding light-emitting device (301); and wherein in the first frame type the second frequency division control signal (FD2) is further used to control the first node (P) or the second node (Q) in the second gate driver circuit (2002) so that it is separated from the fourth node (R) in order to control the output gate control signal so that it has no effective gate pulse, thereby not turning on the corresponding light-emitting device (301). [15] Display panel (100) according to claim 13, wherein in the step-down conversion mode the second frequency division control signal (FD2) is used to control the fourth node (R) in the gate driver circuit (20) of each stage so that it is electrically connected to the first node (P) or the second node (Q); and wherein in a second frame type the first frequency division control signal (FD1) is used to control the third node (S) in the first gate driver circuit (2001) to be electrically connected to the first node (P) or the second node (Q) in order to control the output gate control signal so that it has an effective gate pulse, thereby turning on the corresponding light-emitting device (301); and wherein in the second frame type the first frequency division control signal (FD1) is further used to control the third node (S) in the second gate driver circuit (2002) so that it is separated from the first node (P) or the second node (Q) in order to control the output gate control signal so that it has no effective gate pulse, thereby not turning on the corresponding light-emitting device (301). [16] Display panel (100) according to claim 13, wherein in the up-conversion mode the second frequency division control signal (FD2) is used to control the fourth node (R) in the gate driver circuit (20) of each stage so that it is electrically connected to the first node (P) or the second node (Q); and wherein in a third frame type the first frequency division control signal (FD1) is used to control the third node (S) in the first gate driver circuit (2001) so that it is separated from the first node (P) or the second node (Q) in order to control the output gate control signal so that it has no effective gate pulse, thereby not turning on the corresponding light-emitting device (301); and wherein in the third frame type the first frequency division control signal (FD1) is used to control the first node (P) or the second node (Q) in the second gate driver circuit (2002) so that it is electrically connected to the fourth node (R) to control the output gate control signal so that it has an effective gate pulse, thereby turning on the appropriate light-emitting device (301). [17] Display panel (100) according to claim 14, wherein in the up-conversion mode the second frequency division control signal (FD2) is used to control the fourth node (R) in the gate driver circuit (20) of each stage so that it is electrically connected to the first node (P) or the second node (Q); and wherein in a third frame type the first frequency division control signal (FD1) is used to control the third node (S) in the first gate driver circuit (2001) so that it is separated from the first node (P) or the second node (Q) in order to control the output gate control signal so that it has no effective gate pulse, thereby not turning on the corresponding light-emitting device (301); and wherein in the third frame type the first frequency division control signal (FD1) is used to control the first node (P) or the second node (Q) in the second gate driver circuit (2002) so that it is electrically connected to the fourth node (R) to control the output gate control signal so that it has an effective gate pulse, thereby turning on the appropriate light-emitting device (301). [18] Display panel (100) according to claim 11, wherein the gate drive module (10) comprises n stages of the gate driver circuits (20) connected in succession, and wherein n is a positive integer greater than or equal to 2, and wherein each of the n stages of the gate driver circuits (20) is loaded with the same clock signal; and wherein in a frame the clock signal in the time period in which it is effectively applied to the gate driver circuits (20) of the i-th to the (i+k)-th stage is alternately equal to a first clock voltage and a second clock voltage, and wherein i, k are positive integers greater than or equal to 1; and wherein, when the gate control signal output by the gate driver circuits (20) of the (i+k+1)th to the nth stage does not have an effective gate pulse, the clock signal is constant equal to the first clock voltage or the second clock voltage during the time period in which it is effectively applied to the gate driver circuits (20) of the (i+k+1)th to the nth stage.

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