SEMICONDUCTOR COMPONENT

Abstract

The semiconductor device comprises: a semiconductor layer having a surface; a source region and a drain region positioned on the surface and spaced apart in a first direction when viewed in the thickness direction perpendicular to the surface; a channel region formed on the surface between the source region and the drain region and adjacent to the source region; and a gate electrode positioned on the channel region with an interposed gate insulating film. The semiconductor device further comprises: a trench formed between the source region and the drain region; an insulating film provided on an inner wall of the trench; and an embedded electrode provided within the trench and surrounded by the insulating film.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. GENERAL STATE OF THE ART

[0002] A lateral semiconductor device having a drain region and a source region formed on a main surface of a substrate is known as a typical power semiconductor device (see, for example, Patent Literature 1). DOCUMENT ON THE PRIOR ARTPatent literature

[0003] Patent Literature 1: Japanese Patent Application Laid-Open No. 2000-286417 SUMMARY OF THE INVENTIONTechnical Problem

[0004] There is a need to improve the breakdown voltage of a lateral semiconductor device. Solution to the problem

[0005] A semiconductor device according to a general aspect of the present disclosure includes a semiconductor layer, a source region, a drain region, a channel region, a gate electrode, a drift region, a trench, an insulating film, and an embedded electrode. The semiconductor layer has a surface. The source region and the drain region are disposed on the surface and are spaced apart from each other in a first direction when viewed in a thickness direction orthogonal to the surface. The channel region is formed on the surface between the source region and the drain region. The channel region is adjacent to the source region. The gate electrode is disposed on the channel region, with a gate insulating film disposed therebetween. The drift region is formed between the channel region and the drain region. The trench is formed between the source region and the drain region.The insulating film is arranged on or against the inner walls of the trench. The embedded electrode is arranged in the trench and surrounded by the insulating film. Advantageous effects of the invention

[0006] The semiconductor device according to the one general aspect of the present disclosure improves the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view showing an example of a semiconductor device according to an embodiment. Fig. 2 is a cross-sectional view of the Fig. 1 along the line 2-2. Fig. 3 is a cross-sectional view of the Fig. 1 along the line 3-3. Fig. 4 is a schematic cross-sectional view showing an example of a modified semiconductor device. Fig. 5 is a schematic plan view showing an example of a modified semiconductor device. Fig. 6 is a schematic plan view showing an example of a modified semiconductor device. Fig. 7 is a schematic plan view showing an example of a modified semiconductor device. Fig. 8 is a schematic plan view showing an example of a modified semiconductor device. Fig. 9 is a schematic plan view showing an example of a modified semiconductor device. Fig. 10 is a schematic plan view showing an example of a modified semiconductor device. Fig. 11 is a schematic plan view showing an example of a modified semiconductor device. Fig. 12 is a schematic plan view showing an example of a modified semiconductor device. Fig. 13 is a schematic plan view showing an example of a modified semiconductor device. Fig. 14 is a schematic cross-sectional view showing an example of a modified semiconductor device. Fig. 15 is a schematic cross-sectional view showing an example of a modified semiconductor device. DESCRIPTION OF EMBODIMENTS

[0007] An embodiment of a semiconductor device according to the present disclosure will now be described with reference to the drawings.

[0008] Elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. To facilitate understanding, cross-sectional drawings may not show hatching lines. The accompanying drawings merely illustrate exemplary embodiments according to the present disclosure and are not intended to limit the present disclosure. Terms such as "first," "second," and "third" are used in this disclosure to distinguish items or subjects and not for ordinal purposes.

[0009] This detailed description includes exemplary embodiments of methods, devices, and / or systems according to the present disclosure. This detailed description is for illustrative purposes and is not intended to limit embodiments of the present disclosure or the application and uses of the embodiments. Configuration of the semiconductor device

[0010] Fig. 1 is a schematic plan view showing an example of a semiconductor device according to the present embodiment. Fig. 2 is a cross-sectional view of the Fig. 1 along the line 2-2. Fig. 3 is a cross-sectional view of the Fig. 1 along the line 3-3.

[0011] As in Fig. 2 and Fig. 3, a semiconductor device 10 may include a semiconductor substrate 11, an insulating layer 12, and a semiconductor layer 13.

[0012] The semiconductor substrate 11 may be a silicon (Si) substrate. The semiconductor substrate 11 has a first surface 11u and a second surface 11r located on a side opposite the first surface 11u. The semiconductor substrate 11 may be a p-substrate (denoted by "p-sub") containing a p-type impurity. The semiconductor substrate 11 may be a substrate made of, for example, silicon carbide (SiC) or the like.

[0013] The insulating layer 12 is arranged on the first surface 11u of the semiconductor substrate 11. The insulating layer 12 has a first surface 12u and a second surface 12r, which is arranged on a side opposite the first surface 12u. In the Fig. 2 and Fig. In the example shown in Figure 3, the second surface 12r of the insulating layer 12 is in contact with the first surface 11u of the semiconductor substrate 11. The insulating layer 12 is made of a material including, for example, SiO2. The insulating layer 12 may be formed by oxidizing a surface of the semiconductor substrate 11. The insulating layer 12 may be formed, for example, by a buried oxide (BOX) film.

[0014] The semiconductor layer 13 is formed on the first surface 12u of the insulating layer 12. The semiconductor layer 13 has a first surface 13u and a second surface 13r arranged on a side opposite the first surface 13u. The first surface 13u corresponds to a "surface" of the semiconductor layer 13. In the Fig. 2 and Fig. 3, the second surface 13r of the semiconductor layer 13 is in contact with the first surface 12u of the insulating layer 12. The second surface 13r of the semiconductor layer 13 covers, for example, the entire first surface 12u of the insulating layer 12.

[0015] The semiconductor layer 13 can be formed, for example, by an epitaxial layer. The semiconductor layer 13 is made of a material including Si. The semiconductor layer 13 contains an n-type impurity. The semiconductor layer 13 can, for example, be laminated onto the semiconductor substrate 11 with the insulating layer 12 disposed therebetween. Such a semiconductor device 10 has a silicon-on-insulator (SOI) structure in which the semiconductor layer 13 is formed on the semiconductor substrate 11 with the insulating layer 12 disposed therebetween.

[0016] A direction orthogonal to the first surface 13u of the semiconductor layer 13 is the thickness direction of the semiconductor component 10. This thickness direction is referred to below as the Z direction. Two directions that are orthogonal to each other and to the Z direction are referred to as the X direction and the Y direction. The X direction and the Y direction are parallel to the first surface 13u of the semiconductor layer 13. The X direction corresponds to a "first direction." The Y direction corresponds to a "second direction." Source region, drain region and gate electrode

[0017] As in the Fig. 1 to 3, the semiconductor device 10 has a buffer region 21, a drain region 22, a body region 23, a source region 24 and a contact region 25.

[0018] The buffer region 21 is formed on the first surface 13u of the semiconductor layer 13. The buffer region 21 is an n-type region containing an n-type impurity. As shown in Fig. 1, the body region 23 extends in the Y direction when viewed in the Z direction, which is orthogonal to the first surface 13u of the semiconductor layer 13.

[0019] As in the Fig. 2 and Fig. 3, the drain region 22 is formed in the buffer region 21. The drain region 22 contains an n-type impurity. The drain region 22 has a higher impurity concentration than the body region 23. The drain region 22 is an n + -Type region. As in Fig. 1, the drain region 22 extends in the Y direction when viewed in the Z direction.

[0020] As in the Fig. 2 and Fig. 3, the body region 23 is formed on the first surface 13u of the semiconductor layer 13. The body region 23 is spaced apart from the buffer region 21 in the X direction. The body region 23 is a p-type region containing a p-type impurity. As shown in Fig. 1, the body region 23 extends in the Y direction when viewed in the Z direction.

[0021] As in the Fig. 2 and Fig. 3, the source region 24 is formed in the body region 23. The source region 24 contains an n-type impurity. For example, the source region 24 may have the same impurity concentration as the drain region 22. The source region 24 is an n + -Type region. As in Fig. 1, the source region 24 extends in the Y direction when viewed in the Z direction.

[0022] As in the Fig. 2 and Fig. 3, the contact region 25 is formed in the body region 23. The contact region 25 and the drain region 22 are arranged on opposite sides of the source region 24. The contact region 25 is arranged to contact the source region 24. The contact region 25 contains a p-type impurity. The contact region 25 has, for example, a higher impurity concentration than the body region 23. The contact region 25 is a p + -Type region. As in Fig. 1, the contact region 25 extends in the Y direction when viewed in the Z direction.

[0023] As in Fig. 3, the semiconductor layer 13 arranged between the buffer region 21 and the body region 23 functions as a drift region 13a. As shown in the Fig. 2 and Fig. 3, a gate electrode 32 is arranged on the first surface 13u of the semiconductor layer 13, with a gate insulating layer 31 arranged therebetween. As shown in Fig. 1, the gate electrode 32 extends in the Y-direction. As shown in the Fig. 2 and Fig. 3, the gate insulating film 31 and the gate electrode 32 cover the body region 23 located between the source region 24 and the semiconductor layer 13 in the X direction. In addition, the gate insulating film 31 and the gate electrode 32 cover a part of the source region 24 adjacent to the body region 23. Furthermore, the gate insulating film 31 and the gate electrode 32 cover a part of the semiconductor layer 13 adjacent to the body region 23. The gate insulating film 31 is formed of an insulating material such as silicon oxide (SiO2), silicon nitride (SiN), or the like. The gate electrode 32 is formed of a material including, for example, a conductive polysilicon or the like.

[0024] As in the Fig. 2 and Fig. 3, a portion of the body region 23 facing the gate electrode 32 with the insulating film 31 interposed therebetween functions as a channel region 23a in which an inversion layer (channel) is formed. Trench and embedded electrode

[0025] As in the Fig. 1 and Fig. 2, the semiconductor device 10 has a trench 41, an insulating film 42 and an embedded electrode 43.

[0026] The trench 41 is formed between the source region 24 and the drain region 22. The semiconductor device 10 of the present embodiment has more than one trench 41. When viewed in the Z direction, each trench 41 is formed between the gate electrode 32 and the buffer region 21. The trenches 41 extend in the X direction when viewed in the Z direction. As shown in Fig. 1, the trenches 41 are arranged side by side in the Y direction. In other words, the trenches 41 are arranged side by side in the Y direction, which is orthogonal to the X direction in which the trenches 41 extend. Accordingly, when viewed in the Z direction, the trenches 41 and the semiconductor layers 13 (drift regions 13a) are arranged alternately in the Y direction, which is orthogonal to the X direction in which the trenches 41 extend.

[0027] Each trench 41 has a width W1 in the Y direction that is smaller than a length L1 of the trench 41 in the X direction. The trenches 41 are arranged in the Y direction at a distance W2. For example, the distance W2 between two trenches 41 is greater than the width W1 of the trench 41 in the Y direction.

[0028] As in Fig. As shown in Figure 2, the trench 41 extends from the first surface 13u of the semiconductor layer 13 to the second surface 13r of the semiconductor layer 13 through the semiconductor layer 13. The second surface 13r of the semiconductor layer 13 is in contact with the first surface 12u of the insulating layer 12. Thus, the trench 41 extends from the first surface 13u of the semiconductor layer 13 to the insulating layer 12 through the semiconductor layer 13.

[0029] As in Fig. 1, when viewed in the Z direction, an end of the trench 41 located toward the source region 24 is arranged in the same position as an end of the gate electrode 32 located toward the drain region 22. In other words, the end of the trench 41 located toward the source region 24 coincides with the end of the gate electrode 32 located toward the drain region 22. In the present embodiment, when viewed in the Z direction, an end of the trench 41 located toward the drain region 22 is in contact with the buffer region 21. In other words, the end of the trench 41 located toward the drain region 22 coincides with an end of the buffer region 21 located toward the source region 24.

[0030] As in Fig. As shown in Figure 1, the trench 41 has inner walls 411, 412, 413, and 414. The first inner wall 411 and the second inner wall 412 extend in the X direction. The first inner wall 411 faces the second inner wall 412 in the Y direction. The third inner wall 413 and the fourth inner wall 414 extend in the Y direction. The third inner wall 413 faces the fourth inner wall 414 in the X direction.

[0031] The insulating film 42 covers the inner walls 411 to 414 of the trench 41. The insulating film 42 includes a first insulating film 421 covering the first inner wall 411, a second insulating film 422 covering the second inner wall 412, a third insulating film 423 covering the third inner wall 413, and a fourth insulating film 424 covering the fourth inner wall 414. The insulating films 421 to 424 are each in contact with a corresponding one of the inner walls 411 to 414. The insulating film 42 is formed or made of, for example, silicon oxide or the like.

[0032] The embedded electrode 43 is formed in the trench 41. As shown in the Fig. 1 and Fig. 2, the embedded electrode 43 has a first surface 43u, a second surface 43r, and side surfaces 431, 432, 433, and 434. The first surface 43u faces in the same direction as the first surface 13u of the semiconductor layer 13. The second surface 43r faces in a direction opposite to the first surface 43u. In the present embodiment, the second surface 43r of the embedded electrode 43 is in contact with the first surface 12u of the insulating layer 12. The first side surface 431 and the second side surface 432 face opposite sides in the Y direction. The third side surface 433 and the fourth side surface 434 face opposite sides in the X direction. The side surfaces 431 to 434 are each in contact with a corresponding one of the insulating films 421 to 424. The embedded electrode 43 is formed of a material.made of, for example, a conductive polysilicon or the like. The embedded electrode 43 may be formed or made of a material including tungsten (W) or the like.

[0033] As in Fig. 1, in the present embodiment, a film thickness T1 of the first insulating film 421 is equal to a film thickness T2 of the second insulating film 422. Furthermore, a film thickness T3 of the third insulating film 423 is equal to a film thickness T4 of the fourth insulating film 424. The film thicknesses T1 and T2 each correspond to a "first film thickness." The film thicknesses T3 and T4 each correspond to a "second film thickness." In the present embodiment, the film thicknesses T1 to T4 of the insulating films 421 to 424 are identical.

[0034] As described above, the embedded electrode 43 is arranged in each trench 41. Accordingly, when viewed in the Z direction, the trenches 41, the embedded electrodes 43, and the semiconductor layers 13 (drift regions 13a) are arranged alternately in the Y direction. Connection and terminal

[0035] As in the Fig. 2 and Fig. 3, the semiconductor component 10 has terminals 51, 52, 53, and 54. The drain region 22 is connected to the terminal (D) 51 by or via a connecting element 61. The gate electrode 32 is connected to the terminal (G) 52 by or via a connecting element 62. The embedded electrode 43 is connected to the gate electrode 32 by or via a connecting element 64. The source region 24 is connected to the terminal (S) 53 by or via a connecting element 63. The source region 24 is connected to the contact region 25 by or via a connecting element 65. The terminals 51 to 53 can each be, for example, a pad (electrode) that is designed to enable a connection of a wire or the like to the semiconductor component 10. In the semiconductor component 10, the connecting elements 61 to 65 may each be a conductor formed in one or more connecting layers.The conductor is formed or manufactured from a material that includes, for example, a conductive material such as aluminum (Al), copper (Cu), or the like. The semiconductor substrate 11 is connected to the terminal (sub) 54. The terminal 54 can, for example, be a pad (electrode) configured to enable a connection of the semiconductor component 10 to a die pad or the like. Operation

[0036] The operation of the semiconductor device 10 is described below.

[0037] In the semiconductor device 10, a voltage is applied between the drain region 22 and the source region 24. In the semiconductor device 10, a gate voltage applied to the gate electrode 32 controls the ON / OFF states of the current flowing between the drain region 22 and the source region 24.

[0038] When the gate electrode 32 receives a gate voltage greater than or equal to a threshold voltage, a channel (inversion layer) is formed in the body region 23 (channel region 23a) facing the gate electrode 32 in the Z direction. Electrons flow through the inversion layer from the source region 24 to the semiconductor layer 13. The electric field between the drain region 22 and the source region 24 puts the semiconductor device 10 into an ON state, in which a drift current flows from the drain region 22 to the source region 24.

[0039] The embedded electrode 43 is connected to the gate electrode 32. Thus, the aforementioned gate voltage is applied to the embedded electrode 43. This gate voltage accumulates electrons in a portion of the semiconductor layer 13 facing the embedded electrode 43 with the insulating film 42 interposed therebetween. Such accumulation of electrons has substantially the same benefit as increasing the impurity concentration of the semiconductor layer 13 (drift region 13a) around the trench 41 in which the embedded electrode 43 is disposed. This reduces the on-resistance of the semiconductor device 10.

[0040] When the gate electrode 32 receives a gate voltage equal to or less than the threshold voltage, such as a voltage equivalent to that of the source region 24, the pn junction between the p-type body region 23 and the n-type semiconductor layer 13 is reverse-biased by the voltage between the drain region 22 and the source region 24. This expands a depletion layer from the pn junction. Furthermore, when the gate voltage is applied to the embedded electrode 43 connected to the gate electrode 32, the depletion layer expands in a portion of the semiconductor layer 13 facing the embedded electrode 43 with the insulating film 42 interposed therebetween. In this way, the semiconductor device 10 has relatively high breakdown voltage characteristics. Advantages

[0041] As described above, the present embodiment has the following advantages.

[0042] (1) The semiconductor device 10 includes the semiconductor layer 13, the source region 24, and the drain region 22. The semiconductor layer 13 has the first surface 13u. The source region 24 and the drain region 22 are arranged on the first surface 13u and are spaced apart from each other in the X direction (first direction) when viewed in the Z direction (thickness direction) orthogonal to the first surface 13u. The semiconductor device 10 includes the channel region 23a and the gate electrode 32. The channel region 23a is formed on the first surface 13u between the source region 24 and the drain region 22. The channel region 23a is adjacent to the source region 24. The gate electrode 32 is arranged on the channel region 23a, with the gate insulating film 31 arranged therebetween. The semiconductor device 10 further includes the trench 41, the insulating film 42, and the embedded electrode 43.The trench 41 is formed between the source region 24 and the drain region 22. The insulating film 42 is disposed on the inner walls 411 to 414 of the trench 41. The embedded electrode 43 is disposed in the trench 41 and surrounded by the insulating film 42.

[0043] When the gate electrode 32 receives a gate voltage greater than or equal to a threshold voltage, a channel (inversion layer) is formed in the body region 23 (channel region 23a) facing the gate electrode 32 in the Z direction. Electrons flow through the inversion layer from the source region 24 to the semiconductor layer 13. The electric field between the drain region 22 and the source region 24 puts the semiconductor device 10 into an ON state, in which a drift current flows from the drain region 22 to the source region 24.

[0044] The embedded electrode 43 is connected to the gate electrode 32. Thus, the aforementioned gate voltage is applied to the embedded electrode 43. This gate voltage accumulates electrons in a portion of the semiconductor layer 13 facing the embedded electrode 43 with the insulating film 42 interposed therebetween. Such accumulation of electrons has substantially the same benefit as increasing the impurity concentration of the semiconductor layer 13 (drift region 13a) around the trench 41 in which the embedded electrode 43 is disposed. This reduces the on-resistance of the semiconductor device 10.

[0045] (2) When the gate electrode 32 receives a gate voltage equal to or less than the threshold voltage, such as a voltage equivalent to that of the source region 24, the pn junction between the p-type body region 23 and the n-type semiconductor layer 13 is reverse-biased by the voltage between the drain region 22 and the source region 24. This expands a depletion layer from the pn junction. Furthermore, when the gate voltage is applied to the embedded electrode 43 connected to the gate electrode 32, the depletion layer expands in a portion of the semiconductor layer 13 facing the embedded electrode 43 with the insulating film 42 interposed therebetween.

[0046] In this way, the semiconductor device 10 exhibits relatively high breakdown voltage characteristics. This improves the breakdown voltage of the semiconductor device 10. Modified examples

[0047] The above embodiment may be modified as described below. The above embodiment and the modified examples described below may be combined as long as there is no technical conflict. In the modified examples described below, the same components as the corresponding components of the above embodiment are denoted by the same reference numerals. Such components will not be described in detail.

[0048] In contrast to the above embodiment, the embedded electrode 43, as shown in Fig. 4, be connected to the source region 24. In this case, a depletion layer is formed in the same way as when a gate voltage less than or equal to a threshold voltage is applied to the gate electrode 32. This improves the breakdown voltage.

[0049] As in Fig. 5, the trench 41 may be formed such that the end of the trench 41 disposed toward the drain region 22 is separated or spaced from the buffer region 21 when viewed in the Z direction.

[0050] As in Fig. 6, the trench 41 may be formed such that the end of the trench 41 disposed toward the drain region 22 overlaps the buffer region 21 when viewed in the Y direction.

[0051] As in Fig. As shown in Figure 7, the trench 41 may be formed such that the end of the trench 41 disposed toward the source region 24 is spaced or separated from the gate electrode 32 when viewed in the Z direction. In this case, the insulating film 42 may be formed such that the film thickness T3 of the third insulating film 423 differs from the film thickness T4 of the fourth insulating film 424.

[0052] As in Fig. As shown in Figure 8, the trench 41 may be formed such that the end of the trench 41 disposed toward the source region 24 overlaps the gate electrode 32 when viewed in the Z direction. In this case, the insulating film 42 may be formed such that the film thickness T3 of the third insulating film 423 differs from the film thickness T4 of the fourth insulating film 424.

[0053] As in Fig. As shown in Figure 9, the trench 41 may be formed such that the end of the trench 41 facing the source region 24 is in contact with the body region 23 when viewed in the Z direction. In this case, the insulating film 42 may be formed such that the film thickness T3 of the third insulating film 423 differs from the film thickness T4 of the fourth insulating film 424. Preferably, the embedded electrode 43 does not overlap with the gate electrode 32 when viewed in the Z direction.

[0054] As in Fig. As shown in Figure 10, the trench 41 may be formed such that the end of the trench 41 facing the source region 24 overlaps the body region 23 when viewed in the Y direction. In this case, the insulating film 42 may be formed such that the film thickness T3 of the third insulating film 423 differs from the film thickness T4 of the fourth insulating film 424. Preferably, the embedded electrode 43 does not overlap the gate electrode 32 when viewed in the Z direction.

[0055] As in Fig. 11, when viewed in the Z direction, the trench 41 may be formed such that the width W1 of the trench 41 is greater than the distance W2 between two trenches 41 adjacent in the Y direction. Alternatively, the trench 41 may be formed such that the width W1 of the trench 41 is equal to the distance W2 between two trenches 41 adjacent in the Y direction.

[0056] As in Fig. As shown in Figure 12, when viewed in the Z direction, the film thicknesses T1 to T4 of the insulating film 42 (421 to 424) covering the inner walls 411 to 414 of the trench 41 can be varied. For example, the film thicknesses T1 to T4 can each be greater than a width W3 of the embedded electrode 43.

[0057] As in Fig. 13, the insulating film 42 may be formed such that the film thickness T1 of the first insulating film 421 and the film thickness T2 of the second insulating film 422 are each smaller than each of the film thickness T3 of the third insulating film 423 and the film thickness T4 of the fourth insulating film 424. Alternatively, the insulating film 42 may be formed such that the film thickness T1 of the first insulating film 421 and the film thickness T2 of the second insulating film 422 are each larger than each of the film thickness T3 of the third insulating film 423 and the film thickness T4 of the fourth insulating film 424.

[0058] As in Fig. As shown in Figure 14, the embedded electrode 43 may be spaced apart from the insulating layer 12. The insulating film 42 is disposed between the second surface 43r of the embedded electrode 43 and the insulating layer 12.

[0059] As in Fig. As shown in Figure 15, the trench 41 may be spaced or separated from the insulating layer 12 in the Z direction. In other words, the trench 41 does not need to extend through the semiconductor layer 13.

[0060] Buffer region 21 can be omitted or eliminated.

[0061] The embedded electrode 43 may be connected to a terminal arranged on the semiconductor component. The terminal may be a pad (electrode) configured to enable a connection of a wire or the like to the semiconductor component.

[0062] In this description, the term "on" encompasses not only the meaning of "on" but also the meaning of "above," unless the context indicates otherwise. Accordingly, the expression "first layer formed on the second layer" may, in one embodiment, mean that the first layer is formed in direct contact with the second layer, and in another embodiment, mean that the first layer is arranged over or above the second layer without contacting the second layer. Thus, the term "on" also allows for a structure in which another layer is formed between the first layer and the second layer.

[0063] The Z-axis direction specified in this description does not necessarily have to be the vertical direction and does not necessarily have to completely coincide with the vertical direction. In the structures disclosed above (e.g., the structure shown in Fig.1) are limited to upward and downward with respect to the Z-axis direction as stated in this description, not to upward and downward with respect to the vertical direction. For example, the X-axis direction may be the vertical direction. Alternatively, the Y-axis direction may be the vertical direction.

[0064] The above descriptions are exemplary. In addition to the elements and methods (manufacturing processes) described to illustrate the techniques of this disclosure, one skilled in the art would recognize the potential for numerous combinations and substitutions. The present disclosure encompasses all substitutions, modifications, and variations within the scope of the disclosure, which includes the claims. LIST OF REFERENCE SYMBOLS 10 semiconductor component 11 Semiconductor substrate 11r second surface 11u first surface 12 Insulating layer 12r second surface 12u first surface 13 Semiconductor layer 13a Drift region (“drift region”) 13r second surface 13u first surface 21 buffer region (“buffer region”) 22 Drain region (“drain region”) 23 Body region 23a Canal Region 24 Source region (“source region”) 25 Contact region 31 Gate insulating film 32 Gate electrode 41 Trench or ditch 411 first interior wall 412 second interior wall 413 third interior wall 414 fourth interior wall 42 Insulating film 421 first insulating film 422 second insulating film 423 third insulating film 424 fourth insulating film 43 embedded electrode 43r second surface 43u first surface 431 first page surface 432 second side surface 433 third side surface 434 fourth side surface 51, 52, 53, 54 Terminal 61, 62, 63, 54, 65 connecting element L1 length T1, T2, T3, T4 film thickness W1 Width W2 distance W3 width QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2000-286417

[0003]

Claims

[1] Semiconductor device, comprising: a semiconductor layer having a surface; a source region and a drain region disposed on the surface and spaced apart from each other in a first direction when viewed in a thickness direction orthogonal to the surface; a channel region formed on the surface between the source region and the drain region, the channel region being adjacent to the source region; a gate electrode disposed on the channel region with a gate insulating film disposed therebetween; a trench formed between the source region and the drain region; an insulating film disposed on inner walls of the trench; and an embedded electrode arranged in the trench and surrounded by the insulating film. [2] The semiconductor device according to claim 1, wherein the trench extends in the first direction, wherein a direction orthogonal to both the thickness direction and the first direction is a second direction. [3] A semiconductor device according to claim 2, further comprising: a buffer region in which the drain region is formed, wherein an end of the trench disposed toward the drain region is in contact with the buffer region. [4] A semiconductor device according to claim 2, further comprising: a buffer region in which the drain region is formed, wherein an end of the trench disposed toward the drain region is spaced from the buffer region. [5] A semiconductor device according to claim 2, further comprising: a buffer region in which the drain region is formed, wherein an end of the trench disposed toward the drain region overlaps the buffer region when viewed in the second direction. [6] A semiconductor device according to any one of claims 2 to 5, wherein an end of the trench disposed toward the source region is located at a same position as an end of the gate electrode disposed toward the drain region when viewed in the thickness direction. [7] A semiconductor device according to any one of claims 2 to 5, wherein an end of the trench disposed toward the source region is closer to the drain region than the gate electrode when viewed in the thickness direction. [8] A semiconductor device according to any one of claims 2 to 5, wherein an end of the trench disposed toward the source region overlaps the gate electrode when viewed in the thickness direction. [9] A semiconductor device according to any one of claims 2 to 5, wherein an end of the trench disposed toward the source region is in contact with the channel region. [10] A semiconductor device according to any one of claims 2 to 9, wherein the embedded electrode does not overlap the gate electrode when viewed in the thickness direction. [11] The semiconductor device according to any one of claims 2 to 10, wherein, when viewed in the thickness direction, a first film thickness of the insulating film disposed in the first direction between the embedded electrode and one of the inner walls of the trench is larger than a second film thickness of the insulating film disposed in the second direction between the embedded electrode and one of the inner walls of the trench. [12] The semiconductor device according to claim 11, wherein the first film thickness is greater than a thickness of the embedded electrode in the second direction. [13] A semiconductor device according to any one of claims 2 to 12, wherein the trench is one of a plurality of trenches, and the trenches are spaced apart from each other in the second direction. [14] The semiconductor device according to claim 13, wherein a distance between two of the trenches adjacent to each other in the second direction is greater than a width of one of the two trenches in the second direction. [15] The semiconductor device according to claim 13, wherein a distance between two of the trenches adjacent to each other in the second direction is smaller than a width of one of the two trenches in the second direction. [16] Semiconductor device according to one of claims 1 to 15, further comprising: a semiconductor substrate; and an insulating layer arranged on the semiconductor substrate, wherein the semiconductor layer is arranged on the insulating layer. [17] A semiconductor device according to claim 16, wherein the trench extends from the surface of the semiconductor layer to the insulating layer through the semiconductor layer. [18] A semiconductor device according to claim 16 or 17, wherein the embedded electrode is in contact with the insulating layer. [19] Semiconductor device according to one of claims 1 to 18, further comprising: a connecting element that connects the embedded electrode to the source region. [20] Semiconductor device according to one of claims 1 to 18, further comprising: a connecting element that connects the embedded electrode to the gate electrode.

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