GLASS RECIRCULATOR FOR OPTICAL SIGNAL ROUTING ACROSS PHOTONIC INTEGRATED CIRCUITS

Abstract

Various disclosed embodiments relate to the routing of optical signals from silicon photonic elements, such as a photonic integrated circuit. The present disclosure includes a glass recirculation layer with waveguides at different heights to enable rerouting of such optical signals from silicon photonic elements, such as a photonic integrated circuit. Rerouting of optical signals can be achieved in the glass recirculation layer with reduced losses due to reduced waveguide intersections therein.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Patent Application No. 17 / 957,094, filed September 30, 2022, and entitled “GLASS RECIRCULATOR FOR OPTICAL SIGNAL REROUTING ACROSS PHOTONIC INTEGRATED CIRCUITS,” which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments described herein relate generally to semiconductor devices and packaging, and more particularly to photonic integrated circuits. BACKGROUND

[0003] Silicon photonics devices are a good candidate for low-cost, high-performance devices, such as those used to enhance data-centric technology. However, packaging silicon photonics devices can be challenging, leading to compatibility and integration issues. Furthermore, routing photonic integrated circuit (PIC) signals to and from the PIC, such as fiber connectors and electronic integrated circuits (EIC), can be challenging. It is desirable to have a cost-effective and efficient packaging technology that addresses these and other technical challenges. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example but not limitation, various embodiments discussed in this document. Fig. 1 illustrates a schematic diagram of a photonic integrated circuit using a glass recirculation layer in one example. Fig. 2 illustrates a schematic diagram of a photonic integrated circuit using a glass recirculation layer in one example. Fig. 3 illustrates a schematic diagram of a photonic integrated circuit using a glass recirculation layer in one example. Fig. 4A-4B are schematic diagrams illustrating a glass recirculation layer in one example. Fig. 5 illustrates a schematic flow diagram showing a method of fabricating a photonic integrated circuit using a glass recirculation layer in one example. Fig. 6 illustrates a system including a photonic integrated circuit using a glass recirculation layer in one example. DETAILED DESCRIPTION

[0005] The following description and drawings illustrate specific embodiments sufficiently to enable one skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, procedural, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments recited in the claims include all available equivalents of those claims.

[0006] Silicon photonics (SiP) is a combination of silicon integrated circuits and semiconductor lasers that can be used to fabricate photonic integrated circuits (PICs). PICs can produce or detect optical light at one or more frequencies. PICs can extend, enable, and increase data transmission while consuming less power than conventional circuits. Such PICs can enable energy-efficient bandwidth scaling. PICs can enable faster data transmission over longer distances compared to conventional electronics.

[0007] However, encapsulating silicon photonics devices can be challenging. Fiber coupling compatibility and integration with electronic integrated circuits (EICs) can be difficult due to mode field diameter mismatches and tight alignment tolerances. The use of waveguides in glass can be a good solution for such SIP encapsulation, partly due to the optical and mechanical properties of glass.

[0008] The present disclosure describes, among other things, using a glass layer or substrate (referred to herein as a "glass recirculation layer") to route optical signals with respect to a photonic integrated circuit (PIC). The glass recirculation layer may be used as a substrate or component attached to the PIC to assist in rerouting various signals to and from the PIC and an associated electronic integrated circuit (EIC). The glass recirculation layer may include waveguides to enable an optical signal to be routed between desired locations.

[0009] Optical computation can utilize various silicon photonic components, arrays, and integrated circuits, such as Mach-Zehnder interferometers (MZIs), micro-ring resonators (MRRs), phase shifters, or other PIC configurations to enable matrix multiplication, quantum logic gates, or other applications. However, as silicon photonic arrays increase in size, to accommodate these applications, a larger number of optical signals should be routed, such as within photonic integrated circuits (PICs) or between a PIC and electronic integrated circuits (EICs).

[0010] In particular, as the size of silicon photonics compute arrays increases, optical signals must be routed from one location within such an array to another, where there is a risk of routing waveguides crossing. This can cause intersections on an active silicon photonics layer. Such intersections can induce losses. Previous solutions addressed these challenges by adding waveguide layers, such as silicon or silicon nitride, on top of a PIC to route or recirculate optical signaling across the PIC. However, such amorphous silicon introduces signal loss. Although silicon nitride can exhibit improved power loss compared to crystalline silicon, silicon nitride can also require larger waveguide features and reduced routing density.Furthermore, as the size of photonic silicon arrays increases, more passive waveguide layers would be required to achieve this routing, causing optical signals to be transmitted between them, which would induce additional loss.

[0011] As discussed herein, a glass recirculation layer is used as a substrate or component with a PIC. The glass recirculation layer can be applied and configured to enable optical signal routing using glass waveguides and reduce signal loss. Such a glass recirculation layer can be formed using accessible techniques, such as laser direct writing (LDW). Such methods can enable controlled z-height waveguide formation, such as to reduce waveguide intersections. A cross-section of such a glass recirculation layer would demonstrate the use of a glass substrate with waveguides at varying z-axis points.

[0012] In one example, a semiconductor package may include: an electronic integrated circuit die; a photonic integrated circuit die coupled to the electronic integrated circuit die; and a glass recirculation layer comprising one or more waveguides configured to route one or more optical signals from the photonic integrated circuit die.

[0013] In one example, a semiconductor package may include: an electronic integrated circuit die; a photonic integrated circuit die coupled to the electronic integrated circuit die; and a glass recirculation layer comprising one or more waveguides configured to route one or more optical signals from the photonic integrated circuit die; a package; and a touch screen.

[0014] In one example, a method of fabricating a semiconductor device may include: attaching a glass layer to a photonic integrated circuit; fabricating a plurality of waveguides in the glass layer to produce a glass recirculation layer, wherein at least two of the plurality of waveguides are at different heights; and connecting the photonic integrated circuit and the glass recirculation layer to an electronic integrated circuit.

[0015] Fig. 1 illustrates a cross-sectional diagram of a semiconductor package 100 including a photonic integrated circuit 110 using a glass recirculation layer 120 in one example. The semiconductor package 100 may include the photonic integrated circuit 110, the glass recirculation layer 120 with waveguides 122, a photonic silicon layer 124, an external fiber connector 126, an integrated circuit 130, and a via 132. In the semiconductor package 100, the glass recirculation layer 120 may be located between the photonic integrated circuit 110 and the integrated circuit 130.

[0016] The photonic integrated circuit (PIC) 110 may be configured to produce and receive multiple optical signals, such as in the visible or infrared (IR) spectrum. In some cases, the photonic integrated circuit 110 may be encapsulated by an overmold layer. The photonic integrated circuit 110 may include a single or multiple optical ports where optical signals exit the photonic integrated circuit 110 toward the waveguides 122 in the glass recirculation layer 120. The photonic integrated circuit 110 may be bonded to the glass recirculation layer 120, such as by hybrid bonding. In some cases, bumps, pillars, and combinations thereof may be used to bond the photonic integrated circuit 110 to the glass recirculation layer 120. In one example, the photonic integrated circuit 110 and the glass recirculation layer 120 may be fabricated separately.

[0017] The glass recirculation layer 120 may be, for example, a silicon dioxide or borosilicate glass. In some cases, alternative glass materials may be used. The glass recirculation layer 120 may include the waveguides 122 to enable rerouting of one or more optical signals from the photonic integrated circuit 110. The glass recirculation layer 120 may, in one example, be attached to the photonic circuit 110 through the photonic silicon layer 124. In some cases, gaps between the photonic integrated circuit 110 and the glass recirculation layer 120 may be kept open with air or filled with an index-matching fluid. In some cases, the glass recirculation layer 120 may function as a substrate in the semiconductor package 100. In some cases, the glass recirculation layer 120 may act as a component in the semiconductor package 100.In some cases, the glass recirculation layer 120 may be an amorphous glass or a crystalline glass.

[0018] The glass recirculation layer 120 can be stacked over the photonic silicon layer 124. In this way, various locations on the glass recirculation layer 120 and the photonic silicon layer 124 can be routed to each other by waveguides therein. Waveguides can be fabricated in the glass recirculation layer 120 and / or the photonic silicon layer 124 as desired.

[0019] The waveguides 122 fabricated in the glass recirculation layer 120 can be fabricated, for example, using direct laser writing. The waveguides 122 can be laser-modified waveguides located in the glass recirculation layer 120. The glass recirculation layer 120 can be a separate piece of glass bonded to the photonic integrated circuit 110. The waveguides 122 can be located in the glass recirculation layer 120 extending between various locations on the photonic integrated circuit 110.

[0020] The waveguides 122 may be configured to conduct electromagnetic waves, such as an optical signal produced by the photonic integrated circuit 110, within the assembly 100 or out to an output, such as the external fiber connector 126. The waveguides 122 may be connected to one or more optical fibers through the external fiber connector 126 or other types of outputs for such an optical signal. For example, the waveguides 122 may be aligned with a coupling port sized and shaped for connection to an optical fiber. In some cases, such a coupling port may include V-grooves for connection to an optical fiber.

[0021] The waveguides 122 may be a laser-modified guide, such as by laser direct writing (LDW). The waveguides 122 may be fabricated for proper alignment within the glass recirculation layer 120. For example, the waveguides 122 may be cut at an angle that allows for proper alignment and routing of optical signals produced by the photonic integrated circuit 110. In some cases, the waveguides 122 may be curved.

[0022] The waveguides 122 may include two or more waveguides, such as between different positions on the photonic integrated circuit 110, the integrated circuit 130, the external fiber connector 126, or combinations thereof. The waveguides 122 may be located at different locations within the glass recirculation layer 120. For example, the waveguides 122 may be located at different heights (e.g., z-axis points). The plurality of waveguides 122 may be located to enable optical signal routing between desired locations without the waveguides 122 crossing.

[0023] The external fiber connector 126 may be aligned with one or more of the waveguides 122 to enable movement of the optical signal out of the semiconductor package 100, such as to a fiber. The integrated circuit 130 may be an integrated circuit in communication with the photonic integrated circuit 110. The integrated circuit 130 may be hybrid bonded to the glass recirculation layer 120.

[0024] Via 132 may, for example, include a glass via (TGV), a silicon via (TSV), a combined via traversing both glass recirculation layer 120 and PIC 110, or both a discrete TSV and a discrete TGV that are electrically coupled. Via 132 may, for example, be used for power delivery, input / output, or other uses, such as between photonic integrated circuit 110, integrated circuit 130, other components, and substrates. For example, TGVs may be fabricated in glass recirculation layer 120, and TSVs may be fabricated in photonic integrated circuit 110.

[0025] Fig. 2 illustrates a schematic diagram of a semiconductor package 200 including a photonic integrated circuit 210 using a glass recirculation layer 220 in one example. The semiconductor package 200 may include the photonic integrated circuit 210, the glass recirculation layer 220 with waveguides 222, a photonic silicon layer 210a, an external fiber connector 226, an electronic integrated circuit 230, and a via 232. The semiconductor package 200 may include components similar to those in the semiconductor package 100.

[0026] However, in the semiconductor package 200, the photonic integrated circuit 210 may be located between the electronic integrated circuit 230 and the glass recirculation layer 220. In this case, the integrated circuit 230 may be bonded to the photonic integrated circuit 210. The glass recirculation layer 220 may function as a package core or a substrate.

[0027] Fig. 3 illustrates a schematic diagram of a semiconductor package 300 including a photonic integrated circuit 310 using a glass recirculation layer 320 in one example. The semiconductor package 300 may include the photonic integrated circuit 310, the glass recirculation layer 320 with waveguides 322, a photonic silicon layer 320a, an external fiber connector 326, an electronic integrated circuit 330, and a via 332. The semiconductor package 300 may include components similar to those in the semiconductor package 100.

[0028] However, in the semiconductor package 300, the photonic integrated circuit 310 may be located between the glass recirculation layer 320 and the electronic integrated circuit 330. In this case, the via 332 may include TSVs that extend through the photonic integrated circuit 310 and the photonic silicon layer 320a. No TGVs are present in the semiconductor package 300.

[0029] Semiconductor package 100, semiconductor package 200, and semiconductor package 300 are examples of packages that utilize a glass recirculation layer for optical signal routing for a photonic integrated circuit. In some cases, such packages may be used in devices, such as within a package. In some cases, devices may include other components, such as buttons, touch screens, user interfaces, switches, lights, or other components as appropriate.

[0030] Fig. 4A-4B are schematic diagrams illustrating a stacked recirculation layer 400 in one example. The stacked recirculation layer 400 may include a location 410, a location 412, a potential route 413 with an intersection 414, an intersection 416, an intersection 418, and a location 420, a location 422 with a waveguide 424, and a waveguide 426. Here, waveguides may be fabricated at different z-heights in the glass recirculation layer 400B to eliminate or reduce intersections.

[0031] As the size of silicon photonic computation arrays increases, optical signals may need to be routed from one location in an array to another. Waveguides between such locations may encounter intersections that should be avoided to reduce losses. Optical computation using silicon photonic features, such as Mach-Zehnder interferometers (MZIs), micro-ring resonators (MRRs), and phase shifters, can be used for quantum logic gates, such as for quantum photonics, or matrix multiplication, such as for accelerating artificial intelligence, among other applications.

[0032] As in Fig. As shown in Figure 4A, an exemplary silicon photonics layer 400A may include a first location 410 and a second location 412 that should be connected to a waveguide. In the glass recirculation layer 400A, the waveguides and locations are in the same plane, e.g., the same height within the silicon photonics layer 400A. In this case, the waveguide runs along three intersections 414, 416, 418, with a potential route 413 for connecting the first location 410 and the second location 412. At each of the three intersections 414, 416, 418, the optical signal may be subject to loss.

[0033] In comparison, Fig. 4B, a glass recirculation layer 400B may be stacked over the silicon photonics layer 400A. The exemplary glass recirculation layer 400B may include locations 410, 412, 420, 422. These locations may be connected to the waveguides 424 and 426 in the glass recirculation layer 400B as needed. In this case, the waveguide 424 may be at a different height (e.g., different z-axis) than the waveguide 426. For this reason, the number of intersection points is reduced. Furthermore, the stacked waveguides may help reduce overall intersection points within the silicon photonics layer 400A. In some cases, the waveguides in the silicon photonics layer 400A and the glass recirculation layer 400B may be crossed over each other during routing.

[0034] The glass recirculation layer 400B can be stacked against a PIC or other photonic silicon layer and, using the waveguides, enable optical signals to be routed from location to location as needed. Coupling losses between silicon waveguides and glass waveguides can be approximately 0.2 dB or less per intersection. Other features, such as delay lines, multiplexers, demultiplexers, or other features, can also be integrated into the glass recirculation layer 400B for additional functionality. Such MRRs or MZIs can be used in the silicon photonic layer to switch waveguide channels in the glass recirculation layer on or off as needed.

[0035] Fig. 5 illustrates a schematic flow diagram showing a method 500 for fabricating a photonic integrated circuit using a glass recirculation layer in one example. The method may include step 510, step 512, step 514, step 516, and step 518.

[0036] At step 510, the photonic integrated circuit (PIC) may include a silicon photonic layer for alignment with a glass recirculation layer. A silicon through-via (TSV) may be formed in the photonic integrated circuit. At step 512, a glass recirculation layer may be attached to the package on top of the silicon photonic layer.

[0037] At step 514, waveguides may be formed in the glass recirculation layer, such as by direct laser writing. The waveguides may be formed at varying heights within the glass recirculation layer, such as to enable routing of optical signals from the photonic integrated circuit without intersections.

[0038] At step 516, an electronic integrated circuit (EIC) may be attached to the package. The EIC may be attached, for example, by hybrid bonding, solder bump and fill, pillars, or other methods. In some cases, the EIC may be attached to the PIC opposite the glass recirculation layer. The TSV may be extended through the EIC to enable connectivity between the PIC and the EIC, with optical signals routed through the PIC and the glass recirculation layer.

[0039] At step 518, an external fiber connector may be attached to the assembly, such as to enable the PIC to be connected to a fiber.

[0040] Fig. 6 illustrates a system-level diagram representing an example of an electronic device (e.g., a system) that may include a PIC and glass circuit and / or previously described methods. In one embodiment, system 600 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular phone, a mobile computing device, a smartphone, an internet device, or any other type of computing device. In some embodiments, system 600 includes a system-on-chip (SOC) system.

[0041] In one embodiment, processor 610 includes one or more processor cores 612 and 612N, where 612N represents the Nth processor core within processor 610, where N is a positive integer. In one embodiment, system 600 includes multiple processors including 610 and 605, where processor 605 includes logic similar or identical to the logic of processor 610. In some embodiments, processing core 612 includes, among other things, pre-fetch logic for fetching instructions, decode logic for decoding the instructions, execution logic for executing instructions, and the like. In some embodiments, processor 610 includes a cache 616 for caching instructions and / or data for system 600. Cache 616 may be organized into a hierarchical structure including one or more levels of cache memory.

[0042] In some embodiments, the processor 610 includes a memory controller 614 configured to perform functions that enable the processor 610 to access and communicate with the memory 630, which may include volatile memory 632 and / or non-volatile memory 634. In some embodiments, the processor 610 is coupled to the memory 630 and a chipset 620. The processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, a wireless antenna interface 678 operates in accordance with, among other things, the IEEE 802.11 standard and its associated family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

[0043] In some embodiments, volatile memory 632 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRMA), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. Non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0044] Memory 630 stores information and instructions to be executed by processor 610. In one embodiment, memory 630 may also store temporary variables or other intermediate information while processor 610 executes instructions. In the illustrated embodiment, chipset 620 is connected to processor 610 via point-to-point (PtP or PP) interfaces 617 and 622. Chipset 620 enables processor 610 to be connected to other elements in system 600. In some embodiments of the example system, interfaces 617 and 622 operate according to a PtP communication protocol, such as Intel ® Quick Path Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0045] In some embodiments, chipset 620 is operable to communicate with processor 610, 605N, display device 640, and other devices, including a bus bridge 672, a smart TV 676, I / O devices 674, non-volatile memory 660, a storage medium (such as one or more mass storage devices) 662, a keyboard / mouse 664, a network interface 666, and various forms of consumer electronics 677 (such as a PDA, smartphone, tablet, etc.), etc. In one embodiment, chipset 620 is coupled to these devices through an interface 624. Chipset 620 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and / or receive wireless signals.In one example, any combination of components in a chipset may be separated by a contiguous flexible shield as described in the present disclosure.

[0046] Chipset 620 is connected to display device 640 via interface 626. Display 640 may be, for example, a liquid crystal display (LCD), a light-emitting diode (LED) array, an organic light-emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 610 and chipset 620 are combined into a single SOC. Chipset 620 is also connected to one or more buses 650 and 655 that interconnect various system elements, such as I / O devices 674, non-volatile memory 660, a storage medium 662, a keyboard / mouse 664, and a network interface 666. Buses 650 and 655 may be interconnected via a bus bridge 672.

[0047] In one embodiment, mass storage device 662 includes, but is not limited to, a solid-state drive, a hard disk drive, a Universal Serial Bus flash memory device, or any other form of computer data storage medium. In one embodiment, network interface 666 is implemented by any type of well-known network interface standard, including, but not limited to, an Ethernet interface, a Universal Serial Bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface, and / or any other type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its associated family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMAX, or any other form of wireless communication protocol.

[0048] Although the Fig.6 are depicted as separate blocks within system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 616 is depicted as a separate block within processor 610, cache memory 616 (or selected aspects of 616) may be incorporated into processor core 612. Various notes & examples

[0049] To better illustrate the method and apparatus disclosed herein, a non-limiting list of embodiments is provided: Example 1 is a semiconductor package comprising: an electronic integrated circuit die; a photonic integrated circuit die coupled to the electronic integrated circuit die; and a glass recirculation layer comprising one or more waveguides configured to route one or more optical signals from the photonic integrated circuit die. In Example 2, the subject matter of Example 1 optionally includes a silicon photonics layer between the photonic integrated circuit die and the glass recirculation layer. In Example 3, the subject matter of one or more of Examples 1-2 optionally includes the glass recirculation layer comprising a plurality of waveguides, wherein at least two of the plurality of waveguides are located at different heights. In Example 4, the article of any one or more of Examples 1-3 optionally includes the glass recirculation layer comprising an amorphous glass. In Example 5, the article of any one or more of Examples 1-4 optionally includes the glass recirculation layer comprising a crystalline glass. In Example 6, the subject matter of any one or more of Examples 1-5 optionally includes the glass recirculation layer being disposed between the electronic integrated circuit die and the photonic integrated circuit die. In Example 7, the subject matter of any one or more of Examples 1-6 optionally includes the glass recirculation layer being disposed between the photonic integrated circuit die on a side opposite the electronic integrated circuit die. In Example 8, the subject matter of any one or more of Examples 1-7 optionally includes the glass recirculation layer comprising two or more waveguides, each aligned along a different z-axis. In Example 9, the subject matter of any one or more of Examples 1-8 optionally includes the glass recirculation layer further comprising a substrate. In Example 10, the subject matter of any one or more of Examples 1-9 optionally includes the glass recirculation layer comprising a component. In Example 11, the subject matter of any one or more of Examples 1-10 optionally includes a via, including a glass via, a silicon via, or combinations thereof. In Example 12, the subject matter of Example 11 optionally includes the via being configured to enable connection from the electronic integrated circuit to power, input, output, or combinations thereof. In Example 13, the subject matter of any one or more of Examples 1-12 optionally includes the photonic integrated chip comprising one or more Mach-Zehner interferometers, micro-ring resonators, phase shifters, or combinations thereof. Example 14 is an apparatus comprising: a semiconductor package comprising: an electronic integrated circuit die; a photonic integrated circuit die coupled to the electronic integrated circuit die; and a glass recirculation layer comprising one or more waveguides configured to route one or more optical signals from the photonic integrated circuit die; a package; and a touch screen. In Example 15, the subject matter of Example 14 optionally includes the glass recirculation layer comprising a plurality of waveguides. In Example 16, the subject matter of Example 15 optionally includes at least two of the plurality of waveguides being located at different heights within the glass recirculation layer. Example 17 is a method of fabricating a semiconductor device, the method comprising: attaching a glass layer to a photonic integrated circuit; fabricating a plurality of waveguides in the glass layer to produce a glass recirculation layer, wherein at least two of the plurality of waveguides are at different heights; and connecting the photonic integrated circuit and the glass recirculation layer to an electronic integrated circuit. In Example 18, the subject matter of Example 17 optionally includes that fabricating a plurality of waveguides comprises direct laser writing. In Example 19, the subject matter of any one or more of Examples 17-18 optionally includes wherein connecting the photonic integrated circuit comprises hybrid bonding or solder bumps. In Example 20, the subject matter of any one or more of Examples 17-19 optionally includes connecting the photonic integrated circuit to one or more optical fibers.

[0050] Throughout the specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more individual operations may be performed concurrently, and the operations are not required to be performed in the order illustrated. The structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Likewise, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements are within the scope of the present subject matter.

[0051] Although an overview of the inventive subject matter has been described with reference to specific embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without the intention of limiting the scope of this application to any single disclosure or inventive concept, if indeed more than one is disclosed.

[0052] The illustrated embodiments are described herein in sufficient detail to enable one skilled in the art to practice the disclosed teachings. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The detailed description, therefore, is not to be construed in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0053] As used herein, the term "or" may be interpreted in either an inclusive or exclusive sense. Furthermore, multiple instances of resources, operations, or structures described herein may be provided as a single instance. Furthermore, boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and certain operations are illustrated in the context of particular illustrative configurations. Other assignments of functionality are contemplated and may fall within the scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource.Likewise, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements are within the scope of embodiments of the present disclosure, as represented by the appended claims. The description and drawings are accordingly to be considered as illustrative and not in a limiting sense.

[0054] The foregoing description has been described with reference to specific embodiments for explanatory purposes. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible embodiments to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles involved and their practical application, thereby enabling others skilled in the art to best utilize the various embodiments with various modifications as are suited to the particular use contemplated.

[0055] It should be understood that although the terms "first," "second," and so on may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact could be referred to as a second contact, and similarly, a second contact could be referred to as a first contact without departing from the scope of the present embodiments. The first contact and the second contact are both contacts, but they are not the same contact.

[0056] The terminology used in the description of the embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the embodiments and in the appended examples, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is also to be understood that the term "and / or," as used herein, refers to and includes any and all possible combinations of one or more of the associated listed elements.It is further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of listed features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0057] As used herein, the phrase "if" should be construed in accordance with the context to mean "when" or "at" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" may be construed in accordance with the context to mean "in determining" or "in response to determining" or "in determining [the stated condition or event]" or "in response to detecting [the condition or event]." QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 17 / 957,094

[0001]

Claims

[1] Semiconductor assembly comprising: an electronic integrated circuit die; a photonic integrated circuit die coupled to the electronic integrated circuit die; and a glass layer comprising one or more waveguides for conducting one or more optical signals from the photonic integrated circuit die. [2] The semiconductor device of claim 1, further comprising a silicon photonic layer between the photonic integrated circuit die and the glass layer. [3] The semiconductor device of claim 1, wherein the glass layer comprises a plurality of waveguides and at least two of the plurality of waveguides are located at different heights. [4] The semiconductor device of claim 1, wherein the glass layer comprises an amorphous glass. [5] The semiconductor device of claim 1, wherein the glass layer comprises a partially crystalline glass. [6] The semiconductor device of any of claims 1-5, wherein the glass layer is located between the electronic integrated circuit die and the photonic integrated circuit die. [7] The semiconductor device of any of claims 1-5, wherein the glass layer is attached to the photonic integrated circuit die on a side opposite the electronic integrated circuit die. [8] A semiconductor device according to any one of claims 1-5, wherein the glass layer comprises two or more waveguides, each aligned along a different z-axis. [9] The semiconductor device of any of claims 1-5, wherein the glass layer further comprises a substrate. [10] The semiconductor device of any of claims 1-5, wherein the glass fiber layer further comprises a component. [11] A semiconductor device according to any one of claims 1-5, further comprising a glass via in the glass layer. [12] The semiconductor package of claim 11, wherein the glass via is configured to connect the electronic integrated circuit to power, input, output, or combinations thereof. [13] A semiconductor device according to any one of claims 1-5, wherein the photonic integrated circuit comprises one or more Mach-Zehner interferometers, micro-ring resonators, phase shifters, or combinations thereof. [14] Device comprising: a semiconductor assembly comprising: an electronic integrated circuit die, a photonic integrated circuit die coupled to the electronic integrated circuit die, and a glass layer comprising one or more waveguides for routing one or more optical signals from the photonic integrated circuit die; a housing; and a touch screen. [15] The device of claim 14, wherein the glass layer comprises a plurality of waveguides. [16] The device of claim 15, wherein at least two of the plurality of waveguides are located at different heights within the glass layer. [17] A method of manufacturing a semiconductor device, the method comprising: Attaching a glass layer to a photonic integrated circuit; Fabricating a plurality of waveguides in the glass layer to produce a glass layer, wherein at least two of the plurality of waveguides are at different heights; and Connecting the photonic integrated circuit and the glass layer to an electronic integrated circuit. [18] The method of claim 17, wherein fabricating a plurality of waveguides comprises direct laser writing. [19] The method of any of claims 17-18, wherein connecting the photonic integrated circuit comprises connecting the photonic integrated circuit by hybrid bonding or solder bumps. [20] The method of any of claims 17-18, further comprising connecting the photonic integrated circuit to one or more optical fibers.

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