DETERMINING A CLOCK TRACK CIRCUIT DISABLED STATUS

Abstract

An example device includes a phase detector, a digital discriminator, and logic circuitry. A status signal of the phase detector is based at least in part on a phase relationship between a reference clock and a feedback clock, the feedback clock being generated by a clock tracking circuitry to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuitry may determine a disable status of the clock tracking circuitry based at least in part on samples of the status signal of the phase detector.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of the priority date of U.S. Provisional Patent Application No. 63 / 375,351, filed September 12, 2022, for "DUAL EDGE PFD WITH DYNAMIC DOUBLING AND EDGE LOCKING CLARITY," under 35 USC § 119(e), and claims the benefit of the priority date of U.S. Provisional Patent Application No. 63 / 375,348, filed September 12, 2022, for "PLL PHASE ERROR BASED DIGITAL LOCK DETECTION," the contents and disclosure of which are hereby incorporated by reference in their entirety. AREA

[0002] One or more examples generally relate to error detection, including phase and frequency error detection. One or more examples generally relate to determining a lock state of a clock tracking circuit. BACKGROUND

[0003] Clock tracking circuits, such as phase-locked loops and delay-locked loops, are circuits used to generate a signal with a predetermined relationship to a clock and another oscillating signal. An output signal from a clock tracking circuit is locked to the phase and frequency of a reference signal. Clock tracking circuits are used in a variety of operational contexts, including when two signals with known relationships are used to transmit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To easily identify the discussion of a specified element or particular action, the main numeral(s) in a reference number refer to the figure number in which that element is first introduced. Fig. 1 is a block diagram of an apparatus for determining a lock status of a clock tracking circuit according to one or more examples. Fig. 2 is a block diagram illustrating a phase threshold detection device according to one or more examples. Fig. 3 is a block diagram of an apparatus for determining and indicating a lock status of a clock tracking circuit according to one or more examples. Fig. 4 is a block diagram of an apparatus for determining and indicating a lock status of a clock tracking circuit according to one or more examples. Fig. 5 is a block diagram illustrating a device for setting a sampling rate according to one or more examples. Fig. 6 is a block diagram illustrating an apparatus for sampling a phase detector status signal at a fixed sampling rate according to one or more examples. Fig. 7 is a block diagram illustrating an apparatus for generating a sampling clock for sampling a status signal of a phase detector according to one or more examples. Fig. 8 is a flowchart illustrating a process for determining a lock status of a clock tracking circuit according to one or more examples. Fig. 9 is a flowchart illustrating a process for setting a status signal of a phase detector according to one or more examples. Fig. 10 is a flowchart illustrating a process for setting the phase detector status signal according to one or more examples. Fig. 11 is a flowchart illustrating a process for setting a status signal to indicate a status of the phase difference between a reference clock and a feedback clock, according to one or more examples. Fig. 12 is a flowchart illustrating a process for determining the lock status of the clock tracking circuit based at least in part on the status signal of a phase detector, according to one or more examples. Fig. 13 is a block diagram illustrating a clock tracking circuit that provides a determination of the lock status according to one or more examples. Fig. Figure 14 is a timing diagram illustrating a non-limiting example of a conventional two-edge lock detection where a “zero” state occurs at 180 degrees. Fig. Figure 15 is a timing diagram illustrating a non-limiting example of a conventional two-edge lock detection where a “ZERO” state occurs due to a missing edge at 180 degrees caused by a RESET. Fig. 16 is a block diagram illustrating a device that provides single-edge and dual-edge phase error detection according to one or more examples. Fig. 17 is a block diagram illustrating a device that provides single-edge and dual-edge phase error detection according to one or more examples. Fig. 18 is a flowchart illustrating a process for improved dual-edge phase error detection according to one or more examples. Fig. 19 is a flowchart illustrating a process for setting a status signal to indicate a status of the phase difference between a reference clock and a feedback clock, according to one or more examples. Fig. 20 is a flowchart illustrating a process for setting a status signal to indicate a status of the phase difference between a reference clock and a feedback clock, according to one or more examples. Fig. 21 is a flowchart illustrating a process for determining a status of a phase difference between a reference clock and a feedback clock according to one or more examples. Fig. 22 is a flowchart illustrating a process for determining a phase error according to one or more examples. Fig. 23 is a flowchart illustrating a process for setting a phase error signal to indicate the magnitude and direction of the phase difference between a reference clock and a feedback clock, according to one or more examples. Fig. 24 illustrates an example 2400 of setting a status signal to indicate a status of the phase relationship between a reference clock and a feedback clock based on a false zero threshold, according to one or more examples. Fig. 25 is a timing diagram illustrating an exemplary operation of a two-edge PFD, such as the one shown in Fig. 17 shown device. Fig. Figure 26 is a diagram of a simulation plot showing a PFD transfer function in single-edge mode that has a zero state only at 0° and therefore always aligns rising edges with rising edges. Fig. Figure 27 is a diagram of a simulation plot showing a nominal PFD transfer function in two-edge mode having a false ZERO state at 180° and a desired ZERO state at 0°. Fig. Figure 28 is a diagram of a simulation plot showing a curve representing a dynamic transfer function triggered by two edges. Fig. 29 is a block diagram of circuit logic that, in some examples, may be used to implement various functions, operations, actions, processes, or methods disclosed herein. MODE(S) FOR CARRYING OUT THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown by way of illustration specific examples of examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, and procedural changes may be made without departing from the scope of the disclosure.

[0006] The illustrations presented herein are not intended to be actual views of any particular method or system, device, or structure, but are merely idealized representations used to describe the examples of the present disclosure. The drawings presented herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to enable those skilled in the art to practice the disclosed examples. The use of the terms "exemplary," "as an example," and "for example" means that the accompanying description is illustrative, and while the scope of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of any example or this disclosure to the specified components, steps, features, functions, or the like.

[0008] It will be readily appreciated that the components of the examples generally described herein and illustrated in the drawings may be arranged and configured in a variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure with unnecessary detail. Conversely, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Furthermore, block definitions and the partitioning of logic between various blocks are exemplary of a specific implementation. It will be readily apparent to those skilled in the art that the present disclosure may be practiced using numerous other partitioning solutions.Details of timing considerations and the like have largely been omitted to the extent that such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art would understand that information and signals may be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of illustration and description. Those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured to perform the functions described herein.A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer executes computational instructions (e.g., software code) related to examples of the present disclosure.

[0012] The examples may be described with respect to a process represented as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially concurrently. Furthermore, the order of the acts may be changed. A process may correspond, without limitation, to a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or dispatched as one or more instructions or as code on computer-readable media.Computer-readable media includes both computer storage media and communications media, including any media that supports the transfer of a computer program from one location to another.

[0013] Any reference to an element herein using a label such as "first," "second," etc., does not limit the quantity or order of those elements unless such a limitation is expressly stated. Rather, these labels may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element in any way. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, to an extent understood by one skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the specified parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90% satisfied, at least 95% satisfied, or even at least 99% satisfied.

[0015] As used herein, relational terms such as "over," "under," "upon," "underlying," "above," "beneath" are used without limitation for clarity and convenience in understanding the disclosure and the accompanying drawings and are not associated with or dependent upon any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0016] In this specification, the term "coupled" and derivatives thereof may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. Conversely, when an element is described as being "directly coupled" to another element, no intervening elements or layers are present. The term "connected" may be used interchangeably with the term "coupled" in this specification and has the same meaning unless expressly stated otherwise or the context would indicate otherwise to one of ordinary skill in the art.

[0017] As used herein, the term "activate" in conjunction with "signal" means to place a signal in an active state. The term "deactivate" in conjunction with "signal" means to place a signal in an inactive or default state. For example, signals can be active high and inactive low, or active low and inactive high.

[0018] A "clock signal," or simply a "clock," is a signal that oscillates in a reliably predictable manner between two discrete states—a high state and a low state. The transition from a low state to a high state, or from a high state to a low state, is called an "edge." The type or direction of a change, from a low state to a high state, or from a high state to a low state, is called the "polarity" of the edge. A transition from a low state to a high state is called a "positive polarity" or "rising edge." A transition from a high state to a low state is called a "negative polarity" or "falling edge." One or more circuits may respond to a rising or falling edge of a clock to coordinate actions, as a non-limiting example.

[0019] A clock tracking circuit, such as, without limitation, a phase-locked loop (PLL), produces an output signal having a phase, frequency, or both that are in a predetermined relationship to a phase or frequency of a reference signal. The effect of causing and maintaining such a predetermined relationship between the phase or frequency of an output signal and a reference signal is referred to herein as "tracking." The predetermined relationship may be such that the output signal and the reference signal are in phase or within a predetermined phase difference. The predetermined relationship may be such that the frequency of the output signal is the same as, or a multiple of, a frequency of the reference signal.As a non-limiting example, the frequency of the output signal may be an integer or fractional multiple of the frequency of the reference signal, such as 1 / 200, 1 / 10, 10, or 200 times the frequency of the reference signal.

[0020] A typical clock tracking circuit includes an electronic oscillator, which the clock tracking circuit controls to produce an output signal that tracks a reference signal. An electronic oscillator may include one or more series of control elements (e.g., capacitors, inductors, delay circuits, without limitation) that are voltage-controlled, current-controlled, digitally controlled, or a combination or subcombination thereof. By enabling and disabling the respective control elements, the capacitance, inductance, or delay of the electronic oscillator, respectively, is varied in a predictable manner, thereby changing the output phase and frequency of the electronic oscillator in a predictable manner.

[0021] An electronic oscillator may include multiple inputs for controlling (enabling / disabling) various sets of control elements and, accordingly, regulating the phase and frequency of an output signal. Non-limiting examples of electronic oscillators include a voltage-controlled oscillator (VCO), which generates an output signal exhibiting a phase or frequency controlled by the voltage of a control signal; a current-controlled oscillator (CCO), which generates an output signal exhibiting a phase or frequency controlled by the current of a control signal; a digitally controlled oscillator (DCO), which generates an output signal exhibiting a phase or frequency controlled at least in part by the value of a control code; and combinations / subcombinations thereof.

[0022] When a clock tracking circuit reliably tracks an output signal to a reference signal, it is said to be "locked" or in a "locked state." A lock is also called a "zero state" because the phase error is zero or correspondingly small, or "zero." In the locked state, if the phase or frequency of a reference signal changes, the clock tracking circuit adjusts the phase or frequency of the output signal accordingly to maintain the predetermined relationship. Likewise, if the phase or frequency of the output signal changes in the locked state, the clock tracking circuit adjusts the phase or frequency of the output signal accordingly to maintain the predetermined relationship. To indicate the locked state, an internal signal is generated in the clock tracking circuit.Such a lock state signal may be used, as a non-limiting example, to enable output drivers and initiate other clock tracking calibration functions.

[0023] The threshold for determining a lockout condition (i.e., the thresholds for determining that an output signal operates within a stable, defined range without constraint) depends, as a non-limiting example, on specific operating conditions. For example, some applications may tolerate a lower accuracy (i.e., a larger difference) between the target frequency and the output frequency, while others may not.

[0024] Sometimes, analog control signals to the electronic oscillator (e.g., to an analog proportional input of the electronic oscillator, without limitation) are used to determine a lockout state. From the control signals, it can be inferred whether the output signal is within a stable, defined range. The inventors of this disclosure are aware that such an approach requires analog references and comparators aligned to the specific operating points of the clock tracking circuits that establish their stable, defined range, and that analog components require a large amount of space compared to digital components. Furthermore, while analog control signals can be generated based on the phase error, they do not include direct information about phase errors.The lock status is either inferred, which may be inaccurate or completely inaccurate, or determined using control signals that do not perfectly represent the phase error. In both cases, determining the lock status is subject to error.

[0025] One or more examples relate to a lock status detector for a clock tracking circuit. In some examples, the lock status detector determines the lock status based at least in part on the reference clock and the feedback clock, an UP signal and DOWN signal generated by a binary error detector (e.g., a phase frequency detector, without limitation), or both.

[0026] In one or more examples, the lock status detector includes a phase detector having a phase threshold and a status signal. The phase threshold is adjustable. The phase detector compares the phase difference between two input signals (e.g., a reference clock and a feedback clock, without limitation) to the phase threshold. If the phase difference between the two input signals is greater than or equal to the phase threshold, the phase detector sets its output to a first value. If the phase difference between the two input signals is less than the phase threshold, the phase detector sets its status signal to a second value that is different from the first value. The value of the phase detector status signal indicates the relationship between the phase difference and the phase threshold.The first value indicates that the phase difference between the two input signals is greater than or equal to the phase threshold and that one of the input signals (e.g., a feedback clock, unconstrained) is operating outside the specified deadband of the phase detector. The second value indicates that the phase difference between the two input signals is less than the phase threshold and that one of the input signals (e.g., a feedback clock, unconstrained) is operating within the specified deadband of the phase detector.

[0027] The term "deadband" typically refers to an operating region where a phase detector (or the phase detector output—the error signal) has zero or near-zero gain (i.e., here, gain refers to the magnitude of the error signal) because the phase difference between two input signals is zero or near-zero. In one or more examples, a phase detector has a "set deadband." The set (or set) deadband is set above the phase threshold. In one or more examples, a phase error range associated with a set deadband may be the same or a different phase error range associated with an actual deadband of the phase error detector.

[0028] The status signal can change from an indication outside the deadband to an indication within the deadband in response to a changing phase difference between the input signals. The status signal can change from an indication within the specified deadband to an indication outside the specified deadband in response to a changing phase difference between the input signals. In the context of lockout condition detection, the specified deadband corresponds to a predetermined phase error range that is pre-associated with a lockout condition.

[0029] The phase threshold of the phase detector may be adjustable (e.g., programmable, configurable, or otherwise adjustable, without limitation) such that the phase detector adapts or can adapt to operating conditions, as appropriate, based at least in part on the phase threshold. In one or more examples, the phase threshold may be preset (preset) or set in real time.

[0030] In one or more examples, the status signal of the phase detector is sampled and the status signal samples are decoded to determine the lock status. In one or more examples, a digital discriminator distinguishes between steady-state phase error information and transient phase error information in the status signal. Steady-state phase error corresponds to the phase error that occurs when a clock tracking circuit is locked. Transient phase error corresponds to phase error that is transient in nature and may or may not be present at a given time. In general, steady-state phase error information should be used to determine the lock status, while transient phase error information should be reduced or eliminated in such a determination.

[0031] In one or more examples, the digital discriminator is a digital filter that retains or passes digital signals (e.g., in the status signal, without restriction) indicative of a steady-state phase error and blocks or discards digital signals (e.g., in the status signal, without restriction) indicative of a transient phase error. In one or more examples, the digital discriminator is a state machine that implements a pattern matcher that performs a bit-by-bit comparison of a digital signal with predetermined patterns that indicate the blocking status of the phase detector. In one or more examples, the digital discriminator is an accumulator and a comparator, and the accumulator accumulates the state of the status signal, and the comparator detects when the accumulated state is above a predetermined threshold indicative of a steady-state phase error.The output of the comparator is used as a lock status signal.

[0032] A status signal sample is a value of the status signal at specific intervals, i.e., a discrete-time signal with a discrete value. In particular, the status signal of the phase detector may be a digital signal, i.e., a discrete-time signal with discrete values. The status signal may therefore consist of a series of samples received, for example, in a shift register, as a non-limiting example. In one or more examples, a sampling rate may be set to ensure that a set of received samples is representative of the state of the phase detector. In general, the higher the sampling rate, the greater the number of status signal samples and the more representative the state of the phase detector.

[0033] Fig. 1 is a block diagram of a device 100 for determining a lock status of a clock tracking circuit according to one or more examples. The device 100 may also be referred to as a "lock status detector 100."

[0034] The device 100 includes a phase detector 102, a digital discriminator 106 and a logic circuit 112.

[0035] The device 100 receives a reference clock 118, a feedback clock 120, a phase threshold 116, and, at least in part in response thereto, generates a lock status signal 110. The feedback clock 120 is generated by a clock tracking circuit to track the reference clock 118. The reference clock 118 represents the target frequency and phase that the clock tracking circuit tracks. In one or more examples, the feedback clock 120 may be derived from an output clock generated by the clock tracking circuit to track the reference clock 118 and may be fed back for comparison with the reference clock 118, optionally via a frequency divider. The feedback clock 120 may be the same as the output clock generated by the clock tracking circuit (e.g.,the output clock is passed directly to an input of the phase detector 102 without restriction) or it may indicate one or more properties of the output clock, such as phase, frequency, or pulse width. In the cases shown in . Fig. 1, reference clock 118 and feedback clock 120 are provided directly to the inputs of phase detector 102. In one or more examples, one or more signals indicative of a phase relationship between reference clock 118 and feedback clock 120 may be provided to one or more inputs of phase detector 102, such as, for example, the output of a binary phase detector (such as, without limitation, a bang-bang phase detector), the output of a digital or analog subsampling phase detector, or the output of a digital or analog sampling phase detector, without limitation.

[0036] The phase threshold 116 is a value or range of values that has been predetermined to represent the threshold of a specified deadband at the phase threshold 116, and in the context of lockout state detection, it also represents a phase error amount that has been pre-associated with a lockout state.

[0037] The phase threshold 116 is used by the phase detector 102 to determine a phase error condition between the reference clock 118 and the feedback clock 120. If the phase error is greater than or equal to the phase threshold 116, this indicates that the phase error is outside the range associated with a lockout condition, and if the phase error is less than the phase threshold 116, this indicates that the phase error is within the range associated with a lockout condition. As a non-limiting example, if the phase threshold 116 is set (e.g., by logic circuitry or a user, without limitation) to ±5 degrees, then the device 100 considers the phase error to be within the range associated with a lockout condition as long as the phase difference between the feedback clock 120 and the reference clock 118 is between +5 and -5 degrees.

[0038] The disable status signal 110 indicates the disable status of a clock tracking circuit, i.e., it indicates whether the clock tracking circuit is in a disable state or not. In one or more examples, a first value of the disable status signal 110 indicates that the clock tracking circuit is not in the disable state, and a second value of the disable status signal 110 indicates that the clock tracking circuit is in the disable state. The first value and the second value of the disable status signal 110 are different.

[0039] The phase detector 102 receives the reference clock 118, the feedback clock 120, and the phase threshold 116 and, at least in part in response thereto, generates the status signal 104. The status signal 104 indicates whether or not the feedback clock 120 is operating within the specified deadband of the phase detector 102, as explained below.

[0040] The phase detector 102 determines whether a phase difference between the reference clock 118 and the feedback clock 120 is less than the phase threshold 116. If the phase detector 102 determines that the phase difference is less than the phase threshold 116, the feedback clock 120 is determined to be operating within the specified deadband, and the phase detector 102 sets the status signal 104 to a value indicating that the feedback clock 120 is operating within the specified deadband of the phase detector 102. If the phase detector 102 determines that the phase difference is greater than or equal to the phase threshold 116, the feedback clock 120 is determined to be operating outside the specified deadband, and the phase detector 102 sets the status signal 104 to a value indicating that the feedback clock 120 is operating outside the specified deadband of the phase detector 102.Since the feedback clock 120 is based on the output clock of the clock tracking circuit, a determination of whether or not the feedback clock 120 operates within the specified deadband is also a determination of whether or not the output signal operates within the specified deadband.

[0041] The phase detector 102 may change the value of the status signal 104 from a value indicative of a value outside the specified deadband to a value within the specified deadband in response to a changing phase difference between the reference clock 118 and the feedback clock 120. The phase detector 102 may change the value of the status signal 104 from a value within the specified deadband to a value outside the specified deadband in response to a changing phase difference between the reference clock 118 and the feedback clock 120. Thus, the state of the status signal 104 may change over time, at least in part, in response to changes in the phase difference between the reference clock 118 and the feedback clock 120.

[0042] A value of the phase threshold 116 may be predetermined based at least in part on an acceptable phase difference amount for determining a lockout state. The value of the status signal 104 is based at least in part on whether or not a phase difference between the reference clock 118 and the feedback clock 120 is less than the phase threshold 116, such that the status signal 104 indicates a lockout status of the clock tracking circuit. In other words, the status signal 104 includes information about the phase difference between the feedback clock 120 and the reference clock 118, as well as the lockout status of a clock tracking circuit. The status signal 104 includes information about the steady-state phase error between the feedback clock 120 and the reference clock 118, and the lockout status of the clock tracking circuit may be determined based on the steady-state phase error information.Thus, in one or more examples, a state of the status signal 104 may be decoded to determine a disable status of the clock tracking circuit, as described below.

[0043] The digital discriminator 106 receives the status signal 104 and processes the status signal 104 to generate samples 108 of the status signal 104. The digital discriminator 106 distinguishes between stationary phase error information and transient phase error information in the status signal 104. The digital discriminator 106 stores samples 108 of the status signal 104 that include the stationary phase information.

[0044] Logic circuit 112 processes samples 108 to determine patterns indicative of the lock status in the state information about phase detector 102 included in the group of samples 108. Logic circuit 112 determines the lock status of the clock tracking circuitry from reference clock 118 and feedback clock 120. If logic circuit 112 determines that the lock status is a lock status, it sets lock status signal 110 to a value indicating the lock status. If logic circuit 112 determines that the lock status is not a lock status, it sets lock status signal 110 to a value indicating that no lock status exists.

[0045] Status signal 104 and status signal samples 108 include steady-state phase error information, which logic circuitry 112 uses to determine (e.g., infer, but not limit to) the lock status of the clock tracking circuit. Phase detector 102 changes the state of status signal 104 in a predictable manner so that the state information can be used to determine the lock status.

[0046] Fig. 2 is a block diagram illustrating a device 200 that represents an example of a phase detector according to one or more examples. The device 200 may also be referred to herein as "phase detector 200." The device 200 is a non-limiting example of a phase detector 102 of Fig. 1.

[0047] Generally speaking, if both input signals exhibit a transition from a low state to a high state (rising edge) within a predetermined range, the device 100 activates the threshold detection signal 212, and if both input signals do not exhibit a rising edge within the predetermined range, the device 100 deactivates the threshold detection signal 212. The device 200 performs a binary test; either the phase relationship is within the predetermined range or not.

[0048] In one or more examples, the threshold detection signal 212 may be used as the status signal 104. Once the rising edge of both signals has arrived, the phase detector is re-enabled for the next comparison. In other words, the device 200 sets the threshold detection signal 212 to an enabled (high) state in response to determining that a time difference between the occurrence of a rising edge of the first signal 214 and the occurrence of a rising edge of the second signal 216 is less than the phase threshold 116, and sets the threshold detection signal 212 to a disabled (low) state in response to determining that the time difference between the occurrence of the rising edge of the first signal 214 and the occurrence of the rising edge of the second signal 216 is greater than the phase threshold 116.

[0049] The device 200 includes a first flip-flop 202, a second flip-flop 204, a third flip-flop 220, a fourth flip-flop 218, a first delay circuit 208, a second delay circuit 222, a NAND gate 206, and a NOR gate 210.

[0050] The first flip-flop 202, the second flip-flop 204, the third flip-flop 220, and the fourth flip-flop 218 are edge-triggered flip-flops, a type of flip-flop that responds to the change (or "edge") of its clock input rather than the level of the clock input. Each flip-flop 202, 204, 220, and 224 has a data input (D), a clock input (CLK), and an output (Q). The state at the data input (D) is captured and transferred to the output (Q) in response to the state at the clock input (CLK) experiencing a particular edge transition (either rising or falling, but a rising edge in this example). If an edge transition other than the specified one occurs at the clock input (CLK), the state at the data input (D) is not captured or transmitted, and the state at the output (Q) is the state at the data input (D) at the last occurrence of a specified edge transition at the clock input (CLK).

[0051] In one or more examples, the flip-flops may have a single output Q that can have at least two states, or alternatively, they may have two separate outputs Q and Q', each representing one of the two states.

[0052] The NAND gate 206 is an electronic logic gate that produces an output that is false only when all of its inputs are true. In other words, if any input is low, the output is high. The NOR gate 210 is an electronic logic gate that produces an output that is true only when all of its inputs are false. In other words, if any of the inputs is true, the output is false.

[0053] The first delay circuit 208 and the second delay circuit 222 are delay circuits that introduce a respective predetermined time delay in the propagation of a signal from its input to its output. In one or more examples, the respective predetermined amount of introduced time delay is equal to or at least partially based on the phase threshold 116. In one or more examples, the first delay circuit 208 and the second delay circuit are programmable, with the amount of delay varying based in part on the phase threshold 116.

[0054] The respective data inputs (D) of the first flip-flop 202 and the second flip-flop 204 are coupled to a supply voltage to set the data inputs (D) to a high state. The clock input (CLK) of the first flip-flop 202 is coupled to receive a first signal 214, and the clock input (CLK) of the second flip-flop 204 is coupled to receive a second signal 216. In one or more examples, one of the signals, either the first signal 214 or the second signal 216, is set as the reference clock 118, and the other signal, either the first signal 214 or the second signal 216, is set as the feedback clock 120.

[0055] In one or more examples, the first signal 214 and the second signal 216 may be set by signals indicative of the phase relationship between the reference clock 118 and the feedback clock 120, such as UP and DOWN signals generated by a phase frequency detector, such as a bang-bang phase frequency detector, without limitation. As long as the timing of the rising edges of the first signal 214 and the second signal 216 includes the phase information about the respective signals (e.g., the reference clock 118 and the feedback clock 120, without limitation), they may be used by the device 200 to determine whether a phase difference is within the phase error threshold.

[0056] The output (Q) of the first flip-flop 202 is coupled to the data input (D) of the third flip-flop 220, one input of the first delay circuit 208, and one input of the NAND gate 206. The output (Q) of the second flip-flop 204 is coupled to the data input (D) of the fourth flip-flop 218, one input of the second delay circuit 222, and the other input of the NAND gate 206. The output of the NAND gate 206 is coupled to the respective reset inputs (R) of the first flip-flop 202 and the second flip-flop 204. The output of the first delay circuit 208 is coupled to the clock input (CLK) of the third flip-flop 220, and the output of the second delay circuit 222 is coupled to the clock input (CLK) of the fourth flip-flop 218. The Q output of the third flip-flop 220 is coupled to a first input of the NOR gate 210 and the Q output of the fourth flip-flop 218 is coupled to a second output of the NOR gate 210.The output of the NOR gate 210 represents the threshold detection signal 212.

[0057] The outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are received at the NAND gate 206. When both outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are high, the output of the NAND gate 206 is set to a low state. This low state at the output of the NAND gate 206 resets the first flip-flop 202 and the second flip-flop 204 because their respective reset inputs (R) are active low. When the first flip-flop 202 and the second flip-flop 204 are reset, their outputs (Q) are forced low (i.e., a low state at the reset input (R) overrides the data input (D) and the clock input (CLK), forcing the output (Q) low).

[0058] If one or both outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are in a low state, the output of the NAND gate 206 is set to a high state. The reset inputs (R) of the first flip-flop 202 and the second flip-flop 204 are active low, so that when a high state is received at the respective reset inputs (R), the first flip-flop 202 and the second flip-flop 204 operate normally and are not reset, responding only to the data input (D) and the clock input (clk).

[0059] Accordingly, when both outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are in the high state, the NAND gate 206 resets both flip-flops, thereby setting the respective outputs (Q) of the first flip-flop 202 and the second flip-flop 204 to the low state.

[0060] As an example, assume that the first flip-flop 202, the second flip-flop 204, the third flip-flop 220, and the fourth flip-flop 218 are all initialized to output a low state.

[0061] When the output (Q) of the first flip-flop 202 changes to the high state in response to a rising edge of the first signal 214 and the output (Q) of the second flip-flop 204 is in the low state because the rising edge of the second signal 216 has not yet occurred, the high state is received at the data input (D) of the third flip-flop 220 and at the input of the first delay circuit 208, and the received high state is propagated by the first delay circuit 208. The low state at the output (Q) of the second flip-flop 204 is received at the data input (D) of the fourth flip-flop 218 and at the input of the second delay circuit 222, and the received low state is propagated by the second delay circuit 222.

[0062] After the predetermined delay time of the first delay circuit 208 and the second delay circuit 222, i.e. the delay set by the phase threshold 116, the delayed high state (i.e. the output (Q) of the first flip-flop 202 delayed by the first delay circuit 208) is received at the clock input (CLK) of the third flip-flop 220, so that the clock input (CLK) of the third flip-flop 220 undergoes a change from the low state to the high state (rising edge) and is triggered, whereby the high state received at the data input (D) of the third flip-flop 220 is passed to the Q output of the third flip-flop 220. In addition, after the predetermined delay time, the delayed low state (i.e., the delayed output (Q) of the second flip-flop 204) is received at the clock input (CLK) of the fourth flip-flop 218, and the fourth flip-flop 218 does not undergo a transition from the low state to the high state and is not triggered.The output of the third flip-flop 220 is high, and the output of the fourth flip-flop 218 is the last value at the data input (D) when it was triggered, a low state in this example. The output of the NOR gate 210, the threshold detection signal 212, is therefore low because the Q output of the third flip-flop 220 is high. As stated above, the threshold detection signal 212 being low indicates that the time difference between the occurrence of the rising edge of the first signal 214 and the occurrence of the rising edge of the second signal 216 is greater than the phase threshold 116.

[0063] If the second signal 216 has a rising edge before the predetermined time delay, the second flip-flop 204 is triggered, setting the Q output of the second flip-flop 204 to a high state. Since the Q outputs of the first flip-flop 202 and the second flip-flop 204 are high, the NAND gate 206 resets the first flip-flop 202 and the second flip-flop 204, causing the Q outputs of the first flip-flop 202 and the second flip-flop 204 to fall low. After the predetermined delay time of the first delay circuit 208, the delayed high state (i.e.the output (Q) of the first flip-flop 202, delayed by the first delay circuit 208, is received at the clock input (CLK) of the third flip-flop 220, so that the clock input (CLK) of the third flip-flop 220 undergoes a transition from the low state to the high state (rising edge) and is triggered, whereby the low state received at the data input (D) of the third flip-flop 220 is passed to the Q output of the third flip-flop 220. Similarly, after the predetermined delay time of the second delay circuit 222, the delayed high state (iethe output (Q) of the second flip-flop 204, delayed by the second delay circuit 222, is received at the clock input (CLK) of the fourth flip-flop 218, so that the clock input (CLK) of the third flip-flop 218 undergoes a transition from the low state to the high state (rising edge) and is triggered, whereby the low state received at the data input (D) of the fourth flip-flop 218 is passed to the Q output of the fourth flip-flop 218. The output of the NOR gate 210, the threshold detection signal 212, is thus high, since the Q output of both the third flip-flop 220 and the fourth flip-flop 218 is low.

[0064] The above discussion refers to an example in which the rising edge of the first signal 214 precedes the rising edge of the second signal 216; however, those skilled in the art will recognize that the same results occur when the rising edge of the second signal 216 precedes the rising edge of the first signal 214.

[0065] If both the first signal 214 and the second signal 216 have a rising edge within the phase threshold 116 (i.e., the time between the time at which the first signal 214 has a rising edge and the time at which the second signal 216 has a rising edge is less than the phase threshold 116), then the device 200 sets the threshold detection signal 212 to the low state, and if neither the first signal 214 nor the second signal 216 have a falling edge within the phase threshold 116 (i.e., the time between the time at which the first signal 214 has a rising edge and the time at which the second signal 216 has a rising edge is greater than the phase threshold 116), then the device 200 sets the threshold detection signal 212 to the high state. In the Fig. 2, activation sets the threshold detection signal 212 to the low state and deactivation sets the threshold detection signal 212 to the high state, but the use of other states does not exceed the scope of this disclosure.

[0066] Fig. 3 is a block diagram of a device 300 for distinguishing between a steady-state and a transient phase error in a status signal of a phase detector and for optionally determining a lock status based on this signal, according to one or more examples. The device 300 is a non-limiting example of a digital discriminator 106 and the logic circuit 112 of Fig. 1.

[0067] The device 300 includes a phase detector 102, a digital discriminator 106, and a logic circuit 112. The digital discriminator 106 includes a digital filter 302 and a register 304.

[0068] Digital filter 302 filters status signal 104 of phase detector 102 to block the status signal indicating a transient phase error and to pass the status signal indicating a steady-state phase error. As a non-limiting example, digital filter 302 may be a digital low-pass filter that passes steady-state phase error signals while attenuating high-frequency transient phase error signals. Non-limiting examples of a digital low-pass filter include a moving average filter, a finite impulse response (FIR) filter, a digital loop filter, and adaptive filters.

[0069] Register 304 receives and stores the status signal samples provided by digital filter 302. The status signal samples include steady-state phase error information that can be used to determine the lock status of the clock tracking circuit.

[0070] The logic circuit 112 monitors the status signal samples stored in the register 304, determines lock status information from the status signal samples, determines the lock status of the clock tracking circuit based at least in part on the status information, and sets the lock status signal 110 to indicate the determined lock status.

[0071] Fig. 4 is a block diagram of a device 400 for distinguishing between a steady-state and a transient phase error in a status signal of a phase detector and for optionally determining a lock status based on this signal, according to one or more examples. The device 400 is a non-limiting example of a digital discriminator 106 and the logic circuit 112 of Fig. 1.

[0072] The device 400 includes a digital discriminator 106 and a logic circuit 112. The digital discriminator 106 includes an accumulation register 402 and a comparator 404.

[0073] The accumulation register 402 accumulates states of the status signal 104. The accumulated value 408 stored in the accumulation register 402 ("accumulation value 408"), which represents the integral of the states of the status signal 104, is provided to the comparator 404. The integral of the state of the status signal 104 represents the information about the steady-state phase error.

[0074] Comparator 404 is a digital comparator that determines the relationship between ACC value 408 and a threshold value and sets the respective outputs of comparator 404 to indicate the determined relationship. In one or more examples, the relationships may be whether or not the accumulated value is less than or greater than a predetermined threshold. If the value is greater than the predetermined threshold, it indicates that the clock tracking circuit's lock status is a lock state, and if the value is less than the predetermined threshold, it indicates that the clock tracking circuit's lock status is not a lock state. Logic circuit 112 may set lock status signal 110 to indicate the lock status indicated by comparator 404. Alternatively, in one or more examples, the output of comparator 404 may be provided as lock status signal 110.

[0075] In one or more examples, the number of samples generated is based at least in part on a sampling rate. In one or more examples, the sampling rate at device 400 may be set to achieve a suitable resolution for digital discriminator 106 to process status signal 104 and maintain steady-state phase error information. A suitable resolution is one that ensures that a set of status signal samples is representative of phase error information. In general, the higher the sampling rate, the greater the number of status signal samples and the higher the resolution.

[0076] In some cases, as described below, a processing rate can be set on phase detector 102 to increase the resolution of status signal 104. Status signal 104 can be a digital signal, i.e., a discrete-time signal with discrete values. Increasing the processing rate of phase detector 102 increases the frequency at which it updates status signal 104. One way to increase the processing rate is to increase the clock rate of feedback clock 120 and reference clock 118.

[0077] Fig. 5 is a block diagram illustrating a device 500 for setting a sampling rate according to one or more examples. The device 500 includes a phase detector 102 and a sampling clock divider 502.

[0078] The sampling clock divider 502 receives the feedback clock 120, the reference clock 118, and the sampling rate 504, frequency divides the feedback clock 120 and the reference clock 118 by an amount equal to the sampling rate 504, and generates the divided reference clock 506 and the divided feedback clock 508. The clock rates of the divided reference clocks 506 and the divided feedback clock 508 may be greater or lesser than those of the reference clock 118 and the feedback clock 120, based, for example, on the sampling rate 504.

[0079] The sampling rate 504 may be a value representing, by way of non-limiting example, a number of clock cycles per sampling interval, a number of samples per unit interval, or a divisor. The sampling rate 504 may be preset by a user or logic circuitry.

[0080] The device 600 includes a sampling logic circuit 602, an interpolator 604, a decimator 606, a multiplexer 612, and optionally a digital discriminator 106.

[0081] The sampling logic circuit 602 receives the sampling rate 608, determines whether to upsample based on the sampling rate 608, i.e., whether to increase the number of samples based on interpolation, or whether to downsample based on decimation, i.e., whether to decrease the number of samples based on decimation, generates the decimation rate 614 for the decimator 606 or the interpolation rate 616 for the interpolator 604 based at least in part on the determination, and generates the selection signal 610 to select the output of the decimator 606 or the interpolator 604 via the multiplexer 612 as the status signal samples provided to the digital discriminator 106.If the sampling logic circuit 602 determines that a sampling rate increase should be performed based on the sampling rate 608, the sampling logic circuit 602 determines a value for a target interpolation rate based on the sampling rate 608 and adjusts the interpolation rate 616 based on the determined value. In one or more examples, when the sampling rate increase occurs, the sampling logic circuit 602 may set the decimation rate 614 to a value indicating no decimation. If the sampling logic circuit 602 determines that a sampling rate decrease should be performed based on the sampling rate 608, the sampling logic circuit 602 determines a value for the target decimation rate based on the sampling rate 608 and adjusts the decimation rate 614 based on the determined value.In one or more examples, when decreasing the sampling rate, the sampling logic circuit 602 may set the interpolation rate 616 to a value indicating no interpolation.

[0082] Decimator 606 receives status signal 104 and decimation rate 614, selects every Nth value of status signal 104 (where the Nth value is based at least in part on decimation rate 614), and provides the selected values as status signal samples. As a non-limiting example, decimator 606 may include a shift register to hold and shift bits of status signal 104, and logic circuitry to select which values of status signal 104 to retain (and conversely, which values to discard). Decimator 606 retains the values of status signal 104 that the logic circuitry selects to retain and discards the remaining values.

[0083] The interpolator 604 receives the status signal 104 and the interpolation rate 616, performs an incremental sampling of values for the status signal 104 based at least in part on the interpolation rate 616, and provides the incremented sampling values as status signal samples. As a non-limiting example, the interpolator 604 may include a shift register that holds and shifts bits of the original values of the status signal 104, thereby inserting gaps (e.g., respective gaps may include one or more zeros, without limitation) between the bits of the original values of the status signal 104, and logic circuitry to interpolate values between the original values of the status signal 104 and replace the zeros with the interpolated values (fill the gaps).

[0084] Sometimes it may be advantageous for the sampling clock or sample signal that determines the sampling rate of the status signal 104 to be based at least in part on the reference clock 118, the feedback clock 120, or the phase difference therebetween to increase the amount of stationary phase information in the status signal 104 or its samples.

[0085] Sometimes it may be advantageous for the sampling clock or sample signal that determines the sampling rate of the status signal 104 to be based at least in part on the reference clock 118, the feedback clock 120, or the phase difference therebetween to increase the amount of stationary phase information in the status signal 104 or its samples.

[0086] Fig. 7 is a block diagram illustrating means 700 for generating a sampling clock for sampling a status signal of a phase detector according to one or more examples. Means 300 is a non-limiting example of a clock source for optional sampling clock 306 or optional sampling clock 410.

[0087] The device 700 includes a sample clock divider 704 and a NAND gate 708. The sample clock divider 704 receives the generated clock 710 and the sample rate 706, divides the generated clock 710 based at least in part on the sample rate 706, and generates the sample clock 702. The NAND gate 708 generates the produced clock 710 based at least in part on a reference clock 118 and a feedback clock 120.

[0088] Fig. 8 is a flowchart illustrating a process 800 for determining a lock status of a clock tracking circuit according to one or more examples.

[0089] While the example process 800 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 800. In other examples, various components of an example device or system implementing the process 800 may perform functions at substantially the same time or in a particular sequence.

[0090] According to one or more examples, process 800 includes setting a status signal of a phase detector, wherein the status signal of the phase detector is set based at least in part on an amount of phase difference between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock at operation 802. In one or more examples, the status signal may be set directly based on the feedback clock and the reference clock, or directly based on one or more signals indicative of the phase difference between the reference clock and the feedback clock, such as UP signals and DOWN signals generated by a phase frequency detector.

[0091] According to one or more examples, process 800 includes generating a signal indicative of a disable status of the clock tracking circuit based at least in part on the phase detector status signal at operation 804.

[0092] Fig. 9 is a flowchart illustrating a process 900 for setting a phase detector status signal according to one or more examples. Some or all of the acts of process 900 may be performed by device 100, phase detector 102, or device 200, as a non-limiting example.

[0093] While the example process 900 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 900. In other examples, different components of an example device or system implementing the process 900 may perform functions at substantially the same time or in a particular sequence.

[0094] According to one or more examples, process 900 includes determining, at operation 902, whether or not a phase relationship between a reference clock and a feedback clock falls within a predetermined range. In one or more examples, the phase relationship is a phase difference between the reference clock and the feedback clock. In one or more examples, the phase threshold represents a constraint for the predetermined range. At operation 902, process 900 checks whether the phase relationship between the reference clock and the feedback clock is within a predetermined range using the phase threshold and not needing to measure the exact phase difference.

[0095] According to one or more examples, process 900 includes setting the phase detector status signal based at least in part on the determination at operation 904. In one or more examples, operation 902 is a binary test, meaning that either the phase relationship is within the phase threshold or not. Setting the status signal may include setting a value indicating the result of the binary test of operation 902.

[0096] Fig. 10 is a flowchart illustrating a process 1000 for setting the phase detector status signal according to one or more examples.

[0097] While the example process 1000 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 1000. In other examples, different components of an example device or system implementing the process 1000 may perform functions at substantially the same time or in a particular sequence.

[0098] According to one or more examples, process 1000 includes setting the phase detector status signal to a first value, at least in part in response to determining that a certain difference amount is greater than a phase threshold at operation 1002.

[0099] According to one or more examples, process 1000 includes setting the phase detector status signal to a second value, at least in part in response to determining that a certain difference amount is equal to or less than the phase threshold, wherein the second value is different from the first value at operation 1004.

[0100] Fig. 11 is a flowchart illustrating a process 1100 for setting a status signal to indicate a status of the phase difference between a reference clock and a feedback clock, according to one or more examples. Some or all of the operations of process 2200 may be performed by device 1600 or phase error detector 1604, as a non-limiting example.

[0101] While the example process 1100 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 1100. In other examples, various components of an example device or system implementing the process 1100 may perform functions at substantially the same time or in a particular sequence.

[0102] According to one or more examples, process 1100 includes detecting the occurrence of equal respective edges of the reference clock and the feedback clock at operation 1102.

[0103] According to one or more examples, process 1100 includes setting the status signal to indicate whether or not the detected occurrence of similar respective edges was within a predetermined range at operation 1104.

[0104] According to one or more examples, process 1100 optionally includes setting the status signal to the first value when the time difference between the detected occurrence of equal corresponding edges of the reference clock and the feedback clock at operation 1106 is less than the phase threshold.

[0105] According to one or more examples, process 1100 optionally includes setting the status signal to the second value when the time difference between the detected occurrence of equal corresponding edges of the reference clock and the feedback clock at operation 1108 is greater than or equal to the phase threshold.

[0106] Fig. 12 is a flowchart illustrating a process 1200 for determining the disable status of a clock tracking circuit based at least in part on a status signal of a phase detector, according to one or more examples.

[0107] Although the example illustrates a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not substantially affect the functionality of the sequence. In other examples, different components of an example device or system implementing the operation may perform functions at substantially the same time or in a particular sequence.

[0108] According to one or more examples, process 1200 includes obtaining samples of a status signal of a phase detector, wherein the status of the phase detector is set based at least in part on whether or not a phase relationship between a reference clock and a feedback clock is within a predetermined range at operation 1202. In one or more examples, process 1200 may obtain samples by processing the status signal in a manner (e.g., via digital discriminator 106, without limitation) that propagates or retains steady-state phase error information and discards or blocks transient phase error information.

[0109] According to one or more examples, process 1200 optionally includes obtaining samples including decimating the status signal at operation 1204.

[0110] According to one or more examples, process 1200 optionally includes obtaining sample values including interpolating values based on the status signal at operation 1206.

[0111] Optional operation 1206 and optional operation 1208, some or all of the decimation, interpolation, or both operations may be performed by device 600, as a non-limiting example. In one or more examples, a decimation rate or interpolation rate may be set in response to or based on a sampling rate.

[0112] According to one or more examples, process 1200 includes decoding status information from samples of the phase detector status signal at operation 1208.

[0113] According to one or more examples, process 1200 includes determining the lock status of the clock tracking circuit based at least in part on the decoded status information at operation 1210.

[0114] According to one or more examples, process 1200 optionally includes setting a signal indicative of a lock status of a clock tracking circuit to the determined lock status at operation 1212.

[0115] Fig. 13 is a block diagram illustrating a clock tracking device 1300 (may also be referred to herein as a "clock tracking circuit 1300") that provides a determination of the lock status according to one or more examples. In one or more examples, the clock tracking circuit 1300 may be a hybrid PLL or a digital PLL.

[0116] Clock tracking circuit 1300 generally operates to generate an output clock signal 1308 that is phase-locked and frequency-locked to a reference clock 1314. Clock tracking circuit 1300 includes an error detector 1302, a controller 1304, a digitally controlled oscillator 1306, and a lock status detector 1318.

[0117] Lock status detector 1318 determines the lock status of clock tracking circuit 1300 and generates lock status signal 1322 to indicate the determined lock status. In one or more examples, lock status detectors 1318 may be or include device 100 or device 300.

[0118] In one or more examples, the lock status detector 1318 may determine the lock status of the clock tracking circuit 1300 based on the reference clock 1314 and the feedback clock signal 1316, or alternatively, on the error signal generated by the error detector 1302. Fig. 13 shows a specific, non-limiting example where error detector 1302 generates two error signals that include magnitude and direction information about the phase difference between the set of samples of reference clock 1314 and feedback clock signal 1316, and indirectly about the frequency difference between reference clock 1314 and feedback clock signal 1316. This disclosure is not limited to determining the lock state based on error signals in cases where the error signals are UP and DOWN signals. Any error signal may be used where the timing of the falling edges includes phase information about relevant signals (e.g., reference clock 118 and feedback clock 120, without limitation).In cases where, as non-limiting examples, for example, the error signals generated by error detector 1302 are not suitable for determining the disable status of a clock tracking circuit 1300, or operating conditions might otherwise require it, reference clock 1314 and feedback clock signal 1316 may be used to determine the disable status of clock tracking circuit 1300.

[0119] Error detector 1302 receives reference clock 1314 and feedback clock signal 1316 and generates error signals, including signals UP 1312 and DOWN 1320, that are at least partially responsive thereto. More specifically, error detector 1302 generates an error signal proportional to the phase difference between two input signals to error detector 1302. More specifically, the magnitude and direction of the error signals are proportional to the phase difference between the input signals. When the phase and frequency of the two input signals are substantially equal, the magnitude and direction information in UP 1312 and DOWN 1320 is zero, indicating that the phase and frequency of the two signals are equal.If there is a phase or frequency difference between the two input signals, the magnitude and direction information in UP 1312 and DOWN 1320 is non-zero and proportional to the difference between the phase (and indirectly the frequency) of the two input signals.

[0120] In one or more examples, error detector 1302 may be a binary phase detector, generating error detector 1302 as a binary signal with two separate and distinct component signals, an UP signal and a DOWN signal. Error detector 1302 generates the UP signal and the DOWN signal as a series of pulses, where the pulses of each of the UP signal and the DOWN signal indicate the magnitude and direction of the error. Which of the UP signal and the DOWN signal has a pulse first indicates which of the two input-selected signals leads the other; and conversely, which of the two input-selected signals lags the other. The magnitude of the error signal is represented by the pulse width of a pulse generated in the UP signal or DOWN signal. A larger pulse width indicates a larger phase difference between the two input signals, and a smaller pulse width indicates a smaller phase difference.One of the inputs of error detector 1302 is preset (or preceded) as a reference input to be led, lagged, or locked to, and the other of the inputs of error detector 1302 is preset as a feedback (or "controlled") input to be led, lagged, or locked to. As a non-limiting example, in a clock tracking circuit, the reference signal is provided to the reference input, and the output signal (or a quantity derived therefrom) is provided to the feedback input.

[0121] The reference clock 1314 may be generated from any suitable clock source for a given operating context. The feedback clock signal 1316 may be the same as the output clock signal 1308 generated by the clock tracking circuit 1300 (e.g., the output clock signal 1308 is provided directly to an input of the error detector 1302, without limitation), or it may be a clock signal indicative of the phase and frequency of the output clock signal 1308. For example, the phase and frequency of the feedback clock signal 1316 may be the same or different than the output clock signal 1308, but in either case, they are traceable to the phase and frequency of the output clock signal 1308. In one or more examples, the feedback clock signal 1316 may be a frequency-divided version of the output clock signal 1308 (e.g., via a frequency divider or buffer, without limitation).In one or more cases, the error detector 1302 may be any suitable error detector for producing a digital signal representing the phase error between the reference clock 1314 and the feedback clock signal 1316, including, as a non-limiting example, a bang-bang phase detector, without limitation.

[0122] Digitally controlled oscillator 1306 is an electronic oscillator for generating output clock signal 1308 at least partially in response to control signal 1310, where control signal 1310 is a digital control signal or a digital control code. Control signal 1310 is provided to an input of digitally controlled oscillator 1306.

[0123] The controller 1304 provides the control signal 1310 to the digitally controlled oscillator 1306 to adjust the output clock signal 1308. In one or more examples, the controller 1304 may include circuitry (analog circuitry, digital circuitry, or both) to provide a proportional control path and an integral control path for controlling the digitally controlled oscillator 1306.

[0124] A typical phase frequency detector (PFD) is triggered by either a rising or falling edge, but is not triggered by both a rising and a falling edge. To utilize rising and falling edges of input clock signals, two PFDs are sometimes used: one PFD is triggered by rising edges, the other by falling edges.

[0125] Ideally, the two PFDs should at least perfectly match with respect to: rise and fall times, input-to-output delay (also called "response time"), layout, output loading, and non-idealities (e.g., non-idealities resulting from the manufacturing process, without limitation). A rising-edge triggered PFD and a falling-edge triggered PFD may have non-negligible behavioral differences because they are not perfectly matched. Therefore, sometimes two PFDs triggered by the same edges are used (i.e., both PFDs are triggered by rising edges or both PFDs are triggered by falling edges), with one of the PFDs receiving a non-inverted version of the input clock signals and the other of the PFDs receiving an inverted version of the input clock signals.

[0126] Edge-lock ambiguity can occur when an edge with a first polarity is converted to an edge with a second, different polarity (e.g., a rising edge is converted to a falling edge, or vice versa, without limitation) for dual-edge detection. A clock tracking circuit using dual-edge detection may incorrectly lock a rising edge to a falling edge, or vice versa, due to a ZERO state of the PFD transfer curve at approximately 180 degrees. A ZERO state at 180 degrees, i.e., when two signals are 180 degrees out of phase, is a false positive and can cause a clock tracking circuit to lock out of phase. If the clock tracking circuit locks out of phase, e.g., a rising edge to a falling edge, intervention may be required to unlock.

[0127] Furthermore, due to differences between the rising and falling edge detection circuit paths, reference noise can occur when the clock tracking circuit locks to the opposite edge. Reference noise degrades noise performance. "Reference noise" is an unwanted phase or frequency component in an output signal resulting from a residual difference between the output signal and the reference signal that remains uncorrected due to, as non-limiting examples, non-idealities and imperfections in the error detector or loop filter.

[0128] Fig. 14 is a timing diagram 1400 illustrating a non-limiting example of a conventional two-edge based lock detection having a false zero condition at 180 degrees, as is known to the inventors of this disclosure.

[0129] Timing diagram 1400 includes waveforms for the reference clock, feedback clock, UP signal, DOWN signal, and RESET signal. The waveforms represent an example with a 180-degree phase difference (Δϕ) between the feedback clock and the reference clock.

[0130] At time T0, the UP signal is asserted (rising edge) in response to a rising edge of the reference clock (REFCLK), and the DOWN signal is asserted (rising edge) in response to a falling edge of the feedback clock (FBCLK). A short time after time T0, the RESET signal is asserted (rising edge) in response to both the reference clock and the feedback clock being high. Both the UP signal and the DOWN signal are deasserted (falling edge) in response to the asserted RESET signal.

[0131] At time T1, the UP signal is asserted (rising edge) in response to a falling edge of the reference clock (REFCLK), and the DOWN signal is asserted (rising edge) in response to a rising edge of the feedback clock (FBCLK). A short time after time T1, the RESET signal is asserted (rising edge) in response to both the reference clock and the feedback clock being high. Both the UP signal and the DOWN signal are deasserted (falling edge) in response to the asserted RESET signal.

[0132] If a phase comparison were performed based on the UP signal and the DOWN signal, the phase difference would appear to be zero or negligible, and a conventional two-edge-based lock detector could determine that the clock tracking circuit is in a lock state based on these UP and DOWN signals.

[0133] Sometimes edges occur during the PFD reset time interval and are missed. Missed edges can cause a "False ZERO" condition if the input signals are 180 degrees out of phase.

[0134] Fig. 15 is a timing diagram 1500 showing a non-limiting example of a false zero state with 180 degrees of phase shift due to a missed edge, as is known to the inventors of this disclosure.

[0135] At time T0, the DOWN signal is asserted in response to the rising edge of the feedback clock (rising edge). The UP signal was already high, having previously been asserted in response to the rising edge of the reference clock. Note that the phase difference between the reference clock and the feedback clock is almost 180 degrees.

[0136] At time T1, the RESET signal is activated in response to rising edges of both the UP signal and the DOWN signal in the high state (rising edge).

[0137] At time T2, while the RESET signal is asserted, the reference clock has a falling edge, and the falling edge of the reference clock is missed. The next detected edge is the falling edge of the feedback clock at time T3, and the DOWN signal is asserted in response to the falling edge of the feedback clock (rising edge).

[0138] At time T4, the UP signal is activated in response to a rising edge of the reference clock (rising edge).

[0139] At time T5, the RESET signal is asserted (rising edge) in response to both the UP signal and the DOWN signal being high. Also at time T5, both the UP signal and the DOWN signal are deasserted (falling edge) in response to the RESET signal being asserted.

[0140] In the Fig. In the case shown in Figure 15, the phase information in the first set of UP and DOWN signals is accurate, but the phase information in the second set of UP and DOWN signals is not accurate due to the missed falling edge of the reference clock.

[0141] One or more examples relate to single- or dual-edge-triggered phase error detection. Dual-edge phase error detection is only performed when the phase error is less than the false zero threshold. The false zero threshold is a threshold of 180 degrees or less, which, depending on the specific operating conditions, ensures that a false zero condition does not occur.

[0142] Fig. 16 is a block diagram illustrating an apparatus 1600 that provides single and dual edge triggered phase error detection according to one or more examples.

[0143] Device 1600 includes a phase detector 1602 and a phase error detector 1604. The phase error detector 1604 may alternatively be a single-edge trigger 1606 or a dual-edge trigger 1608.

[0144] Phase detector 1602 generates status signal 1616 at least in part in response to two input signals, here reference clock 1610 and feedback clock 1612. Phase detector 1602 determines a phase difference between reference clock 1610 and feedback clock 1612 and the status of the determined phase difference. Status signal 1616 indicates a status of phase difference 1618 between reference clock 1610 and feedback clock 1612.

[0145] The phase difference status 1618 is a value representing the instantaneous status of the phase difference between the reference clock 1610 and the feedback clock 1612, or a set of consecutive values representing the continuous status of the phase difference between the reference clock 1610 and the feedback clock 1612.

[0146] In one or more examples, the status of the phase difference 1618 that the phase detector 1602 detects is whether a phase relationship between the reference clock 1610 and the feedback clock 1612 is less than the false zero threshold, e.g., 180 degrees, optionally by some threshold to avoid a false zero state. If the phase detector 1602 determines that the phase relationship between the reference clock 1610 and the feedback clock 1612 is less than the false zero threshold, the phase detector 1602 sets the status signal 1616 to a first value. If the phase detector 1602 determines that the phase relationship between the reference clock 1610 and the feedback clock 1612 is greater than the false zero threshold, the phase detector 1602 sets the status signal 1616 to a second value that is different from the first value.

[0147] The phase detector 1602 may change the value of the status signal 1616 from a value indicating that the phase relationship is less than 180 degrees to a value indicating that it is not less than 180 degrees in response to a changing (i.e., increasing) phase difference between the reference clock 1610 and the feedback clock 1612. Thus, in one or more examples, the status of the phase difference 1618 and the state of the status signal 1616 may change over time, at least in part, in response to changes in the phase difference between the reference clock 1610 and the feedback clock 1612.

[0148] The phase error detector 1604 receives the reference clock 1610, the feedback clock 1612, and the phase threshold status signal 1616 and generates the error signal 1614 at least in part in response thereto.

[0149] In one or more examples, phase error detector 1604 generates an error signal proportional to a phase difference between two input selected signals (here, reference clock 1610 and feedback clock 1612). More specifically, the magnitude and direction of the phase error indicated by the error signal are proportional to the phase difference between the input selected signals. If the phase and frequency of the two selected input signals are substantially the same, the magnitude and direction information of the error signal is zero, indicating that the phase and frequency of the two signals are the same. If there is a phase or frequency difference between the two input signals, the magnitude and direction information of the error signal is non-zero and proportional to the difference between the phase (and indirectly the frequency) of the two input signals.

[0150] In one or more examples, phase error detector 1604 may be a binary phase detector that generates error signal 1614 as a binary signal having two separate and distinct component signals, an UP signal and a DOWN signal. Phase error detector 1604 generates the UP signal and the DOWN signal as a series of pulses, where the pulses of each of the UP signal and the DOWN signal indicate the magnitude and direction of the error. The first one of the UP signal and the DOWN signal to have a pulse indicates which of the two input-selected signals leads the other; and conversely, which of the two input-selected signals lags the other. The magnitude of error signal 1614 is represented by the pulse width of a pulse generated in the UP signal or the DOWN signal.A larger pulse width indicates a larger phase difference between the two input signals, and a smaller pulse width indicates a smaller phase difference. One of the inputs of phase error detector 1604 is preset as a reference input to be led, lagged, or locked to, and the other of the inputs of phase error detector 1604 is preset as a feedback (or "controlled") input to be led, lagged, or locked to. As a non-limiting example, in a clock tracking circuit, the reference signal is provided to the reference input, and the output signal (or a quantity derived therefrom) is provided to the feedback input.

[0151] The phase error detector 1604 operates either with a single-edge trigger 1606 (triggered by one edge) or with a two-edge trigger 1608 (triggered by two edges).

[0152] While the phase error detector 1604 with a single-edge trigger 1606 is only triggered on edges of the reference clock 1610 and the feedback clock 1612 with a first polarity (i.e., it generates an error signal 1614 in response thereto), it is not triggered on edges that have a second, different polarity. The edges with the first polarity can be rising or falling edges, and the edges with the second polarity can be the other rising or falling edge. Single-edge triggering (triggered by one edge) is also referred to as "single-pole edge triggering." In single-edge triggering 1606, the phase information about the reference clock 1610 and the feedback clock 1612 in the error signal 1614 is based exclusively on the edges of the reference clock 1610 and the feedback clock 1612 with the first polarity.

[0153] In dual-edge triggering 1608, phase error detector 1604 triggers (i.e., generates an error signal 1614 in response to) edges of reference clock 1610 and feedback clock 1612 having a first polarity, as well as edges of reference clock 1610 and feedback clock 1612 having a second, different polarity. The first-polarity edges can be rising or falling edges, and the second-polarity edges can be the other rising or falling edge. Dual-edge triggering (triggered by two edges) may also be referred to as "two-pole edge triggering," where "two polarities" refers to the first polarity and the second, different polarity.In dual edge triggering 1608, the phase information about the reference clock 1610 and the feedback clock 1612 in the error signal 1614 is based on edges of the reference clock 1610 and the feedback clock 1612 with the first polarity and edges of the reference clock 1610 and the feedback clock 1612 with the second polarity.

[0154] The "single-edge trigger 1606" or "double-edge trigger 1608" is asserted at the phase error detector 1604, at least in part in response to a value of the status signal 1616. A first value of the status signal 1616 indicates that the phase difference between the reference clock 1610 and the feedback clock 1612 is less than the false zero threshold. A second value of the status signal 1616 indicates that the phase difference between the reference clock 1610 and the feedback clock 1612 is greater than or equal to the false zero threshold.In this way, the phase error detector 1604 can operate as a single-edge trigger 1606 while the phase difference between the reference clock 1610 and the feedback clock 1612 is greater than or equal to the false zero threshold, and as a double-edge trigger 1608 while the phase difference between the reference clock 1610 and the feedback clock 1612 is less than the false zero threshold.

[0155] In dual edge triggering, edges fed into the phase error detector 1604 are converted to the same polarity if this polarity is not already present.

[0156] If an edge of the feedback clock 1612 or the reference clock 1610 has a different polarity, it is converted to the same polarity. The phase error detector 1604 could disable edges of the feedback clock 1612 and the reference clock 1610 with different polarities if the phase error were greater than or equal to 180 degrees. By limiting phase error detection based on edges with a first polarity until the phase error is less than 180 degrees, and then detecting the phase error based on both edges with the first polarity and edges with a second polarity, it is ensured that "false ZERO" conditions do not occur.

[0157] One or more examples generally relate to phase error detection, which operates with single-edge triggering until the phase error between two input signals is less than 180 degrees, and then operates with double-edge triggering. In single-edge mode, phase error detection is based at least in part on unconverted versions of the input signals. In double-edge mode, phase error detection is based at least in part on converted versions of the input signals.

[0158] Examples reduce or eliminate the false zero condition that would otherwise occur in the PFD transfer function in dual-edge mode and that could potentially prevent the clock tracking circuit from locking for a sufficiently small phase error.

[0159] Fig. 17 is a block diagram illustrating a device 1700 that provides single-edge and dual-edge triggered phase error detection according to one or more examples. The device 1700 may also be referred to herein as "phase error detector 1700."

[0160] The device 1700 dynamically transitions from single-edge lock detection to double-edge lock detection. The device 1700 transitions from single-edge lock detection in response to determining that the phase error between two input signals is less than the false zero threshold, in this case, 180 degrees.

[0161] The device 1700 includes a phase detector 1702, an inverter 1704, an inverter 1706, an AND gate 1708, an AND gate 1710, a first flip-flop 1712, a second flip-flop 1714, a third flip-flop 1716, a fourth flip-flop 1718, an OR gate 1722, an OR gate 1724, a delay 1726, and a NAND gate 1728.

[0162] The phase detector 1702 is a non-limiting example of the phase detector 1602 of Fig. 16 (the status of the phase difference 1618 is omitted only to Fig. 17 not to be unnecessarily overloaded). The remaining sequential logic circuit in Fig. 17 is a non-limiting example of the phase error detector 1604 of Fig. 16, and the UP signals 1738 and the DOWN signal 1740 are examples of component error signals of the error signal 1614.

[0163] The phase detector 1702 generates the status signal 1732 at least in part in response to two input signals, here the reference clock 1734 and the feedback clock 1736. The phase detector 1702 may be, as a non-limiting example, the phase detector 200 of Fig. 2, in which the threshold for the "False ZERO" state is set to 180 degrees. The status signal 104 indicates the phase relationship between the reference clock 1734 and the feedback clock 1736, namely, whether it is less than the threshold for the "False ZERO" state, to ensure that the ZERO states discussed above do not occur. The phase detector 1702 determines whether or not the phase relationship between the reference clock 1734 and the feedback clock 1736 is less than 180 degrees and sets the status signal 1732 to a value based on this determination. In the Fig. In the specific, non-limiting example illustrated in Figure 17, the set value of status signal 1732 is maintained unless / until the phase difference exceeds the 180-degree threshold. In other examples, it is expressly contemplated that once the value of status signal 1732 is set to indicate that the phase difference is less than 180 degrees, it will not change unless / until the phase relationship exceeds the 180-degree threshold.

[0164] If the phase detector 1702 determines that the phase difference is not less than 180 degrees, the phase detector 1702 sets the status signal 1732 to a value indicating this. In the Fig. 17, the phase detector 1702 uses a high or "1" state to indicate that the phase difference is less than 180 degrees and uses a low or "0" state to indicate that the phase difference is not less than 180 degrees. Other conventions may be used with minor circuit changes to the device 1700 that would be readily apparent to one of ordinary skill in the art, and the use of other conventions does not exceed the scope of this disclosure.

[0165] The first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, and the fourth flip-flop 1718 are edge-triggered flip-flops. Each flip-flop 202, 204, 220, and 224 has a data input (D), a clock input (CLK), and an output (Q).

[0166] When the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, or the fourth flip-flop 1718 is reset, its respective output (Q) is forced low (i.e., the low state at the reset input (R) overrides the data input (D) and the clock input (CLK), forcing the output (Q) low). The respective reset inputs (R) of the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, and the fourth flip-flop 1718 are active low.

[0167] Delay 1726 is a delay circuit that introduces a predetermined time delay in the propagation of a signal from its input to its output. In one or more examples, the introduced predetermined time delay is equal to, or at least partially based on, an appropriate time to allow components in a clock tracking circuit a minimum turn-on time to settle before the state of the output of phase error detector 1700 changes.

[0168] The respective data inputs (D) of the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, and the fourth flip-flop 1718 are coupled to a supply voltage to set the data inputs (D) to a high state. The clock input (CLK) of the first flip-flop 1712 receives the reference clock 1734, and the clock input (CLK) of the third flip-flop 1716 receives the feedback clock 1736. One of the inputs of the OR gate 1722 receives the output (Q) of the first flip-flop 1712, and one of the inputs of the OR gate 1722 receives the output of the second flip-flop 1714. The output of the OR gate 1722 is provided as the UP signal 1738. One of the inputs of OR gate 1724 receives the output (Q) of third flip-flop 1716, and one of the inputs of OR gate 1724 receives the output of fourth OR gate 1724 of the fourth flip-flop. The output of OR gate 1724 is provided as DOWN signal 1740.

[0169] An input of delay 1726 receives the output of NAND gate 1728. The respective reset inputs (R) of first flip-flop 1712 and third flip-flop 1716 receive the output of delay 1726, which is the delayed output of NAND gate 1728. The output of delay 1726, i.e., the delayed output of NAND gate 1728, may also be referred to herein as reset signal 1742. As long as at least one of the inputs of NAND gate 1728 is set to the low state, its output is set to the high state, whereby neither the first flip-flop 1712 nor the third flip-flop 1716 are reset.

[0170] While the phase difference between reference clock 1734 and feedback clock 1736 is greater than or equal to 180 degrees, phase detector 1702 maintains the clock inputs (CLK) of second flip-flop 1714 and fourth flip-flop 1718 low via inverter 1704, AND gate 1708, inverter 1706, and AND gate 1710. While the clock inputs (CLK) are maintained low, the respective outputs (Q) of second flip-flop 1714 and fourth flip-flop 1718 do not change their reset state and are therefore low. This state corresponds to setting device 1700 to single-edge triggered operation. If the phase difference between the reference clock 1734 and the feedback clock 1736 is less than 180 degrees, the phase detector 1702 sets the device 1700 to dual edge triggering, as described below.

[0171] In single-edge mode, device 1700 is triggered by a rising edge. When reference clock 1734 or feedback clock 1736 transitions from low to high (i.e., has a rising edge), the corresponding UP signal 1738 or DOWN signal 1740 transitions from low to high. When the other reference clock 1734 or feedback clock 1736 transitions from low to high, the other corresponding UP signal 1738 or DOWN signal 1740 transitions from low to high. The first flip-flop 1712 and the third flip-flop 1716 are reset after a predetermined delay time provided by delay 1726 in response to both the UP signal 1738 and the DOWN signal 1740 transitioning from low to high by the action of NAND gate 1728.The respective outputs (Q) of the first flip-flop 1712 and the third flip-flop 1716 are set (forced) low in response to the reset. In response to the outputs (Q) of the first flip-flop 1712 and the third flip-flop 1716 changing from high to low, the UP signal 1738 and the DOWN signal 1740 change from high to low. When the respective outputs (Q) of the flip-flops are forced low, the Reset signal 1742 changes from high to low due to the action of the NAND gate 1728.

[0172] When the phase difference between reference clock 1734 and feedback clock 1736 is less than 180 degrees, phase detector 1702 enables dual-edge mode at device 1700. Specifically, phase detector 1702 sets and maintains status signal 1732 high. One of the inputs of AND gate 1708 and AND gate 1710 is set high in response to status signal 1732 being set high. The other input of AND gate 1708 and AND gate 1710 receives the inverted reference clock 1734 via inverter 1704 and the inverted feedback clock 1736 via inverter 1706, respectively. Holding either input of AND gate 1708 and AND gate 1710 high effectively sets the respective outputs of AND gate 1708 and AND gate 1710 to synchronize to reference clock 1734 and feedback clock 1736, respectively.the feedback clock 1736, and thus sets the respective clock inputs (CLK) of the second flip-flop 1714 and the fourth flip-flop 1718 to respond to the inverted reference clock 1734 and the inverted feedback clock 1736, respectively. Setting the respective clock inputs (CLK) of the second flip-flop 1714 and the fourth flip-flop 1718 to respond to the inverted reference clock 1734 and the feedback clock 1736 means that the respective clock inputs (CLK) of the second flip-flop 1714 and the fourth flip-flop 1718 are set to respond to the falling edges of the reference clock 1734 and the feedback clock 1736. Thus, when the reference clock 1734 or the feedback clock 1736 changes from high to low (i.e., has a falling edge), the corresponding second flip-flop 1714 or the fourth flip-flop 1718 is triggered and its output (Q) changes from low to high.

[0173] In dual-edge mode, rising-edge triggering is performed in the same way as in the single-edge mode described above. With falling-edge triggering, when the reference clock 1734 or the feedback clock 1736 transitions from high to low (i.e., has a falling edge), the corresponding UP signal 1738 or DOWN signal 1740 transitions from low to high via the respective OR gate 1722 and OR gate 1724. When the other reference clock 1734 or the feedback clock 1736 transitions from high to low, the other corresponding UP signal 1738 or DOWN signal 1740 transitions from low to high.The first flip-flop 1712 and the third flip-flop 1716 are reset after a predetermined delay time provided by the delay 1726 in response to both the UP signal 1738 and the DOWN signal 1740 transitioning from low to high by the action of the NAND gate 1728. The respective outputs (Q) of the second flip-flop 1714 and the fourth flip-flop 1718 are set (forced) low in response to the reset. In response to the outputs (Q) of the first flip-flop 1712 and the third flip-flop 1716 transitioning from high to low, the UP signal 1738 and the DOWN signal 1740 transition from high to low.

[0174] Fig. 18 is a flowchart illustrating a process 1800 for enhanced dual-edge detection according to one or more examples. Some or all of the operations of process 1800 may be performed by, as a non-limiting example, device 1600 or phase error detector 1604, phase error detector 1700.

[0175] While the example process 1800 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 1800. In other examples, various components of an example device or system implementing the process 1800 may perform functions at substantially the same time or in a particular sequence.

[0176] According to one or more examples, the method includes generating an error signal via a phase error detector that is proportional to a phase difference between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock at operation 1802.

[0177] According to one or more examples, the method includes, in response to a status signal indicating the status of the phase difference between the reference clock and the feedback clock, setting the phase error detector to respond to both.

[0178] The edges of the reference clock and the feedback clock have a first polarity; or the edges of the reference clock and the feedback clock have a first polarity and the edges of the reference clock and the feedback clock have a second polarity, wherein the second polarity is different from the first polarity at operation 1804.

[0179] Fig. 19 is a flowchart illustrating a process 1900 for setting a status signal to indicate a status of the phase difference between a reference clock and a feedback clock, according to one or more examples. Some or all of the operations of process 1900 may be performed by device 1600 or phase detector 1602, as a non-limiting example.

[0180] While the example process 1900 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 1900. In other examples, different components of an example device or system implementing the process 1900 may perform functions at substantially the same time or in a particular sequence.

[0181] According to one or more examples, the method includes determining a respective state of the phase difference between the reference clock and the feedback clock at operation 1902.

[0182] According to one or more examples, the method includes setting the status signal to indicate the determined respective status of the phase difference at operation 1904.

[0183] Fig. 20 is a flowchart illustrating a process 2000 for setting a status signal to indicate a status of the phase difference between a reference clock and a feedback clock, according to one or more examples. Some or all of the operations of process 2000 may be performed by device 1600 or phase detector 1602, as a non-limiting example.

[0184] While the example process 2000 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 2000. In other examples, different components of an example device or system implementing the process 2000 may perform functions at substantially the same time or in a particular sequence.

[0185] According to one or more examples, the method includes setting the status signal to a first value to indicate that a phase difference between the reference clock and the feedback clock is less than a false zero threshold at operation 2002.

[0186] According to one or more examples, the method includes setting the status signal to a second value to indicate that the phase difference between the reference clock and the feedback clock is greater than or equal to the false zero threshold, wherein the second value is different from the first value at operation 2004.

[0187] Fig. 21 is a flowchart illustrating a process 2100 for determining the status of a phase difference between a reference clock and a feedback clock, according to one or more examples. Some or all of the operations of process 2100 may be performed by device 1600 or phase detector 1602, as a non-limiting example.

[0188] While the example process 2100 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 2100. In other examples, different components of an example device or system implementing the process 2100 may perform functions at substantially the same time or in a particular sequence.

[0189] According to one or more examples, the method includes determining a first status of the phase relationship in response to determining that the phase relationship is less than a false zero state threshold at operation 2102.

[0190] According to one or more examples, the method includes determining a second status of the phase relationship in response to determining that the phase relationship is greater than or equal to the false zero state threshold at operation 2104.

[0191] Fig. 22 is a flowchart illustrating a process 2200 for determining a phase error according to one or more examples. Some or all of the operations of process 2200 may be performed by device 1600 or phase error detector 1604, as a non-limiting example.

[0192] While the example process 2200 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 2200. In other examples, different components of an example device or system implementing the process 2200 may perform functions at substantially the same time or in a particular sequence.

[0193] According to one or more examples, the method includes: while the phase error detector is set to respond to edges of the reference clock and the feedback clock having the first polarity, determining the phase error by the phase error detector based at least in part on edges of the first polarity, at operation 2202.

[0194] According to one or more examples, the method includes: while the phase error detector is set to respond to edges of the reference clock and the feedback clock having the first polarity and to edges of the reference clock and the feedback clock having the second polarity, determining the phase error by the phase error detector based at least in part on edges of the reference clock and the feedback clock having the first polarity and on edges of the reference clock and the feedback clock having the second polarity, at operation 2204.

[0195] Fig. 23 is a flowchart illustrating a process 2300 for setting a phase error signal to indicate a magnitude and direction of the phase difference between a reference clock and a feedback clock, according to one or more examples. Some or all of the operations of process 2200 may be performed by device 1600 or phase error detector 1604, as a non-limiting example.

[0196] While the example process 2300 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 2300. In other examples, various components of an example device or system implementing the process 2300 may perform functions at substantially the same time or in a particular sequence.

[0197] According to one or more examples, the method includes: while the phase error detector is set to respond to edges of the reference clock and the feedback clock having the first polarity, setting an error signal by the phase error detector (e.g., error signal 1614 of Fig. 16 or UP signal 1738 and DOWN signal 1740 from Fig. 17, without limitation) to indicate, at operation 2302, the magnitude and direction of the phase error between edges of the reference clock and the feedback clock having the first polarity.

[0198] According to one or more examples, the method includes, while the phase error detector is set to respond to edges of the reference clock and the feedback clock having the first polarity and to edges of the reference clock and the feedback clock having the second polarity, detecting an error signal by the phase error detector (e.g., error signal 1614 of Fig. 16 or UP signal 1738 and DOWN signal 1740 from Fig. 17, without limitation) to indicate, at operation 2304, the magnitude and direction of the phase difference between edges of the reference clock and the feedback clock having the first polarity and edges of the reference clock and the feedback clock having the second polarity.

[0199] Fig. 24 illustrates an example 2400 of setting a status signal to indicate a status of the phase relationship between a reference clock and a feedback clock based on a false zero threshold, according to one or more examples.

[0200] Although example 2400 illustrates a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of 2400. In other examples, different components of an example device or system implementing 2400 may perform functions at substantially the same time or in a particular sequence.

[0201] According to some examples, the method includes detecting the occurrence of equal respective edges of the reference clock and the feedback clock at operation 2402.

[0202] According to some examples, the method includes setting the status signal to the first value responsive to a time difference between the detected occurrence of equal corresponding edges of the reference clock and the feedback clock at block 2404 that is less than a false zero threshold.

[0203] According to some examples, the method includes setting the status signal to the second value responsive to the time difference between the detected occurrence of equal respective edges of the reference clock and the feedback clock at block 2406 when it is greater than or equal to the false zero state threshold.

[0204] Fig. 25 is a timing diagram 2500 illustrating an example operation of a dual-edge PFD such as device 1700, without limitation.

[0205] Timing diagram 2500 includes waveforms for the following signals: reference clock 1734, feedback clock 1736, UP signal 1738, DOWN signal 1740, and RESET signal 1742. The waveforms represent an example with a small phase difference (Δϕ).

[0206] At time T0, the UP signal 1738 is activated in response to a rising edge of the reference clock 1734 (causing a rising edge).

[0207] At time T1, the DOWN signal 1740 is activated in response to a rising edge of the feedback clock 1736 (causing a rising edge).

[0208] At time T1 (plus an optional delay due to delay 1726, which, however, is Fig. 18), in response to the rising edges of the UP signal 1738 and the DOWN signal 1740, and when both are high, the reset signal 1742 is activated (causing a rising edge), maintained high for a predetermined period of time, and then deactivated (causing a falling edge). In particular, in the exemplary device 1700 of Fig. 17 the reset signal 1742 Active Low (as described above with respect to the reset inputs (R) of the respective flip-flops of the device 1700 of Fig. 17), nevertheless Fig. 25 represents a pulse (low state to high state and then high state to low state) to simplify the description. Any convention can be used without exceeding the scope (e.g., "Active Low" or "Active High").

[0209] At time T1 + the predetermined time period (during which the UP signal 1738 and the DOWN signal 1740 are maintained in a high state), both the UP signal 1738 and the DOWN signal 1740 are deactivated (causing corresponding falling edges) in response to the activation of the reset signal 1742.

[0210] From time T0 to time T1, a phase comparison of the phase frequency detector PFD is performed between the reference clock 1734 and the feedback clock 1736 using the timing of their respective rising edges, and the phase detector PFD determines that the phase difference (Δϕ) is less than 180 degrees and activates the status signal 1732 (the status signal 1732 is in Fig. 25 not shown). Activating the status signal 1732 enables dual-edge detection and, in particular, triggering the reference clock 1734 and the feedback clock 1736 on both rising and falling edges.

[0211] At time T2, the UP signal 1738 is activated in response to a falling edge of the reference clock 1734 (causing a rising edge).

[0212] At time T3, the DOWN signal 1740 is activated in response to a falling edge of the feedback clock 1736 (causing a rising edge).

[0213] At time T3+, in response to falling edges of the UP signal 1738 and the DOWN signal 1740, and when both are low, the Reset signal 1742 is asserted (causing a rising edge), held high for a predetermined period of time, and then deasserted (causing a falling edge).

[0214] At time T3 + the predetermined time period (during which the UP signal 1738 and the DOWN signal 1740 are maintained in a high state), both the UP signal 1738 and the DOWN signal 1740 are deactivated (causing corresponding falling edges) in response to the activation of the reset signal 1742.

[0215] Fig. Figure 26 is a diagram 2600 of a simulation plot showing a curve representing a PFD transfer function in the single-edge mode of a phase error detector according to one or more examples. The PFD has a zero state only at 0 degrees, but not at 180 degrees, and therefore always aligns rising edges with rising edges.

[0216] Fig. Figure 27 is a diagram 2700 of a simulation plot showing a curve representing a nominal PFD transfer function in dual-edge mode, having an undesired ZERO state at 180 degrees and a desired ZERO state at 0 degrees. The false ZERO state at 180 degrees allows the clock tracking circuit to phase lock with opposite edges, thereby increasing mismatches and reference noise.

[0217] Fig. Figure 28 is a diagram 2800 of a simulation plot showing a curve representing the transfer function of the dynamic dual-edge mode. At 180 degrees, there is no longer a zero state. Therefore, the PFD will force the PLL to lock the rising edge to the rising edge, as in the case of the single-edge mode. For a small phase error, the dual-edge mode is activated, resulting in a 2x gain of the transfer curve (triggered by both rising and falling edges instead of just one of the two edges) and a doubling of the PFD rate. The 2x slope parts of the curve correspond to the circuit operating in dual-edge mode with 2x gain (for this range of phase error). A negative phase error refers to the case where the feedback clock leads the reference clock. A positive phase error refers to the case where the feedback clock lags the reference clock.

[0218] It will be understood by those skilled in the art that functional elements of examples disclosed herein (e.g., functions, operations, actions, processes, and / or methods) may be implemented in any suitable hardware, software, firmware, or combinations thereof. Fig. Figure 29 illustrates non-limiting examples of implementations of functional elements disclosed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware capable of executing the functional elements.

[0219] Fig. 29 is a block diagram of circuitry 2900 that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. Circuitry 2900 includes one or more processors 2902 (sometimes referred to herein as "processors 2902") operably coupled to one or more data storage devices 2906 (sometimes referred to herein as "memory 2906"). Memory 2906 includes machine-executable code 2908 stored thereon, and processors 2902 include logic circuitry 2904. Machine-executable code 2908 includes information describing functional elements that may be implemented (e.g., performed) by logic circuitry 2904. The logic circuit 2904 is adapted to implement (e.g., perform) the functional elements described by the machine-executable code 2908.Circuit logic 2900 should be considered special-purpose hardware for executing functional elements disclosed herein when executing the functional elements described by machine-executable code 2908. In some examples, processor(s) 2902 may perform the functional elements described by machine-executable code logic 2904 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0220] When machine-executable code 2908 implements the logic circuitry of processors 2902, machine-executable code 2908 adapts processor(s) 2902 to perform operations of the examples disclosed herein, including determining a lock status of a clock tracking circuit. As a non-limiting example, machine-executable code 2908 may adapt processors 2902 to perform some or all of the operations of one or more of the following processes: process 800, process 900, process 1000, process 1100, or process 1200.

[0221] As a non-limiting example, machine-executable code 2908 may adapt processors 2902 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following devices: device 100, device 200, device 300, device 400, device 500, device 600, device 700. More specifically, features, functions, or operations disclosed herein for one or more of the following: phase detector 102, a digital discriminator 106, and a logic circuit 112 of Fig. 1; the device 200 includes a first flip-flop 202, a second flip-flop 204, a third flip-flop 220, a fourth flip-flop 218, a first delay circuit 208, a second delay circuit 222, a NAND gate 206 and a NOR gate 210 of Fig.2; and digital filter 302 and register 304; accumulation register 402, comparator 404, sample clock divider 502, sample logic circuit 602, interpolator 604, decimator 606, multiplexer 612, clock tracking circuit 1300, error detector 1302, control unit 1304, controlled oscillator 1306, or lock status detector 1318.

[0222] When machine-executable code 2908 implements the logic circuitry of processors 2902, machine-executable code 2908 adapts processor(s) 2902 to perform operations of the examples disclosed herein, including dual-edge triggered phase error detection. As a non-limiting example, machine-executable code 2908 may adapt processor(s) 2902 to perform some or all of the operations of one or more of the following: process 1800, process 1900, process 2000, process 2100, process 2200, process 2300, process 2400, timing diagram 2500, diagram 2600, diagram 2700, or diagram 2800.

[0223] Also as a non-limiting example, machine-executable code 2908 may adapt processors 2902 to perform some or all of the features, functions, or operations disclosed herein for one or more of devices 1600 and devices 1700. More specifically, features, functions, or operations disclosed herein for one or more of the following: phase detector 1602, phase error detector 1604, single-edge trigger 1606, dual-edge trigger 1608; Phase detector 1702, inverter 1704, inverter 1706, AND gate 1708, AND gate 1710, first flip-flop 1712, second flip-flop 1714, third flip-flop 1716, fourth flip-flop 1718, OR gate 1722, OR gate 1724, delay 1726, NAND gate 1728.

[0224] The processor(s) 2902 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof configured to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer executes functional elements corresponding to the machine-executable code 2908 (e.g., software code, firmware code, hardware descriptions) related to examples of the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but processors 502 may alternatively include any conventional processor, controller, microcontroller, or state machine. Processor(s) 2902 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0225] In some examples, the memory 2906 includes volatile data storage (e.g., random access memory (RAM)), non-volatile data storage (e.g., without limitation, flash memory, a hard disk drive, a solid-state drive, erasable programmable read-only memory (EPROM)). In some examples, the processor(s) 2902 and the memory 2906 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), without limitation). In some examples, the processor(s) 2902 and the memory 2906 may be implemented in separate devices.

[0226] In some examples, machine-executable code 2908 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by memory 2906, which may be directly accessible by processor(s) 2902, and executed by processor(s) 2902 using at least logic circuitry 2904. Also as a non-limiting example, the computer-readable instructions may be stored on memory 2906, transferred to a storage device (not shown) for execution, and executed by processors 502 using at least logic circuitry 2904. Accordingly, in some examples, logic circuitry 508 includes electrically configurable logic circuitry 2904.

[0227] In some examples, machine-executable code 2908 may describe hardware (e.g., circuit logic) to be implemented in logic circuitry 2904 to perform the functional elements. This hardware may be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), may be used. As non-limiting examples, Verilog™, SystemVerilog™, or very large-scale integration (VLSI) hardware description languages (VHDL) may be used.

[0228] HDL descriptions can be converted at will into descriptions at any of numerous other levels of abstraction. As a non-limiting example, a high-level description can be converted into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g.,The operations to be performed (e.g., gates, flip-flops, registers, without limitation) of logic circuit 2904 may be described in an RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples, machine-executable code 2908 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0229] In examples where machine-executable code 2908 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 2906) implements the hardware description described by machine-executable code 2908. As a non-limiting example, processor(s) 2902 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 2904 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 2904. Also as a non-limiting example, logic circuitry 2904 may include hard-wired logic manufactured by a manufacturing system (not shown, but including storage 2906) according to the hardware description of machine-executable code 2908.

[0230] Regardless of whether the machine-executable code 2908 includes computer-readable instructions or a hardware description, the logic circuit 2904 is adapted to perform the functional elements described by the machine-executable code 2908 when implementing the functional elements of the machine-executable code 2908. It should be noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description can perform.

[0231] As used in the present disclosure, the terms "module" or "component" may refer to specific hardware implementations configured to perform the actions of the module or component and / or software objects or software routines stored on and / or executable by general-purpose hardware (e.g., computer-readable media, processing devices, without limitation) of the computing system. In some examples, the various components, modules, engines, and services described in the present disclosure may be implemented as objects or processes executing on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by general purpose hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are contemplated.

[0232] As used in the present disclosure, the term "combination" with respect to a plurality of elements may include a combination of all of the elements or any of various different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0233] Terms used in the present disclosure, and particularly in the appended claims (e.g., without limitation, the body of the appended claims), are generally intended to be "open-ended" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "comprising" should be interpreted as "at least comprising," the term "includes" should be interpreted as "includes, but not limited to"). As used herein, the term "each" means "some or a whole." As used herein, the term "all" means a "whole."

[0234] Furthermore, if a specific number of introduced claim statements are intended, that intention will be expressly stated in the claim, and in the absence of such reciting, no such intention exists. As an aid to understanding, for example, the following accompanying claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that the introduction of a claim statement by the indefinite articles "a" or "an" limits a particular claim containing such introduced claim statement to examples containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g.,"a" and / or "an" shall be interpreted to mean "at least one" or "one or more", without limitation); the same applies to the use of certain articles used to introduce claim particulars.

[0235] Additionally, even if a particular number of an introduced claim statement is explicitly stated, one of ordinary skill in the art will recognize that such a statement should be interpreted to mean at least the stated number (e.g., simply stating "two statements" without other modifiers means at least two statements, or two or more statements, without limitation). Furthermore, where a convention analogous to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without limitation.

[0236] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including either term, one term or the other, or both. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B."

[0237] Other non-limiting examples include: Example 1: A device comprising: a phase detector, wherein a status signal of the phase detector is based at least in part on a phase relationship between a reference clock and a feedback clock, the feedback clock being generated by a clock tracking circuit to track the reference clock; a digital discriminator for sampling the status signal of the phase detector; and logic circuitry for determining a disable status of the clock tracking circuit based at least in part on samples of the status signal of the phase detector. Example 2: The device of example 1, wherein the phase detector sets the status signal based at least in part on a phase threshold and the phase relationship between the reference clock and the feedback clock. Example 3: The device according to one of examples 1 and 2, wherein a value of the phase threshold is adjustable. Example 4: The device of any one of examples 1 to 3, wherein the phase detector for: setting the status signal is responsive at least in part to determining that a certain difference amount is greater than a phase threshold. Example 5: The device of any one of examples 1 to 4, wherein the phase detector is responsive to: setting the phase detector status signal to a second value at least in part to determining that a certain difference amount is equal to or less than a phase threshold, the second value being different from a first value. Example 6: The device of any one of examples 1 to 5, wherein to determine the lock status of the clock tracking circuit, the logic circuit is to: decode lock status information from samples of the status signal of a phase detector; and determine the lock status of the clock tracking circuit based at least in part on the decoded lock status information. Example 7: The device according to any one of examples 1 to 6, wherein the logic circuit is for setting a lock status signal to a first value to indicate a lock status and for setting the lock status signal to a second value to indicate that no lock status exists. Example 8: The device according to any one of examples 1 to 7, wherein the phase detector is for: detecting the occurrence of equal respective edges of the reference clock and the feedback clock; and for setting the status signal to indicate whether or not the detected occurrence of equal respective edges was within a predetermined range. Example 9: The device according to any one of examples 1 to 8, wherein the phase detector for: setting the status signal to a first value is responsive to a time difference between the detected occurrence of like respective edges of the reference clock and the feedback clock is less than a phase threshold. Example 10: The device of any one of examples 1 to 9, wherein the phase detector is responsive to: setting the status signal to a second value based on the time difference between the detected occurrence of equal respective edges of the reference clock and the feedback clock is greater than or equal to the phase threshold. Example 11: The device according to any one of examples 1 to 10, wherein the digital discriminator includes a decimator for decimating values of the status signal. Example 12: The device according to any one of examples 1 to 11, wherein the digital discriminator includes an interpolator for interpolating values based on the status signal. Example 13: The device of any one of examples 1 to 12, wherein the digital discriminator includes a digital filter to block a status signal indicative of a transient phase error and pass a status signal indicative of a steady-state phase error. Example 14: A method comprising: setting a status signal of a phase detector, wherein the status signal of the phase detector is set based at least in part on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock; and generating a signal indicative of a disable status of the clock tracking circuit based at least in part on the status signal of the phase detector. Example 15: The method of Example 14, comprising: determining whether or not a phase relationship between the reference clock and the feedback clock is within a predetermined range; and setting the status signal of the phase detector based at least in part on the determination. Example 16: The method of any one of examples 14 and 15, comprising: setting the status signal of the phase detector to a first value, at least in part in response to determining that a certain difference amount is greater than a phase threshold. Example 17: The method of any one of examples 14 to 16, comprising: setting the status signal of the phase detector to a second value, at least in part in response to determining that a certain difference amount is equal to or less than a phase threshold, wherein the second value is different from a first value. Example 18: The method of any one of examples 14 to 17, detecting the occurrence of equal respective edges of the reference clock and the feedback clock; and setting the status signal to indicate whether or not the detected occurrence of equal respective edges was within a predetermined range. Example 19: The method of any one of examples 14 to 18, wherein setting the status signal to indicate whether or not the detected occurrence of like respective edges was within the predetermined range comprises: setting the status signal to a first value in response to a time difference between the detected occurrence of like respective edges of the reference clock and the feedback clock being less than a phase threshold. Example 20: The method of any one of examples 14 to 19, wherein setting the status signal to indicate whether or not the detected occurrence of like respective edges was within the predetermined range comprises: setting the status signal to a second value in response to a time difference between the detected occurrence of like respective edges of the reference clock and the feedback clock being greater than or equal to a phase threshold. Example 21: The method of any one of examples 14 to 120, wherein samples of the phase detector status signal are obtained; lock status information is decoded from samples of the phase detector status signal; and the lock status of the clock tracking circuit is determined based at least in part on the decoded lock status information.

[0238] Although the present disclosure has been described herein with reference to certain illustrated examples, those of ordinary skill in the art will recognize and understand that the present invention is not limited thereto. Rather, many additions, omissions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below, along with their legal equivalents. Furthermore, features of one example may be combined with features of another example and still be included within the scope of the invention contemplated by the inventor. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 375,351

[0001] US 63 / 375,348

[0001]

Claims

[1] Facility comprising: a phase detector, wherein a status signal of the phase detector is based at least in part on a phase relationship between a reference clock and a feedback clock, the feedback clock being generated by a clock tracking circuit to track the reference clock; a digital discriminator for sampling the status signal of the phase detector; and a logic circuit for determining a disable status of the clock tracking circuit based at least in part on samples of the phase detector status signal. [2] The device of claim 1, wherein the phase detector sets the status signal based at least in part on a phase threshold and the phase relationship between the reference clock and the feedback clock. [3] Device according to claim 2, wherein a value of the phase threshold is adjustable. [4] The device of claim 1, wherein the phase detector: setting the status signal to a first value at least in part in response to determining that a certain difference amount is greater than a phase threshold. [5] The device of claim 1, wherein the phase detector: setting the phase detector status signal to a second value, at least in part in response to determining that a certain difference amount is equal to or less than a phase threshold, wherein the second value is different from a first value. [6] The device of claim 1, wherein the logic circuit for determining the lock status of the clock tracking circuit: Decodes information on the lock status of samples of the status signal of a phase detector; and determines the lock status of the clock tracking circuit based at least in part on the decoded lock status information. [7] The device of claim 1, wherein the logic circuit sets a lock status signal to a first value to indicate a lock state and sets the lock status signal to a second value to indicate that a lock status does not exist. [8] Device according to claim 1, wherein the phase detector: to detect the occurrence of identical respective edges of the reference clock and the feedback clock; and sets the status signal to indicate whether the detected occurrence of identical respective edges was within a predetermined range or not. [9] Device according to claim 8, wherein the phase detector: sets the status signal to a first value in response to a time difference between the detected occurrence of equal respective edges of the reference clock and the feedback clock being less than a phase threshold. [10] Device according to claim 8, wherein the phase detector: sets the status signal to a second value in response to a time difference between the detected occurrence of equal respective edges of the reference clock and the feedback clock being greater than or equal to a phase threshold. [11] The device of claim 1, wherein the digital discriminator includes a decimator for decimating values of the status signal. [12] The device of claim 1, wherein the digital discriminator includes an interpolator for interpolating values based on the status signal. [13] The device of claim 1, wherein the digital discriminator includes a digital filter to block a status signal indicative of a transient phase error and to pass a status signal indicative of a steady-state phase error. [14] Method comprising: Setting a status signal of a phase detector, wherein the status signal of the phase detector is set based at least in part on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock; and Generating a signal indicative of a lock status of the clock tracking circuit based at least in part on the phase detector status signal. [15] A method according to claim 14, comprising: Determining whether or not the phase relationship between the reference clock and the feedback clock is within a threshold range; and Setting the phase detector status signal based at least in part on the determination. [16] A method according to claim 14, comprising: Setting the phase detector status signal to a first value, at least in part in response to determining that a certain difference amount is greater than a phase threshold. [17] A method according to claim 14, comprising: Setting the phase detector status signal to a second value, at least in part in response to determining that a certain difference amount is equal to or less than a phase threshold, wherein the second value is different from a first value. [18] A method according to claim 14, detecting the occurrence of equal respective edges of the reference clock and the feedback clock; and setting the status signal to indicate whether or not the detected occurrence of equal respective edges was within a predetermined range. [19] The method of claim 18, wherein setting the status signal to indicate whether or not the detected occurrence of the same respective edges was within the predetermined range comprises: Setting the status signal to a first value in response to a time difference between the detected occurrence of equal respective edges of the reference clock and the feedback clock being less than a phase threshold. [20] The method of claim 18, wherein setting the status signal to indicate whether or not the detected occurrence of the same respective edges was within the predetermined range comprises: Setting the status signal to a second value in response to a time difference between the detected occurrence of equal respective edges of the reference clock and the feedback clock being greater than or equal to a phase threshold. [21] Method according to claim 14, Obtaining samples of the phase detector status signal; Information about the lock status is decoded from samples of the phase detector status signal; and Determining the lock status of the clock tracking circuit based at least in part on the decoded lock status information.

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