APPARATUS, SYSTEM, AND METHOD FOR COMPILING CODE FOR A PROCESSOR

Abstract

For example, a compiler may be configured to identify a first masked memory access operation based on source code, wherein the first masked memory access operation is based on a first mask expression comprising one or more mask sheets; determine a second masked memory access operation by reconfiguring the first masked memory access operation based on an identified mask sheet of the one or more mask sheets, wherein the second masked memory access operation is based on a second mask expression that is logically simplified compared to the first mask expression; and generate target code based on compiling the source code, wherein the target code is based on the second masked memory access operation.

Description

CROSS-REFERENCE

[0001] This application claims the benefit of and priority from U.S. Provisional Patent Application No. 63 / 415,309, entitled "APPARATUS, SYSTEM, AND METHOD OF VECTOR PROCESSING," filed October 12, 2022, the entire disclosure of which is incorporated herein by reference. BACKGROUND

[0002] A compiler can be configured to compile source code into target code that is configured for execution by a processor.

[0003] It is necessary to provide a technical solution to support efficient processing functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For simplicity and clarity, the elements depicted in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others to clarify the illustration. Furthermore, reference numbers may be repeated in the figures to indicate corresponding or analogous elements. The figures are listed below. Fig. 1 is a schematic block diagram representation of a system according to some example aspects. Fig. 2 is a schematic representation of a compiler according to some exemplary aspects. Fig. 3 is a schematic diagram of a vector processor according to some example aspects. Fig. 4 is a schematic flowchart representation of a method of compiling code for a processor, according to some example aspects. Fig. 5 is a schematic representation of a product according to some exemplary aspects.

[0005] In the following detailed description, numerous specific details are provided to provide a thorough understanding of some aspects. However, those skilled in the art will understand that some aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, units, and / or circuits have not been described in detail to avoid obscuring the discussion.

[0006] Some sections of the following detailed description are presented in the form of algorithms and symbolic representations of operations on data bits or binary digital signals in a memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing field to communicate the content of their work to others skilled in the art.

[0007] An algorithm is considered here and generally to be a self-consistent sequence of actions or operations that lead to a desired result. This includes physical manipulations of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has sometimes been found convenient, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be understood, however, that all these and similar expressions are to be associated with the corresponding physical quantities and are merely convenient labels for these quantities.

[0008] Terms such as "processing", "calculating", "determining", "setting", "analyzing", "testing" or the like may refer to the operation(s) and / or process(es) of a computer, computer platform, computer system, or other electronic computing device that manipulates and / or converts data represented as physical (e.g., electronic) quantities in the registers and / or memory of the computer into other data similarly represented as physical quantities in the registers and / or memory of the computer or other information storage medium that can store instructions for performing operations and / or processes.

[0009] The terms "plurality" and "a plurality," as used herein, include, for example, "several" or "two or more." For example, "a plurality of elements" includes two or more elements.

[0010] References to "an aspect," "an aspect," "an exemplary aspect," "various aspects," etc., indicate that the aspect(s) so described may include a particular feature, structure, or property, but not every aspect necessarily includes that particular feature, structure, or property. Furthermore, the repeated use of the phrase "in an aspect" does not necessarily refer to the same aspect, although it may.

[0011] As used herein, the use of the ordinal adjectives "first," "second," "third," etc., to describe a common object, unless otherwise noted, merely indicates that different instances of like objects are being referred to and is not intended to imply that the objects so described must be in any particular sequence, whether temporally, spatially, in rank, or in any other way.

[0012] For example, some aspects may take the form of a completely hardware-related aspect, a completely software-related aspect, or an aspect that includes both hardware and software elements. Some aspects may be implemented in software, including, but not limited to, firmware, resident software, microcode, or the like.

[0013] Furthermore, some aspects may take the form of a product in the form of a computer program accessible from a computer-usable or computer-readable medium that provides program code for use by or in connection with a computer or any instruction execution system. For example, a computer-usable or computer-readable medium may be or include a device that can contain, store, communicate, transmit, or transport the program for use by or in connection with the instruction execution system, device, or apparatus.

[0014] In some example aspects, the medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or apparatus) or transmission medium.

[0015] In some example aspects, a data processing system capable of storing and / or executing program code may include at least one processor coupled directly or indirectly to storage elements, for example, via a system bus. The storage elements may include, for example, local memory used during actual execution of the program code, mass storage, and cache memories that may provide temporary storage of at least a portion of the program code to reduce the number of times code is retrieved from mass storage during execution.

[0016] In some example aspects, input / output or I / O devices (including, but not limited to, keyboards, displays, pointing devices, etc.) may be coupled to the system either directly or through intermediate I / O control devices. In some example aspects, network adapters may be coupled to the system to couple the computing system to other computing systems or remote printers or storage devices, for example, through intermediate private or public networks. In some example aspects, modems, cable modems, and Ethernet cards are exemplary examples of types of network adapters. Other suitable components may also be used.

[0017] Some aspects may be used in connection with various devices and systems, such as a computing unit, a computer, a mobile computer, a non-mobile computer, a server computer, or the like.

[0018] As used herein, the term "circuitry" may refer to, be a part of, or include an application-specific integrated circuit (ASIC), an integrated circuit, an electronic circuit, a processor (shared, dedicated, or in a group), and / or memory (shared, dedicated, or in a group) executing one or more software or firmware programs, combinational logic circuitry, and / or other suitable hardware components that provide the described functionality. In certain aspects, some functions associated with the circuitry may be implemented by one or more software or firmware modules. In some aspects, the circuitry may include logic operable at least partially in hardware.

[0019] The term "logic" may, for example, refer to computational logic embedded in the circuitry of a computing device and / or computational logic stored in a memory of a computing device. For example, a processor of the computing device may access the logic to execute the computational logic to perform computational functions and / or operations. For example, the logic may be embedded in various types of memory and / or firmware, e.g., in silicon blocks of various chips and / or processors. Logic may be included in and / or implemented as part of various circuits, e.g., in processor circuitry, control circuitry, and / or the like. In one example, the logic may be embedded in volatile memory and / or non-volatile memory, including random access memory, read-only memory, programmable memory, magnetic memory, flash memory, persistent memory, and the like.Logic may be executed by one or more processors using memory, such as registers, read-only memory, buffers, and / or the like, coupled to the one or more processors, such as as required to execute the logic.

[0020] It will now Fig. 1, which schematically illustrates a block diagram of a system 100 according to some example aspects.

[0021] As in Fig. 1, the system 100 may include a computing unit 102 according to some example aspects.

[0022] In some example aspects, device 102 may be implemented using suitable hardware components and / or software components, such as processors, controllers, memory devices, storage devices, input devices, output devices, communication devices, operating systems, applications, or the like.

[0023] In some example aspects, device 102 may include, for example, a computer, a mobile computing device, a non-mobile computing device, a laptop, a notebook, a tablet computer, a handheld computer, a personal computer (PC), or the like.

[0024] For example, in some example aspects, device 102 may include one or more processors 191, an input unit 192, an output unit 193, a memory unit 194, and / or a storage unit 195. Device 102 may optionally include other suitable hardware and / or software components. In some example aspects, some or all components of one or more devices 102 may be enclosed in a common housing or package and connected to one another or connected in one operation via one or more wired or wireless connections. In other aspects, components of one or more devices 102 may be distributed across multiple or separate devices.

[0025] In some example aspects, processor 191 may include, for example, a central processing unit (CPU), a digital signal processor (DSP), one or more processor cores, a single-core processor, a dual-core processor, a multi-core processor, a microprocessor, a host processor, a controller, a plurality of processors or controllers, a chip, a microchip, one or more circuits, a circuit assembly, a logic unit, an integrated circuit (IC), an application-specific integrated circuit (ASIC), or other suitable general-purpose or special-purpose processor or controller. Processor 191 may execute instructions, for example, from an operating system (OS) of a device 102 and / or from one or more suitable applications.

[0026] In some example aspects, input device 192 may include, for example, a keyboard, keypad, mouse, touchscreen, touchpad, trackball, stylus, microphone, or other suitable pointing or input device. Output device 193 may include, for example, a monitor, screen, touchscreen, flat panel display, light-emitting diode (LED) display, liquid crystal display (LCD) display, plasma display, one or more speakers or headphones, or other suitable output devices.

[0027] In some example aspects, memory 194 includes, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), flash memory, volatile memory, non-volatile memory, cache memory, a buffer, short-term storage, long-term storage, or other suitable storage devices. Storage device 195 may include, for example, a hard drive, a solid-state drive (SSD), or other suitable removable or non-removable storage devices. Memory device 194 and / or storage device 195 may, for example, store data processed by device 102.

[0028] In some example aspects, device 102 may be configured to communicate with one or more other devices over at least one network 103, e.g., a wireless and / or wired network.

[0029] In some example aspects, the network 103 may include a wired network, a local area network (LAN), a wireless network, a wireless LAN (WLAN), a radio network, a cellular network, a WiFi network, an IR network, a Bluetooth (BT) network, and the like.

[0030] In some example aspects, device 102 may be configured to perform one or more operations, modules, processes, methods, and / or the like, e.g., as described herein.

[0031] In some example aspects, the device 102 may include a compiler 160 that may be configured to generate target code 115, for example, based on source code 112, as described below.

[0032] In some example aspects, the compiler 160 may be configured to translate the source code 112 into the target code 115, as described below.

[0033] In some example aspects, compiler 160 may include or be implemented as software, a software module, an application, a program, a subroutine, instructions, an instruction set, computational code, words, values, symbols, and / or the like.

[0034] In some example aspects, the source code 112 may include computer code written in a source language.

[0035] In some example aspects, the source language may include a programming language. For example, the source language may include a high-level programming language, such as the C programming language, the C++ programming language, and / or the like.

[0036] In some example aspects, the target code 115 may include computer code written in a target language.

[0037] In some exemplary respects, the target language may include a low-level language such as assembly language, object code, machine code, or the like.

[0038] In some example aspects, the target code 115 may include one or more object files that may, for example, create and / or form an executable program.

[0039] In some example aspects, the executable program may be configured to run on a target computer. For example, the target computer may include particular computer hardware, a particular machine, and / or a particular operating system.

[0040] In some example aspects, the executable program may be configured to execute on a processor 180, as described below.

[0041] In some example aspects, processor 180 may include a vector processor 180, e.g., as described below. In other aspects, processor 180 may include any other type of processor.

[0042] Some exemplary aspects are described herein with respect to a compiler, e.g., compiler 160, configured to compile source code 112 into target code 115 configured to be executed by a vector processor 180, as described below. In other aspects, a compiler, e.g., compiler 160, configured to compile source code 112 into target code 115 configured to be executed by any other type of processor 180.

[0043] In some example aspects, processor 180 may be implemented as part of device 102.

[0044] In other respects, processor 180 may be implemented as part of any other device, e.g., separate from device 102.

[0045] In some example aspects, the vector processor 180 (also referred to as an "array processor") may include a processor that may be configured to process an entire vector into one instruction, e.g., as described below.

[0046] From other perspectives, the executable program may be configured to run on any other additional or alternative processor type.

[0047] In some example aspects, vector processor 180 may be designed to support high-performance image and / or vector processing. For example, vector processor 180 may be configured to process 1 / 2 / 3 / 4D arrays of fixed-point data and / or floating-point arrays very quickly and / or efficiently.

[0048] In some example aspects, vector processor 180 may be configured to process arbitrary data, e.g., structures with pointers to structures. For example, vector processor 180 may include a scalar processor to compute the non-vector data, e.g., assuming the non-vector data is minimal.

[0049] In some example aspects, compiler 160 may be implemented as a local application executed by device 102. For example, memory unit 194 and / or storage unit 195 may store instructions leading to compiler 160, and / or processor 191 may be configured to execute the instructions leading to compiler 160 and / or perform one or more computations and / or processes of compiler 160, e.g., as described below.

[0050] In other aspects, the compiler 160 may include a remote application executed by any suitable computer system, e.g., a server 170.

[0051] In some example aspects, server 170 may include at least one of a remote server, a web-based server, a cloud server, and / or any other server.

[0052] In some example aspects, server 170 may include a suitable memory and / or storage device 174 on which instructions leading to compiler 160 are stored and a suitable processor 171 to execute the instructions, e.g., as described below.

[0053] In some example aspects, the compiler 160 may include a combination of a remote application and a local application.

[0054] In one example, compiler 160 may be downloaded and / or received by the user of device 102 from another computer system, e.g., a server 170, so that compiler 160 may be executed locally by users of device 102. For example, the instructions may be received and stored, e.g., temporarily in memory or a suitable short-term storage or buffer of device 102, e.g., before being executed by processor 191 of device 102.

[0055] In another example, compiler 160 may include a client module executed locally by device 102 and a server module executed by server 170. For example, the client module may include and / or be implemented as a local application, a web application, a website, a web client, e.g., a Hypertext Markup Language (HTML) web application, or the like.

[0056] For example, one or more first operations of compiler 160 may be performed locally, such as by device 102, and / or one or more second operations of compiler 160 may be performed remotely, such as by server 170.

[0057] In other aspects, compiler 160 may include or be implemented by any other suitable arrangement and / or scheme of computing units.

[0058] In some example aspects, the system 100 may include an interface 110, e.g., a user interface, to interface between a user of the device 102 and one or more elements of the system 100, e.g., the compiler 160.

[0059] In some example aspects, the interface 110 may be implemented using any suitable hardware and / or software components, such as processors, controllers, memory devices, storage devices, input devices, output devices, communication devices, operating systems, and / or applications.

[0060] In some aspects, the interface 110 may be implemented as part of a suitable module, system, device, or component of the system 100.

[0061] From other perspectives, the interface 110 may be implemented as a separate element of the system 100.

[0062] In some example aspects, interface 110 may be implemented as part of device 102. For example, interface 110 may be connected to and / or included as part of device 102.

[0063] For example, interface 110 may be implemented as middleware and / or as part of any suitable application of device 102. For example, interface 110 may be implemented as part of compiler 160 and / or as part of an operating system of device 102.

[0064] In some example aspects, interface 110 may be implemented as part of server 170. For example, interface 110 may be connected to and / or included as part of server 170.

[0065] In one example, interface 110 may include or be a part of a web-based application, a website, a web page, a plug-in, an ActiveX control, a rich content component, such as a Flash or Shockwave component, or the like.

[0066] In some example aspects, the interface 110 may, for example, be connected to and / or include a gateway (GW) 113 and / or an application programming interface (API) 114, for example, to communicate information and / or communications between elements of the system 100 and / or to one or more other, e.g., internal or external, parties, users, applications, and / or systems.

[0067] In some aspects, the interface 110 may include any suitable graphical user interface (GUI) 116 and / or any other suitable interface.

[0068] In some example aspects, the interface 110 may be configured to receive the source code 112, for example, from a user of the device 102, e.g., via the GUI 116 and / or the API 114.

[0069] In some example aspects, the interface 110 may be configured to transfer the source code 112 to, for example, the compiler 160 to generate the target code 115, for example, as described below.

[0070] It will now Fig. 2, which schematically illustrates a compiler 200 according to some exemplary aspects. For example, the compiler 160 ( Fig. 1) implement one or more elements of the compiler 200 and / or perform one or more operations and / or functionalities of the compiler 200.

[0071] In some exemplary aspects, as in Fig. 2, the compiler 200 may be configured to generate a target code 233, for example, by compiling a source code 212 in a source language.

[0072] In some exemplary aspects, as in Fig. 2, the compiler 200 may include a front end 210 configured to receive and parse the source code 212 in the source language.

[0073] In some example aspects, the front end 210 may be configured to generate intermediate code 213, for example, based on the source code 212.

[0074] In some example aspects, intermediate code 213 may include a degraded representation of source code 212.

[0075] In some example aspects, front-end 210 may be configured to perform, for example, lexical analysis, syntax analysis, semantic analysis, and / or other additional or alternative type of analysis of source code 212.

[0076] In some example aspects, the front-end 210 may be configured to identify errors and / or problems with a result of analyzing the source code 212. For example, the front-end 210 may be configured to generate error information, e.g., including error and / or warning messages that may, for example, identify a location in the source code 212 where an error or problem is detected.

[0077] In some exemplary aspects, as in Fig. 2, compiler 200 may include a middle end 220 configured to receive and process intermediate code 213 and generate customized, e.g., optimized, intermediate code 223.

[0078] In some example aspects, the middle end 220 may be configured to perform one or more adjustments, e.g., optimizations, to the intermediate code 213 to generate, for example, the adjusted intermediate code 223.

[0079] In some example aspects, the middle end 220 may be configured to perform one or more optimizations to the intermediate code 213, for example, regardless of the type of target computer, to execute the target code 233.

[0080] In some exemplary aspects, the middle end 220 may be implemented to support the use of the optimized intermediate code 223, for example, for different machine types.

[0081] In some example aspects, the middle end 220 may be configured to optimize the intermediate representation of the intermediate code 223, for example, to improve the performance and / or quality of the generated target code 233.

[0082] In some example aspects, the one or more optimizations of the intermediate code 213 may include, for example, inline expansion, dead code elimination, constant transfer, loop conversion, parallelization, and / or the like.

[0083] In some exemplary aspects, as in Fig. 2, the compiler 200 may include a backend 230 configured to receive and process the customized intermediate code 213 and generate the target code 233 based on the customized intermediate code 213.

[0084] In some example aspects, the backend 230 may be configured to perform one or more operations and / or processes that may be specific to the target computer to execute the target code 233. For example, the backend 230 may be configured to process the optimized intermediate code 213 by applying analysis, transformation, and / or optimization operations to the customized intermediate code 213, which may be configured, for example, based on the target computer to execute the target code 233.

[0085] In some example aspects, the one or more analysis, conversion, and / or optimization operations applied to the adapted intermediate code 213 may include, for example, resource and storage decisions, e.g., register allocation, instruction scheduling, and / or the like.

[0086] In some example aspects, the target code 233 may include target-dependent assembly code that may be specific to the target computer and / or a target operating system of the target computer that is to execute the target code 233.

[0087] In some example aspects, the target code 233 may include target-dependent assembly code for a processor, e.g., vector processor 180 ( Fig. 1).

[0088] In some example aspects, compiler 200 may include a Vector Micro-Code Processor (VMP) compiler for Open Computing Language (OpenCL), e.g., as described below. In other aspects, compiler 200 may include or be implemented as part of any other vector processor compiler.

[0089] In some example aspects, the VMP OpenCL compiler may include a Low Level Virtual Machine (LLVM)-based (LLVM-based) compiler that may be configured according to an LLVM-based compilation scheme, for example, to lower OpenCL C code to VMP accelerator assembly code suitable for execution by vector processor 180, for example ( Fig. 1).

[0090] In some example aspects, compiler 200 may include one or more technologies that may be required to compile code into a format suitable for a VMP architecture, e.g., in addition to open source LLVM compiler passes.

[0091] In some exemplary aspects, FE 210 may be configured to parse and translate the OpenCL C code, e.g., through an Abstract Syntax Tree (AST), into, for example, an LLVM Intermediate Representation (IR).

[0092] In some exemplary aspects, compiler 200 may include a dedicated API, for example, to identify a correct pattern for compiler pattern matching suitable for, for example, the VMP. For example, the VMP may be configured as a complex instruction set machine (CISC) implementing a very complex instruction set architecture (ISA) that may be difficult to address from standard C code. According to this case, compiler pattern matching may not easily identify the correct pattern, and in this case, the compiler may require a dedicated API.

[0093] In some exemplary aspects, FE 210 may implement one or more built-in vendor extensions that may, for example, target VMP-specific ISAs, in addition to standard OpenCL integrations that may be optimized for a VMP machine.

[0094] In some exemplary aspects, FE 210 may be configured to implement OpenCL structures and / or work item functions.

[0095] In some example aspects, ME 220 may be configured to process LLVM IR code, which may, for example, be general and target-independent, although it may include one or more hooks for specific target architectures.

[0096] In some example aspects, ME 220 may perform one or more custom passes, for example, to support the VMP architecture as described below.

[0097] In some example aspects, ME 220 may be configured to perform one or more CFG (Control Flow Graph) linearization operations, as described below.

[0098] In some example aspects, CFG linearization may be configured to linearize the code, for example, by converting if statements to selection patterns, if the VMP vector code does not support standard control flow.

[0099] In an example, ME 220 can receive a specific code, e.g. as follows: If (x > 0) { A = A + 5;} else { B = B * 2;}

[0100] According to this example, ME 220 can be configured to apply CFG linearization to the given code, e.g., as follows: tmpA=A+5; tmpB=B*2; mask=x>0; A=Select mask,tmpA, A B=Select not mask,tmpB, B Example (1)

[0101] In some example aspects, ME 220 may be configured to perform one or more auto-vectorization analysis operations, e.g., as described below.

[0102] In some example aspects, the auto-vectorization analysis may be configured to vectorize a given code, e.g., automatically vectorize it to utilize the vector capabilities of the VMP.

[0103] In some example aspects, ME 220 may be configured to perform auto-vectorization analysis, e.g., to vectorize code in scalar form. For example, some or all of the auto-vectorization analysis operations may not be performed, e.g., if the code is already provided in vectorized form.

[0104] In some exemplary aspects, e.g., in some use cases and / or scenarios, a compiler may not always be able to automatically vectorize code, e.g., due to data dependencies between loop iterations.

[0105] In one example, ME 220 can receive a specific code, e.g., as follows: char* a,b,c; for (int i=0; i < 2048; i++) { a[i]=b[i]+c[i];}

[0106] According to this example, ME 220 can be configured to perform CFG auto-vectorization analysis by applying a first conversion, e.g., as follows: char* a,b,c; for (int i=0; i < 2048; i+=32) { a[i.i+31]=b[i...i+31]+c[i...i+31];} Example (2a)

[0107] For example, ME 220 may be configured to perform CFG auto-vectorization analysis by applying a second transformation, e.g., after the first transformation, e.g., as follows: char32* a,b,c; for (int i=0; i < 64; i++) { a[i]=b[i]+c[i];} Example (2b)

[0108] In some example aspects, ME 220 may be configured to perform one or more Scratch Pad Memory Loop Access Analysis (SPMLAA) operations, such as described below.

[0109] In some exemplary respects, the SPMLAA may define processing blocks (PBs), such as those that should later be outlined and compiled for VMP.

[0110] In some example aspects, the processing blocks may include accelerated loops that may be executed by the vector unit of the VMP.

[0111] In some example aspects, a PB, e.g., each PB, may include memory references. For example, some or all memory accesses may reference local memory banks.

[0112] In some example aspects, the VMP may enable access to memory banks via AGUs, e.g., AGUs 320 as described below with reference to Fig. 3, and scatter-gather units (SG).

[0113] In some exemplary aspects, the AGUs may be preconfigured, e.g., before the execution of a loop. For example, the number of loop iterations may be calculated, e.g., before executing a processing block.

[0114] In some example aspects, image references, e.g., some or all of the image references, may be created at this stage, and steps and offsets may be calculated, e.g., per dimension for each reference.

[0115] In some example aspects, ME 220 may be configured to perform one or more AGU planner analysis operations, e.g., as described below.

[0116] In some example aspects, the AGU scheduler analysis may include an iterator assignment that may cover image references, e.g., all image references, from the entire processing block.

[0117] In some example aspects, an iterator may cover a single reference or a group of references.

[0118] In some example aspects, one or more references to memory may be merged and / or the same access may be reused through shuffle instructions and / or values ​​read from previous iterations may be stored.

[0119] In some example aspects, other references to memory, such as those without a linear access pattern, may be processed using a scatter-gather (SG) unit, but this may result in a performance penalty because indexes and / or masks may need to be maintained.

[0120] In some example aspects, a plan may be configured as an array of iterators within a processing block. For example, a processing block may theoretically have multiple plans.

[0121] In some exemplary aspects, the AGU planner analysis may be configured to create all possible plans for all PBs and select a combination, e.g., a best combination, from all valid combinations.

[0122] In some exemplary aspects, the total number of iterators in a valid combination may be restricted, e.g., to not exceed the number of available AGUs on a VMP.

[0123] In some example aspects, one or more parameters, e.g., including step size, width, and / or base, may be defined for an iterator, e.g., for each iterator as part of the AGU planner analysis. For example, min-max ranges may be defined for the iterators in a dimension, e.g., in each dimension, e.g., as part of the AGU planner analysis.

[0124] In some example aspects, the AGU scheduler analysis may be configured to track and evaluate a reference to memory, e.g., any reference to memory to an image, e.g., to understand its access pattern.

[0125] In an example according to Examples 2a / 2b, the image “a”, which is the base address, can be accessed with steps of 32 bytes for 64 iterations.

[0126] In some example aspects, the LLVM may include a scalar evaluation analysis (SCEV) that may compute an access pattern, e.g., to understand each reference to images.

[0127] In some exemplary aspects, ME 220 may utilize masking capabilities of the AGUs, e.g., to avoid maintaining an induction variable that may degrade performance.

[0128] In some example aspects, ME 220 may be configured to perform one or more rewrite analysis operations, e.g., as described below.

[0129] In some example aspects, the rewrite analysis may be configured to transform the code of a processing block, e.g., while setting iterators and / or changing memory access instructions.

[0130] In some exemplary aspects, setting the iterators, e.g., all iterators, in IR can be implemented in target-specific intrinsic functions. For example, setting the iterators can be in a pre-header of an outermost loop.

[0131] In some example aspects, the rewrite analysis may include loop perfection analysis, as described below.

[0132] In some exemplary aspects, the code can be compiled with the goal that essentially all calculations should be performed within the innermost loop.

[0133] For example, loop perfection analysis can lift instructions, such as moving an operation that is performed after a final iteration of the loop into a loop.

[0134] For example, loop perfection analysis can lower instructions, such as moving an operation that is performed before a first iteration of the loop into a loop.

[0135] For example, loop perfection analysis can raise and / or lower instructions, e.g., such that essentially all instructions are moved from outer loops to the innermost loops.

[0136] For example, the loop perfection analysis can be configured to provide a technical solution to support VMP iterators, e.g., to work only with perfectly nested loops.

[0137] For example, loop perfection analysis may lead to a situation where there are no instructions between the "for" statements that make up the loop, e.g., to support VMP iterators, which cannot emulate such cases.

[0138] In some example aspects, the loop perfection analysis may be configured to convert a nested loop into a single summarized loop.

[0139] In one example, ME 220 can receive a specific code, e.g., as follows: for (int i = 0; i < N; i++) { int sum = 0; for (int j = 0; j < M; j++) { sum += a[j + stride * i]; res[i] = sum;}

[0140] According to this example, ME 220 can be configured to perform loop perfection analysis to combine the nested loop in the code into a single combined loop, for example, as follows: for (int k = 0; k < N * M; k++) { sum = (k % M == 0 ? 0 : sum); sum += a[k % M + stride * (k / M)]; res[k / M] = sum;} Example (3)

[0141] In some example aspects, ME 220 may be configured to perform one or more vector loop contour analysis operations, as described below.

[0142] In some example aspects, the vector loop outline analysis may be configured to split code between a scalar subsystem and a vector subsystem, e.g., vector processing block 310 ( Fig. 3) and scalar processor 330 ( Fig. 3), as described below with reference to Fig. 3 described.

[0143] In some example aspects, the VMP accelerator may include the scalar and / or vector subsystems, e.g., as described below. For example, each of the subsystems may have different compute units / processors. According to

[0024] , scalar code may be compiled on a scalar compiler, e.g., an SSC compiler, and / or accelerated vector code may be executed on the VMP vector processor.

[0144] In some exemplary aspects, the vector loop outline analysis may be configured to create a separate function for a loop body of the accelerated vector code. These functions may, for example, be marked for VMP and / or continue to the VMP backend, while the rest of the code can be compiled by the SSC compiler.

[0145] In some example aspects, one or more parts of a vector loop, such as vector unit configuration and / or vector register initialization, may be performed by a scalar unit. However, these parts may be performed at a later stage, such as by backpatching into the scalar code, since the scalar code may still be in LLVM IR prior to processing by the SSC compiler.

[0146] In some exemplary aspects, BE 230 may be configured to translate the LLVM IR into machine instructions. For example, BE 230 may not be target-agnostic and may be familiar with target-specific architecture and optimizations, e.g., compared to ME 220, which may be target-specific architecture agnostic.

[0147] In some example aspects, BE 230 may be configured to perform one or more analyses that may be specific to a target computer, such as a VMP computer, to which the code is lowered, although BE 230 may use the common LLVM.

[0148] In some example aspects, BE 230 may be configured to perform one or more instruction descent analysis operations, e.g., as described below.

[0149] In some example aspects, the instruction descent analysis may be configured to translate LLVM IR into directed instructions (Machine IR, MIR), for example, by translating the LLVM IR into a directed acyclic graph (DAG).

[0150] In some example aspects, the DAG may undergo a legalization process of instructions, for example, based on the data types and / or VMP instructions that can be supported by a VMP HW.

[0151] In some example aspects, the instruction depression analysis may be configured to perform a pattern matching process, e.g., after the instruction legalization process, to, for example, depression of a node, e.g., each node, in the DAG, e.g., into a VMP-specific machine instruction.

[0152] In some example aspects, the instruction descent analysis may be configured to generate the MIR, e.g., after the pattern matching process.

[0153] In some example aspects, the instruction descent analysis may be configured to descent the instruction according to the machine application binary interface (ABI) and / or calling conventions.

[0154] In some example aspects, BE 230 may be configured to perform one or more unit balancing analysis operations, e.g., as described below.

[0155] In some exemplary aspects, the unit balancing analysis may be configured to balance instructions between VMP compute units, e.g., data processing units 316 ( Fig. 3), as described below with reference to Fig. 3, be balanced.

[0156] In some exemplary aspects, the unit balancing analysis may be familiar with some or all of the available arithmetic conversions and / or perform conversions according to an optimal algorithm.

[0157] In some example aspects, BE 230 may be configured to perform one or more modulo scheduler (pipelined) analysis operations, e.g., as described below.

[0158] In some example aspects, the pipeliner may be configured to schedule the instructions according to one or more constraints, such as data dependency, resource constraints, and / or other constraints, for example, using Swing Modulo Scheduling (SMS) heuristics and / or other additional and / or alternative heuristics.

[0159] In some example aspects, the pipeliner may be configured to create a schedule for a group of Very Long Instruction Word (VLIW) instructions, such as an initiation interval (II), that the program traverses, for example, during a steady state.

[0160] In some example aspects, a performance metric, which may be based on a number of cycles that a typical loop can execute, may be measured, for example, as follows: (Size of input data in bytes) * II / (bytes consumed / generated per iteration)

[0161] In some exemplary aspects, the pipeliner may attempt to minimize II, e.g., as much as possible, to improve performance.

[0162] In some example aspects, the pipeliner may be configured to calculate a minimum II and create a schedule accordingly. For example, if the pipeliner fails to meet the schedule, it may attempt to increase the II and retry the schedule, e.g., until a predefined II threshold is exceeded.

[0163] In some example aspects, BE 230 may be configured to perform one or more register mapping analysis operations, e.g., as described below.

[0164] In some example aspects, the register allocation analysis may be configured to attempt to allocate a register in an efficient, e.g., optimal, manner.

[0165] In some example aspects, the register mapping analysis may assign values ​​to bypass vector registers, general purpose vector registers, and / or scalar registers.

[0166] In some example aspects, the values ​​may include private variables, constants, and / or values ​​that are rotated across iterations.

[0167] In some exemplary aspects, the register mapping analysis may implement an optimal heuristic that matches one or more VMP register file (regfile) constraints. For example, in some use cases, the register mapping analysis may not use a standard LLVM register mapping.

[0168] In some exemplary aspects, the register mapping analysis may fail in some cases, which may mean that the loop cannot be compiled. According to this case, the register mapping analysis may implement a retry mechanism that returns to the modulo scheduler and attempts to reschedule the loop, e.g., with an increased initiation interval. For example, increasing the initiation interval may reduce register pressure and / or aid compilation of the vector loop, e.g., in many cases.

[0169] In some example aspects, BE 230 may be configured to perform one or more SSC configuration analysis operations, e.g., as described below.

[0170] In some example aspects, the SSC configuration analysis may be configured to determine a configuration for running the kernel, such as the AGU configuration.

[0171] In some exemplary aspects, the SSC configuration analysis may be performed at a later stage, for example, due to configurations computed after legalization, register mapping analysis, and / or modulo scheduling analysis.

[0172] In some example aspects, the SSC configuration analysis may include a zero-overhead loop (ZOL) mechanism in the vector loop. For example, the ZOL mechanism may configure a loop execution count based on an access pattern of memory references in the loop, for example, to avoid executing instructions that check the loop exit condition on each iteration.

[0173] In some example aspects, a VMP compilation flow may include one or more steps, e.g., some steps that may be called during the compilation flow in a test library (testlib), such as a wrapper script for compilation, execution, and / or program testing. These steps may, for example, be executed outside of the LLVM compiler.

[0174] In some example aspects, a PCB Hardware Description Language (PHDL) simulator may be implemented to perform one or more roles of an assembler, encoder, and / or linker.

[0175] In some exemplary aspects, compiler 200 may be configured to provide a technical solution to support robustness, allowing the compilation of a wide range of loops with hardware constraints. For example, compiler 200 may be configured to support a technical solution that does not generate verification errors.

[0176] In some exemplary aspects, compiler 200 may be configured to provide a technical solution that supports programmability, allowing a user to express code in various ways that can be correctly compiled for the VMP architecture.

[0177] In some example aspects, compiler 200 may be configured to provide a technical solution to support an enhanced user experience, which may enable the user to debug and / or profile code. For example, the enhanced user experience may provide informative error messages, reporting tools, and / or a profiler.

[0178] In some example aspects, compiler 200 may be configured to provide a technical solution to support improved performance, e.g., to optimize VMP assembly code and / or iterator accesses, which may result in faster execution. For example, improved performance may be achieved by high utilization of the compute units and leveraging their complex CISC.

[0179] It will now Fig. 3, which schematically illustrates a vector processor 300 according to some example aspects. For example, the vector processor 180 ( Fig. 1) implement one or more elements of the vector processor 300 and / or perform one or more operations and / or functionalities of the vector processor 300.

[0180] In some example aspects, the vector processor 300 may include a vector microprocessor (VMP).

[0181] In some example aspects, the vector processor 300 may include a WVM (Wide Vector Machine) that supports, for example, Very Long Instruction Word (VLIW) and / or Single Instruction / Multiple Data (SIMD) architectures.

[0182] In some example aspects, the vector processor 300 may be configured to provide a technical solution to support high performance for short integer types, which may be common in, for example, computer vision and / or deep learning algorithms.

[0183] In other aspects, the vector processor 300 may include any other type of vector processor and / or be configured to support other additional or alternative functionality.

[0184] In some exemplary aspects, as in Fig. 3, the vector processor 300 may include a vector processing block (vector processor) 310, a scalar processor 330, and a direct memory access (DMA) 340, as described below.

[0185] In some exemplary aspects, as in Fig. 3, the vector processing block 310 may be configured to efficiently process, for example, image data and / or vector data. For example, the vector processing block 310 may be configured to use vector calculation units, for example, to accelerate calculations.

[0186] In some example aspects, scalar processor 330 may be configured to perform scalar calculations. For example, scalar processor 330 may be used as "glue logic" for programs that include vector calculations. For example, some, e.g., even most, calculations of the programs may be performed by vector processing block 310. However, several tasks, for example, some essential tasks, e.g., scalar calculations, may be performed by scalar processor 330.

[0187] In some example aspects, the DMA 340 may be configured to interface with one or more memories in a chip that includes the vector processor 300.

[0188] In some example aspects, the DMA 340 may be configured to read inputs from main memory and / or write outputs to main memory.

[0189] In some example aspects, the scalar processor 330 and the vector processing block 310 may use respective local memories to process data.

[0190] In some exemplary aspects, as in Fig. 3, the vector processor 300 may include a fetch and decode unit 350 that may be configured to control the scalar processor 330 and / or the vector processing block 310.

[0191] In some example aspects, operations of the scalar processor 330 and / or the vector processing block 310 may be triggered by instructions stored in a program memory 352.

[0192] In some example aspects, the DMA 340 may be configured to transfer data in parallel with the execution of the program instructions in the memory 352, for example.

[0193] In some example aspects, the DMA 340 may be controlled by software, e.g., via configuration registers, rather than instructions, and accordingly may be considered a second "thread of execution" in the vector processor 300.

[0194] In some example aspects, the scalar processor 330, the vector processing block 310, and / or the DMA 340 may include one or more data processing units, such as a set of data processing units as described below.

[0195] In some example aspects, the computing units may include hardware configured to perform calculations, such as an arithmetic logic unit (ALU).

[0196] In one example, a computing device may be configured to add numbers and / or store the numbers in a memory.

[0197] In some example aspects, the computing units may be controlled by instructions encoded, for example, in program memory 352 and / or configuration registers. For example, the configuration registers may be mapped as memory and written to by the memory-to-store instructions of scalar processor 330.

[0198] In some example aspects, the scalar processor 330, the vector processing block 310, and / or the DMA 340 may include a state configuration that includes a set of registers and memories, as described below.

[0199] In some exemplary aspects, as in Fig. 3, the vector processor block 310 may include a set of vector memories 312, which may be configured, for example, to store data to be processed by the vector processor block 310.

[0200] In some exemplary aspects, as in Fig. 3, the vector processor block 310 may include a set of vector registers 314, which may be configured, for example, for use in data processing by the vector processor block 310.

[0201] In some example aspects, the scalar processor 330, the vector processing block 310, and / or the DMA 340 may be coupled to a set of memory maps.

[0202] In some example aspects, a memory map may include a set of addresses accessible by a computing device that can load and / or store data from registers and memories.

[0203] In some exemplary aspects, as in Fig. 3, the vector processing block 310 may include a plurality of address generation units (AGUs) 320, which may include addresses accessible to them, e.g., in one or more memories 312.

[0204] In some exemplary aspects, as in Fig. 3, the vector processor block 310 may include a plurality of data processing units 316, for example, as described below.

[0205] In some example aspects, computing units 316 may be configured to process instructions, e.g., including multiple numbers at a time. In one example, an instruction may include 8 numbers. In another example, an instruction may include 4 numbers, 16 numbers, or any other number of numbers.

[0206] In some example aspects, two or more computing units 316 may be used simultaneously. In one example, computing units 316 may process and execute a plurality of different instructions, e.g., three different instructions including, for example, eight numbers, during a single cycle.

[0207] In some example aspects, computing units 316 may be asymmetric. For example, first and second computing units 316 may support different instructions. For example, a first computing unit 316 may perform an addition and / or a second computing unit 316 may perform a multiplication. For example, both operations may be performed by one or more additional computing units 316.

[0208] In some example aspects, data processing units 316 may be configured to support arithmetic operations on many combinations of input and output data types.

[0209] In some example aspects, data processing units 316 may be configured to support one or more operations that may be less common. For example, processing units 316 may support operations that operate on a look-up table (LUT) of a vector processor 300 and / or any other operations.

[0210] In some example aspects, data processing units 316 may be configured to support efficient computation of nonlinear functions, histograms, and / or random data access, which may be useful, for example, for implementing algorithms such as image scaling, Hough transforms, and / or other algorithms.

[0211] For example, in some example aspects, vector memories 312 may include memory banks of 16K or other sizes that may be accessed in the same cycle.

[0212] In one example, a maximum memory access size may be 64 bits. According to this example, a peak throughput may be 256 bits, e.g., 64x4 = 256. For example, a high memory bandwidth may be implemented to utilize the computing capabilities of the data processing units 316.

[0213] In one example, two data processing units 316 can support 16 8-bit multiply-and-accumulate (MAC) operations per cycle. According to this example, the two data processing units 316 may not be useful, for example, if the input numbers are not fetched at this speed and / or there are not exactly 256 bits of input, e.g., 16 x 8 x 2 = 256.

[0214] In some example aspects, AGUs 320 may be configured to perform memory-related operations, such as loading and storing data from / to vector memory 314.

[0215] In some example aspects, AGUs 320 may be configured to calculate addresses of input and output data elements, for example, to process I / O and utilize data processing units 316, e.g., when raw bandwidth is insufficient.

[0216] In some example aspects, AGUs 320 may be configured to calculate the addresses of the input and / or output data elements, for example, based on configuration registers written by scalar processor 330, for example, before a block of vector instructions, e.g., a loop, is entered.

[0217] For example, AGUs 320 may be configured to write an image base pointer, width, height, and / or step to the configuration registers to step through an image, for example.

[0218] In some example aspects, AGUs 320 may be configured to handle addressing, e.g., all addressing, to provide a technical solution where compute units 316 do not have the burden of incrementing pointers or counters in a loop and / or the burden of checking for end-of-line conditions, e.g., to set a counter in the loop to zero.

[0219] In some exemplary aspects, as in Fig. As shown in Figure 3, AGUs 320 may include four AGUs, and accordingly, four memories 312 may be accessed in one cycle. From other perspectives, any other number of AGUs 32 may be implemented.

[0220] In some example aspects, AGUs 320 may not be "tied" to memory banks 312. For example, one AGU 320, e.g., any AGU 320, may access one memory 312, e.g., any memory 312, as long as two or more AGUs 320 do not attempt to access the same memory 312 in the same cycle.

[0221] In some example aspects, vector registers 314 may be configured to support communication between the data processing units 316 and the AGUs 320.

[0222] In one example, the total number of vector registers 314 may be 28, which may be divided into multiple subsets, e.g., based on their function. For example, a first subset of vector registers 314 may be used for input / output of all compute units 316 and / or AGUs 320; and / or a second subset of vector registers 314 may not be used for output of some operations, e.g., most operations, and may be used for one or more other operations, e.g., storing loop-invariant inputs.

[0223] In some example aspects, a compute unit 316, e.g., each compute unit 316, may include one or more registers to host an output of a most recently executed operation, which may, for example, be fed as inputs to other compute units 316. For example, these registers may "bypass" the vector registers 314 and operate faster than if these outputs were written to the first set of vector registers 314.

[0224] In some example aspects, fetch and decode unit 350 may be configured to support low-overhead vector loops, such as very low-overhead vector loops (also referred to as "zero-overhead vector loops"). In such cases, for example, it may not be necessary to check for an exit condition during execution of the vector loop.

[0225] For example, a termination condition (exit) may be signaled by an AGU 320, for example, when the AGU 320 has completed iterating over a configured memory.

[0226] For example, the fetch and decode unit 350 may exit the loop, for example, when the AGU 320 signals the termination condition.

[0227] For example, the scalar processor 330 may be used to configure the loop parameters, such as first and last instructions and / or the exit condition.

[0228] In one example, vector loops may be used, for example, in conjunction with high memory bandwidth and / or low-cost addressing to solve a control and data flow problem, for example, to provide a technical solution that enables the data processing units 316 to process data, e.g., without significant additional overhead.

[0229] In some example aspects, scalar processor 330 may be configured to provide one or more functionalities that may be complementary to those of vector processing block 310. For example, a large portion, e.g., most, of the work in a vector program may be performed by data processing units 316. For example, scalar processor 330 may be used to, for example, "glue" together the various blocks of vector code of the vector program.

[0230] In some example aspects, the scalar processor 330 may be implemented separately from the vector processing block 310. In other aspects, the scalar processor 330 may be configured to share one or more components and / or functionality with the vector processing block 310.

[0231] In some example aspects, the scalar processor 330 may be configured to perform operations that are not suitable for execution in the vector processing block 310.

[0232] For example, scalar processor 330 may be used to execute 32-bit C programs. Scalar processor 330 may, for example, be configured to support 1-, 2-, and / or 4-byte C code data types and / or some or all of C code's arithmetic operators.

[0233] For example, the scalar processor 330 may be configured to provide a technical solution to perform operations that cannot be performed in the vector processing block 310, for example, without using a full CPU.

[0234] In some example aspects, the scalar processor 330 may include a scalar memory 332, which may be, for example, 16K or other size, and may be configured to store data, such as variables used by the scalar portions of a program.

[0235] For example, the scalar processor 330 may store local and / or global variables declared by portable C code that may be allocated to scalar data storage by a compiler, e.g., compiler 200 ( Fig. 2).

[0236] In some exemplary aspects, as in Fig. 3, the scalar processor 330 may include or be coupled to a set of vector registers 334 that may be used in a data processing process executed by the scalar processor 330.

[0237] In some example aspects, the scalar processor 330 may be coupled to a scalar memory map that may assist the scalar processor 330 in accessing substantially all states of the vector processor 300. For example, the scalar processor 330 may configure the vector units and / or the DMA channels via the scalar memory map.

[0238] In some example aspects, the scalar processor 330 may not be permitted to access one or more control registers for blocks that may be used by external processors to execute and debug vector programs.

[0239] In some example aspects, DMA 340 may be configured to communicate with one or more other components of a chip implementing vector processor 300, for example, via main memory. For example, DMA 340 may be configured to transfer blocks of data, such as large, contiguous blocks of data, to support scalar processor 330 and / or the vector processing block, which may manipulate data stored in local memories. For example, a vector program may read data from the chip's main memory using DMA 340.

[0240] In some example aspects, DMA 340 may be configured to communicate with other elements of the chip, for example, via a plurality of DMA channels, e.g., 8 DMA channels or any other number of DMA channels. For example, a DMA channel, i.e., each DMA channel, may be capable of transferring a rectangular patch from the local memories to the chip's main memory, or vice versa. In other aspects, the DMA channel may transfer any other type of data block between the local memories and the chip's main memory.

[0241] In some example aspects, a rectangular patch may be defined by a base pointer, a width, a height, and a step size.

[0242] For example, at maximum throughput, 8 bytes can be transferred per cycle, but overhead may be incurred for each patch and / or for each row in a patch.

[0243] In some example aspects, DMA 340 may be configured to transfer data in parallel with computations, e.g., across multiple DMA channels, as long as executing instructions do not access any local memory involved in the transfer.

[0244] For example, because all channels access the same memory, using multiple channels to perform a transfer may not save I / O cycles compared to, for example, using a single channel. However, the multiple DMA channels can be used to schedule multiple transfers and execute them in parallel with computations. This can be advantageous compared to, for example, a single channel, where a second transfer may not be scheduled before the first is complete.

[0245] In some exemplary aspects, DMA 340 may be associated with a memory mapper that can assist the DMA channels in accessing vector memory and / or the scalar data. For example, access to the vector memory may be performed in parallel with computations. For example, parallel access to the scalar data is generally not permitted because the scalar processor 330 may be involved in almost any meaningful program and is likely to access its local variables while the transfer is being performed, which may result in a memory conflict with the active DMA channel.

[0246] In some exemplary aspects, DMA 340 may be configured to provide a technical solution to support the parallelization of I / O and computations. For example, a program performing computations may not need to wait for I / O, e.g., if those computations can be performed quickly by vector processing block 310.

[0247] In some example aspects, an external processor, e.g., a CPU, may be configured to initiate execution of a program on vector processor 300. For example, vector processor 300 may remain idle until program execution is initiated.

[0248] In some example aspects, the external processor may be configured to debug the program, i.e., execute a single step at a time, stop when the program reaches breakpoints, and / or check the contents of registers and memory in which the program variables are stored.

[0249] In some example aspects, external memory mapping may be implemented to assist the external processor in controlling the vector processor 300 and / or debugging the program, for example, by writing to control registers of the vector processor 300.

[0250] In some example aspects, external memory mapping may be implemented by a superset of scalar memory mapping. This implementation may, for example, make all registers and memory defined by the architecture of vector processor 300 accessible to a debugger backend running on the external processor.

[0251] In some example aspects, the vector processor 300 may trigger an interrupt signal, for example, when the vector processor 300 terminates a program.

[0252] In some example aspects, the interrupt signal may be used, for example, to implement a driver that manages a queue of programs scheduled for execution by the vector processor 300 and / or to start a new program, e.g., by the external processor, for example, upon completion of a previously executed program.

[0253] Referring to Fig. 1, in some example aspects, compiler 160 may be configured to generate target code 115 based on one or more loops, which may be based on source code 112, for example, as described below.

[0254] In some example aspects, compiler 160 may be configured to compile one or more operations according to a compilation scheme that may be configured to provide a technical solution to reduce or even eliminate the use of induction variables, for example, in one or more masked memory access operations in a loop, as described below.

[0255] In some example aspects, the one or more masked memory access operations in the loop may include a masked load operation, a masked store operation, a masked select operation, and / or any other masked memory access operation, e.g., as described below.

[0256] In some example aspects, a masked memory access instruction may include a conditional operation based on a mask expression containing a logical condition, as described below.

[0257] For example, in some example aspects, the conditional operation of the masked memory access instruction may be performed based on whether the mask expression is true or false.

[0258] In some example aspects, a mask expression may include one or more Boolean conditions that may, for example, be based on and / or represent a result of a condition.

[0259] In some example aspects, the mask expression may include one or more mask sheets that satisfy one or more Boolean conditions.

[0260] In some example aspects, a mask sheet may correspond to a corresponding Boolean condition, as described below.

[0261] In one example, a loop may include a mask expression, which can be defined based on one or more Boolean conditions, for example, as follows: char Mask=(a>x)|(b<10);

[0262] For example, this mask expression may include a first sheet and a second sheet. For example, the first sheet may include a first Boolean condition (a>x), and the second sheet may include a second Boolean condition (b<10).

[0263] According to this example, a result of the mask expression may be true, for example, if the first Boolean condition of the first leaf (a>x) is true and / or the second Boolean condition of the second leaf (b<10) is true.

[0264] In some exemplary aspects, such as some use cases, scenarios, and / or implementations, implementing a masked operation in a loop may require resolving one or more technical issues, as described below.

[0265] In some exemplary aspects, such as some use cases, scenarios, and / or implementations, calculating some masks in a loop may be computationally intensive and / or expensive.

[0266] For example, computing a mask (also called an "induction-based mask") based on an induction variable (IV) of a loop that encloses the mask may require maintaining an IV for the loop, comparing the IV to a boundary, reserving mask registers, and / or one or more additional or alternative operations based on the IV.

[0267] In one example, an induction variable of a loop may include a variable that can be incremented or decremented, e.g., by a fixed amount, for example, on each iteration of the loop. In another example, an induction variable of a loop may be a function, e.g., a linear function, of another induction variable of the loop.

[0268] For example, in some use cases, scenarios, and / or implementations, some transformations of loops, e.g., loop vectorization transformations, may introduce one or more induction-based masks, e.g., to filter out out-of-bounds values / calculations.

[0269] This filtering can be done, for example, by a masked operation, which can be configured to select according to an IV-based mask, for example, between loaded / calculated values ​​and some default values.

[0270] For example, in some use cases, scenarios, and / or implementations, the computation of the masked operations may be computationally intensive, e.g., when implemented by one or more target processor architectures that may not have efficient means of maintaining inductions.

[0271] As an example, some target architectures may have other hardware (HW) mechanisms for controlling the execution of a loop and for controlling the limits of memory accesses (“bounded loads / stores”).

[0272] In some example aspects, compiler 160 may be configured to identify one or more masked memory accesses based on source code 112 and compile the identified masked memory accesses according to a masked operation compilation scheme, e.g., as described below.

[0273] In some example aspects, the compiler 160 may be configured to generate the target code 115 by compiling the source code 112, for example, according to the masked operation compilation scheme as described below.

[0274] In some example aspects, the identified masked memory access operation may be based on a mask expression, as described below.

[0275] In some example aspects, the compilation scheme for masked operations may be configured to provide a technical solution to reduce, eliminate, optimize, and / or preclude the use of induction variables in the identified masked memory access operations, as described below.

[0276] In some example aspects, the compilation scheme for masked operations may be configured to provide a technical solution to exclude one or more mask sheets, which may be based on an IV (IV-based mask sheet), from the mask expression, e.g., as described below.

[0277] In some example aspects, the compilation scheme for masked operations may be configured to provide a technical solution to maintain in the mask expression one or more mask sheets that may not be based on an IV (non-IV-based mask sheets), as described below.

[0278] In some example aspects, the compilation scheme for masked operations may be configured to provide a technical solution to generate target code 115, for example, based on masked memory access operations that are not based on induction variables and / or that do not require handling of induction variables, as described below.

[0279] In some example aspects, the compilation scheme for masked operations may be configured to provide a technical solution that may improve the performance of the executing program, e.g., an image processing program, by, for example, excluding one or more, e.g., some or all, IV-based mask sheets from the mask expression, as described below.

[0280] In some example aspects, the compilation scheme for masked operations may be configured to convert a first mask expression into a second mask expression, for example, by reconfiguring the first mask expression, as described below.

[0281] In some example aspects, the second mask expression may be configured to simplify or exclude one or more mask sheets of the first mask expression, e.g., as described below.

[0282] In some example aspects, the compilation scheme for masked operations may be configured to convert a first mask expression into a logical form including a first logical expression part and a second logical expression part, as described below.

[0283] In some example aspects, the first logical expression part may be based on one or more mask sheets of the first mask expression, e.g., as described below.

[0284] In some example aspects, the first logical expression part may include an additional expression (Expr1) that may be obtained from the mask expression, for example, by replacing the one or more mask leaves of the first mask expression and / or one or more "don't-care" leaves of the first mask expression, for example, with a constant 0 or 1, as described below.

[0285] In one example, the compilation scheme for masked operations may be configured to convert an original mask expression into a logical form, for example, which may be represented as follows: P1 & ∼P2 & P3 & ... & Expr1 where P1, P2, P3 denote mask sheets of the original mask expression and the expression Expr1 can be obtained from the original mask expression, for example by replacing the mask sheets P1, P2, and / or P3 and / or one or more “don't-care” mask sheets, for example by a constant “0” or “1”.

[0286] In some example aspects, the compilation scheme for masked operations may be configured to create a truth table of the first mask expression, as described below.

[0287] In some example aspects, the compilation scheme for masked operations may be configured to create the truth table of the first mask expression, for example, based on the mask leaves of the first mask expression, as described below.

[0288] In some example aspects, the compilation scheme for masked operations may be configured to identify one or more mask sheets to be simplified and / or replaced, for example, according to the truth table as described below.

[0289] For example, the identified mask leaves may be represented by one or more ANDed leaves of the logical form corresponding to the first mask expression, as described below.

[0290] In some example aspects, the compilation scheme for masked operations may be configured to replace one or more of the identified mask sheets with iterator min / max parameters, as described below.

[0291] For example, the compilation scheme for masked operations may be configured to assign the identified mask sheets, which may be represented, for example, by the logical form literals P1 & ~P2 & P3, to one or more AGUs, as described below.

[0292] In some example aspects, the compilation scheme for masked operations may be configured such that the second mask expression is generated, for example, based on the second part of the logical expression, i.e., the expression Expr1 of the logical form, which may remain, for example, after the identified mask leaves are assigned to the AGUs, as described below.

[0293] In some example aspects, compiler 160 may be configured to identify a first masked memory access operation, e.g., in a loop, based on, for example, source code 112, e.g., as described below.

[0294] In some example aspects, the first masked memory access operation may be based on a first mask expression including one or more mask sheets, as described below.

[0295] In some example aspects, compiler 160 may be configured to determine an identified mask sheet of the one or more mask sheets of the first mask expression, for example, based on at least one predefined criterion, as described below.

[0296] In some example aspects, compiler 160 may be configured to determine an identified mask sheet of the one or more mask sheets of the first mask expression, for example, based on a criterion related to an effect of the identified mask sheet on a logical value of the first mask expression, as described below.

[0297] In some example aspects, compiler 160 may be configured to determine a second masked memory access operation by reconfiguring the first masked memory access operation, for example, based on the identified mask sheet of the first mask expression, as described below.

[0298] In some example aspects, the second masked memory access operation may be based on a second mask expression, e.g., as described below.

[0299] In some example aspects, the second mask expression may be logically simplified, for example, compared to the first mask expression, e.g., as described below.

[0300] In some example aspects, compiler 160 may be configured to configure the second masked memory access operation, for example, such that a number of mask leaves in the second mask expression is less than a number of mask leaves in the first mask expression of the first masked memory access operation, as described below.

[0301] In some example aspects, the second masked memory access operation may include a masked load operation to conditionally load values ​​from a memory according to the second mask expression, as described below.

[0302] In some example aspects, the second masked memory access operation may include a masked store operation to conditionally load values ​​into memory according to the second mask expression, as described below.

[0303] In some example aspects, the second masked memory access operation may include any other additional or alternative type of masked operation.

[0304] In some example aspects, compiler 160 may be configured to generate target code 115, for example, based on compiling source code 112, as described below.

[0305] For example, in some example aspects, the target code 115 may be based on the second masked memory access operation, as described below.

[0306] In some example aspects, compiler 160 may be configured to generate target code 115 configured, for example, for execution by a Very Long Instruction Word (VLIW) Single Instruction / Multiple Data (SIMD) target processor, e.g., processor 180.

[0307] In other respects, the compiler 160 may be configured to generate the target code 115 configured, for example, for execution by another suitable processor type.

[0308] In some example aspects, the compiler 160 may be configured to generate the target code 115, for example, based on the source code 112 that includes Open Computing Language (OpenCL) code.

[0309] In other aspects, the compiler 160 may be configured to generate the target code 115 based on, for example, the source code 112 including another suitable type of code.

[0310] In some example aspects, the compiler 160 may be configured to compile the source code 112 into the target code 115, for example, according to a Low Level Virtual Machine (LLVM)-based (LLVM-based) compilation scheme.

[0311] In other aspects, the compiler 160 may be configured to compile the source code 112 into the target code 115 according to any other suitable compilation scheme.

[0312] In some example aspects, the identified mask sheet may be based on an induction variable of the loop, for example, as described below.

[0313] In some example aspects, compiler 160 may be configured to determine the identified mask sheet, for example, based on a determination that the identified mask sheet is based on an IV of a loop that includes the first masked memory access operation, for example, as described below.

[0314] In some example aspects, compiler 160 may be configured to configure AGU instructions, for example, based on the identified mask sheet, as described below.

[0315] In some example aspects, the AGU instructions may include memory access instructions of an AGU to perform the second masked memory access operation, e.g., as described below.

[0316] In some example aspects, compiler 160 may be configured to generate target code 115 based on, for example, the AGU instructions, e.g., as described below.

[0317] In some example aspects, the AGU instructions may include at least one of a lower and an upper bound of a memory access range to be applied by the AGU for the second masked memory access operation, as described below.

[0318] In some example aspects, the compiler 160 may be configured to configure the AGU instructions to define a memory access range, for example, based on the identified mask sheet, as described below.

[0319] In some example aspects, the compiler 160 may be configured to configure the AGU instructions to configure the AGU to apply the memory access range for the second masked memory access operation, as described below.

[0320] In some example aspects, the compiler 160 may be configured to configure the AGU instructions to define a lower bound of the memory access range, for example, based on the identified mask sheet, as described below.

[0321] In some example aspects, the compiler 160 may be configured to configure the AGU instructions to define an upper bound of the memory access range, for example, based on the identified mask sheet, as described below.

[0322] In some example aspects, the second mask expression may exclude the identified mask, as described below.

[0323] In some example aspects, compiler 160 may be configured to configure the second masked memory access operation to exclude one or more IV-based mask sheets of the first masked memory access operation that are based on an IV of a loop that includes the first masked memory access operation, as described below.

[0324] In some example aspects, compiler 160 may be configured to configure the second masked memory access operation to exclude any IV-based mask sheets of the first masked memory access operation that are based on an IV of a loop that includes the first masked memory access operation, e.g., as described below.

[0325] In some example aspects, compiler 160 may be configured to configure the second masked memory access operation to include, for example, only non-IV-based mask sheets that are not based on an IV of a loop that includes the first masked memory access operation, as described below.

[0326] In other aspects, compiler 160 may be configured to configure the second masked memory access operation to exclude only some of the IV-based mask leaves of the first masked memory access operation.

[0327] In some example aspects, compiler 160 may be configured to configure the second masked memory access operation to, for example, maintain one or more, e.g., some or all, non-IV-based mask sheets of the first masked memory access operation that are not based on an IV of a loop enclosing the first masked memory access operation, e.g., as described below.

[0328] In some example aspects, compiler 160 may be configured to determine the identified mask sheet of the first mask expression, for example, based on a criterion that may include the requirement that all possibilities of a logical true value of the first mask expression may result from the same logical value of the identified mask sheet, for example, as described below.

[0329] In some example aspects, compiler 160 may be configured to determine the identified mask sheet of the first mask expression, for example, based on a criterion that may include a requirement that all possibilities of a logical true value of the first mask expression may be independent of a logical value of the identified mask sheet, for example, as described below.

[0330] In some example aspects, compiler 160 may be configured to determine the identified mask sheet of the first mask expression, for example, based on another additional or alternative criterion.

[0331] In some example aspects, compiler 160 may be configured to determine the identified mask sheet, for example, based on a truth table corresponding to the first mask expression, as described below.

[0332] In one example, compiler 160 may compile source code 112 of a program to be executed by a target processor, such as a processor 180, such as a target vector processor.

[0333] For example, compiler 160 may identify a loop that includes a first masked memory access operation, e.g., as follows: for(int y = 0; y < height; y++) for(int x = 0; x < width; x++) { for(int z = 0; z < depth; z++) { int index = y * ystride + x * xstride + z; char s = inp1 [index]; char t = inp1 [index + 1]; char Mask = ~((x < a) | (~(s >= b) & (t <= 10))); char val = masked_load(inp2 + index, 0, Mask); out[index] = val + 7;}}} Example (4a)

[0334] As shown in Example 4a, the first masked memory access operation may include a first masked load operation, e.g., char val = masked_load(inp2+ index, 0, Mask), which may be based on a mask, e.g., Mask.

[0335] As shown in Example 4a, the first masked load can be based on a first mask expression, e.g., char Mask = ~((x < a) | (~(s >= b) & (t <= 10))).

[0336] As illustrated in Example 4a, the first mask expression may include three mask sheets. For example, the first mask expression may include a first mask sheet, e.g., (x < a), a second mask sheet, e.g., (s >= b), and / or a third mask sheet, e.g., (t <= 10).

[0337] As illustrated in Example 4a, the first mask sheet may include an IV-based mask sheet, which may be based on an induction variable x of the loop that includes the first masked load.

[0338] As shown in Example 4a, the second and third mask sheets may include non-IV-based mask sheets, since, for example, they cannot be based on an induction variable of the loop including the first masked load.

[0339] For example, as shown in Example 4a, the second mask sheet may be based on the variables s and b and / or the third mask sheet may be based on a variable t.

[0340] In some example aspects, the compiler 160 may be configured to identify the first masked operation in the loop, for example, based on the source code 112.

[0341] In some example aspects, compiler 160 may be configured to determine the first mask sheet as the identified mask sheet of the first mask expression, for example, based on determining that the first mask sheet is an IV-based sheet, as described below.

[0342] In some example aspects, compiler 160 may be configured to determine the first mask sheet as the identified mask sheet of the first mask expression, for example, based on a criterion requiring that all possibilities of a logical true value of the first mask expression can result from the same logical value of the first mask sheet, as described below.

[0343] In some example aspects, compiler 160 may be configured to determine whether or not the criterion is met with respect to the mask leaves of the first mask expression, for example, based on a truth table corresponding to the first mask expression, as described below.

[0344] In some exemplary aspects, the first mask expression can be represented by the three mask sheets, for example as follows: ∼P &∼(0|(∼Q & R)). where P = (x < a), Q = (s >= b) and R = (t <= 10).

[0345] In some exemplary aspects, the compiler 160 may be configured to determine a truth table corresponding to expression (1), e.g., as follows: Table (1) P Q R Mask 0 0 0 1 0 1 0 1 0 1 1 1

[0346] For example, as shown in truth table (1), the mask sheet P can always be 0 to make Mask=True. For example, as shown in truth table (1), the mask sheet P can be invariant in the truth table, meaning the value of the mask sheet P can be 0 in all entries of the truth table.

[0347] For example, based on this determination, the mask sheet P can be extracted outside the logical expression with a negative sign (logical NOT), e.g., while the mask sheet P is replaced by a constant logical “0”, e.g., as follows: ∼P &∼(0|(∼Q & R)).

[0348] As shown in truth table (1), the values ​​of other mask leaves, such as leaves Q and R, can vary in truth table (1). For example, these mask leaves may not be invariant or "don't care." Accordingly, these mask leaves Q and R can remain in the logical expression.

[0349] As shown in expression (2), expression (2) can include a constant value, such as 0, instead of the mask sheet P. For example, since the sign of the mask sheet P is negative, the constant value zero can be selected.

[0350] For example, expression (2) may be logically equivalent to expression (1). For example, if P = 0, the second part (~(0 | (~Q & R))) of expression (2) may be exactly equal to expression (1), and the first part (~P) of expression (2) may not change the second part of expression (2), e.g., as (~P)=1. For example, expression (2) may be a logical AND operation of the first part of expression (2) with the logical value "1", e.g., as ~P = 1.

[0351] For example, the logical NOT operation can be zero when P = 1, e.g., ~P = 0. According to this, expression (2) can be zero. As shown in truth table (1), expression (1) can be zero, for example, when P = 1.

[0352] In some example aspects, compiler 160 may be configured to further simplify expression (2), for example, based on the equality: “0 | A = A”.

[0353] For example, compiler 160 may be configured to further simplify the expression (~(0 | (~Q & R))) into the expression (Q & ~R). For example, compiler 160 may be configured to optimize the other mask sheets, e.g., optimize by default so that they are (Q | ~R) = (s >= b) | ~(t <= 10).

[0354] For example, the compiler 160 may be configured to further simplify expression (2), for example, by an instruction that combines an operation (instcombine), e.g., after this pass.

[0355] In some example aspects, the compiler 160 may be configured to use a truth table to provide a technical solution that supports determining a logical expression, e.g., expression (2), based on a first mask expression, e.g., expression (1), for example, even with regard to relatively complex mask expressions.

[0356] In some example aspects, the truth table may be implemented to provide a technical solution that supports determining a simplified logical expression based on a mask expression, for example, also with regard to mask expressions that are not easily simplified, for example, using one or more conversions, e.g., according to de Morgan's laws and / or other conversion rules and / or laws.

[0357] In an example, a mask expression may include the following mask with the additional mask sheets A and B: Mask2=(∼(P|(∼Q & R))& A)|(∼(P|(∼Q & R))& ∼A & B)|(∼(P|(∼Q & R))& ∼A & ∼B)

[0358] For example, a truth table can be used to determine that the logical expression ~P & ~(0 | (~Q & R)) can be logically equivalent to the mask Mask2, even if the mask Mask2 cannot be easily converted into a simplified logical expression, e.g., based on De Morgan's rules.

[0359] In some example aspects, compiler 160 may be configured to determine a second masked memory access operation by reconfiguring the first masked load operation, for example, based on the first mask sheet P.

[0360] In some example aspects, the second masked memory access operation may be based on a second mask expression, which may, for example, be logically simplified compared to the first mask expression.

[0361] For example, the second mask expression may be based on the second part of expression (2), e.g., ~(0 | (~Q & R)), which may be logically simplified compared to expression (1), for example.

[0362] In some example aspects, compiler 160 may be configured to configure AGU instructions that include memory access instructions of an AGU to perform the second masked memory access operation, e.g., as described below.

[0363] In some example aspects, the compiler 160 may configure the AGU instructions based on at least one mask sheet of the first masked memory access operation, e.g., as described below.

[0364] For example, in some example aspects, compiler 160 may configure the AGU instructions to selectively restrict the memory access of the second masked memory access operation, for example, based on at least one mask sheet of the first masked memory access operation to be excluded from the second masked memory access operation, as described below.

[0365] For example, in some example aspects, compiler 160 may configure the AGU instructions to selectively restrict the memory access of the second masked memory access operation, for example, in a manner that is logically equivalent to the at least one mask sheet of the first masked memory access operation that is to be excluded from the second masked memory access operation, as described below.

[0366] In some example aspects, the compiler 160 may configure the AGU instructions based on the first mask sheet of the first masked memory access operation, as described below.

[0367] For example, in some example aspects, compiler 160 may configure the AGU instructions to selectively restrict the memory access of the second masked memory access operation, for example, based on the first mask sheet of the first masked memory access operation, as described below.

[0368] In some example aspects, compiler 160 may be configured to configure AGU instructions to define a memory access range to be accessed by the second masked memory access operation, e.g., as described below.

[0369] In some example aspects, compiler 160 may be configured to configure AGU instructions to define the memory access range, for example, based on the first mask sheet of the first masked memory access operation, as described below.

[0370] In some example aspects, compiler 160 may be configured to configure AGU instructions to selectively limit the second masked memory access operation to the memory access range, which may be based on the first mask sheet of the first masked memory access operation, as described below.

[0371] In some example aspects, compiler 160 may be configured to configure AGU instructions to selectively restrict the second masked memory access operation to the memory access range, for example, in a manner that may be logically equivalent to the first mask sheet of the first masked memory access operation, as described below.

[0372] In some example aspects, compiler 160 may be configured to configure AGU instructions to define a lower and / or upper bound of the memory access range to be applied by the AGU for the second masked memory access operation, as described below.

[0373] For example, compiler 160 may configure the lower and / or upper bound of the memory access range, for example, based on the first mask sheet P, as described below.

[0374] In some example aspects, compiler 160 may be configured to identify a first mask sheet in a first mask expression of a first masked memory access operation in a loop, for example, based on a determination that the first mask sheet is based on an induction variable, e.g., an induction variable x, of the loop, as described below.

[0375] In some example aspects, compiler 160 may be configured to configure a second masked memory access operation, for example, by reconfiguring the first masked memory access operation based on the first mask sheet, as described below.

[0376] In some example aspects, compiler 160 may be configured to configure AGU instructions to define a lower bound, e.g., a lower bound xmin, and / or an upper bound, e.g., an upper bound xmax, of a memory access range to be applied by the AGU for the second masked memory access operation, as described below.

[0377] In some example aspects, the compiler 160 may be configured to configure the AGU instructions to define the lower bound, e.g., the lower bound xmin, and / or the upper bound, e.g., the upper bound xmax, for example, based on a logical condition for the induction variable, e.g., an induction variable x, that may be defined by the first mask sheet, e.g., as described below.

[0378] In some example aspects, compiler 160 may be configured to translate the first mask sheet -P = (x >= a) in expression (2), for example, into a boundary for an AGU memory access instruction, e.g., for the second masked memory access operation.

[0379] For example, compiler 160 may be configured to configure an AGU lower bound (xmin) of the AGU memory access instruction in a compiled loop, which may be based on the loop of Example 4a, e.g., as described below.

[0380] For example, the compiler 160 may be configured to configure the AGU lower bound (xmin) of the AGU memory access instruction, for example, based on the first mask sheet ~P = (x >= a) in expression (2).

[0381] For example, the compiler 160 may be configured to configure the AGU lower bound (xmin) of the AGU memory access instruction, for example, by setting the AGU lower bound (xmin) to the value of a (xmin=a), which may be logically equivalent to the condition of the first mask sheet ~P = (x >= a) in expression (2).

[0382] For example, the compiler 160 may be configured to configure the AGU instructions of the AGU memory access instruction in a compiled loop, which may be based on the loop of Example 4a, to define, for example, an AGU lower bound (xmin = a) that may be based on the first mask sheet ~P = (x >= a) in expression (2), e.g., as follows: agu1 = allocate_agu("load"); set_base(agu1, inp1) / / ... other agu1 parameters agu2 = allocate_agu("load"); set_base(agu2, inp2) set_x_minmax(agu2, a, width); / / ... other agu2 parameters agu3 = allocate_agu("store"); set_base(agu3, out); / / ... other agu3 parameters Loop: char s = agu1.load(); char t = agu1.load(); char NewMask = (s >= b) | (t > 10); char val = agu2.masked_load(0, NewMask); agu3.store(val + 7); Example (4b)

[0383] As shown in Example 4b, the compiled loop may include a masked memory access operation, which may include a masked load operation based on the second mask (NewMask), e.g., char val = agu2.masked_load(0, NewMask).

[0384] As shown in Example 4b, the masked loading can be based on the second mask, e.g., NewMask, which can be defined based on the second mask expression, e.g., char NewMask = (s >= b) | (t > 10).

[0385] As shown in Example 4b, the second mask expression may be based on the second part of expression (2), which may, for example, be logically simplified compared to expression (1).

[0386] As shown in Example 4b, the second mask expression can only include two mask sheets, e.g., two non-IV-based mask sheets, e.g., ~(s >= b), and t (t <= 10).

[0387] As shown in Example 4b, the second mask expression can only include non-IV-based mask sheets.

[0388] As shown in Example 4b, the second mask expression can exclude all IV-based mask sheets of mask expression (1).

[0389] As shown in Example 4b, the second mask expression can exclude any IV-based mask sheets.

[0390] As shown in Example 4b, the second mask expression may not include the first mask sheet P of Expression (1). For example, the second mask expression may exclude the first mask sheet P, which may be based on the induction variable x.

[0391] In some example aspects, as illustrated in Example 4b, compiler 160 may allocate a first AGU, e.g., agu1, to load data from a first input pointer, e.g., inp1, for example.

[0392] In some exemplary aspects, as illustrated in Example 4b, compiler 160 may generate the compiled loop to include a first load instruction, e.g., char s = agu1.load(), to load, for example, agu1, a char value based on the pointer inp1[index] into a char variable s.

[0393] In some exemplary aspects, as illustrated in Example 4b, the compiler 160 may generate the compiled loop to include a second load instruction, e.g., chart = agu1.load(), to load, for example, a char value based on the pointer inp1[index+1] into a char variable t by agu1.

[0394] In some example aspects, as illustrated in Example 4b, compiler 160 may allocate a second AGU, e.g., agu2, to perform, for example, a masked load operation, e.g., to load data from a second input pointer, e.g., inp2, according to the mask NewMask.

[0395] In some exemplary aspects, as illustrated in Example 4b, the compiler 160 may configure an AGU instruction for the second AGU to, for example, specify a lower and an upper bound for a dimension of the agu2 corresponding to the induction variable x.

[0396] In some exemplary aspects, as illustrated in Example 4b, the compiler 160 may set the lower and / or upper bound of the second AGU executing the masked load instruction, for example, based on the first leaf of Expression (1), e.g., ∼ P = ~ (x <a).

[0397] In one example, lowering the lower bound for the masked load to be performed by the second AGU according to the condition (x>=a) may be logically equal to the leaf ∼ P=~ (x <a) sein.

[0398] In some exemplary aspects, as illustrated in Example 4b, the compiler 160 may generate an AGU instruction, e.g., set_x_minmax(agu2, a, width), to set the lower bound for the dimension of the agu2 corresponding to the induction variable x to a.

[0399] For example, the AGU instruction, e.g., set_x_minmax(agu2, a, width), can restrict agu2, e.g., to load data from the pointer inp2, e.g., only if the IV x is equal to or greater than a. This restriction can be made, for example, according to the condition of the first leaf of expression (1), e.g., ∼ P=~ (x<a)= (x> =a).

[0400] In some exemplary aspects, as illustrated in Example 4b, compiler 160 may set the upper bound of the AGU instruction for agu2 to width, for example, to load data from the pointer inp2, for example, according to the condition of the IV x in the inner loop of Example 4a, e.g., for(int x = 0; x < width; x++).

[0401] In some exemplary aspects, as illustrated in Example 4b, the first mask sheet of expression (1) may become redundant, for example, when configuring agu2 according to the command set_x_minmax(agu2, a, width).

[0402] For example, the mask NewMask may not need to be used to calculate the condition ~(x<a)= (x> =a) should be used, since this condition may already be met by setting the lower limit of agu2 (xmin=a).

[0403] In some exemplary aspects, as illustrated in Example 4b, compiler 160 may exclude the mask sheet P from the mask NewMask.

[0404] For example, as shown in Example 4b, the masked load instruction char val = agu2.masked_load(0, NewMask) can be based on the mask NewMask.

[0405] In some exemplary aspects, as illustrated in Example 4b, compiler 160 may generate the compiled loop, which may be configured, for example, to define the second mask expression, for example, based on the mask NewMask, e.g., char NewMask = (s >= b) | (t > 10), which may exclude the first mask leaf P.

[0406] In some exemplary aspects, as illustrated in Example 4b, compiler 160 may generate the compiled loop to include a third load instruction, e.g., val = agu2.masked_load(0, NewMask), to load, for example, by agu2, a char value based on the pointer inp2 into a char variable val, for example, based on the mask NewMask.

[0407] In some example aspects, as illustrated in Example 4b, compiler 160 may allocate a third AGU, e.g., agu3, to store data based on an output pointer, e.g., out.

[0408] In some exemplary aspects, as illustrated in Example 4b, the compiler 160 may generate the compiled loop to include a store instruction, e.g., agu3.store(val + 7), to store, for example, agu3, a result of the sum val+7 in the output pointer out.

[0409] It will now Fig. 4, which schematically illustrates a method of compiling code for a processor. For example, one or more acts of the method of Fig. 4 from a system, e.g. System 100 ( Fig. 1), a device, e.g., device 102 ( Fig. 1), a server, e.g., server 170 ( Fig. 1), and / or a compiler, e.g. Compiler 160 ( Fig. 1) and / or Compiler 200 ( Fig. 2) are carried out.

[0410] In some example aspects, as indicated in block 402, the method may include identifying a first masked memory access operation based on source code, wherein the first masked memory access operation is based on a first mask expression including one or more mask sheets. For example, compiler 160 ( Fig. 1) be configured to identify the first masked memory access operation in a loop operation, for example, based on source code 112 ( Fig. 1), as described above.

[0411] In some example aspects, as indicated in block 404, the method may include determining a second masked memory access operation, for example, by reconfiguring the first masked memory access operation based on an identified mask sheet of the one or more mask sheets. For example, the second masked memory access operation may be based on a second mask expression that is logically simplified compared to the first mask expression. For example, the compiler 160 ( Fig. 1) be configured to determine the second masked memory access operation by reconfiguring the first masked memory access operation based on the identified mask sheet, as described above.

[0412] In some example aspects, as indicated in block 406, the method may include generating target code based on compiling the source code, wherein the target code is based on the second masked memory access operation. For example, the compiler 160 ( Fig. 1) be configured to use the destination code 115 ( Fig. 1) for example, generated based on the second masked memory access operation as described above.

[0413] It will be Fig. 5, which schematically illustrates a product of manufacture 500 according to some exemplary aspects. Product 500 may include one or more tangible computer-readable ("machine-readable") non-transitory storage media 502 that may contain computer-executable instructions, e.g., implemented by logic 504, that, when executed by at least one computer processor, enables the at least one computer processor to perform one or more operations on device 102 ( Fig. 1), the server 170 ( Fig. 1) and / or the compiler 160 ( Fig. 1) to implement the device 102 ( Fig. 1), the server 170 ( Fig. 1) and / or the compiler 160 ( Fig. 1) to cause one or more operations and / or functionalities to be carried out, triggered and / or implemented, and / or to carry out one or more operations and / or functionalities that are intended to be carried out with reference to the Fig.1 to 4, and / or to execute, initiate, and / or implement one or more of the operations described herein. The terms "non-transitory machine-readable medium" and "computer-readable non-transitory storage medium" may be construed to include all computer-readable media, with the sole exception of a transient transmitted signal.

[0414] In some example aspects, the product 500 and / or the machine-readable storage medium 502 may include one or more types of computer-readable storage media capable of storing data, including volatile memory, non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. For example, machine-readable storage media 502 may include RAM, DRAM, double data rate DRAM (DDR-DRAM), SDRAM, static RAM (SRAM), ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content-addressable memory (CAM), polymer memory, phase-change memory, ferroelectric memory, silicon oxide-nitride-oxide-silicon (SONOS) memory, a disk, a hard disk, and the like.The computer-readable storage medium may include any suitable medium related to the downloading or transmission of a computer program from a remote computer to a requesting computer, carried by data signals embodied in a carrier wave or other propagation medium over a communications link, such as a modem, radio, or network connection.

[0415] In some example aspects, logic 504 may include instructions, data, and / or code that, when executed by a machine, may cause the machine to perform a method, process, and / or operations as described herein. For example, the machine may include any suitable processing platform, computing platform, computing unit, processing unit, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware, software, firmware, and the like.

[0416] In some example aspects, logic 504 may include or be implemented as software, a software module, an application, a program, a subroutine, instructions, an instruction set, arithmetic code, words, values, symbols, and the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, style, or syntax to instruct a processor to perform a particular function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language, machine code, and the like. EXAMPLES

[0417] The following examples refer to further aspects.

[0418] Example 1 includes a product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions that, when executed by at least one processor, enable the at least one processor to cause a compiler to identify a first masked memory access operation based on source code, wherein the first masked memory access operation is based on a first mask expression comprising one or more mask sheets; determine a second masked memory access operation by reconfiguring the first masked memory access operation based on an identified mask sheet of the one or more mask sheets, wherein the second masked memory access operation is based on a second mask expression that is logically simplified compared to the first mask expression;and generate target code based on compiling the source code, the target code being based on the second masked memory access operation;

[0419] Example 2 includes the subject matter of Example 1 and optionally, wherein the instructions, when executed, cause the compiler to determine the identified mask sheet based on a criterion relating to an effect of the identified mask sheet on a logical value of the first mask expression,

[0420] Example 3 includes the subject matter of Example 2, and optionally, wherein the criterion includes a requirement that all possibilities of a true logical value of the first mask expression result from the same logical value of the identified mask sheet.

[0421] Example 4 includes the subject matter of example 2 or 3, and optionally, wherein the criterion includes a requirement that all possibilities of a true logical value of the first mask expression are independent of a logical value of the identified mask sheet.

[0422] Example 5 includes the subject matter of any of Examples 1 to 4, and optionally, wherein the instructions, when executed, cause the compiler to determine the identified mask sheet based on a determination that the identified mask sheet is based on an induction variable (IV) of a loop comprising the first masked memory access operation.

[0423] Example 6 includes the subject matter of any of Examples 1 to 5, and optionally, wherein the instructions, when executed, cause the compiler to configure the address generation unit (AGU) instructions based on the identified mask sheet, wherein the AGU instructions comprise memory access instructions of an AGU to perform the second masked memory access operation, wherein the target code is based on the AGU instructions.

[0424] Example 7 includes the subject matter of Example 6, and optionally, wherein the instructions, when executed, cause the compiler to configure the AGU instructions to define a memory access range based on the identified mask sheet, the memory access range to be applied by the AGU for the second masked memory access operation.

[0425] Example 8 includes the subject matter of Example 7, and optionally, wherein the instructions, when executed, cause the compiler to configure the AGU instructions to define at least one of a lower and an upper bound of the memory access range based on the identified mask sheet.

[0426] Example 9 includes the subject matter of any of Examples 1 to 8, and optionally, wherein the second mask expression excludes the identified mask sheet.

[0427] Example 10 includes the subject matter of any of Examples 1 to 9, and optionally wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to exclude one or more induction variable (IV)-based (IV-based) mask leaves of the first masked memory access operation that are based on an IV of a loop comprising the first masked memory access operation.

[0428] Example 11 includes the subject matter of any of Examples 1 to 10, and optionally, wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to exclude all induction variable (IV)-based (IV-based) mask leaves of the first masked memory access operation that are based on an IV of a loop comprising the first masked memory access operation.

[0429] Example 12 includes the subject matter of any of Examples 1 to 11, and optionally wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to maintain one or more non-induction variable (IV)-based (non-IV-based) mask leaves of the first masked memory access operation that are not based on an IV of a loop comprising the first masked memory access operation.

[0430] Example 13 includes the subject matter of any of Examples 1 to 12, and optionally wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to include only non-IV-based mask sheets that are not based on an IV of a loop comprising the first masked memory access operation.

[0431] Example 14 includes the subject matter of any of Examples 1 to 13, and optionally, wherein the instructions, when executed, cause the compiler to determine the identified mask sheet based on a truth table corresponding to the first mask expression.

[0432] Example 15 includes the subject matter of any of Examples 1 to 14, and optionally, wherein a number of mask sheets in the second mask printout is less than a number of mask sheets in the first mask printout.

[0433] Example 16 includes the subject matter of any of Examples 1 to 15, and optionally, wherein the second masked memory access operation comprises a masked load operation to conditionally load values ​​from a memory according to the second mask expression.

[0434] Example 17 includes the subject matter of any of Examples 1 to 16, and optionally, wherein the second masked memory access operation comprises a masked store operation to conditionally store values ​​in a memory according to the second mask expression.

[0435] Example 18 includes the subject matter of any of Examples 1 to 17, and optionally, wherein the source code comprises Open Computing Language (OpenCL) code.

[0436] Example 19 includes the subject matter of any of Examples 1 to 18, and optionally, wherein the computer-executable instructions, when executed, cause the compiler to compile the source code into the target code according to a Low Level Virtual Machine (LLVM)-based (LLVM-based) compilation scheme.

[0437] Example 20 includes the subject matter of any of Examples 1 through 19, and optionally, wherein the target code is configured for execution by a Very Long Instruction Word (VLIW) Single Instruction / Multiple Data (SIMD) target processor.

[0438] Example 21 includes the subject matter of any of Examples 1 to 20, and optionally, wherein the target code is configured for execution by a target vector processor.

[0439] Example 22 includes a compiler configured to perform any of the described operations of any of Examples 1 through 21.

[0440] Example 23 includes a computing device configured to perform any of the described operations of any of Examples 1 to 21.

[0441] Example 24 includes a computer system comprising at least one memory for storing instructions and at least one processor for retrieving instructions from the memory and executing the instructions to cause the computer system to perform any of the described operations of any of Examples 1 to 21.

[0442] Example 25 includes a computer system comprising a compiler for generating target code according to any of the described operations of any of Examples 1 to 21 and a processor for executing the target code.

[0443] Example 26 includes an apparatus comprising means for performing any of the described operations of any of Examples 1 to 21.

[0444] Example 27 includes a device comprising: a memory interface; and processing circuitry configured to perform any of the described operations of any of Examples 1 to 21.

[0445] Example 28 includes a method comprising any of the described operations of any of Examples 1 to 21.

[0446] Functions, operations, components, and / or features described herein with reference to one or more aspects may be combined with or used in combination with one or more other functions, operations, components, and / or features described herein with reference to one or more other aspects, or vice versa.

[0447] While certain features have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes that remain within the true spirit of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 415,309

[0001] Cited non-patent literature

[0000] Title “APPARATUS, SYSTEM, AND METHOD OF VECTOR PROCESSING”, published on October 12, 2022

[0001]

Claims

[1] A product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions that, when executed by at least one processor, enable the at least one processor to cause a compiler to: identifying a first masked memory access operation based on source code, the first masked memory access operation based on a first mask expression comprising one or more mask sheets; Determining a second masked memory access operation by reconfiguring the first masked memory access operation based on an identified mask sheet of the one or more mask sheets, wherein the second masked memory access operation is based on a second mask expression that is logically simplified compared to the first mask expression; and Generating a target code based on compiling the source code, the target code being based on the second masked memory access operation. [2] The product of claim 1, wherein the instructions, when executed, cause the compiler to determine the identified mask sheet based on a criterion related to an effect of the identified mask sheet on a logical value of the first mask expression. [3] The product of claim 2, wherein the criterion includes a requirement that all possibilities of a true logical value of the first mask expression result from the same logical value of the identified mask sheet. [4] The product of claim 2, wherein the criterion includes a requirement that all possibilities of a true logical value of the first mask expression are independent of a logical value of the identified mask sheet. [5] The product of claim 1, wherein the instructions, when executed, cause the compiler to determine the identified mask sheet based on a determination that the identified mask sheet is based on an induction variable (IV) of a loop comprising the first masked memory access operation. [6] The product of claim 1, wherein the instructions, when executed, cause the compiler to configure address generation unit (AGU) instructions based on the identified mask sheet, the AGU instructions comprising memory access instructions of an AGU to perform the second masked memory access operation, the target code being based on the AGU instructions. [7] The product of claim 6, wherein the instructions, when executed, cause the compiler to configure the AGU instructions to define a memory access range based on the identified mask sheet, the memory access range to be applied by the AGU for the second masked memory access operation. [8] The product of claim 7, wherein the instructions, when executed, cause the compiler to configure the AGU instructions to define at least one of a lower and upper bound of the memory access range based on the identified mask sheet. [9] The product of claim 1, wherein the second mask printout excludes the identified mask sheet. [10] The product of any one of claims 1 to 9, wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to exclude one or more induction variable (IV)-based (IV-based) mask leaves of the first masked memory access operation that are based on an IV of a loop that includes the first masked memory access operation. [11] The product of any of claims 1 to 9, wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to exclude all induction variable (IV)-based (IV-based) mask leaves of the first masked memory access operation that are based on an IV of a loop that includes the first masked memory access operation. [12] The product of any of claims 1 to 9, wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to maintain one or more non-IV-based mask leaves of the first masked memory access operation that are not based on an IV of a loop comprising the first masked memory access operation. [13] The product of any of claims 1 to 9, wherein the instructions, when executed, cause the compiler to configure the second masked memory access operation to include only non-IV-based mask sheets that are not based on an IV of a loop that includes the first masked memory access operation. [14] A product according to any one of claims 1 to 9, wherein the instructions, when executed, cause the compiler to determine the identified mask sheet based on a truth table corresponding to the first mask expression. [15] A product according to any one of claims 1 to 9, wherein a number of mask sheets in the second mask print is less than a number of mask sheets in the first mask print. [16] The product of any of claims 1 to 9, wherein the second masked memory access operation comprises a masked load operation to conditionally load values ​​from a memory according to the second mask expression. [17] The product of any one of claims 1 to 9, wherein the second masked memory access operation comprises a masked store operation to conditionally store values ​​in a memory according to the second mask expression. [18] The product of any of claims 1 to 9, wherein the source code comprises Open Computing Language (OpenCL) code. [19] The product of any of claims 1 to 9, wherein the computer-executable instructions, when executed, cause the compiler to compile the source code into the target code according to a Low Level Virtual Machine (LLVM)-based (LLVM-based) compilation scheme. [20] The product of any one of claims 1 to 9, wherein the target code is configured for execution by a Very Long Instruction Word (VLIW) Single Instruction / Multiple Data (SIMD) target processor. [21] The product of any of claims 1 to 9, wherein the target code is configured for execution by a target vector processor. [22] Computer system comprising: at least one memory for storing instructions; and at least one processor for retrieving the instructions from the memory and executing the instructions to cause the computer system to: identifying a first masked memory access operation based on source code, the first masked memory access operation based on a first mask expression comprising one or more mask sheets; Determining a second masked memory access operation by reconfiguring the first masked memory access operation based on an identified mask sheet of the one or more mask sheets, the second masked memory access operation being based on a second mask expression that is logically simplified compared to the first mask expression; Generating the target code based on compiling the source code, wherein the target code is based on the second masked memory access operation; and Output the target code. [23] The computer system of claim 22, wherein the instructions, when executed, cause the computer system to configure address generation unit (AGU) instructions based on the identified mask sheet, the AGU instructions comprising memory access instructions of an AGU to perform the second masked memory access operation, the target code being based on the AGU instructions. [24] The computer system of claim 22, comprising the target processor. [25] Method comprising: identifying a first masked memory access operation based on source code, the first masked memory access operation based on a first mask expression comprising one or more mask sheets; Determining a second masked memory access operation by reconfiguring the first masked memory access operation based on an identified mask sheet of the one or more mask sheets, wherein the second masked memory access operation is based on a second mask expression that is logically simplified compared to the first mask expression; and Generating a target code based on compiling the source code, the target code being based on the second masked memory access operation. [26] The method of claim 25, comprising configuring instructions of an address generation unit (AGU) based on the identified mask sheet, wherein the AGU instructions comprise memory access instructions of an AGU to perform the second masked memory access operation, wherein the target code is based on the AGU instructions.

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