DISTRIBUTED HARDWARE ARCHITECTURE IN A DATA ACCELERATOR

Abstract

A method includes obtaining data to be processed using at least one data transformation operation. The method further includes determining a processing path for the data to pass through at least a first data transformation engine and a second data transformation engine. The method also includes passing the data to the first data transformation engine. The first data transformation engine is to perform a first data transformation operation on the data. The method further includes passing the data to the second data transformation engine, wherein the second data transformation engine is to perform a second data transformation operation on the data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This U.S. patent application claims priority to U.S. Provisional Patent Application No. 63 / 378,978, entitled "HARDWARE DISTRIBUTED ARCHITECTURE," filed October 10, 2022, the disclosure of which is hereby incorporated by reference in its entirety. FIELD OF TECHNOLOGY

[0002] This disclosure relates generally to a distributed hardware architecture and more particularly to a distributed hardware architecture in a data conversion accelerator. BACKGROUND

[0003] Unless otherwise stated herein, the contents described herein are not prior art within the meaning of the claims of the present application and are not recognized as prior art by inclusion in this section.

[0004] The need for network processing is constantly growing and often requires a long-term technical solution. For example, network processing can face various challenges that arise from the requirements of a network processing system, such as improving performance, scaling based on usage, interoperability, functional flexibility, energy efficiency, and / or cost. Network processing can include systems and methods for packet processing of packets received over a network. Some network processing approaches may focus on meeting one or more of the above requirements, but the focus may also be associated with the cost of the other requirements mentioned above. For example, focusing on improving cost and / or performance may result in reduced scalability and / or functional flexibility.

[0005] The subject matter claimed in the present disclosure is not limited to implementations that solve any disadvantages or operate only in environments such as those described above. Rather, this background is provided merely to illustrate an example of a technology area in which some of the implementations described in the present disclosure may be implemented. SUMMARY

[0006] In one embodiment, a data accelerator includes an interface connection for receiving data to be processed from a host controller. The data accelerator includes one or more data transformation engines, each individually configured to perform a particular, at least one, data transformation operation on the data. The data accelerator includes a queuing system for determining a processing path of the data from the interface connection and through the one or more data transformation engines. The one or more data transformation engines are individually configured to forward the data to a next machine via the processing path.

[0007] In another example, a method comprises obtaining data to be processed with at least one data transformation operation. The method further comprises determining a processing path for the data that passes through at least a first data transformation engine and a second data transformation engine. The method also comprises passing the data to the first data transformation engine. The first data transformation engine is to perform a first data transformation operation on the data. The method further comprises passing the data to the second data transformation engine, wherein the second data transformation engine is to perform a second data transformation operation on the data.

[0008] The objects and advantages of the embodiments will be realized and attained by at least the elements, features, and combinations particularly pointed out in the claims.

[0009] Both the foregoing general description and the following detailed description are exemplary and are intended to illustrate and not to limit the invention as claimed. DESCRIPTION OF THE DRAWINGS

[0010] Exemplary implementations are described and explained in more detail using the attached drawings in which they are shown: Fig. 1 shows an exemplary environment of a network processing system with a distributed hardware architecture; Fig. Figure 2 shows an example of the flow of multiple packets through a network processing system with a distributed hardware architecture; Fig. 3 shows a flowchart of an exemplary method for network processing using a distributed hardware architecture; Fig. 4 shows a schematic representation of a computer in the exemplary form of a computing device; Fig. 5 shows an exemplary data conversion accelerator using a distributed hardware architecture; and Fig. 6 shows a flowchart of another example of a method for network processing using a distributed hardware architecture. DETAILED DESCRIPTION

[0011] Some existing network processing systems aim to improve one or more aspects of network processing (e.g., higher performance, utilization-based scaling, interoperability, functional flexibility, energy efficiency, and / or cost), but these improvements may come at the expense of other aspects of network processing. Two existing approaches, for example, are a hardware pipe architecture (HPA) and a firmware distributed architecture (FDA).

[0012] The HPA system can be arranged as a pipe or as a processing sequence that may include a physical pipe. The HPA system can be arranged so that incoming packets can be received at incoming ports and processed sequentially by a series of processing components included in the HPA system. All packets pass through each of the processing components, taking into account which processing operations may or may not be applied to each of the packets. The HPA system can therefore have a simple structure that is efficient in terms of the amount of hardware used for the processing operations, the connectivity between the processing components (and the incoming ports), and the overall complexity of the HPA system.

[0013] Disadvantages of the HPA approach include pipe and / or architectural redesign when a new processing stage is added; rigid packet flow through the processing components due to the pipe design of HPA systems, which may result in high processing overhead and / or long processing time even for small operations (e.g., a single packet requiring a second classification operation must be passed through all processing components of the HPA system for the single classification operation); and / or scaling of the HPA may require redesign and / or duplication of the processing components, increasing the hardware components and / or associated costs.

[0014] Furthermore, sharing resources that can be used in processing components may not be possible between HPA systems. In cases where a first HPA system contains a high-performance processing component (e.g., a high-performance classifier) ​​and a second HPA system contains a similar but less powerful processing component, the second HPA system may not be able to utilize the high-performance processing component because the high-performance processing component may be restricted to use in the first HPA system.

[0015] The FDA system can be configured as a hub-like system, with one or more central processing units (CPUs) configured to receive incoming traffic, and each CPU can perform most or all of the processing for a specific packet. There is no need to follow a rigid sequence of steps when processing packets (e.g., since there is no pipe like in the HPA system), and the FDA system can be scaled up or down as needed.

[0016] A disadvantage of the FDA system is the amount of hardware required to perform its operations (especially compared to the HPA system described here). This amount of hardware may increase the costs associated with processing packets in the FDA system, e.g., measured in terms of the area of ​​the HPA system (e.g., the cost of the physical components) and / or the power consumed by the HPA system components. Alternatively or additionally, the components (e.g., the CPUs) in the FDA system may be less suitable for conserving power, as turning the CPUs on and off may be at least an order of magnitude slower than the hardware components in the HPA system. For example, turning a CPU on and off (in an FDA system) may take approximately 25 microseconds, while turning a processing component (in an HPA system) takes approximately 2 microseconds, so a larger buffer may also be required for the FDA system.

[0017] In general, the HPA approach and the FDA approach may experience one or more challenges related to scalability (including development time and integration of new components / CPUs), interoperability (e.g., packets from Ethernet devices, Wi-Fi devices, Data over Cable Service Interface Specification (DOCSIS) devices, Passive Optical Network (PON) devices, etc.), functional flexibility (e.g., impact on operational availability with regard to changes to the system), and / or cost (e.g., impact of scaling up or down in terms of power, area, and / or speed), as described here.

[0018] In some aspects of the present disclosure, a network processing system may include multiple packet processing components connected to a system communications channel. Further, the network processing system may include a queuing system that may receive packets (e.g., using one or more access ports), determine a processing path for the packets through the multiple packet processing components, and individually transmit portions of the processing path to the multiple packet processing components. As such, the network processing system of the present disclosure may be configured to scale up and down by adjusting the number of packet processing components, which may result in improved performance, reduced cost, and / or functional flexibility.Alternatively or additionally, the packet processing components of the network processing system can perform packet processing operations (as opposed to individual CPUs), which can result in a performance improvement compared to some previous approaches described above.

[0019] Fig. 1 illustrates an exemplary network processing system 100 (or system 100) employing a distributed hardware architecture (HDA) in accordance with at least one embodiment of the present disclosure. System 100 may include access ports 110, a buffer 115, a queuing system 120, a forward-looking packet processing component 125, output ports 130, a first packet processing component 135a, a second packet processing component 135b, a third packet processing component 135c, a fourth packet processing component 135d, a fifth packet processing component 135e, collectively referred to as packet processing components 135, a system communication channel 140, and an external communication channel 145.

[0020] The system communication channel 140 may be coupled to one or more of the components included in the system 100 and facilitate communication between the components, which may include the transfer of data and / or packets between the components. The system communication channel 140 may be, for example, a bus (e.g., a main interconnect bus), a crossbar, and / or a network-on-a-chip (NOC). For example, the access ports 110, the buffer 115, the queuing system 120, the output ports 130, and the packet processing components 135 may be interconnected (and configured to transmit data and / or packets) via the system communication channel 140.

[0021] The access ports 110 may be configured to receive incoming packets that may be generated by one or more packet generation systems 105. The combination of the access ports 110 and the packet generation systems 105 may be referred to as an interface connection, as this combination may form an interface between the system 100 and the systems and / or devices that generate the packets used in the system 100.

[0022] Packet generation systems 105 may include one or more systems or devices that can generate and / or forward packets that system 100 receives via access ports 110. Packet generation systems 105 may include an Ethernet device, a Wi-Fi device, a Data over Cable Service Interface Specification (DOCSIS) device, a Passive Optical Network (PON) device, and / or other packet-generating systems or devices. System 100 may include dedicated access ports 110 that may correspond to packet generation systems 105. For example, a first access port may be configured to receive packets from an Ethernet device, a second access port may be configured to receive packets from a Wi-Fi device, and so on.

[0023] The access ports 110 can be configured to support the reception of a predetermined number of packets per second. For example, a first access port of the access port 110 can support the reception of approximately 100,000 packets per second. In cases where the number of packets to be received by the system 100 exceeds the capabilities of the first access port (e.g., more than 100,000 packets per second), one or more additional access ports can be added to the access ports 110 to support the additional packets.

[0024] When the access ports 110 receive packets from the packet generation system 105, the access ports 110 may instruct the packets to be stored in the buffer 115. While the received packets are stored in the buffer 115, the access ports 110 may assign a descriptor (e.g., a packet descriptor) to each received packet, where the packet descriptor may be used to route the received packet through the system 100, such as to the queuing system 120 and / or to the subsequent packet processing components 135 (e.g., a subsequent packet processing component), as described herein. The queuing system 120 may receive the packet descriptor associated with the received packet from the access ports 110 and determine a processing path for the packet through the system 100, as described herein. A packet descriptor may be created at any time, including when a packet is introduced into the system 100.For simplicity, we refer to a “packet descriptor” here, and it is understood that any type of descriptor can be used for any purpose within the scope of this disclosure.

[0025] Alternatively or additionally, the received packets may be received from a portion of the queuing system 120, where the queuing system 120 may determine a processing path for the packet through the system 100, as described herein. Alternatively or additionally, the received packets may be received from an individual packet processing queue associated with the packet processing components 135, where the received packets may be retrieved from the individual packet processing queue and processed by the associated packet processing components 135. In general, the queuing system 120 may be a single component (e.g., as the queuing system 120 in Fig. 1), may be included as logical portions of packet processing components 135 and / or may be a combination of both. For example, queuing system 120 may be a single component to perform a first operation on a particular packet (e.g., a learning operation and / or determining a packet descriptor associated with the particular packet), and queuing system 120, included as a logical portion of packet processing components 135, may perform a second operation on the particular packet, such as determining a subsequent packet descriptor to route the particular packet through system 100.

[0026] Buffer 115 may include any storage device that can be used to store the packets received from access ports 110. For example, buffer 115 may be a database in which the packets are stored until they are processed by one or more of the packet processing components 135 within system 100 and subsequently transferred to and out of system 100 at output ports 130. Output ports 130 may include connections to other devices that can use the processed packets, such as hardware devices, processing devices, and the like. For example, output ports 130 may provide direct memory access to one or more subsystems so that the one or more subsystems can receive the packets processed by system 100.

[0027] Queue system 120 may include at least one queue manager and one buffer manager. The buffer manager may allocate one or more memory buffers (e.g., pools of memory buffers) and / or allocate the memory buffers to packet processing components 135 based on various rules. For example, the buffer manager may allocate a first number of memory buffers to a first packet processing component based on a first policy associated with the first packet processing component, and the buffer manager may allocate a second number of memory buffers to a second packet processing component based on a second policy associated with the second packet processing component. In another example, the buffer manager may allocate one or more memory buffers to one or more packet processing components based on a policy of system 100.Furthermore, the queue manager may be configured to store the packet descriptor and the associated received packet as a linked list so that operations associated with the packet descriptor can be attributed to the associated packet.

[0028] The queue manager of queuing system 120 may be configured to access the packet descriptor associated with a particular packet when packet processing components 135 perform operations on the packet. For example, for a particular packet processing component, the queue manager may access the packet descriptor associated with the packet a first time to determine a particular packet processing component to which the particular packet should be forwarded (e.g., as part of the packet received by the particular packet processing component), and the queue manager may access the packet descriptor a second time to write a new packet descriptor (which may be used, for example, to route the particular packet to a subsequent packet processing component).

[0029] In cases where the number of packets processed by system 100 meets a threshold with respect to the queue manager included in queuing system 120 (e.g., the rate of packets to be processed is a threshold greater than the rate the queue manager can handle, or the rate of packets to be processed is a threshold less than the rate the queue manager can handle), the number of queue managers in queuing system 120 may be scaled up or down accordingly. In cases where another queue manager is added to queuing system 120, the multiple queue managers may be distributed laterally or vertically, where the distribution (e.g., laterally or vertically) may be programmable by an operator (e.g., a user) of system 100.

[0030] For example, lateral distribution may assign a first queue manager to perform operations with respect to a first group of packet processing components 135 (e.g., first packet processing component 135a and second packet processing component 135b) and may assign a second queue manager to perform operations with respect to a second group of packet processing components 135 (e.g., third packet processing component 135c, fourth packet processing component 135d, and fifth packet processing component 135e). In another example, vertical distribution may facilitate packet processing components 135 to receive packets using either a first queue manager or a second queue manager, allowing packet processing components 135 to use multiple queues to receive packets for processing.

[0031] Some packets received by system 100 (e.g., a new packet received via access ports 110) may not have a known processing path through system 100. The processing path may describe the route a particular packet takes through system 100, including the packet processing components 135, by which the packet may be processed before leaving the system via output ports 130. The processing path may include instructions for the packets to a particular one of the packet processing components 135, e.g., using the packet descriptor, after which the packet processing components 135 may update the packet descriptor to direct the packet to a subsequent packet processing component and / or to output ports 130.In cases where a packet does not contain a processing path, the queuing system 120 may receive the packet via a learning queue and perform an analysis of the packet to determine the processing path through the system 100 for the packet, e.g., to a particular packet processing component. The particular packet processing component may then determine a subsequent packet processing component, and so on.For example, the queuing system 120 may determine that operations to be performed on a first packet may be performed by the first packet processing component 135a, the first packet processing component 135a may determine that subsequent processing may be performed by the second packet processing component 135b, and the second packet processing component 135b may determine that subsequent processing may be performed by the fifth packet processing component 135e, such that the queuing system 120 and the packet processing components 135 may determine a processing path for the first packet.

[0032] In these and other embodiments, packet processing components 135 may individually include a processing rules table (e.g., a lookup table) that may be used to determine a subsequent packet processing component based on the results of the processing performed therein. The processing rules table may be customizable, e.g., based on a particular packet stream, changes to system 100, changes determined by queuing system 120, etc. Alternatively or additionally, the lookup table in packet processing components 135 may be updated based on instructions received from queuing system 120.

[0033] The learning queue may store packets received via the access ports 110 that do not yet have a processing path, for example, when a new packet stream is received by the system 100. The learning queue may be used by the system 100 to determine how to process the packets contained in a particular packet stream. For example, a first packet and a second packet may be retrieved from a first packet stream via the access ports 110 and stored in the learning queue (since neither the first nor the second packet may have a processing path).Queuing system 120 may receive the first packet (or a packet descriptor associated with the first packet, as described herein) from the learning queue, determine an associated processing path for the first packet, and queue the first packet based on the processing path. Queuing system 120 may then be configured to perform queuing operations on the second packet based on the learning performed on the first packet of the first stream.

[0034] In general, queuing system 120 may include at least one computing device that may be configured to perform the operations described herein with respect to queuing system 120. Throughout the present disclosure, reference to queuing system 120 performing an operation may be made using the computing device included therein, unless otherwise described. Queuing system 120 may determine a processing path for each packet descriptor that may be associated with each packet received by system 100.For example, a first packet descriptor may be associated with a first packet, a second packet descriptor with a second packet, and a third packet descriptor with a third packet, and queuing system 120 may determine a first processing path corresponding to the first packet descriptor, a second processing path corresponding to the second packet descriptor, and a third processing path corresponding to the third packet descriptor. In some embodiments, a single packet descriptor may be used for more than one packet and / or for a group of packets.

[0035] While the queuing system 120 determines the processing paths for the packet descriptors associated with the packets, the queuing system 120 may transmit at least a portion of a particular processing path to the packet processing components 135 that may be included in the particular processing path. For example, in cases where a first packet descriptor contains a processing path that includes a route from the first packet processing component 135a to the second packet processing component 135b and the fourth packet processing component 135d, the queuing system 120 may transmit the following instructions to the corresponding packet processing components: • to the first packet processing component 135a: Upon completion, a packet associated with the first packet descriptor should be forwarded to the second packet processing component 135b; • to the second packet processing component 135b: upon completion, a packet associated with the first packet descriptor should be forwarded to the fourth packet processing component 135d; and • to the fourth packet processing component 135d: Upon completion, a packet associated with the first packet descriptor should be forwarded to the output ports 130.

[0036] In such cases, the queuing system 120 may direct the processing flow of the packets by transmitting instructions corresponding to the packet descriptors associated with the packets to the packet processing components 135. Following packet processing operations performed by the packet processing components 135, the packet processing components 135 may update the packet descriptors to forward the packets to subsequent packet processing components. Therefore, each particular packet may be forwarded to an appropriate packet processing component according to the associated packet descriptor, and / or the processing path associated with a particular packet may be updated as needed or desired by the queuing system 120 and / or the packet processing components 135 updating the processing flow.In cases where the queuing system 120 determines process flow updates, the queuing system 120 may transmit the instructions to the packet processing components 135 as described. In general, the instructions transmitted from the queuing system 120 to the packet processing components 135 may be a lookup table, elements of a lookup table, and / or other stored instructions to instruct a particular packet processing component to route a packet to a subsequent packet processing component of the packet processing components 135 and / or the output ports 130.

[0037] Using the described processing path, the queuing system 120 may be configured to route some packets along a specific path through the system 100 (e.g., through the packet processing components 135). Furthermore, in cases where multiple packet processing components are configured to perform the same or a similar packet processing operation as in the system 100, the processing path determined by the queuing system 120 may route a specific packet to a specific packet processing component and / or perform operations in an order (e.g., bypassing a sequencing operation), which may reduce processing operations compared to existing approaches (e.g., HPA and FDA).For example, in cases where multiple first packet processing components 135a are included in the system 100 (and may vary in their capabilities), the processing path may route a particular packet to a more powerful first packet processing component 135a as opposed to a less powerful first packet processing component 135a, which may be based on the availability of the first packet processing components 135a, a priority of the particular packet relative to other packets, etc.

[0038] The packet processing components 135 can be individually configured to perform a packet processing operation on the received packets. For example, the packet processing components 135 can be configured to perform a parsing operation, a classification operation, a measurement operation, a sequencing operation, a modification operation, and / or other packet processing operations. The packet processing components 135 can be configured to retrieve packets from a queue, for example, a queue individually associated with the packet processing operation. For example, the first packet processing component 135a, which performs a parsing operation as the packet processing operation, can retrieve packets from a first queue (e.g.,a parsing queue), the second packet processing component 135b, which performs a classification operation as the packet processing operation, may retrieve packets from a second queue (e.g., a classification queue), and so on.

[0039] In some embodiments, the packet processing components may obtain a packet on which a packet processing operation is to be performed from an associated queue based on the packet processing operation. For example, the first packet processing component 135a, which may be configured to perform a parsing operation, may obtain a packet from a parsing queue, and a second packet processing component 135b, which may be configured to perform a classification operation, may obtain a packet from a classification queue.

[0040] Alternatively or additionally, in cases where more than one similar packet processing component configured to perform a particular packet processing operation (e.g., a first packet processing component 135a and a second packet processing component 135a, both configured to perform a parsing operation) are present in system 100, the similar packet processing components may be configured to operate on a common queue. For example, a first parsing component and a second parsing component may be configured to use a parsing queue to receive packets for processing (e.g., to perform a parsing operation on them).

[0041] In general, the packet processing components 135 can be scaled up or down, e.g., with regard to their utilization and / or system requirements. For example, in cases where the first packet processing component 135a is unable to process packets at a rate equal to or greater than the rate at which packets are sent to the first packet processing component 135a, the queuing system 120 can determine that a second first packet processing component 135a can be added to the system 100 to increase the packet processing operations associated with the first packet processing component 135a. The number of packet processing components 135 can be scaled up (e.g., more packet processing components) or down (e.g., fewer packet processing components) as determined by the queuing system 120, such as with regard to the utilization of one of the packet processing components 135.

[0042] In cases where the packet processing components 135 are scaled up or down, the queuing system 120 may be configured to re-regulate the power for a particular packet processing component. For example, in cases where a utilization limit associated with a particular packet processing component indicates that the particular packet processing component is under-utilized (e.g., the number of packets processed by the particular packet processing component is below a threshold rate relative to a maximum number of packets that can be processed by the particular packet processing component), the queuing system 120 may instruct the removal of the power provided to the particular packet processing component, such that the particular packet processing component may be inoperable.

[0043] In another example, in cases where a utilization limit associated with a first packet processing component indicates that the first packet processing component is overloaded (e.g., the number of packets processed by the first packet processing component is above a threshold rate relative to a maximum number of packets that can be processed by the first packet processing component), the queuing system 120 may instruct that power be supplied to a second packet processing component so that the second packet processing component is operational and can begin processing packets in conjunction with the first packet processing component.

[0044] In general, the utilization limit may be preprogrammed (e.g., prior to packet processing operations) or the utilization limit may be reprogrammed, e.g., by a user via a user interface. For example, the user may determine that power readjustments are occurring more frequently than desired (or more frequently than necessary to meet a desired efficiency or other metric), and the user may reprogram the utilization limit to a higher (or lower) value via a user interface and the queuing system 120. For example, the user may set a new utilization limit, enter the new utilization limit into the queuing system 120 via the user interface, and the queuing system 120 may write the new utilization limit to the packet processing components 135.

[0045] The following is an example system illustrating the power management of system 100 compared to an HPA system. The example system may include eight access ports, each of the access ports configured to support 10G transmissions. Thus, the example system may support 80G (e.g., 8 * 10G = 80G). Furthermore, the example system may include a first port with 100% capacity and second through eighth ports, each with 5% capacity. The load of the example system represented as data may be 13.5G (e.g., 10G + 7 * 10G * 5% = 13.5G), and the load of the example system represented as a percentage of the maximum load may be approximately 17% (e.g., 13.5G / 80G). Assuming that in the example system each port can handle 10G speeds, the example system includes five packet processing components, and each of the packet processing components has equivalent performance (e.g.10 mW), a comparison can be made between an HPA implementation and an HDA system similar to System 100. For example, the power consumption of an HPA system might be approximately 400 mW, determined based on the eight ports, the five functions, and the 10 mW per function (e.g., 8 * 5 * 10 mW = 400 mW). In another example, an HDA system might be approximately 100 mW, determined based on two ports (e.g., two ports would deliver 20 G, which is greater than the example system's 13.5 G load), the five functions, and the 10 mW per function (e.g., 2 * 5 * 10 mW = 100 mW). The HDA system is designed to reduce power consumption compared to HPA systems (and other existing solutions) by enabling and disabling ports, processing components, and / or other aspects of the system as needed, e.g., based on the usage of system components.

[0046] In these and other embodiments, packet processing components 135 configured to perform the same or a similar packet processing operation (e.g., multiple parsing components) may be arranged to share resources with each other. Shared resources may include, but are not limited to, databases, lookup tables, settings tables, buffering devices, and / or other resources. For example, multiple packet processing components may be configured to share a common queue for packet processing, and / or instructions received in connection with a lookup table for forwarding processed packets may be shared among packet processing components 135 performing the same or a similar packet processing operation.

[0047] The queues associated with packet processing components 135 may be configured to receive packets that may be moved from access ports 110, buffer 115, queuing system 120, and / or packet processing components 135 (e.g., after a packet processing operation performed by a first packet processing component, the first packet processing component may move the packet to a queue associated with a second packet processing component). As described herein, the packets may be generated from various sources, such as Ethernet devices, Wi-Fi devices, DOCSIS devices, and / or PON devices. In such cases, packet processing components 135 may be configured to perform the packet processing operation for a received packet regardless of the source of the packet.For example, in cases where the first packet processing component 135a performs an analysis operation (), the first packet processing component 135a may perform the analysis operation on a first packet generated with an Ethernet device and / or on a second packet generated with a DOCSIS device.

[0048] A particular packet processing component of the packet processing components 135 may send a ready signal to the queuing system 120 to indicate that the particular packet processing component is ready for a packet on which the packet processing operation is to be performed. In response to the ready signal, the queuing system 120 may forward a packet to the particular packet processing component (e.g., the packet may be forwarded from a packet processing queue specific to the particular packet processing component, or the packet may be forwarded from a default queue that may be stored in the buffer 115).

[0049] The packet processing components 135 may individually include a storage portion that can be used to store one or more packets to be processed by the packet processing components 135. Alternatively or additionally, the packet processing components 135 may individually store the packet descriptors associated with the packets, and a separate storage device may store the packets (e.g., the buffer 115, the external devices 150, and / or other storage devices). The storage portion may be configured to store multiple packets and / or packet descriptors, the number of which may be known to the queuing system 120. For example, the queuing system 120 may send a request to a packet processing component to respond with a number of packets equal to the number of packets that can be stored by the packet processing component.Furthermore, the packet processing components 135 may individually use the packet count to determine when to transmit the ready signal to the queuing system 120, e.g., when a threshold related to the packet count is met. For example, in cases where the packet count associated with a particular packet processing component is X, the particular packet processing component may transmit the ready signal to the queuing system 120 when a threshold of X2 is met. Using the packet count and the associated threshold, a packet processing component may be configured to maintain a constant flow of packets to be processed, which may improve the throughput and / or efficiency of the packet processing component and / or system 100. The threshold associated with determining when to transmit the ready signal may be predetermined or preprogrammed in the packet processing components 135. Alternatively or additionally, a user of system 100 may be able to adjust the threshold, e.g., via a user interface and queuing system 120, to reconfigure the threshold.

[0050] In cases where multiple packet processing components are available to perform a packet processing operation, each of the multiple packet processing components may send a ready signal to the queuing system 120, and the queuing system 120 may send a packet to each of the multiple packet processing components to perform the packet processing operation. In such cases, the queuing system 120 may be responsible for sending packets to the multiple packet processing components, which may reduce or eliminate race conditions between the multiple packet processing components receiving packets. Such circumstances may exist when the system 100 is a stateless system, such that the processing of certain packets may not depend on the processing of previous packets. In cases where the system 100 is not stateless (e.g.,a stateful system in which the processing of certain packets depends on the processing of previous packets), a sequencing operation may be performed on the packets, e.g., by a sequencing component and / or portions of the packet processing components 135, as described herein.

[0051] Alternatively or additionally, the respective packet processing component may pull a packet from the queue (e.g., either from the packet processing queue or from the default queue) when the respective packet processing component is available to perform packet processing. In cases where multiple packet processing components are available to perform a packet processing operation, each of the multiple packet processing components may pull a packet from the queue as soon as the packet processing component is available to perform the packet processing operation.

[0052] The packet processing components 135 may be configured to perform an associated packet processing operation on a received packet. Upon completion of the packet processing operation, the packet processing components 135 may generate a process result. The process result may be a vector that provides instructions for forwarding the packet to a next packet processing queue. For example, upon completion of a packet processing operation, the first packet processing component 135a may generate a process result that may instruct forwarding the packet to a subsequent packet processing component, such as the third packet processing component 135c (e.g., the packet processing queue associated with the third packet processing component 135c), based on the packet descriptor and / or the processing path associated with the packet.The instructions for forwarding the packet from the first packet processing component 135a to the third packet processing component 135c based on the packet descriptor and / or the processing path may be obtained from the queuing system 120, as described herein.

[0053] The vector may contain the process result and an error code. The error code may be generated as a result of the packet processing operation and may provide an indication of unexpected operations and / or results associated with the packet and the packet processing operation. The error code may be used to determine packets to discard, to provide debug information related to the packets, to determine a subsequent processing path for the packets, and / or other operations associated with the flow of packets through system 100. In some cases, the vector may be a concatenation of the error code and the process result.

[0054] In general, packet processing components 135 may include a lookup table that can be used to forward a packet to a subsequent packet processing component or the output ports 130. The lookup table may be programmable with respect to the packet descriptor and / or the processing path, e.g., by the queuing system 120. For example, after determining the processing path for a packet (e.g., using the packet descriptor, as described herein), the queuing system 120 may transmit instructions to the packet processing components 135, where the instructions may be used to program the lookup table. The programmed lookup table may then be used by the packet processing components 135 to forward packets to a subsequent packet processing component or the output ports 130, as described herein.

[0055] The vector generated during the packet processing operation can be compared to the lookup table to determine where the packet can be forwarded. In cases where the vector does not match a subsequent destination (e.g., a packet processing component 135 or the output ports 130), the packet may be forwarded to a default queue, where the queuing system 120 can determine the subsequent destination for the packet. The default queue may be stored in buffer 115 and / or another storage device and may be managed by the queuing system 120 to forward packets that could not be successfully forwarded using the functionality described herein.

[0056] The future-proof packet processing component 125 may be an example of one or more additional packet processing components that may be added to the system 100 in response to the need or desire to support additional packet processing operations. For example, in cases where the system 100 is to support the encryption and / or decryption of packets, an encryption / decryption packet processing component may be added as the future-proof packet processing component 125. In such cases, the encryption / decryption packet processing component may be connected to the system communication channel 140, maintain a queue for packet processing operations (e.g.,the queuing system 120 may create and / or allocate a queue for encryption / decryption packet processing operations), and then the future-proof packet processing component 125 (e.g., the encryption / decryption packet processing component) may be commissioned to perform encryption / decryption packet processing operations within the system 100.

[0057] The system 100 may be included as part of an electronic chip, such as a microchip, an integrated circuit, etc., where the electronic chip may include one or more processing devices, processing units, motors, systems, etc., which may be generally referred to as external devices 150. In some cases, the system 100 may use the external communication channel 145 to transmit and / or receive data from the external devices 150. For example, in cases where the system 100 includes encryption as a packet processing operation and the electronic chip includes an encryption engine as the external device 150, the system 100 may use the external communication channel 145 to transmit a packet to the external device 150 (e.g., the encryption engine), and the system 100 may receive an encrypted packet (e.g.,the packet processed by the encryption engine) from the external device 150 via the external communication channel 145.

[0058] As described herein, the queuing system 120 may include a user interface that provides a user with an interface for setting various thresholds associated with the system 100 and / or the operations performed by the system 100. Alternatively or additionally, the user interface may provide a visualization and / or description of one or more states associated with the system 100 and / or the components included in the system 100, such as the packet processing components 135. For example, the user interface associated with the queuing system 120 may enable the user to pause the system 100 through user input, pause the operations performed by the queuing system 120, view the packet processing components 135 to determine utilization (e.g.,B, number of packets processed per time) and / or packet processing therein, insert artificial packets and / or packet descriptors into the system 100 (e.g., into one or more of the packet processing components 135), determine whether any of the packet processing components 135 may be limited in functionality (e.g., reduced processing speed, paused operations, etc.), and the like. Thus, the user interface may enable a user to obtain statistics associated with the system 100, including the queuing system 120, the packet processing components 135, and / or other portions of the system 100.Alternatively or additionally, the user interface may enable a user to perform troubleshooting operations on the system 100 and / or components of the system 100 using one or more of the aforementioned operations available to the user via the user interface.

[0059] Some packets received by system 100 may include ordering requirements associated with the packets and / or associated packets. For example, Ethernet packets must be ordered during transmission. System 100 may be configured to perform out-of-order processing, where packet processing components 135 may process a packet that may be out of order relative to other associated packets (e.g., the packets may be Ethernet packets that require ordering after processing by system 100). As such, system 100 may include a packet processing component configured to perform sequencing of the packets. The sequencing component may be one of packet processing components 135, future-proof packet processing component 125, and / or one of external devices 150.In cases where multiple packet processing components 135 may be configured to perform the same packet processing operation (e.g., multiple parsing components), the sequencing component may be included in the grouping of the multiple packet processing components 135 (e.g., in one of the multiple packet processing components 135 and / or distributed among the multiple packet processing components 135) and may be configured to perform sequencing operations therein.

[0060] The sequencing component can receive the packets (to be sequenced) and reorder the packets as needed using a port number and a sequence number that can be assigned to the packets. The port number and / or sequence number can be assigned to the packets by the queuing system 120 (e.g., the buffer manager or the queue manager) when they are received at the access port 110. Thus, the sequencing component can reorder the packets as needed and output the reordered packets to the output ports 130.

[0061] The sequencing component may be configured to perform sequencing based on a maximum latency of the system 100. In cases where the system 100 (e.g., the buffer 115) contains N jobs, the sequencing component may reorder N jobs in the worst case.

[0062] Changes, additions, or omissions may be made to the system 100 without departing from the scope of the present disclosure. The names of the various elements as described are for illustrative purposes only and are not limiting. Furthermore, the system 100 may include any number of other elements or be implemented in systems or contexts other than those described. For example, each of the components of Fig. 1 be divided into additional components or combined into fewer components.

[0063] Fig. 2 shows an exemplary flow 200 of multiple packets through a network processing system using a distributed hardware architecture, in accordance with at least one embodiment of the present disclosure. The flow 200 may be executed by processing logic that may include hardware (circuitry, dedicated logic, etc.), software (such as executing on a general-purpose computer system or a dedicated machine), or a combination of both, where the processing logic may be included in any computer system or device, such as the queuing system 120 of Fig. 1.

[0064] For simplicity, the methods described herein are illustrated and described as a series of acts. However, the acts according to this disclosure may occur in different orders and / or concurrently, as well as with other acts not illustrated and described herein. Further, not all illustrated acts may be used to perform the methods according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that the methods may alternatively be represented as a series of interconnected states via a state diagram or events. Furthermore, the methods disclosed in this specification may be stored on an article of manufacture, such as a non-transitory computer-readable medium, to facilitate the transport and transfer of such methods to computing devices.The term "article of manufacture," as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage medium. Although represented as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0065] In block 202, a first packet and a second packet may be transmitted via one or more access ports (e.g., the access ports 110 of Fig. 1). The first packet can be retrieved via a first access port, and the second packet can be retrieved via the first access port or a second access port.

[0066] In block 204, a first processing path for the first packet and a second processing path for the second packet may be determined. The first processing path may be different from the second processing path. For example, the first processing path may include a first packet processing component (e.g., one of the packet processing components 135 of Fig. 1), a second packet processing component and a third packet processing component (including the order of the packet processing components), and the second processing path may include the second packet processing component, the first packet processing component, and a fourth packet processing component.

[0067] At block 206, the first packet may be added to a first queue based on the first processing path, and the second packet may be added to a second queue based on the second processing path. The first queue may be associated with the first packet processing component, and the second queue may be associated with the second packet processing component. In general, each of the packet processing components may include a queue associated with it.

[0068] In block 208, a first packet processing operation for the first packet may be performed by the first packet processing component and a second packet processing operation for the second packet may be performed by the second packet processing component.

[0069] In block 210, it is determined whether additional packet processing operations should be performed for the first packet and / or the second packet based on the first processing path and the second processing path, respectively. For example, the last packet processing operation performed on the packet was the last packet processing operation included in the processing path. In cases where additional packet processing operations (with respect to the first packet and / or the second packet) need to be performed, flow 200 may continue to block 206. In cases where no further packet processing operations need to be performed, flow 200 may continue to block 212.

[0070] In block 212, the packets whose processing is complete (e.g., the first packet and / or the second packets) may be sent to one or more output ports (e.g., the output ports 130 of Fig. 1). The output ports can be used to transmit the packets to other systems or devices and / or be available for other operations, such as direct memory access.

[0071] Changes, additions, or omissions may be made to flow 200 without affecting the scope of the present disclosure. The designations of the various elements as described are for illustrative purposes only and are not limiting. Furthermore, flow 200 may include any number of other elements or be implemented in systems or contexts other than those described.

[0072] Fig. 3 shows a flow diagram of an exemplary method 300 for network processing using a distributed hardware architecture according to at least one embodiment of the present disclosure. The method 300 may be performed by processing logic that may include hardware (circuitry, dedicated logic, etc.), software (such as executing on a general-purpose computer system or a dedicated machine), or a combination of both, with the processing logic being embodied in any computer system or device, such as the queuing system 120 of Fig. 1 may be included.

[0073] In block 302, a first packet may be received from a queuing system. In some embodiments, a first packet descriptor may be assigned to the first packet. The first packet may be received from an Ethernet device, a Wi-Fi device, a Data over Cable Service Interface Specification (DOCSIS) device, or a Passive Optical Network (PON) device.

[0074] In block 304, a processing path for the first packet through the queuing system may be determined. Alternatively or additionally, in cases where a first packet descriptor is associated with the first packet, a processing path for the first packet descriptor may be determined. The processing path may include traversing at least one first packet processing component. In some embodiments, the first packet may be received in a learning queue as part of determining the processing path. Further, the processing path for the first packet may be determined by the queuing system, wherein the processing path may include at least a first section and a second section.

[0075] In some embodiments, the first portion and the second portion may be transmitted to the respective packet processing components. For example, the first portion may be transmitted to the first packet processing component and the second portion may be transmitted to a second packet processing component.

[0076] In some cases, the first packet may be routed by the first packet processing component to the second queue of the packet processing component using the first portion of the processing path. Furthermore, after the second packet processing operation, the first packet may be routed by the second packet processing component to an output port using the second portion of the processing path.

[0077] In some cases, the first packet may be received from an access port. The input port may assign a first packet descriptor to the first packet, and the first packet may be transmitted to the queuing system. The queuing system may be configured to read the packet descriptor and forward the first packet to the first queue at a first time before the first packet processing operation. Alternatively or additionally, the queuing system may be configured to change the packet descriptor for the first packet at a second time after the packet processing operation.

[0078] In block 306, the first packet may be forwarded to a first queue of the first packet processing component based on the processing path.

[0079] In block 308, the first packet processing component may perform a first packet processing operation for the first packet. Alternatively or additionally, the first packet processing component may determine a second packet processing component to which the first packet may be forwarded.

[0080] In block 310, the first packet may be forwarded to a second queue of the second packet processing component based on the processing path.

[0081] In block 312, the second packet processing component may perform a second packet processing operation for the first packet.

[0082] In some embodiments, processing statistics of the first packet processing operation and the second packet processing operation may be obtained by the queuing system. In response to the processing statistics associated with the first packet processing component satisfying a first utilization limit, the power supply to the first packet processing component may be re-regulated by the queuing system. Alternatively or additionally, in response to the processing statistics associated with the first packet processing component satisfying a second utilization limit, the power supply to a third packet processing component may be re-regulated by the queuing system.

[0083] Changes, additions, or omissions may be made to the method 300 without affecting the scope of the present disclosure. The designations of the various elements as described are for illustrative purposes only and are not limiting. Furthermore, the method 300 may include any number of other elements or be implemented in systems or contexts other than those described.

[0084] Fig. 4 shows a schematic representation of a computer in the exemplary form of a computing device 400, in which a set of instructions may be executed to cause the computer to perform one or more of the methods discussed herein. The computing device 400 may include a mobile phone, a smartphone, a netbook computer, a rackmount server, a router computer, a server computer, a personal computer, a mainframe computer, a laptop computer, a tablet computer, a desktop computer, etc., in which a set of instructions may be executed to cause the computer to perform one or more of the methods discussed herein. In alternative embodiments, the computer may be connected (e.g., networked) to other computers on a LAN, an intranet, an extranet, or the Internet. The computer may operate in the capacity of a server in a client-server network environment.The computer may be a personal computer (PC), a set-top box (STB), a server, a network router, a switch or bridge, or any other computer capable of executing a set of instructions (sequential or otherwise) that specify the actions to be performed by that computer. Although only a single computer is illustrated, the term "computer" may also encompass any collection of computers that individually or collectively execute a set (or multiple sets) of instructions to perform one or more of the methods discussed herein.

[0085] The example computing device 400 includes a processing device (e.g., a processor) 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 406 (e.g., flash memory, static random access memory (SRAM)), and a data storage device 416 that communicate with each other via a bus 408.

[0086] Processing device 402 is one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. In particular, processing device 402 may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. Processing device 402 may also include one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 402 is configured to execute instructions 426 to perform the operations and steps discussed herein.

[0087] Computing device 400 may further include a network interface 422 capable of communicating with a network 418. Computing device 400 may also include a display device 410 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 412 (e.g., a keyboard), a cursor control device 414 (e.g., a mouse), and a signal generating device 420 (e.g., a speaker). In at least one embodiment, display device 410, alphanumeric input device 412, and cursor control device 414 may be combined into a single component or device (e.g., an LCD touchscreen).

[0088] The data storage device 416 may include a computer-readable storage medium 424 having stored thereon one or more sets of instructions 426 embodying one or more of the methods or functions described herein. The instructions 426 may also reside entirely or at least partially in the main memory 404 and / or the processing device 402 while being executed by the computing device 400, with the main memory 404 and the processing device 402 also representing computer-readable media. The instructions may further be transmitted or received over a network 418 via the network interface device 422.

[0089] While the computer-readable storage medium 426 is illustrated as a single medium in one embodiment, the term "computer-readable storage medium" may include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable storage medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by the computer, and that causes the computer to perform one or more of the methods of the present disclosure. Accordingly, the term "computer-readable storage medium" may include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0090] Fig. 5 shows an example of a data conversion accelerator 500 using a distributed hardware architecture in accordance with at least one embodiment of the present disclosure.

[0091] In an example implementation, various types of accelerators and / or coprocessors may also benefit from the present disclosure. Data transformation accelerators are coprocessor devices used to accelerate data transformation operations for data analytics, big data, storage, security, and networking applications. Storage and encryption accelerators are examples of such accelerators. The data transformation operations may include (but are not limited to) data compression, decompression, encryption, decryption, authentication tag (MAC) generation, authentication, data deduplication hash generation, and non-volatile memory express protection information (NVMe PI) generation, NVMe protection information verification, and real-time verification.

[0092] Such an accelerator can be connected to a host computer or server platform via PCI Express (PCIe). The accelerator can also be connected via other interface technologies (e.g., USB). The accelerator can be controlled from the host platform by accessing control registers or other mechanisms via the interfaces mentioned above. In the case of PCIe, for example, access to the registers can be via the PCIe Base Address Register (BAR) space.

[0093] An accelerator may contain one or more data transformation engines as computational resources. Algorithm acceleration can be provided by the data transformation engines. Algorithm acceleration can include data transformation operations such as compression, decompression, encryption, decryption, authentication tag (MAC) generation and verification, data deduplication, NVMe PI generation and verification, and real-time verification. The data transformation engines can process the data in a highly parallel manner. A host computer or server can submit commands to the accelerator along with the source data to be transformed. The host computer can also provide control information or metadata describing the specific algorithmic transformation to be applied to the source data.Based on the metadata, the data transformation engines can perform operations on the source data. Once the process is complete, the transformed data can be returned to the host computer via interfaces such as PCIe.

[0094] The data transformation engines may be connected in a pipeline within the accelerator. Alternatively or additionally, the data transformation engines may be distributed and connected via a system communication channel, as in Fig. 5. There may be more than one pipeline, and additional pipelines may operate in a parallel arrangement. In some embodiments, the pipeline may run in an encoding direction or a decoding direction. Alternatively or additionally, in cases where the data transformation engines are not arranged in a pipeline, instructions may allow operations on source data to be performed by the data transformation engines in a pipeline-like manner in either the encoding direction or the decoding direction.

[0095] For example, in a pipeline in the encryption direction, the following operations can be performed using metadata associated with the source data: NVME PI (T10-DIF or T10-DIX) may be verified in the source data; data compression; padding to align compressed data so that the compressed data meets criteria for an encryption algorithm or NVME PI; encryption; insertion and / or generation of NVME PI on the transformed data; calculation of authentication tags generated from the data at a selected position of the pipeline or distributed (circuit) arrangement; calculation of a deduplication hash using one or more hash engines at one or more points in the pipeline or distributed arrangement;and real-time verification (RTV), in which after the input data is encoded, the encoded data is decoded and compared with the input data for error verification.

[0096] The selection of operations for a particular data block can be based on the metadata provided to the accelerator along with the source data. Based on the metadata, one or more operations can be applied to the source data.

[0097] In another example, the following operations may be performed in a pipeline in the decode direction using metadata associated with the encoded data: verification and removal of NVME PI (T10-DIF or T10-DIX) in the encrypted data; decryption; depadding; decompression; insertion and / or generation of NVME PI in the decompressed data; verification of authentication tags at a selected position of the pipeline; and calculation of deduplication hash using one or more hash engines at one or more points in the pipeline.

[0098] In both the encoding and decoding directions, the operations (e.g., as described above) may be performed by the data transformation engines 535. For example, the first data transformation engine 535a may be configured to perform a decryption operation, the second data transformation engine 535b may be configured to perform a decompression operation, etc. The number of data transformation engines 535 may be larger or smaller than in Fig. 5 and may be associated with the various operations performed by the data accelerator 500.

[0099] In one embodiment, a pipeline associated with the data accelerator 500 may include fixed logic between the data transformation engines 535. Alternatively or additionally, some or all of the data transformation engines 535 may be programmable to implement the operations performed by the data transformation engines 535. For example, instead of hard-wired logic between the data transformation engines 535, software-implemented programmable accelerator blocks 537 may be placed between the data transformation engines 535 in a pipeline, implemented with hard-wired logic. In the distributed hardware architecture, the programmable accelerator blocks 537 may be represented as discrete blocks that are placed between the data transformation engines 535 (e.g.,in a pipelined arrangement) and / or implemented following operations performed by the data transformation engines 535 in a distributed arrangement. The programmable accelerator blocks 537 may be a microcontroller or a microprocessor running firmware to process data originating from a previous stage of the pipeline (which may be fixed logic or another software-controlled accelerator block). Alternatively or additionally, the programmable accelerator blocks 537 may send data to the next stage of the pipeline, which may have fixed logic or another software-implemented accelerator block.

[0100] The processing in the programmable accelerator blocks 537 can be implemented entirely in firmware and / or software using a CPU or a microcontroller. Alternatively or additionally, the programmable accelerator blocks 537 can be partially implemented in hardware, and some functions that could potentially change can be implemented in firmware or software. In the case of a data compression block, for example, the dictionary lookup (static or adaptive dictionary) in the compression algorithm can be implemented in fixed logic to generate the tokens, such as length / distance pairs for substring matches, while the lossless encoding of the tokens can be implemented in software or firmware using the Huffman code, asymmetric number systems (ANS), and / or other encoding algorithms.Partial hardware and / or firmware / software implementation may enable efficient resource sharing and / or provide the advantage of using one block for multiple similar algorithms. Optionally, instead of implementing the programmable logic using software or firmware, one or more programmable hardware logic blocks may be used. These may be located on the same chip on which one or more data transformation engines 535 are implemented and / or they may be implemented as a separate chiplet connected via a die-to-die interconnect (e.g., Universal Chiplet Interconnect (UCI) or other technologies). The programmable blocks may perform various transformation operations based on transformation instructions from a host processor.The instruction may optionally contain metadata that can be used to program the programmable data transformation engines 535.

[0101] In another embodiment, the position of the data transformation engines in the pipeline may be changed based on an instruction and metadata associated with the host processor instruction, rather than a predefined pipeline (e.g., a fixed sequence of transformation operation blocks arranged as a pipeline). The position of the data transformation engines 535 within the pipeline may be based on user input. Alternatively or additionally, a subset of data transformation engines 535 may be used. For example, the first data transformation engine 535a and the third data transformation engine 535c may be used in a particular pipeline, while the second data transformation engine 535b and the fourth data transformation engine 535d may not be included in the particular pipeline. Some of the data transformation engines 535 may be implemented in hardware.Alternatively or additionally, some of the data transformation engines 535 may be programmable, e.g., through the use of software, firmware, or programmable hardware logic. For example, the resource management unit 520 may determine a need for a particular data transformation engine and program an existing data transformation engine to perform operations associated with the particular data transformation engine. The configuration / reconfiguration may be performed for each instruction based on the instruction and the metadata associated with each instruction. Alternatively or additionally, the configuration / reconfiguration may be performed for a group of instructions, where the group of instructions may have the same metadata.

[0102] In another embodiment, a pool of data transformation engines 535 may exist within the data accelerator 500 that do not need to be organized a priori. Based on user input (e.g., a command), the data transformation engines 535 may be organized based on metadata associated with the command. The organization of the data transformation engines 535 may be per-command based on the command and / or the metadata associated with each command. Alternatively or additionally, the organization of the data transformation engines 535 may be per-command based on the command and / or the metadata associated with each command. Alternatively, or additionally, the organization of the data transformation engines 535 may be per-command based on a group of commands, where the group of commands may have the same metadata.

[0103] In some embodiments, a scheduling or resource management unit 520 may create various concatenations of data transformation engines on the fly based on one or more optimization criteria. The resource management unit 520 may order the data transformation engines based on the instructions and / or the metadata associated with the instructions. The resource management unit 520 may ensure that there is no structural conflict in the allocation of the data transformation engines 535. In cases where there are not enough data transformation engines 535 available for the outstanding instructions, the resource management unit 520 may prioritize higher-priority instructions to form the concatenation of the data transformation engines 535, and some of the instructions may be pending.The optimization criteria in the resource management unit 520 may be based on the best possible utilization of the hardware resources, correspond to a performance profile, or represent a service level agreement for commands of different classes.

[0104] Fig. 6 shows a flowchart of another example of a method 600 for network processing using a distributed hardware architecture according to at least one embodiment of the present disclosure. The method 600 may be performed by processing logic that may include hardware (circuitry, dedicated logic, etc.), software (such as executing on a general-purpose computer system or a dedicated machine), or a combination of both, with the processing logic being embodied in any computer system or device, such as the queuing system 120 of Fig. 1 or the resource management unit 520 of Fig. 5 may be included.

[0105] In block 602, the processing logic may receive data to be processed with at least one data transformation operation. The at least one data transformation operation refers to at least one of the following operations: data compression, decompression, encryption, decryption, authentication tag (MAC) generation, authentication, data deduplication generation, hash generation, and non-volatile memory express protection information (NVMe PI) generation, NVMe PI verification, or real-time verification. The data may be received from a host controller, with the method being performed by an accelerator. Passing the data to the first data transformation engine may include identifying the first data transformation engine from a pool of data transformation engines.Forwarding the data to the first data transformation engine includes determining a criterion for a transformation command associated with the first data transformation engine and selecting the first data transformation engine based on the determined criterion for the transformation command that exceeds a threshold priority. The determined criteria indicate that the transformation command has a higher priority than a second transformation command, the second transformation command being in a hold state. The determined criteria relate to a performance profile or to the realization of a service level agreement for commands belonging to different classes of commands.

[0106] In block 604, the processing logic may determine a processing path for the data to pass through at least a first data transformation engine and a second data transformation engine. The first data transformation engine is implemented with fixed logic, and the second data transformation engine is implemented as a programmable data transformation engine. The first data transformation engine and the second data transformation engine are implemented on a single die or on a single chip. The first data transformation engine is implemented on a first chiplet, and the second data transformation engine is implemented on a second chiplet.

[0107] In block 606, the processing logic may forward the data to the first data transformation engine. The first data transformation engine may perform a first data transformation operation on the data. The data is passed to the first data transformation engine based on a particular transformation command received from a host controller, wherein the first data transformation engine is configured to execute the particular transformation command. The particular transformation command includes at least one piece of control information or metadata used to pass the data to the first data transformation engine. The control information includes instructions from the host controller related to processing the data. The metadata includes information about one or more types of transformations or transformation commands to be performed on the data.

[0108] In block 608, the processing logic may pass the data to the second data transformation engine. The second data transformation engine may perform a second data transformation operation on the data. The data is passed to the first data transformation engine or to the second data transformation engine based on user input. Passing the data to the first data transformation engine may include passing a first subset of the data to the first data transformation engine. The first data transformation engine is to perform the first data transformation operation on the first subset of the data. Passing the data to the second data transformation engine may include passing a second subset of the data to the second data transformation engine.The second data transformation engine is to perform the second data transformation operation on the second subset of the data. Determining the processing path for the data, which passes through at least the first data transformation engine and the second data transformation engine, may include determining one or more data transformation instructions to be executed based on the control information or the metadata. Routing the data to the first data transformation engine and routing the data to the second data transformation engine may include determining that no structural conflict occurs in a mapping between the first data transformation engine and the second data transformation engine.

[0109] At block 610, the processing logic may cause the data to be provided to the host controller in response to performing the first data transformation operation and the second data transformation operation on the data.

[0110] Changes, additions, or omissions may be made to the method 300 without affecting the scope of the present disclosure. The designations of the various elements as described are for illustrative purposes only and are not limiting. Furthermore, the method 300 may include any number of other elements or be implemented in systems or contexts other than those described.

[0111] An example method includes identifying metadata associated with a data transformation instruction. The metadata may be located in a memory pointed to by an address associated with the data transformation instruction. The method may also include identifying one or more data transformation engines in a data accelerator. The method may include arranging the one or more data transformation engines in the data accelerator based on the transformation instruction and the metadata.

[0112] Another example method includes obtaining a first packet descriptor associated with a first packet. The first packet descriptor may be located in a buffer pointed to by an address associated with the first packet. The method may include ordering one or more packet processing components in a network processing system based on the first packet and the first packet descriptor. The method may further include performing a packet processing operation to obtain data using the ordered one or more packet processing components. The method may also include reordering the one or more packet processing components based on the second packet and the second packet descriptor in response to receiving a second packet and a second packet descriptor.

[0113] For simplicity, the methods described herein are illustrated and described as a series of acts. However, the acts according to this disclosure may occur in different orders and / or concurrently, as well as with other acts not illustrated and described herein. Further, not all illustrated acts may be used to perform the methods according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that the methods may alternatively be represented as a series of interconnected states via a state diagram or events. Furthermore, the methods disclosed in this specification may be stored on an article of manufacture, such as a non-transitory computer-readable medium, to facilitate the transport and transfer of such methods to computing devices.The term "article of manufacture," as used herein, is intended to encompass a computer program accessible by any computer-readable device or storage medium. Although depicted as individual blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0114] While a number of implementations have been described, it should be understood that various changes may be made without affecting the spirit and scope of the disclosure. Accordingly, other embodiments are also within the scope of the following claims.

[0115] As is common practice, the various features illustrated in the drawings may not be drawn to scale. The illustrations presented in the present disclosure are not intended to be actual views of any particular apparatus (e.g., device, system, etc.) or method, but are merely idealized representations used to describe various embodiments of the disclosure. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. For example, the drawings may not depict all components of a particular apparatus (e.g., device) or all operations of a particular method.

[0116] The terms used in the present disclosure, and particularly in the appended claims (e.g., in the body of the appended claims), should generally be understood as "open-ended terms" (e.g., the term "including" should be interpreted as "including, but not limited to").

[0117] If a specific number of introductory claims is intended, this intention will be expressly mentioned in the claim; if such mention is absent, there will be no intention. For ease of understanding, for example, in the following appended claims, the introductory phrases “at least one” and “one or more” may be used to introduce lists of claims. However, the use of such phrases should not be construed to mean that the introduction of a claim by the indefinite articles “a” or “an” limits a particular claim containing such an introduced claim to implementations containing only one such claim, even if the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g.,, "a" and / or "an" should be interpreted to mean "at least one" or "one or more"; the same applies to the use of certain articles used to introduce claims.

[0118] Even if a specific number of introduced claims is expressly recited, the skilled person will recognize that such a list is to be interpreted as meaning at least the recited number (e.g., the mere list "two lists" without other modifiers means at least two lists or two or more lists). In cases where the phrase "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such a construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0119] Furthermore, any disjunctive word or phrase preceding two or more alternative terms in the description, claims, or drawings should be understood to include the possibility of including exactly one of the terms, one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B."

[0120] Furthermore, the terms "first," "second," "third," etc., are not necessarily used here to denote a specific order or number of elements. In general, the terms "first," "second," "third," etc., are used as generic labels to distinguish between different elements. Unless it is demonstrated that the terms "first," "second," "third," etc., denote a specific order, these terms should not be understood to denote a specific order. Unless it is demonstrated that the terms "first," "second," "third," etc., denote a specific number of elements, these terms should not be understood to denote a specific number of elements. For example, a first widget can be described as a first page, and a second widget can be described as a second page.The use of the term "second page" in reference to the second widget may serve to distinguish that page of the second widget from the "first page" of the first widget, and is not intended to imply that the second widget has two pages.

[0121] All examples and conditional expressions provided in the present disclosure are intended for educational purposes to facilitate the reader's understanding of the present disclosure and the concepts the inventor contributed to advancing the prior art, and are to be construed as not limiting to the specifically recited examples and conditions. Although implementations of the present disclosure have been described in detail, various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 378,978

[0001]

Claims

[1] A process comprising: Obtaining data to be processed through at least one data transformation operation; Determining a processing path for the data to pass through at least a first data transformation engine and a second data transformation engine; Passing the data to the first data transformation engine, wherein the first data transformation engine performs a first data transformation operation on the data; and Passing the data to the second data transformation engine to perform a second data transformation operation on the data. [2] The method of claim 1, wherein the at least one data transformation operation relates to at least one of the following elements: Data compression, decompression, encryption, decryption, authentication tag (MAC) generation, authentication, data deduplication hash generation and non-volatile memory express protection information generation (= NVMe PI generation), NVMe PI verification or real-time verification. [3] The method of claim 1, wherein the first data transformation engine is implemented with fixed logic and the second data transformation engine is implemented as a programmable data transformation engine. [4] The method of claim 1, wherein the first data transformation engine and the second data transformation engine are implemented on a single chip. [5] The method of claim 1, wherein the first data transformation engine is implemented on a first chiplet and the second data transformation engine is implemented on a second chiplet. [6] The method of claim 1, wherein the data is passed to the first data transformation engine or to the second data transformation engine based on a user input. [7] The method of claim 1, wherein passing the data to the first data transformation engine comprises passing a first subset of the data to the first data transformation engine, the first data transformation engine performing the first data transformation operation on the first subset of the data, wherein passing the data to the second data transformation engine comprises passing a second subset of the data to the second data transformation engine, the second data transformation engine performing the second data transformation operation on the second subset of the data. [8] The method of claim 1, wherein the data is passed to the first data transformation engine based on a particular transformation command received from a host controller, the first data transformation engine being configured to execute the particular transformation command. [9] The method of claim 8, wherein the respective transformation instruction includes at least one piece of control information or metadata used to direct the data to the first data transformation engine. [10] The method of claim 9, wherein the control information includes instructions from the host controller relating to the processing of the data. [11] The method of claim 9, wherein the metadata includes information about one or more types of transformations or transformation commands to be performed on the data. [12] The method of claim 9, wherein determining the processing path for the data passing through at least the first data transformation engine and the second data transformation engine comprises determining a plurality of data transformation instructions to be executed based on the control information or the metadata. [13] The method of claim 1, wherein the data is received from a host controller, the method being to be performed by an accelerator. [14] The method of claim 13 further comprises causing the data to be made available to the host controller in response to performing the first data transformation operation and the second data transformation operation on the data. [15] The method of claim 1, wherein passing the data to the first data transformation engine comprises identifying the first data transformation engine from a pool of data transformation engines. [16] The method of claim 1, wherein routing the data to the first data transformation engine and routing the data to the second data transformation engine comprises determining that no structural conflict occurs in an association of the first data transformation engine and the second data transformation engine. [17] The method of claim 1, wherein passing the data to the first data transformation engine comprises: Determining a criterion for a transformation instruction associated with the first data transformation engine; and Selecting the first data transformation engine based on the determined criteria for the transformation instruction that exceed a threshold priority. [18] The method of claim 17, wherein the determined criteria indicate that the transformation instruction has a higher priority than a second transformation instruction, the second transformation instruction being in a hold state. [19] The method according to claim 17, wherein the determined criteria relate to a performance profile or to the realization of a service level agreement for commands belonging to different command classes. [20] A data accelerator comprising: an interface connection to receive the data to be processed from a host controller; one or more data transformation engines individually configured to perform a specific, at least one data transformation operation on the data; and a queuing system to determine a processing path of the data from the interface connection and through the one or more data transformation engines, wherein the one or more data transformation engines are individually configured to forward the data to a next machine using the processing path.

Images