2.5D packaging structure for improving power signal transmission and method for preparing the same

Abstract

A 2.5D packaging structure for improving power signal transmission and a method for preparing the same, wherein a passive component module is bonded in a substrate groove so that a chip power region is electrically connected to the substrate in a vertical direction through passive components arranged in the vertical direction, thereby shortening a power supply distance and solving a power voltage drop problem; a wiring power region, a wiring signal region, C4 solder bump, and microbump are respectively prepared in a chip module in combination with the chip power region and the chip signal region, respectively, to reduce a flatness tolerance during bonding of the chip module and improve electrical performance; and further, the heat dissipation effect of the packaging structure can be improved by including a heat dissipation member.

Description

2.5D packaging structure for improving power signal transmission and preparation method thereof Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing and relates to a 2.5D packaging structure for improving power signal transmission and a preparation method thereof. Background Art

[0002] 2.5D packaging technology is a packaging technology that can realize the homogeneous or heterogeneous integration of multiple chips. In the 2.5D packaging structure, the chips can achieve high-density circuit interconnection through a TSV interposer with through-silicon vias (TSV).

[0003] 2.5D packaging technology typically requires process steps such as chip processing, ball placement, interconnection between the TSV interposer and the redistribution layer (RDL), bonding between the chip and passive components, and plastic encapsulation. Because the passive components are horizontally bonded to the substrate surface, the chip power supply area must pass through the TSV interposer and substrate before connecting to the passive components. This long transmission distance results in IR voltage drop and reduced electrical performance.

[0004] The existing method to solve the power signal transmission problem is usually to increase the platform voltage source, for example, from 0.9V to 1.1V to ensure electrical performance, but this method will cause the overall power of the chip to increase.

[0005] Therefore, it is necessary to provide a 2.5D packaging structure and a preparation method thereof for improving power signal transmission.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a 2.5D packaging structure and a preparation method thereof for improving power signal transmission, so as to solve the problem of difficulty in effectively transmitting power signals in the prior art.

[0008] To achieve the above objectives, the present invention provides a 2.5D packaging structure for improving power signal transmission, the 2.5D packaging structure comprising:

[0009] A substrate, the substrate comprising a first substrate surface and an opposite second substrate surface, and the substrate having a substrate groove extending from the first substrate surface to the second substrate surface;

[0010] A passive component module, the passive component module is bonded in the substrate groove, the passive component module includes a first rewiring layer, a passive component, a second rewiring layer and a packaging layer, the first rewiring layer is electrically connected to the substrate, the passive component is vertically bonded between the first rewiring layer and the second rewiring layer, a first end of the passive component is electrically connected to the first rewiring layer, and a second end of the passive component is electrically connected to the second rewiring layer, and the packaging layer is located between the first rewiring layer and the second rewiring layer and covers the passive component;

[0011] A TSV interposer module, wherein the TSV interposer module is bonded to the first surface of the substrate, the TSV interposer module comprises a TSV interposer layer and a third redistribution layer, the TSV interposer layer is electrically connected to the substrate, and the third redistribution layer is located on a surface of the TSV interposer layer and is electrically connected to the TSV interposer layer;

[0012] a first filling layer, wherein the first filling layer fills the connection gaps between the passive component module, the TSV intermediate module, and the substrate;

[0013] A chip module, wherein the chip module is bonded to the passive component module and the TSV interposer module, the chip module includes a chip and a fourth redistribution layer, the chip includes a chip power area and a chip signal area, the fourth redistribution layer includes a wiring power area electrically connected to the chip power area and a wiring signal area electrically connected to the chip signal area, the wiring power area is electrically connected to the second redistribution layer, and the wiring signal area is electrically connected to the third redistribution layer;

[0014] A second filling layer is provided, where the second filling layer fills the connection gaps between the passive component module, the TSV intermediate module, and the chip module.

[0015] Optionally, the passive element includes one or a combination of a capacitor, a resistor, and an inductor.

[0016] Optionally, the wiring density of the wiring signal area is greater than the wiring density of the wiring power area, and the number of wiring layers of the wiring signal area is greater than the number of wiring layers of the wiring power area, the wiring power area and the second rewiring layer are electrically connected through C4 bumps, and the wiring signal area and the third rewiring layer are electrically connected through micro bumps.

[0017] Optionally, a heat dissipation element located on the chip is further included, and the heat dissipation element includes a heat dissipation housing or a heat sink.

[0018] Optionally, the second surface of the substrate further includes metal bumps.

[0019] The present invention also provides a method for preparing a 2.5D packaging structure for improving power signal transmission, comprising the following steps:

[0020] Providing a substrate, the substrate comprising a first substrate surface and an opposite second substrate surface, and the substrate having a substrate groove extending from the first substrate surface to the second substrate surface;

[0021] A passive component module and a TSV interposer module are provided, the passive component module is bonded in the substrate groove, and the TSV interposer module is bonded to the first surface of the substrate, and the passive component module and the TSV interposer module are respectively electrically connected to the substrate; wherein, the passive component module includes a first redistribution layer, a passive component, a second redistribution layer and a packaging layer, the first redistribution layer is electrically connected to the substrate, the passive component is vertically bonded between the first redistribution layer and the second redistribution layer, the first end of the passive component is electrically connected to the first redistribution layer, the second end of the passive component is electrically connected to the second redistribution layer, and the packaging layer is located between the first redistribution layer and the second redistribution layer to cover the passive component; the TSV interposer module includes a TSV interposer and a third redistribution layer, the TSV interposer is electrically connected to the substrate, and the third redistribution layer is located on the surface of the TSV interposer and is electrically connected to the TSV interposer;

[0022] forming a first filling layer, wherein the first filling layer fills the connection gaps between the passive component module, the TSV intermediate module and the substrate;

[0023] Providing a chip module, bonding the chip module to the passive component module and the TSV interposer module, the chip module comprising a chip and a fourth redistribution layer, the chip comprising a chip power region and a chip signal region, the fourth redistribution layer comprising a wiring power region electrically connected to the chip power region and a wiring signal region electrically connected to the chip signal region, the wiring power region being electrically connected to the second redistribution layer, and the wiring signal region being electrically connected to the third redistribution layer;

[0024] A second filling layer is formed, where the second filling layer fills the connection gaps between the passive component module, the TSV intermediate module, and the chip module.

[0025] Optionally, the step of forming the passive component module includes:

[0026] providing a supporting substrate;

[0027] forming a first redistribution layer on the supporting substrate;

[0028] Providing a passive component, vertically bonding the passive component to the first redistribution layer, with a first end of the passive component electrically connected to the first redistribution layer;

[0029] forming a packaging layer, wherein the packaging layer covers the passive component and the first redistribution layer and exposes the second end of the passive component;

[0030] forming a second redistribution layer on the packaging layer, wherein the second redistribution layer is electrically connected to the second end of the passive component;

[0031] The supporting substrate is removed and cut to form the passive component module.

[0032] Optionally, a method of vertically bonding the passive component to the first rewiring layer includes a patch bonding method or a stencil bonding method.

[0033] Optionally, the passive element includes one or a combination of a capacitor, a resistor, and an inductor.

[0034] Optionally, the method further includes forming a heat dissipation element on the chip, wherein the heat dissipation element includes a heat dissipation housing or a heat sink; and forming a metal bump on the second surface of the substrate.

[0035] As described above, the present invention provides a 2.5D packaging structure for improving power signal transmission and a method for preparing the same. A passive component module is bonded in a groove of a substrate, so that the chip power area is electrically connected to the substrate in a vertical direction through the vertically arranged passive components, thereby shortening the power supply distance and solving the power supply voltage drop problem. The chip module is configured to have a wiring power area, a wiring signal area, C4 bumps, and micro bumps corresponding to the chip power area and the chip signal area, thereby reducing the flatness tolerance during chip module bonding and improving electrical performance. Furthermore, the heat dissipation effect of the packaging structure can be improved by providing a heat dissipation element. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a flow chart showing a process for preparing a 2.5D packaging structure for improving power signal transmission according to an embodiment.

[0037] FIG2 is a schematic structural diagram of a substrate in an embodiment.

[0038] FIG. 3 is a schematic structural diagram showing the passive component module being bonded to the substrate groove in the embodiment.

[0039] FIG. 4 is a schematic structural diagram showing the passive component module after forming the first redistribution layer in the embodiment.

[0040] FIG5 a is a schematic diagram showing the state of bonding passive components by using a patch method when preparing a passive component module in an embodiment.

[0041] FIG5 b is a schematic diagram showing a state of bonding passive components by using a stencil lamination method when preparing a passive component module in an embodiment.

[0042] FIG6 is a schematic diagram showing the structure of the passive component module after bonding the passive components in the embodiment.

[0043] FIG. 7 is a schematic diagram showing the structure of a passive component module after forming a packaging layer in an embodiment.

[0044] FIG. 8 is a schematic structural diagram showing a passive component module after forming a second redistribution layer in an embodiment.

[0045] FIG. 9 is a schematic diagram showing the structure of the passive component module after removing the supporting substrate in the embodiment.

[0046] FIG10 is a schematic diagram showing an enlarged structure of a passive component module according to an embodiment.

[0047] FIG. 11 is a schematic structural diagram showing a structure after the TSV interposer module is bonded to the first surface of the substrate in an embodiment.

[0048] FIG. 12 is a schematic diagram showing an enlarged structure of a TSV interposer module according to an embodiment.

[0049] FIG13 is a schematic diagram showing the structure after the first filling layer is formed in the embodiment.

[0050] FIG14 is a schematic diagram showing the structure of the chip module after bonding in the embodiment.

[0051] FIG15 is a schematic diagram showing an enlarged structure of a chip module in an embodiment.

[0052] FIG16 is a schematic diagram showing the structure after the second filling layer is formed in the embodiment.

[0053] FIG. 17 is a schematic diagram showing the structure after forming the heat dissipation element and the metal bumps in the embodiment.

[0054] Explanation of component numbers: 100-substrate; 101-substrate groove; 200-passive component module; 210-support substrate; 220-separation layer; 230-nozzle; 240-stencil; 201-first redistribution layer; 202-passive component; 203-packaging layer; 204-second redistribution layer; 300-TSV interposer module; 301-TSV interposer layer; 302-third redistribution layer; 400-first filling layer; 500-chip module; 501-chip power supply area; 502-chip signal area; 503-wiring power supply area; 504-wiring signal area; 505-C4 bump; 506-micro bump; 600-second filling layer; 700-heat dissipation element; 800-metal bump. DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0057] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0058] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0059] As shown in FIG16 , this embodiment provides a 2.5D packaging structure for improving power signal transmission. The 2.5D packaging structure includes a substrate 100 , a passive component module 200 , a TSV intermediate module 300 , a first filling layer 400 , a chip module 500 , and a second filling layer 600 .

[0060] 2 , the substrate 100 includes a first substrate surface and an opposite second substrate surface, and the substrate 100 has a substrate groove 101 extending from the first substrate surface to the second substrate surface.

[0061] Specifically, in this embodiment, the substrate 100 is a PCB substrate having an internal electrical connection layer, and electrical lead-out terminals for electrical connection, such as metal pads, are provided on the two opposite sides of the substrate 100 and in the substrate groove 101 to facilitate subsequent electrical connection of the substrate 100 with other devices. Among them, in order to reduce the vertical size of the finally prepared 2.5D packaging structure, thereby reducing the vertical transmission distance of the power signal, and to reduce the height difference between the passive component module 200 and the TSV intermediate module 300 after bonding, the thickness of the prepared passive component module 200 is about 400-600μm, and the thickness of the TSV in the prepared TSV intermediate module 300 is about 100μm, so as to improve the surface levelness between the passive component module 200 and the TSV intermediate module 300 after bonding, so as to facilitate the subsequent electrical connection between the chip module 500 and the passive component module 200 and the TSV intermediate module 300. In this embodiment, the substrate groove 101 is set in the substrate 100. The width and depth of the substrate groove 101 can be set as needed, and are not overly limited here. The specific type of the substrate 100 is not overly limited here.

[0062] Referring to Figures 3 and 10, the passive component module 200 is bonded in the substrate groove 101. The passive component module 200 includes a first rewiring layer 201, a passive component 202, a second rewiring layer 204 and a packaging layer 203. The first rewiring layer 201 is electrically connected to the substrate 100. The passive component 202 is vertically bonded between the first rewiring layer 201 and the second rewiring layer 204. The first end of the passive component 202 is electrically connected to the first rewiring layer 201, and the second end of the passive component 202 is electrically connected to the second rewiring layer 204. The packaging layer 203 is located between the first rewiring layer 201 and the second rewiring layer 204 and covers the passive component 202.

[0063] The passive component module 200 and the substrate 100 can be electrically connected via C4 bumps, but this is not a limitation and is not intended to be limiting. The materials and number of wiring layers of the first and second redistribution layers 201 and 204 are not limited herein and can be single-layer or multi-layer wiring, depending on the needs.

[0064] As an example, the passive component 202 may include one or a combination of a capacitor, a resistor, and an inductor. There is no excessive restriction on the type of the passive component 202 in the passive component module 200 and the passive component 202 may be selected as needed.

[0065] 11 and 12 , the TSV interposer module 300 is bonded to the first surface of the substrate. The TSV interposer module 300 includes a TSV interposer layer 301 and a third redistribution layer 302 . The TSV interposer layer 301 is electrically connected to the substrate 100 . The third redistribution layer 302 is located on the surface of the TSV interposer layer 301 and is electrically connected to the TSV interposer layer 301 .

[0066] The TSV interposer module 300 and the substrate 100 can be electrically connected via C4 bumps, but this is not a limitation and is not intended to be limiting. The material and number of wiring layers of the third redistribution layer 302 are not limited herein and can be single-layer or multi-layer, depending on the needs.

[0067] 13 , the first filling layer 400 fills the connection gaps between the passive component module 200 , the TSV interposer module 300 and the substrate 100 , so that the first filling layer 400 can protect the electrical connections between the passive component module 200 , the TSV interposer module 300 and the substrate 100 , thereby improving bonding stability and electrical performance.

[0068] The first filling layer 400 can be made of insulating material, and the specific type is not limited here.

[0069] Referring to Figures 14 and 15, the chip module 500 is bonded to the passive component module 200 and the TSV intermediate module 300. The chip module 500 includes a chip and a fourth redistribution layer. The chip includes a chip power area 501 and a chip signal area 502. The fourth redistribution layer includes a wiring power area 503 electrically connected to the chip power area 501 and a wiring signal area 504 electrically connected to the chip signal area 502. The wiring power area 503 is electrically connected to the second redistribution layer 204, and the wiring signal area 504 is electrically connected to the third redistribution layer 302.

[0070] The type of the chip can be set according to needs and is not overly limited here.

[0071] As an example, the wiring density of the wiring signal area 504 is greater than the wiring density of the wiring power supply area 503, and the number of wiring layers of the wiring signal area 504 is greater than the number of wiring layers of the wiring power supply area 503. The wiring power supply area 503 is electrically connected to the second rewiring layer 204 through the C4 bump 505, and the wiring signal area 504 is electrically connected to the third rewiring layer 302 through the micro bump 506.

[0072] Specifically, the chip signal area 502 needs to transmit high-frequency signals. In order to avoid signal loss, it has denser line width and line spacing than the chip power area 501, and has more wiring layers. For example, the line width and line spacing of the chip signal area 502 are generally less than 10μm, and the number of wiring layers is generally 3 to 4 layers; the chip power area 501 transmits voltage and current. In order to avoid line burning, it requires a larger line width and line spacing. For example, the line width and line spacing of the chip power area 501 generally need to be greater than 10μm, and the number of wiring layers is generally 1 to 2 layers. Among them, when there is a thickness difference between the wiring power area 503 and the wiring signal area 504, in order to compensate for the thickness difference, the C4 bump 505 with a larger size can be formed on the surface of the wiring power area 503, such as the thickness of the C4 bump 505 can be 100-150 μm, etc., and the micro bump 506 with a smaller size can be formed on the surface of the wiring signal area 504, such as the thickness of the micro bump 506 can be 20-40 μm, etc., so that by arranging connecting bumps with different sizes in different areas, thickness compensation can be performed to reduce the flatness tolerance of the chip module 500 during bonding, thereby improving the electrical performance of the chip module 500 after bonding with the passive component module 200 and the TSV intermediate module 300.

[0073] 16 , the second filling layer 600 fills the connection gaps between the passive component module 200 , the TSV interposer module 300 and the chip module 500 , so that the electrical connections between the passive component module 200 , the TSV interposer module 300 and the chip module 500 are protected by the second filling layer 600 , thereby improving bonding stability and electrical performance.

[0074] The second filling layer 600 can be made of insulating material, and the specific type is not limited here.

[0075] As an example, referring to FIG. 17 , a heat dissipation element 700 located on the chip may be further included, wherein the heat dissipation element 700 may include a heat dissipation housing or a heat sink.

[0076] Specifically, the heat dissipation element 700 and the chip can be in direct contact or in indirect contact via thermally conductive adhesive, thereby improving the heat dissipation effect through the heat dissipation element 700. In this embodiment, the heat dissipation element 700 is a heat dissipation housing bonded to the surface of the substrate 100, thereby providing a protective cavity. Of course, in another embodiment, the heat dissipation element 700 can also be a heat sink located on the chip, which is not limited here.

[0077] As an example, referring to FIG. 17 , a metal bump 800 may be further included on the second surface of the substrate. The metal bump 800 is electrically connected to the substrate 100 , so that the substrate 100 can be electrically connected to other devices through the metal bump 800 .

[0078] The metal bumps 800 may include a ball grid array (BGA) and may have a thickness of, for example, 350 to 550 μm. The material of the metal bumps 800 is not limited herein.

[0079] This embodiment further provides a method for preparing a 2.5D packaging structure for improving power signal transmission. The 2.5D packaging structure can be prepared using the following method, but is not limited thereto.

[0080] Referring to FIG. 1 , the preparation of the 2.5D package structure may include the following steps:

[0081] S1: providing a substrate, wherein the substrate comprises a first substrate surface and an opposite second substrate surface, and the substrate comprises a substrate groove extending from the first substrate surface to the second substrate surface;

[0082] S2: providing a passive component module and a TSV intermediary module, bonding the passive component module into the substrate groove, and bonding the TSV intermediary module onto the first surface of the substrate;

[0083] S3: forming a first filling layer, wherein the first filling layer fills the connection gaps between the passive component module, the TSV intermediate module, and the substrate;

[0084] S4: providing a chip module, and bonding the chip module to the passive component module and the TSV interposer module;

[0085] S5: forming a second filling layer, wherein the second filling layer fills the connection gaps between the passive component module, the TSV intermediate module, and the chip module.

[0086] The preparation of the 2.5D packaging structure is introduced below with reference to FIG. 2 to FIG. 17 .

[0087] First, referring to FIG. 1 and FIG. 2 , step S1 is performed to provide a substrate 100 . The substrate 100 includes a first substrate surface and an opposite second substrate surface. The substrate 100 has a substrate groove 101 extending from the first substrate surface to the second substrate surface.

[0088] Specifically, the structure of the substrate 100 may refer to the above contents regarding the 2.5D packaging structure, which will not be elaborated here.

[0089] Next, referring to Figures 1, 3 and 11, step S2 is performed to provide a passive component module 200 and a TSV interposer module 300, bond the passive component module 200 into the substrate groove 101, and bond the TSV interposer module 300 to the first surface of the substrate, and the passive component module 200 and the TSV interposer module 300 are respectively electrically connected to the substrate 100.

[0090] Specifically, the structures of the passive component module 200 and the TSV intermediate module 300 may refer to the above-mentioned contents regarding the 2.5D packaging structure, which will not be described in detail here.

[0091] The passive component module 200 and the TSV intermediate module 300 may be bonded to the substrate 100 using, for example, C4 bump technology to form C4 bumps for electrical connection. For the preparation of the C4 bumps, reference may be made to existing preparation processes. The material of the C4 bumps is not limited herein. The size of the C4 bumps may include, for example, 90 to 120 μm, but is not limited thereto.

[0092] The order in which the passive component module 200 and the TSV interposer module 300 are bonded to the substrate 100 can be selected as needed. For example, the passive component module 200 can be bonded first and then the TSV interposer module 300 as shown in Figures 3 and 11. Of course, in another embodiment, the TSV interposer module 300 can be bonded first and then the passive component module 200, or the passive component module 200 and the TSV interposer module 300 can be bonded simultaneously. The specific order is not excessively limited here.

[0093] As an example, the steps of forming the passive component module 200 may include:

[0094] As shown in FIG4 , a support substrate 210 is first provided. The support substrate 210 may include, for example, a glass substrate or a silicon substrate. Furthermore, to facilitate subsequent stripping operations, the support substrate 210 preferably has a separation layer 220 on its surface, such as an LTHC light-to-heat conversion layer, so that the support substrate 210 can be separated by laser heating of the LTHC light-to-heat conversion layer.

[0095] Next, as shown in FIG4 , a first redistribution layer 201 is formed on the support substrate 210 , wherein the first redistribution layer 201 may include a single-layer wiring or a multi-layer wiring, and the specific number of layers, material, and preparation process are not limited herein;

[0096] Next, as shown in FIG5a and FIG5b, a passive component 202 is provided, and the passive component 202 is bonded vertically to the first rewiring layer 201, and the first end of the passive component 202 is electrically connected to the first rewiring layer 201; wherein, FIG5a illustrates a state diagram of the passive component 202 bonded by the patch method, and FIG5b illustrates a state diagram of the passive component 202 bonded by the stencil bonding method. When the patch method is adopted, in order to realize the vertical bonding of the passive component 202, the existing SMT machine needs to be improved, such as in the SMT machine. A rotating mechanical component is provided to change the rotation direction of the suction nozzle 230, thereby achieving vertical bonding of the passive component 202. When a stencil lamination method is adopted, a mesh hole matching the size of the passive component 202 can be provided on the stencil 240. After the stencil 240 and the first rewiring layer 201 are aligned, the passive component 202 on the stencil 240 can drop onto the first rewiring layer 201 through the mesh hole to achieve fast and efficient alignment and vertical bonding, thereby finally completing the bonding of the passive component 202, as shown in FIG6.

[0097] Next, as shown in FIG7 , a packaging layer 203 is formed. The packaging layer 203 covers the passive component 202 and the first redistribution layer 201 and exposes the second end of the passive component 202 to facilitate subsequent electrical extraction. The material and preparation of the packaging layer 203 are not limited herein.

[0098] Next, as shown in FIG8 , a second redistribution layer 204 is formed on the packaging layer 203 , and the second redistribution layer 204 is electrically connected to the second end of the passive component 202 . The second redistribution layer 204 may include a single-layer wiring or multiple-layer wiring, and the specific number of layers, material, and preparation process are not limited herein.

[0099] Next, referring to FIG. 9 and FIG. 10 , the support substrate 210 is removed and cut to form the passive component module 200 .

[0100] As an example, the passive component 202 may include one or a combination of a capacitor, a resistor, and an inductor, and may be bonded as needed.

[0101] Next, referring to FIG. 13 , step S3 is performed to form a first filling layer 400 . The first filling layer 400 fills the connection gaps between the passive component module 200 , the TSV intermediate module 300 , and the substrate 100 .

[0102] Among them, the method for forming the first filling layer 400 can adopt a dispensing method to avoid contamination of the electrical lead-out terminals on the surface of the passive component module 200 and the TSV intermediate module 300, so as to facilitate subsequent electrical connection, but it is not limited to this. The material of the first filling layer 400 can be an insulating material, and the specific type is not overly limited here.

[0103] Next, referring to FIG. 14 , step S4 is executed to provide a chip module 500 , and bond the chip module 500 to the passive component module 200 and the TSV interposer module 300 .

[0104] The structure of the chip module 500 can be found in the above-mentioned content regarding the 2.5D packaging structure, which will not be described in detail here.

[0105] Next, referring to FIG. 16 , step S5 is performed to form a second filling layer 600 . The second filling layer 600 fills the connection gaps between the passive component module 200 , the TSV intermediate module 300 , and the chip module 500 .

[0106] The second filling layer 600 may be formed by a dispensing method, but is not limited thereto. The second filling layer 600 may be made of any insulating material, and the specific type is not particularly limited.

[0107] Furthermore, referring to FIG. 17 , the method may further include forming a heat dissipation element 700 on the chip. The heat dissipation element 700 may include a heat dissipation housing or a heat sink.

[0108] For an introduction to the heat dissipation element 700 , please refer to the above contents regarding the 2.5D packaging structure, which will not be elaborated here.

[0109] Furthermore, referring to FIG. 17 , the process may further include forming metal bumps 800 on the second surface of the substrate.

[0110] Specifically, the metal bump 800 may include a ball grid array, and may have a thickness of, for example, 350 to 550 μm. The material and preparation of the metal bump 800 are not limited herein.

[0111] In summary, the 2.5D packaging structure and preparation method for improving power signal transmission of the present invention bond a passive component module in a substrate groove, so that the chip power area is electrically connected to the substrate in the vertical direction through the passive components arranged vertically, thereby shortening the power supply distance and solving the power supply voltage drop problem; the chip module is combined with the chip power area and the chip signal area to prepare corresponding wiring power areas, wiring signal areas, C4 bumps and micro bumps, so as to reduce the flatness tolerance during chip module bonding and improve electrical performance; further, the heat dissipation effect of the packaging structure can be improved by setting a heat dissipation element.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A 2.5D packaging structure for improving power signal transmission, characterized in that: The 2.5D packaging structure includes: A substrate, the substrate comprising a first substrate surface and an opposite second substrate surface, and the substrate has a substrate groove extending from the first substrate surface to the second substrate surface; A passive component module, the passive component module is bonded in the groove of the substrate, the passive component module comprises a first rewiring layer, a passive component, a second rewiring layer and a packaging layer, the first rewiring layer is electrically connected to the substrate, the passive component is vertically bonded between the first rewiring layer and the second rewiring layer, the first end of the passive component is electrically connected to the first rewiring layer, the second end of the passive component is electrically connected to the second rewiring layer, and the packaging layer is located between the first rewiring layer and the second rewiring layer to cover the passive component; A TSV interposer module, wherein the TSV interposer module is bonded to the first surface of the substrate, the TSV interposer module comprises a TSV interposer layer and a third rewiring layer, the TSV interposer layer is electrically connected to the substrate, and the third rewiring layer is located on a surface of the TSV interposer layer and is electrically connected to the TSV interposer layer; A first filling layer, wherein the first filling layer fills the connection gap between the passive component module, the TSV intermediate module and the substrate; A chip module, wherein the chip module is bonded to the passive component module and the TSV interposer module, the chip module comprises a chip and a fourth rewiring layer, the chip comprises a chip power region and a chip signal region, the fourth rewiring layer comprises a wiring power region electrically connected to the chip power region and a wiring signal region electrically connected to the chip signal region, and the wiring power region is electrically connected to the second rewiring layer, and the wiring signal region is electrically connected to the third rewiring layer; A second filling layer is used to fill the connection gaps between the passive component module, the TSV intermediate module and the chip module.

2. The 2.5D packaging structure according to claim 1, characterized in that: The passive element includes one or a combination of capacitors, resistors and inductors.

3. The 2.5D packaging structure according to claim 1, characterized in that: The wiring density of the wiring signal area is greater than the wiring density of the wiring power area, and the number of wiring layers in the wiring signal area is greater than the number of wiring layers in the wiring power area. The wiring power area is electrically connected to the second re-wiring layer through a C4 bump, and the wiring signal area is electrically connected to the third re-wiring layer through a micro bump.

4. The 2.5D packaging structure according to claim 1, characterized in that: It also includes a heat dissipation element located on the chip, and the heat dissipation element includes a heat dissipation housing or a heat sink.

5. The 2.5D packaging structure according to claim 1, characterized in that: The second surface of the substrate also includes metal bumps.

6. A method for preparing a 2.5D packaging structure for improving power signal transmission, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a first substrate surface and an opposite second substrate surface, and the substrate having a substrate groove extending from the first substrate surface to the second substrate surface; A passive component module and a TSV intermediary module are provided, the passive component module is bonded in the groove of the substrate, and the TSV intermediary module is bonded on the first surface of the substrate, and the passive component module and the TSV intermediary module are respectively electrically connected to the substrate; wherein the passive component module comprises a first rewiring layer, a passive component, a second rewiring layer and a packaging layer, the first rewiring layer is electrically connected to the substrate, the passive component is vertically bonded between the first rewiring layer and the second rewiring layer, the first end of the passive component is electrically connected to the first rewiring layer, the second end of the passive component is electrically connected to the second rewiring layer, and the packaging layer is located between the first rewiring layer and the second rewiring layer to cover the passive component; the TSV intermediary module comprises a TSV intermediary layer and a third rewiring layer, the TSV intermediary layer is electrically connected to the substrate, and the third rewiring layer is located on the surface of the TSV intermediary layer and is electrically connected to the TSV intermediary layer; forming a first filling layer, wherein the first filling layer fills the connection gap between the passive component module, the TSV intermediate module and the substrate; Providing a chip module, bonding the chip module to the passive component module and the TSV interposer module, the chip module comprising a chip and a fourth rewiring layer, the chip comprising a chip power region and a chip signal region, the fourth rewiring layer comprising a wiring power region electrically connected to the chip power region and a wiring signal region electrically connected to the chip signal region, the wiring power region is electrically connected to the second rewiring layer, and the wiring signal region is electrically connected to the third rewiring layer; A second filling layer is formed, wherein the second filling layer fills the connection gaps between the passive component module, the TSV intermediate module and the chip module.

7. The method for preparing the 2.5D packaging structure according to claim 6, characterized in that: The steps of forming the passive component module include: providing a supporting substrate; forming a first rewiring layer on the supporting substrate; Providing a passive component, bonding the passive component vertically on the first re-distribution layer, and electrically connecting a first end of the passive component to the first re-distribution layer; forming a packaging layer, wherein the packaging layer covers the passive element and the first rewiring layer and exposes the second end of the passive element; A second redistribution layer is formed on the packaging layer, and the second redistribution layer is connected to the second Terminal electrical connection; The supporting substrate is removed and cut to form the passive component module.

8. The method for preparing the 2.5D packaging structure according to claim 7, characterized in that: The method of vertically bonding the passive component to the first rewiring layer includes a chip bonding method or a stencil bonding method.

9. The method for preparing the 2.5D packaging structure according to claim 6, characterized in that: The passive element includes one or a combination of capacitors, resistors and inductors.

10. The method for preparing the 2.5D packaging structure according to claim 6, characterized in that: The method also includes the step of forming a heat dissipation element on the chip, wherein the heat dissipation element includes a heat dissipation housing or a heat sink; and the step of forming a metal bump on the second surface of the substrate.

Images