SYSTEM-INTEGRATED 2.5D STRUCTURE

Abstract

A 2.5D system-level integrated structure comprising a stacked 3D integrated package that integrates different generations of system chips into a single package. Applying a hybrid interconnection technique to the system integration chip, the first metal pads and the second metal pads belonging to multiple system chips with different dimensions and features from different generations are interconnected to reduce the through-path of the electrical connection. The system integration chip improves packaging chip density and data throughput within the same package size.

Description

FIELD OF THE INVENTION

[0001] The present disclosure relates to the field of semiconductor packaging and, more particularly, to a system-integrated 2.5D structure. BACKGROUND OF THE INVENTION

[0002] Science and technology have advanced so much that end users today demand equipment that is increasingly smaller, faster, more energy-efficient, and with higher performance. The main trend in industrial development has focused on the miniaturization and multifunctionality of electronic consumer products. Therefore, a major challenge in the field of modern semiconductor chip packaging has become how to integrate and package a number of different types of high-density chips together to form a system or subsystems that are powerful but consume minimal power.

[0003] System-level packaging technology, as an emerging heterogeneous integration technology, has become the preferred packaging platform for more chips, integrating a variety of functional chips and components into a single package body. Therefore, this system realizes more functionality, lower power consumption, better performance, smaller size, and other advantages within a short development cycle. This system provides ultra-highly integrated system-level packaging that can integrate different generations of SOCs within a single packaging structure in multifunctional system synergy, as well as other advantages such as functional density, high compatibility, high integration, and high flexibility, meeting the increasing demand for packaging components and functions. SUMMARY OF THE INVENTION

[0004] The present disclosure provides an integrated 2.5D system-level structure to solve the challenges of limited functionality, low integration, and difficulty in interoperating chips from different generations in current technologies.

[0005] The present disclosure provides a 2.5D system-level integrated structure with the following advantageous effects: The system integration chip is a system-stacked 3D packaging structure that integrates system chips or wafers of different generations into the same packaging chip using hybrid bonding. It stacks older-generation system chips onto later-generation system chips by arranging their different sizes so that the same packaging structure size can achieve more functionality, thereby significantly improving the functional density of the packaging structure and optimizing the chip size. The system-level integrated chip is applied to the 2.5D packaging structure to form a 2.5D system-level integrated structure and integrates HBM / DDR / Flash / transistors / filters / passive components and other electronic chips.Therefore, the packaging of the same size achieves more functionality and the multifunctional systems all work together, eliminating the need for separate preparation of multiple packaging structures and their interconnections, thereby improving chip performance and increasing economic benefits in addition to the advantages of strong integrity, high flexibility and wide compatibility.

[0006] When the first signal interface from the first chip in the system integration chip is electrically connected to the corresponding interface of the system wafer, the first metal pad and the second metal pad are aligned to directly electrically connect, thereby reducing the through path of the electrical connection, thereby reducing the parasitic capacitance in the packaging structure, and thereby improving the signal transmission efficiency; the distance between the first metal pads and between the second metal pads can be arranged to less than 5 µm, so that the number of metal pads in a unit area can increase, thereby increasing the number of data channels and data throughput, thereby improving integration;Sizes of the first metal pad and the second metal pad do not need to have the same dimensional width, so the accuracy of placement of the hybrid bonded chip can be arranged, resulting in production efficiency.; BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1a to Fig. 4 show schematic diagrams of structures obtained at each of the process steps during the preparation process of manufacturing the integrated system-level chip in one embodiment of the present disclosure. Fig. 5 to Fig. 7 show schematic structural diagrams obtained at each of the process steps during the preparation process of manufacturing an integrated 2.5D system-level structure in an embodiment of the present disclosure. Reference symbol 1 First wafer 11 First matrix 2 system wafers 3 First dielectric layer 4 First metal contact point 5 Second dielectric layer 6 Second metal contact point 7 Metal support 8 Plastic encapsulation layer 9 Redistribution layer 91 Dielectric wiring layer 92 Metallic wiring layer 10 External interface 100 system integration chip 110 Intermediate substrate 120 TSV leading pillars 131 First dielectric wiring layer 132 First metallic wiring layer 140 Second die 150 First plastic encapsulation layer 151 Lower Filler Adhesive 161 Second dielectric wiring layer 162 Second metallic wiring layer 170 First external interface DETAILED DESCRIPTION OF THE INVENTION

[0007] Embodiments of the present disclosure are described below using certain specific examples, and other advantages and effects of the present disclosure can be readily appreciated by those skilled in the art from what is disclosed in this specification. The present disclosure may also be implemented or applied through other various exemplary embodiments. Various modifications or changes may also be made to any details in the specification based on different aspects and applications without departing from the spirit of the present disclosure.

[0008] For example, while the embodiments of the present disclosure are described in detail for convenience of description, the cross-sectional view showing the device structure is not partially enlarged according to the general scale, and the schematic diagram is only an example that should not limit the scope of protection. Furthermore, actual manufacturing should include the length, width, and depth of the three-dimensional spatial dimensions.

[0009] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner, so that the illustrations only show the components related to the present disclosure and are not drawn according to the actual implementation of the number of components, shapes and sizes of the actual implementation of the components of the type, number and proportion of the actual implementation of the components may be an arbitrary change, and the layout of the components of the type may be more complex.

[0010] As in Fig. 1a- Fig. 7, the present disclosure provides a method for preparing a system-level 2.5D integrated structure, and the structure and advantageous effects of the system-level 2.5D integrated structure are described in detail, and the method for preparing the system-level 2.5D integrated structure includes the following steps.

[0011] As in Fig. 1a to Fig. 1c, a first wafer 1 is provided, a first dielectric layer 3 and a first metal pad 4 disposed in the first dielectric layer 3 are formed on the first wafer 1, the first metal pad 4 is electrically connected to the first wafer 1, and an encapsulated scribe is formed to form a first die 11.

[0012] In particular, as in Fig. 1a, a first wafer 1 is provided. The first wafer 1 has been manufactured and has a complete internal structure with an external signal interface, such as a plurality of memory chips capable of realizing a storage role, a programmable logic device chip capable of realizing a programming role, such as a system wafer for integrating information processing. The above example is a non-limiting example selected according to actual needs. In this embodiment, the first wafer 1 is an older-generation system wafer with a small-size specification.Depositing a first dielectric layer 3 on the first wafer 1, wherein the first dielectric layer 3 is an intermetallic dielectric layer comprising silicon oxide, silicon nitride, silicon nitride, silicon carbide, or another inorganic dielectric layer with low K. The first dielectric layer 3 may be an organic dielectric layer formed by polymers such as benzocyclobutene BCB, polyimide PI, etc., and the first dielectric layer 3 may also be a combination of an inorganic dielectric layer and an organic dielectric layer according to the actual needs of the setting, but is not limited to these. The first dielectric layer 3 is patterned with a metal pad contact hole, the metal pad contact hole having a first signal interface of the first wafer 1.Depositing a barrier layer and a metal mat layer in the metal mat contact holes, wherein the material forming the metal mat layer is preferably copper, but may also be other suitable metals or metal alloys such as nickel, tin, etc. After filling the metal pad contact holes, the deposition of a metal layer with a preset thickness on the first dielectric layer 3 is continued, and then the metal surface layer is removed by a polishing process such as chemical mechanical polishing, as shown in FIG. Fig. 1b, to obtain a flattened first dielectric layer 3 with a first metal pad 4 disposed in the first dielectric layer 3. The first dielectric layer 3 and the first metal pad 4 are capable of rearranging the first signal interface on the front side of the first wafer 1 such that the first signal interface is electrically connected to the first metal pad 4, wherein the first metal pad 4 is disposed differently from the first signal interface. The first wafer 1 is plasticized and then scribed to form a single first die 11.

[0013] As in Fig. 2a to Fig. 2b, a system wafer 2 is provided, a second dielectric layer 5 and a second metal pad 6 disposed in the second dielectric layer 5 are formed on the system wafer 2, wherein the second metal pad 6 is electrically connected to the system wafer 2.

[0014] In particular, as in Fig. 2a, a system wafer 2 is provided, and the system wafer 2 is a newer generation system wafer with a large size. A second signal interface is provided on the surface of the system wafer 2. As shown in Fig. 2b, a second dielectric layer 5 and a second metal pad 6 disposed in the second dielectric layer 5 are formed on the surface of the system wafer 2. The second dielectric layer 5 and the second metal pad 6 are capable of rearranging the second signal interface on the front side of the system wafer 2 such that the second signal interface is electrically connected to the second metal pad 6, wherein the second metal pad 6 is disposed differently from the second signal interface. The specific method for forming the second dielectric layer 5 with the second metal pad 6 can be found in the above-described method for forming the first dielectric layer 3 with the first metal pad 4 and will not be repeated here.

[0015] As in Fig. 3, a metal support 7 is formed on the second metal pad 6, the first die 11 is bonded to the system wafer 2 by hybrid bonding to form a plastic encapsulation layer 8, and the plastic encapsulation layer 8 wraps around the first die 11, the metal support 7 and the second dielectric layer 5 and exposes the surface of the metal support 7.

[0016] Specifically, in this embodiment, metal supports 7 are formed on both sides of the second metal pads 6, and the metal supports 7 are electrically connected to the second signal interface of the system wafer 2 through the second metal pads 6 to provide power transmission and signal transmission; this can free up more space on the system wafer 2 for the integration of the first die 11, increase the degree of integration, and optimize the die size. However, the position of the metal support 7 is not limited to this, and depending on the actual layout requirements, the metal support 7 may be located on a single side of the second metal pad 6 or at other suitable positions, such as the second metal pad 6 in the center.

[0017] The metal supports 7 include, but are not limited to, copper supports and titanium supports, and the forming methods include, but are not limited to, PVD, CVD, sputtering, electroplating, and chemical plating. In one embodiment, a metallic copper layer may be formed by a PVD process, followed by forming a photoresist on the metallic copper layer, patterning the photoresist and etching the metallic copper layer, and finally removing the photoresist by forming the metal supports 7 on the second metal pads 6 on both sides.

[0018] By connecting the first die 11 to the system wafer 2 by a hybrid connection method, that is, connecting between the corresponding first metal pad 4 and the second metal pad 6, and connecting between the corresponding first dielectric layer 3 and the second dielectric layer 5.

[0019] Specifically, hybrid bonding combines metal-to-metal bonding and dielectric-to-dielectric bonding, wherein the first signal interface of the first die 11 is electrically directly connected to a corresponding interface of the system wafer 2 by bonding the first metal pad 4 to the second metal pad 6, which enables reduction of the through paths of the electrical connections, reduction of the parasitic capacitance in the packaging structure, and improvement of the signal transmission efficiency between the first die 11 and the system wafer 2; while maintaining vertical metal interconnections, the auxiliary effect of dielectric bonding is utilized to improve the physical and mechanical properties between the stacked chips and enhance the comprehensive performance of the stacked chips.In detail, hybrid bonding technology differs from conventional bump welding technology in that hybrid bonding technology has no protruding bumps and the surface of the dielectric layer is very smooth. By attaching two chips together at room temperature, raising the temperature, and annealing them, the copper of the first and second metal pads expands and firmly bonds to form an electrical connection with high current carrying capacity and a small bonding pitch, thereby reducing power consumption per bonding channel and achieving low time delay. In addition to metal bonding, the dielectric layers are also bonded together, with no gaps between the first and second dielectric layers and no need for filler adhesive, thus providing better heat dissipation and bond strength.In this embodiment, the first die 11 is shown as the system wafer 2, but the number of first dies 11 may be 1, 3, or more than 3, depending on the requirements of the actual functional system. By hybrid bonding the first die 11 and the system wafer 2, the integration of system chips or wafers of different generations into the same packaging chip is realized, effectively utilizing the dimensional characteristics of chips of different generations, such as the large size of later-generation chips and the small size of older-generation chips. This technique overlays the system chips of different generations, stacks the older-generation system chips on the newer-generation system chips, and realizes more functions in the same packaging size, thereby significantly improving the functional density of the packaging structure, optimizing the wafer size, high flexibility, and wider compatibility.

[0020] Materials of the plastic encapsulation layer 8 include, but are not limited to, epoxy-based resins, liquid thermosetting epoxies, plastic molding compounds, and methods for forming the plastic encapsulation layer 8 include compression molding, transfer molding, liquid seal molding, vacuum lamination, spin-coating, or other suitable methods. After forming the plastic encapsulation layer 8, a flattening process is performed using methods including, but not limited to, grinding methods to make the surface of the metal support 7 flush with the surface of the plastic encapsulation layer 8.

[0021] As an example, the dimensions of the first metal contact pad 4 are not the same as the dimensions of the second metal contact pad 6.

[0022] In particular, as in Fig. 4, in this embodiment, the first metal pad 4 is perfectly aligned with the second metal pad 6 when bonded, each having the same dimensional size. However, in actual manufacturing, the size of the first metal pad 4 and the second metal pad 6 is not the same; the first metal pad 4 may be larger than the second metal pad 6; or conversely, the second metal pad 6 may be larger than the first metal pad 4. Therefore, smoothness and accuracy of chip placement can be achieved during hybrid bonding, thereby improving production efficiency.

[0023] As an example, the distance between two of the first metal contact points 4 or between two of the second metal contact points 6 is both less than 5 µm.

[0024] In particular, in a practical example, applying the disclosed technique has reduced the distance between two of the first metal pads 4 and two of the second metal pads 6 from more than 10 µm to less than 5 µm, thus increasing the density of the metal pads, resulting in a higher metal channel density, thereby increasing data throughput and improving the level of integration. In a real case, the distance between two of the first metal pads 4 is 3 µm, and the distance between two of the second metal pads 6 is 3 µm. In another case, the distance between two of the first metal pads 4 is 1 µm, and the distance between two of the second metal pads 6 is 1 µm.

[0025] As in Fig. 4, a redistribution layer 9 is formed on the surface of the plastic encapsulation layer 8, the redistribution layer 9 comprising a dielectric wiring layer 91 and a metallic wiring layer 92 disposed in the dielectric wiring layer 91 and electrically connected to the metal support 7, and an external interface 10 is formed on the metallic wiring layer 92 remote from the surface of the metal support 7 to form a system integration chip 100.

[0026] Specifically, a dielectric wiring layer 91 is formed on the surface of the plastic encapsulation layer 8. The material of the dielectric wiring layer 91 includes one of epoxy, silicone, PI, PBO, BCB, silicon oxide, phosphor-silicon glass, and fluorine-containing glass. The cross-section of the structure shows the dielectric wiring layer 91, the metal support 7, and a metallic wiring layer 92 patterned within the dielectric wiring layer 91, with the metallic wiring layer 92 electrically connected to the metal support 7.The material of the metallic wiring layer 92 includes one or a combination of copper, aluminum, titanium, and nickel. The method for forming the metallic wiring layer 92 includes, but is not limited to, PVD, CVD, sputtering, electroplating, and chemical plating. The metallic wiring layer 92 includes a single-layer or multi-layer structure. In the present disclosure, all metallic wiring layers include single-layer or multi-layer structures unless otherwise stated.

[0027] An external interface 10 is formed on the surface of the metallic wiring layer 92 remote from the metallic support 7, the external interface 10 including solder balls and metal pads. In this embodiment, the external interface includes solder balls made of materials including, but not limited to, copper, nickel, and tin.

[0028] The metal support 7 is directly connected to the redistribution layer 9 on the top side for power supply to the system wafer 2 and for electrical signal transmission. Compared to a conventional silicon via, the metal support 7 is larger and less resistive, providing more stable power transmission and lower time delay.

[0029] After forming the external interface 10, to further reduce the height of the packaging structure, the thickness of the substrate of the system wafer 2 may also be thinned, and the substrate may be flattened using methods such as grinding and then packaged to form the system-level integrated chip 100. Applying the system-level integrated chip 100 to a 2.5D packaging structure to form a 2.5D system-level integrated structure. As a non-limiting example, a preparation method for applying the system-level integrated chip 100 to a 2.5D packaging structure is described below. Other methods may be used according to actual production needs, but are not limited thereto.

[0030] As in Fig. 5, an intermediate substrate 110 is provided with a conductive TSV (silicon via) pillar 120 formed in the intermediate substrate 110 having a first surface and a second surface opposite each other.

[0031] Specifically, the intermediate substrate 110 includes, among others, a glass substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate for supporting the isolation of a chip located on the first surface and an external signal interface located on the second surface. In this example, the intermediate substrate 110 is a silicon substrate. TSV holes through the intermediate substrate 110 are formed in the intermediate substrate 110 using laser drilling, mechanical drilling, reactive ion deep etching, light-assisted electrochemical etching, and the like. Filling the TSV holes with conductive material to form a conductive TSV pillar 120, wherein the conductive material is one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, etc.is, with filling processes, including, but not limited to, electroplating, chemical plating and at the same time, in order to prevent the diffusion of the conductive material into the intermediate substrate 110, a layer of one or a combination of Ta, TaN, Ti, TiN may be first deposited as a diffusion barrier layer or as an adhesion layer.

[0032] As in Fig. 6, a first redistribution layer is formed on the first surface, the first redistribution layer comprising a first dielectric wiring layer 131 and a first metallic wiring layer 132 electrically coupled to the conductive TSV pillar 120 disposed in the intermediate substrate 110, a second die 140 and the system integration chip 100 are provided, the mounting of the second die 140 and the system integration chip 100 on the first metallic wiring layer 132 being spaced around the head.

[0033] Specifically, depositing a first dielectric interconnect layer 131 on the first surface, patterning the first dielectric interconnect layer 131, exposing the conductive TSV pillar 120. Graphically depositing a barrier layer and a first metallic interconnect layer 132 on the first dielectric interconnect layer 131, wherein the first metallic interconnect layer 132 is electrically connected to the conductive TSV pillar 120, and an electrical signal interface of the conductive TSV pillar 120 is electrically connected to the first metallic interconnect layer 132 via the intermediate substrate 110.

[0034] The second die 140 includes various chips and devices, such as HBM (High Bandwidth Memory), DDR (Double Rate Synchronous Dynamic Random Memory), flash memory, transistors, and filters. The second die 140 also includes passive device integration chips, such as capacitors, resistors, and inductors. In this example, the number of the second die 140 and the system integration chip 100 is both shown as one. However, according to actual practice, the number of the second die 140 or the system integration chip 100 may be greater than or equal to 2, such as 3, 4, 5, and so on, and no limitation is made herein.

[0035] As an example, the flip-flop process is followed by the step of filling the gap between the second die 140 and the first dielectric wiring layer 131 and filling the gap between the system integration chip 100 and the first dielectric wiring layer 131 with a bottom fill adhesive.

[0036] In particular, after the flip-flop process, a bottom fill adhesive 151 may also fill the gap between the second die 140 and the first dielectric wiring layer 131 and the gap between the system integration chip 100 and the first dielectric wiring layer 131 to increase the drip resistance and bonding strength of the encapsulation structure and improve the encapsulation quality. The bottom fill adhesive 151 includes a filler material with smaller particles, such as epoxy resin, and the filling method includes, but is not limited to, one or more of capillary filling, mold filling, dispensing, and spin-coating.

[0037] As an example, the first plastic encapsulation layer 150 is also provided, wherein the first plastic encapsulation layer 150 wraps the second die 140, the system integration chip 100, with the first dielectric wiring layer 131. After forming the first plastic encapsulation layer 150, the surface of the first plastic encapsulation layer 150 may also be thinned and flattened according to practical needs, without being limited thereto.

[0038] As in Fig. 7, a second redistribution layer is formed on the second surface, the second redistribution layer comprising a second dielectric wiring layer 161 and a second metallic wiring layer 162 electrically connected to the conductive TSV pillar 120 disposed in the second dielectric wiring layer 161, and a first external interface 170 is formed on the second metallic wiring layer 162 remote from the surface of the conductive TSV pillar 120.

[0039] Similarly, the second metallic wiring layer 162 is electrically connected to the conductive TSV pillar 120, and the electrical signal interface of the conductive TSV pillar 120 is electrically connected to the second metallic wiring layer 162 via the intermediate substrate 110. The first external interface 170 includes solder balls and metal pads, with the first external interface 170 including solder balls in this example.

[0040] In summary, as in Fig. As shown in Figure 7, the described integrated 2.5D structure at system level includes: an intermediate substrate 110 comprising a first surface and a second surface opposite each other; a conductive TSV pillar 120 penetrating the intermediate substrate 110; a first redistribution layer disposed on the first surface of the intermediate substrate 110, comprising a first dielectric wiring layer 131 patterned with a first metallic wiring layer 132 electrically connected to the conductive TSV column 120 disposed in the intermediate substrate 110; a system integration chip 100 flip-folded on the surface of the first metallic wiring layer 132, which is a system-integrated 3D packaging structure including at least one system wafer 2 with a first die 11 hybrid-bonded to the system wafer 2; a second die 140 flip-folded on the surface of the first metallic wiring layer 132 is spaced from the system integration chip 100; a second redistribution layer disposed on the second surface, comprising a second dielectric wiring layer 161 having a second metallic wiring layer 162 electrically connected to the conductive TSV column 120 disposed in the intermediate substrate 110; and a first external interface 170 located on a surface of the second metallic wiring layer 162 remote from the conductive TSV pillar 120.

[0041] As an example, the first die 11 is a system chip belonging to different generations of semiconductor technologies in the same packaging chip as the system wafer 2.

[0042] As an example, the system integration chip 100 includes Fig. 4: a system wafer 2; a second dielectric layer 5 and a second metal pad 6 formed on the system wafer 2, the second metal pad 6 being patterned in the second dielectric layer 5 and electrically connected to the system wafer 2; a metal support 7 formed on and electrically connected to the second metal pad 6; a first die 11; a first dielectric layer 3 and a first metal pad 4 formed on the first die 11, the first metal pad 4 being disposed in the first dielectric layer 3 and electrically connected to the first die 11, the first dielectric layer 3 being connected correspondingly to the second dielectric layer 5, and the first metal pad 4 being connected correspondingly to the second metal pad 6; a plastic encapsulation layer 8, wherein the plastic encapsulation layer 8 encapsulates the first die 11, the metal support 7 with the second dielectric layer 5 and exposes the surface of the metal support 7; a redistribution layer 9 formed on the surface of the plastic encapsulation layer 8, the redistribution layer 9 comprising a dielectric wiring layer 91 and a metallic wiring layer 92 disposed in the dielectric wiring layer 91 and electrically connected to the metallic support 7; and an external interface 10 formed on the surface of the metallic wiring layer 92 remote from the metallic support 7.

[0043] In one case, the distance between two of the first metal contact points 4 is less than 5 µm and the distance between two of the second metal contact points 6 is less than 5 µm.

[0044] As an example, the dimension of the first metal pad 4 is not the same as the dimension of the second metal pad 6.

[0045] As an example, the metal support 7 is located on the side of the strip of the second metal contact points 6.

[0046] As examples, the first wafer 1 has a first signal interface on the front side, the first signal interface is electrically connected to the first metal pad 4, the configuration of the first metal pad 4 is different from the configuration of the first signal interface; the system wafer 2 has a second signal interface on the front side, the second signal interface is electrically connected to the second metal pad 6, the configuration of the second metal pad 6 is different from the configuration of the second signal interface.

[0047] As examples, the gap between the second die 140 and the first dielectric wiring layer 131 is filled with the lower fill adhesive 151, and the gap between the system integration chip 100 and the first dielectric wiring layer 131 is filled with the lower fill adhesive 151.

[0048] As an example, a first plastic encapsulation layer 150 is provided, wherein the first plastic encapsulation layer 150 wraps the second die 140, the system integration chip 100 with the first dielectric wiring layer 131.

[0049] As an example, the substrate of system wafer 2 is thinned and flattened.

[0050] In summary, the present disclosure provides a 2.5D system-integrated structure with the following advantageous effects: The system-integrated chip is a 3D system-stacked packaging structure that integrates system chips or wafers of different generations of semiconductor technologies into the same packaging chip using hybrid bonding, and stacks the lower- or older-generation system chips onto the higher- or later-generation system chips according to their characteristics, such as sizes and other characters. In order to realize more functions in the packaging structure of the same size, improve the functional density of the packaging structure, and optimize the wafer size, a system integration chip is applied to the 2.5D packaging structure to form a 2D integrated system.Forming a 5D system-level structure that integrates a variety of electronic chips and components, such as HBM / DDR / Flash / transistors / filters / passive device integration chips, allows for more functions to be realized in the same package size. It enables the same package size to realize more multifunctional systems that work together, eliminating the need for separate preparation of multiple packaging structures, eliminating the need for additional packaging structure connections, improving the overall performance of the integrated 2.5D system-level structure, and increasing economic benefits. In addition, the system also has the advantages of high flexibility and broad compatibility.

[0051] When the first signal interface of the first die in the system integration chip is electrically connected to the corresponding interface of the system wafer, the first metal pad and the second metal pad are aligned to directly electrically connect, thereby reducing the through path of the electrical connection, thereby reducing the parasitic capacitance in the packaging structure and improving the signal transmission efficiency; the distance between two of the first metal pads and between two of the second metal pads can be arranged to a pitch of less than 5 µm, so that the number of metal pads in the unit area can increase, thereby increasing the data channel density, data throughput, and the integration level;The size of the first metal pad and the second metal pad do not need to be the same, so as to overcome the problem of the placement accuracy of the hybrid interconnect chip and improve production efficiency.

[0052] The above embodiments merely illustrate the principles of the present disclosure and their effectiveness and are not intended to limit the disclosure. Anyone skilled in the art may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Accordingly, any equivalent modifications or changes made by persons of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein are still intended to be covered by the claims of the present disclosure.

Claims

[1] Integrated 2.5D system-level structure, including: an intermediate substrate having a first surface and a second surface opposite each other; a TSV conductive pillar having a first end and a second end opposite the first end, extending through the intermediate substrate; a first redistribution layer disposed on the first surface of the intermediate substrate, the first redistribution layer comprising a first dielectric wiring layer patterned with a first metallic wiring layer, the first metallic wiring layer being electrically connected to the first end of the TSV conductive pillars disposed in the intermediate substrate; a system integration chip flip-chip mounted on a first surface of the first metallic wiring layer, the system integration chip comprising a first system chip and a second system chip, the first system chip being connected to the second system chip; a second die flip-chip mounted on the first surface of the first metallic wiring layer, the second die being spaced from the system integration chip; a second redistribution layer disposed on the second surface of the intermediate substrate, the second redistribution layer comprising a second dielectric wiring layer patterned with a second metallic wiring layer, the second metallic wiring layer being electrically connected to the second end of the TSV conductive column; and a first external interface disposed on the second metallic wiring layer connected to the second end of the TSV conductive pillar. [2] The 2.5D system-level integrated structure of claim 1, wherein the first system chip and the second system chip belong to different generations of semiconductor technologies. [3] The 2.5D system-level integrated structure of claim 1, wherein the system integration chip further comprises: a second dielectric layer and second metal pads formed on the second system chip, the second metal pads being patterned in the second dielectric layer and electrically connected to the second system chip; a metal support formed on and electrically connected to the second metal contact pads; a first dielectric layer and first metal pads formed on the first system chip, the first metal pads being patterned in the first dielectric layer and electrically connected to the first system chip, the first dielectric layer and the second dielectric layer being aligned and connected respectively, and the first metal pads being connected respectively to the second metal pads; a plastic encapsulation layer, the plastic encapsulation layer enclosing the first system chip and the metal support connected to the second metal pads and exposing a top surface of the metal support; a redistribution layer formed on a surface of the plastic encapsulation layer, the redistribution layer comprising a dielectric wiring layer and a metallic wiring layer patterned in the dielectric wiring layer, the metallic wiring layer being electrically connected to the metal support; and an external interface formed on a surface of the metallic wiring layer remote from the metallic support. [4] The system-level 2.5D integrated structure of claim 3, wherein a distance between two of the first metal pads is less than 5 µm and a distance between the second metal pads is less than 5 µm. [5] The system-level 2.5D integrated structure of claim 3, wherein a dimension of one of the first metal pads and a dimension of one of the second metal pads are different. [6] The 2.5D system-level integrated structure of claim 3, wherein the metal support is disposed on one of the second metal pads on one side of the second system chip. [7] The 2.5D system-level integrated structure of claim 3, wherein the first system chip comprises a first signal interface on a surface, the first signal interface being electrically connected to the first metal pads, a configuration of the first metal pads being different from a configuration of the first signal interface; wherein the second system chip comprises a second signal interface on a surface, the second signal interface being electrically connected to the second metal pads, and a configuration of the second metal pads being different from a configuration of the second signal interface. [8] The 2.5D system-level integrated structure according to claim 1, wherein a gap between the second die and the first dielectric wiring layer is filled with a bottom fill adhesive, and wherein a gap between the system integration chip and the first dielectric wiring layer is filled with the bottom fill adhesive. [9] The 2.5D system-level integrated structure of claim 1, wherein a first plastic sealing layer is provided, the first plastic encapsulation layer surrounding the second die, the system integration chip, and the first dielectric wiring layer. [10] The system-level 2.5D integrated structure of claim 1, wherein the intermediate substrate is thinned and planarized.

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