Improved contact structure for a power supply on a semiconductor device and methods for manufacturing the same

Abstract

Semiconductor structure (100) which exhibits: a plurality of source / drain regions (1220) within a field-effect transistor; a rear metal contact (1930) electrically connected to at least one source / drain region of the plurality of source / drain regions, wherein the rear metal contact includes a first tapered profile whose upper (CD1) and lower (CD2) dimensions are the upper and lower dimensions of the rear metal contact, respectively, and the upper dimension (CD1) is smaller than the lower dimension (CD2); and a rear busbar (1920) which is electrically connected to the at least one source / drain area by the rear metal contact, wherein the rear busbar includes a second tapered profile, the upper (CD3) and lower (CD4) dimensions of which are the upper and lower dimensions of the rear busbar respectively, and the upper dimension (CD3) of the rear busbar is larger than its lower dimension (CD4).

Description

BACKGROUND

[0001] The present invention relates generally to the field of semiconductor devices and in particular to a power supply for active devices.

[0002] Modern integrated circuits (ICs) consist of transistors, capacitors, and other components mounted on semiconductor substrates. These components are initially isolated from one another on the substrate but are subsequently interconnected to form functional circuits. Typical interconnect structures include lateral connections such as metal traces (wiring) and vertical connections such as vias and contacts. Power is supplied to the integrated circuits via busbars located within the metal layers of the ICs. The bottom metal layer (M0 or M1), for example, can contain multiple metal traces such as VDD busbars and VSS busbars.

[0003] With the increasing miniaturization of integrated circuits (ICs), backside power rails (BPRs) – that is, power rails formed on the back of the wafer, typically beneath the transistor fins – and a backside power supply (the "backside" being beneath the transistor substrate) have been proposed to alleviate design problems and enable technology scaling beyond the 5 nm technology node. BPR technology can free up resources for dense logic interconnects, which limit the performance of modern processors; allow for further scaling of a standard logic cell by eliminating the overhead in the area occupied by the power rails; and permit thicker, low-resistance power rails that enable lower voltage drops (IR).Although previous approaches to semiconductor manufacturing were generally suitable for their intended purposes, they were not entirely satisfactory in every respect. One particularly interesting area is the formation of metal contacts on the back of ICs, as described, for example, in DE 10 2020 119 415 A1 and DE 11 2022 005 536 T5. SUMMARY

[0004] According to one embodiment of the present disclosure, a semiconductor structure comprises a plurality of source / drain regions within a field-effect transistor, a rear metal contact electrically connected to at least one source / drain region of the plurality of source / drain regions, wherein the rear metal contact includes a first tapered profile, and a rear current rail electrically connected to the at least one source / drain region through the rear metal contact, wherein the rear current rail includes a second tapered profile, the second tapered profile being different from the first tapered profile.

[0005] According to a further embodiment of the invention as presented in the disclosure, a method for forming a semiconductor structure comprises forming a plurality of source / drain regions within a field-effect transistor, forming a rear metal contact which is electrically connected to at least one source / drain region of the plurality of source / drain regions, wherein the rear metal contact comprises a first tapered profile, and forming a rear busbar which is electrically connected to the at least one source / drain region through the rear metal contact, wherein the rear busbar comprises a second tapered profile, wherein the second tapered profile differs from the first tapered profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description, which serves as an example and is not intended to limit the invention exclusively to it, is best understood in conjunction with the accompanying drawings, in which: Fig. 1 is a top view of a semiconductor structure at an intermediate step during a semiconductor manufacturing process, showing various cross-sectional views used to describe embodiments of the present disclosure; Fig. 2 a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents the formation of a nanosheet stack according to an embodiment of the present disclosure; Fig. 3 A cross-sectional view of the semiconductor structure along the line Y1-Y1', as shown in Fig. 1 is shown, which represents a structuring of the nanosheet stack and a formation of nanosheet fins according to an embodiment of the present disclosure; Fig. 4A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. Figure 1 shows a deposition of a dummy gate and a sacrificial hard mask according to an embodiment of the present disclosure; Fig. 4B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 4C is a cross-sectional view of the semiconductor structure along a line XX' according to an embodiment of the present disclosure; Fig. 5A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents the removal of a sacrificial layer of a nanosheet stack according to an embodiment of the present disclosure; Fig. 5B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 5C is a cross-sectional view of the semiconductor structure along a line XX' according to an embodiment of the present disclosure; Fig. 6A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. Figure 1 shows a formation of a side wall spacer element according to an embodiment of the present disclosure; Fig. 6B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 6C is a cross-sectional view of the semiconductor structure along a line XX' according to an embodiment of the present disclosure; Fig. 7A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents a deepening of nanosheet fins and a formation of internal spacer elements according to an embodiment of the present disclosure; Fig. 7B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 7C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 8A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents the formation of a spacer element protective layer and the structuring of rear contacts according to an embodiment of the present disclosure; Fig. 8B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 8C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 9A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents a sigma etching of a first semiconductor layer according to an embodiment of the present disclosure; Fig. 9B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 9C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 10A a cross-sectional view of the semiconductor structure along Y1-Y1', as in Fig. Figure 1 shows a process of forming a placeholder layer and removing a planarization layer according to an embodiment of the present disclosure; Fig. 10B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 10C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 11A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. Figure 1 shows a removal of the spacer protective layer and the formation of a back-end-of-line connection plane and a support wafer according to an embodiment of the present disclosure; Fig. 11B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 11C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 12A a cross-sectional view of the semiconductor structure along Y1-Y1', as in Fig. Figure 1, which represents the completion of front-end-of-line (FEOL) processing steps according to an embodiment of the present disclosure; Fig. 12B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 12C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 13A a cross-sectional view of the semiconductor structure along Y1-Y1', as in Fig. Figure 1 shows a process which involves performing a replacement metal gate process, performing a middle-of-line contact structuring and metallization, and forming a back-end-of-line interconnect plane and a support wafer according to an embodiment of the present disclosure; Fig. 13B a ​​cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 13C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 14A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. Figure 1, which represents the removal of a semiconductor substrate according to an embodiment of the present disclosure; Fig. 14B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 14C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 15A a cross-sectional view of the semiconductor structure along Y1-Y1', as in Fig. 1 is shown, which represents a removal of the first sacrificial layer and an etching of sections of the first semiconductor layer to expose the placeholder layer, according to an embodiment of the present disclosure; Fig. 15B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 15C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 16A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents the removal of remaining Si-containing surface areas according to an embodiment of the present disclosure; Fig. 16B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 16C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 17A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents a formation of a first rear-side interlayer dielectric according to an embodiment of the present disclosure; Fig. 17B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 17C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 18A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 shown, which represents a selective removal of the placeholder layer according to an embodiment of the present disclosure; Fig. 18B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 18C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 19A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. 1 is shown, which represents a deposition of a back-side metal according to an embodiment of the present disclosure; Fig. 19B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 19C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 20A a cross-sectional view of the semiconductor structure along Y1-Y1', as in Fig. 1 shown, which represents a structuring of a rear busbar according to an embodiment of the present disclosure; Fig. 20B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to one embodiment of the present disclosure; Fig. 20C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure; Fig. 21A a cross-sectional view of the semiconductor structure along Y1-Y1', as shown in Fig. Figure 1 shows a rear power supply network formed according to an embodiment of the present disclosure; Fig. 21B a cross-sectional view of the semiconductor structure along a line Y2-Y2', as shown in Fig. 1 shown, according to an embodiment of the present disclosure according to the invention; and Fig. 21C is a cross-sectional view of the semiconductor structure along line XX' according to an embodiment of the present disclosure according to the invention.

[0007] The drawings are not necessarily to scale. They are merely schematic representations and are not intended to depict specific parameters of the invention. The drawings are intended only to illustrate typical embodiments of the invention. In the drawings, identical reference numerals represent identical elements. DETAILED DESCRIPTION

[0008] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments serve only to illustrate the claimed structures and methods, which may be embodied in various forms. This invention can, however, be embodied in many different forms and should not be interpreted as being limited to the exemplary embodiments set forth herein. Details of generally known features and techniques may be omitted from the description to avoid making the present embodiments unnecessarily unclear. The claimed semiconductor structure and the corresponding method for forming the semiconductor structure are defined by the independent claims.

[0009] For descriptive purposes, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "above", "lowest", and derivatives thereof shall refer to the disclosed structures and procedures as they are oriented in the figures of the drawings. Terms such as "above", "above", "over", "on", "positioned on", or "positioned over" mean that a first element, such as a first structure, is located on top of a second element, such as a second structure, whereby intermediate elements, such as an interface structure, may be located between the first and second elements.The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intervening conductive, insulating, or semiconductor layers.

[0010] To avoid any ambiguity in the presentation of embodiments of the invention, some processing steps or operations from the prior art may be summarized in the following detailed description for the purposes of presentation and / or illustration, and in some cases not described in detail. In other cases, some processing steps or operations from the prior art may not be described at all. It is understood that the following description focuses primarily on characteristic features or elements of various embodiments of the present invention.

[0011] It is understood that, although the disclosed embodiments contain a detailed description of an exemplary nanosheet FET architecture with silicon and silicon-germanium nanosheets, the implementation of the teachings mentioned herein is not limited to the specific FET architecture described herein. Rather, embodiments of the present invention are capable of being implemented together with any other type of FET unit, now known or subsequently developed.

[0012] Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating it, in which improved backside metal contacts are formed for connecting to busbars located on the back side of the wafer. The backside metal contacts and the backside busbars are formed by backside processes performed after completion of BEOL processes and flipping of the wafer. In particular, a sigma etching process is performed to obtain backside contacts with a first taper angle that differs from a second taper angle of the backside busbars.The Sigma etching process and the use of a placeholder material enable the simultaneous deposition of conductive metals to form rear contacts and rear busbars in fewer processing steps, thereby simplifying the manufacturing process and increasing the contact area between rear metal contacts and rear busbars for improved unit performance and reliability.

[0013] An embodiment in which the semiconductor structure can be formed with an improved rear metal contact is described below with reference to the accompanying drawings. Fig. Sections 1 to 21C are described in detail.

[0014] With reference to Fig. Figure 1 shows a top view of a semiconductor structure 100 in an intermediate step during a semiconductor manufacturing process according to an embodiment of the present disclosure. In particular, the figure represents Fig. Figure 1 shows different cross-sectional views of the semiconductor structure 100, which are used to describe embodiments of the present disclosure. The cross-sectional views are shown along a line X-X', a line Y1-Y1', and a line Y2-Y2'. As shown in the figure, line X' represents a section along a nanosheet fin structure or nanosheet fin region 20 of the semiconductor structure 100, line Y1-Y1' represents a cross-section through source / drain regions in NFET regions 12 and PFET regions 16 of the semiconductor structure 100, and line Y2-Y2' represents a section along a gate structure or gate region 24 of the semiconductor structure 100.

[0015] In this embodiment, the cross-sectional view along the line Y1-Y1' may further include a view of NFET regions 12 and / or PFET regions 16 and a surface region (an NP boundary) 14 between the NFET and PFET regions 12 and 16. Furthermore, the cross-sectional view along the line Y1-Y1' may include a view of a region 22 of a shared buried power rail (BPR).

[0016] With reference to Fig. Figure 2 shows a cross-sectional view of the semiconductor structure 100 after forming a nanosheet stack 10 according to an embodiment of the present disclosure. This embodiment is a Fig. 2 to show a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as in Fig. 1 shown.

[0017] In the illustrated example, the semiconductor structure 100 comprises a substrate 102, a first sacrificial layer 104 located above the substrate 102, and a first semiconductor layer 106 arranged above the first sacrificial layer 104. According to one embodiment, the first sacrificial layer 104 and the first semiconductor layer 106 are stacked vertically on top of each other in a direction perpendicular to the substrate 102, as illustrated in the figure.

[0018] The substrate 102 can, for example, be a solid substrate made of any of the various known semiconductor materials, such as silicon, germanium, a silicon-germanium alloy, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide or indium gallium phosphide. Typically, the substrate 102 can be, but is not limited to, several hundred micrometers thick. In other embodiments, the substrate 102 can be a multilayer semiconductor, such as a semiconductor-on-insulator or SiGe-on-insulator, wherein a buried insulator layer separates a base substrate from an upper semiconductor layer.

[0019] Furthermore, with reference to Fig. 2. According to one embodiment, the first sacrificial layer 104 can be formed on the substrate 102 by means of an epitaxial growth process. For example, in the described embodiment, the first sacrificial layer 104 is formed by epitaxial growth of a layer of SiGe with a germanium concentration that varies from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, the first sacrificial layer 104 is produced from epitaxially grown SiGe with a germanium concentration of about 30 atomic percent. In one or more embodiments, the first sacrificial layer 104 can act as an etch stop layer during subsequent removal of the substrate.Similarly, the first semiconductor layer 106 is formed by epitaxial growth of a Si layer to a thickness varying from about 30 nm to about 150 nm, although other thicknesses are within the scope of the invention. In some embodiments, the first sacrificial layer 104 may contain SiO2. In such embodiments, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 may be an SOI wafer, wherein the first sacrificial layer 104 is the buried oxide (BOX) having a thickness in the range of about 20 nm to about 100 nm and regions in between.

[0020] In general, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed using the substrate 102 as a seed layer by epitaxial growth. Terms such as "epitaxial growth and / or epitaxial deposition" and "epitactically formed and / or grown" refer to the growth of a semiconductor material on a depositional surface of a semiconductor material, where the semiconductor material being grown has the same or substantially similar crystalline properties as the semiconductor material of the depositional surface.In an epitaxial deposition process, the chemical reactants supplied by the source gases are controlled, and the system parameters are set such that the deposited atoms impact the semiconductor substrate's deposition surface with sufficient energy to move across the surface and orient themselves toward the crystal arrangement of atoms on the deposition surface. Therefore, an epitaxial semiconductor material exhibits the same or substantially similar crystalline properties as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface adopts a {100} orientation.In some embodiments, epitaxial growth and / or deposition processes are selective towards forming on a semiconductor surface and do not deposit material on dielectric surfaces such as silicon dioxide or silicon nitride surfaces.

[0021] Non-restrictive examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). The temperature for an epitaxial deposition process can range from 500 °C to 900 °C.Although higher temperatures typically lead to faster deposition, faster deposition can result in crystal defects and cracking in thin films.

[0022] A variety of different precursors can be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, a gas source for the deposition of an epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source, including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorosilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source, including, but not limited to, germanium, digerman, halogerman, dichlorgerman, trichlorogerman, tetrachlorogerman, and combinations thereof.In contrast, an epitaxial silicon germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, helium, and argon can be used.

[0023] In the illustrated embodiment, an alternating sequence of layers of a sacrificial semiconductor material and layers of a semiconductor channel material, stacked vertically one above the other in a direction perpendicular to the substrate 102, forms the nanosheet stack 10, as illustrated in the figure. Specifically, the alternating sequence includes a sacrificial layer 108 of the nanosheet stack over the first semiconductor layer 106, a second sacrificial semiconductor layer 110 over the sacrificial layer 108 of the nanosheet stack, and a semiconductor channel layer 112 over the second sacrificial semiconductor layer 110. In the example shown in the figure, alternating second sacrificial semiconductor layers 110 and semiconductor channel layers 112 are formed in a (nanosheet) stack 10 over the sacrificial layer 108 of the nanosheet stack.The term "sacrifice," as used herein, means a layer or other structure that (or part of it) is removed prior to the completion of the final unit.

[0024] For example, in the described example, sections of the second sacrificial semiconductor layers 110 are removed from the stack in the channel region of the unit to allow the semiconductor channel layers 112 to detach from the nanosheet stack 10. It should be noted that, although in the present example the second sacrificial semiconductor layers 110 and the semiconductor channel layers 112 are made of silicon germanium (SiGe) and silicon (Si), respectively, any combination of sacrificial and channel materials can be used according to the techniques described. For example, a selective etching technology can be used instead, which allows Si to be used as the sacrificial material between Si-Ge channel layers.

[0025] Furthermore, with reference to Fig. 2. A first (sacrificial) layer in the stack, i.e., the sacrificial layer 108 of the nanosheet stack, is formed on the first semiconductor layer 106 by means of an epitaxial growth process. For example, in the described embodiment, the sacrificial layer 108 of the nanosheet stack is formed by epitaxial growth of a SiGe layer with a higher germanium concentration, varying between about 45 atomic percent and about 70 atomic percent. In a preferred embodiment, the sacrificial layer 108 of the nanosheet stack contains a SiGe layer with a germanium concentration of about 55 atomic percent. The higher concentration of germanium atoms allows the sacrificial layer 108 of the nanosheet stack to be selectively removed from the remaining alternating layers of the nanosheet stack 10, as will be explained in detail below.As just an example, the sacrificial layer 108 of the nanosheet stack can be formed with a thickness that varies from about 5 nm to about 20 nm, although thicknesses of more than 20 nm and less than 5 nm can also be used.

[0026] In general, layers in the nanosheet stack 10 (e.g., SiGe and Si layers) can be formed by epitaxial growth using the first semiconductor layer 106 as a seed layer. For example, the second sacrificial semiconductor layers 110 are formed by epitaxial growth of a SiGe layer. In this embodiment, the germanium concentration of the second sacrificial semiconductor layers 110 can vary from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, each of the second sacrificial semiconductor layers 110 contains a SiGe layer with a germanium concentration of about 30 atomic percent.

[0027] To further construct the nanosheet stack 10, the semiconductor channel layers 112 are formed by epitaxial growth of a Si layer. As shown in the figure, the second sacrificial semiconductor layers 110 and the semiconductor channel layers 112 have substantially similar or identical thicknesses. The nanosheet stack 10 is grown by alternately forming (SiGe) sacrificial semiconductor layers 110 and (Si) semiconductor channel layers 112 on the sacrificial layer 108 of the nanosheet stack. Accordingly, each of the second sacrificial semiconductor layers 110 and the semiconductor channel layers 112 in the nanosheet stack 10 can be formed in the same manner as described above, e.g., by means of an epitaxial growth process, to a thickness varying from about 6 nm to about 12 nm, although other thicknesses are within the scope of the invention.

[0028] In this way, each layer in the nanosheet stack 10 has dimensions in the nanoscale and can therefore also be referred to as a nanosheet. Furthermore, the (Si) semiconductor channel layers 112 in the nanosheet stack 10, as highlighted above, are used to form the channel layers of the unit. Consequently, the dimensions of the semiconductor channel layers 112 define the dimensions of the channel region of the semiconductor structure 100.

[0029] As highlighted above, the task is to create a stack of alternating (sacrificial and channel) SiGe and Si layers on the wafer. The number of layers in the stack can be adjusted depending on the specific application. Therefore, the configurations shown and described herein are merely examples intended to illustrate the techniques presented. For instance, the present nanosheet stack could contain 10 more or fewer layers than shown in the figures.

[0030] The nanosheet stack 10 can be used to create a gate-all-around unit containing vertically stacked nanosheets made of a semiconductor channel material for a unit with a positive channel field-effect transistor (hereinafter referred to as "PFET") or a negative channel field-effect transistor (hereinafter referred to as "NFET").

[0031] In the illustrated embodiment, the semiconductor structure 100 further comprises a hard mask layer 202, which is formed by depositing a hard mask material (e.g., silicon nitride) over the nanosheet stack 10, for example, using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable dielectric deposition technique. By way of example only, the hard mask layer 202 can be formed with a thickness varying from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm can also be used.

[0032] With reference to Fig. Figure 3 shows a cross-sectional view of the semiconductor structure 100 after structuring the nanosheet stack 10 to form a plurality of nanosheet fins (hereinafter referred to as "nanosheet fins") according to an embodiment of the present disclosure. This embodiment is a Fig. 3 to show a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as in Fig. 1 shown.

[0033] After the separation of the in Fig. Following the hard mask layer 202 shown in Figure 2, photolithographic structuring is subsequently performed on the deposited hard mask layer 202 to form a plurality of individual fin hard masks. According to an exemplary embodiment, reactive ion etching (RIE) can be used to etch through the nanosheet stack 10 to form nanosheet fins 302. The etching process can continue until upper portions of the first semiconductor layer 106 located between adjacent nanosheet fins 302 have been removed, forming a plurality of (not shown) trenches. The plurality of (not shown) trenches formed during the photolithographic structuring process are subsequently filled with an insulating material to form areas 310 of shallow trench isolation (STI), as shown in the figure.

[0034] The process for forming the STI regions 310 is standard and generally known in the art. It typically involves depositing the insulating material to substantially fill the majority of the (not shown) trenches created after removing the sections of the first semiconductor layer 106 located between adjacent nanosheet fins 302. According to one embodiment, the STI regions 310 electrically insulate the nanosheet fins 302. The STI regions 310 can be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the STI regions 310 include silicon dioxide, silicon nitride, hydrogenated silicon carbon dioxide, low-k dielectrics based on silicon, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.After forming the STI areas 310, the hard mask layer 202 (. Fig. 2) removed from the semiconductor structure 100 using any suitable etching technique.

[0035] With reference to Fig. Figures 4A to 4C show cross-sectional views of the semiconductor structure 100 after deposition of a dummy gate 410 and a sacrificial hard mask 420 according to an embodiment of the present disclosure. In this embodiment, Fig. 4A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 4B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 4C is a cross-sectional view of the semiconductor structure 100 along a line X-X', as shown in Fig. 1 shown.

[0036] The dummy gate 410 and the sacrificial hard mask 420 form a sacrificial gate structure for the semiconductor structure 100. The process for forming the dummy gate 410 and the sacrificial hard mask 420 is typical and generally known in the art. In one or more embodiments, the dummy gate 410 is formed from amorphous silicon (a-Si), and the sacrificial hard mask 420 is formed from silicon nitride (SiN), silicon oxide, an oxide / nitride stack, or similar materials and configurations.

[0037] After the deposition of the dummy gate 410 and the sacrificial hard mask 420 on the semiconductor structure 100, the dummy gate 410 and the sacrificial hard mask 420 are patterned, as shown in the figures. As is known to those skilled in the art, the process for patterning the dummy gate 410 typically involves exposing a pattern onto a (not shown) photoresist layer and transferring the pattern to the sacrificial hard mask 420 and the dummy gate 410 using a known lithography and RIE processing technique, as shown in Fig. 4C is shown. The dummy gate 410 is formed and structured above a top semiconductor channel layer 112 and along sidewalls of the nanosheet fins 302. As shown in Fig. As shown in Figure 4C, the structuring of the dummy gate 410 exposes sections of the top semiconductor channel layer 112, which is located between sacrificial gate structures. As mentioned above, the cross-sectional view of Fig. 4A along Y1-Y1', as in Fig. 1 shown, so that Fig. 4A does not represent the victim-gate structure formed by the dummy gate 410 and the victim hard mask 420.

[0038] With reference to Fig. 5A to 5C show cross-sectional views of the semiconductor structure 100 after removal of the sacrificial layer 108 of the nanosheet stack ( Fig. 4A to 4C) according to one embodiment of the present disclosure. In this embodiment, Fig. 4A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 5B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 5C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0039] As shown in the illustrated embodiment, the removal of the sacrificial layer 108 of the nanosheet stack ( Fig. 4A to 4C) first openings 502 in area regions of the semiconductor structure 100, of which the sacrificial layer 108 of the nanosheet stack ( Fig. 4A to 4C). According to one embodiment, the sacrificial layer 108 of the nanosheet stack is selectively removed from the first semiconductor layer 106, the second sacrificial semiconductor layers 110, the semiconductor channel layers 112, the dummy gate 410, and the sacrificial hard mask 420. For example, a highly selective dry etching process can be used to remove the sacrificial layer 108 of the nanosheet stack ( Fig. 4A to 4C) to selectively remove.

[0040] With reference to Fig. Figures 6A to 6C show cross-sectional views of the semiconductor structure 100 after forming a sidewall spacer element 610 according to an embodiment of the present disclosure. In this embodiment, Fig. 6A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 6B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 6C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0041] In this embodiment, a spacer material is deposited on the semiconductor structure 100. As in Fig. As shown in Figure 6C, the spacer material is deposited along the sidewalls of the dummy gate 410 and the sacrificial hard mask 420 to form the sidewall spacer 610. The spacer material forming the sidewall spacer 610 essentially fills the space shown in Figure 6C. Fig. The first openings 502 are shown in Figures 5A to 5C. The sidewall spacer 610 can be formed using a spacer pull-down formation process. Furthermore, the sidewall spacer 610 can be formed using a sidewall image transfer (SIT) spacer formation process, which includes the deposition of a spacer material followed by directional RIE of the deposited spacer material. In one or more embodiments, the spacer material deposited between a lower surface of the nanosheet fins 302 and the substrate 102 can be referred to as the lower dielectric insulating layer 620. In some embodiments, the lower dielectric insulating layer 620 and the sidewall spacer 610 can be made of different materials.

[0042] Non-restrictive examples of different spacer material materials for forming the sidewall spacer 610 and the lower dielectric insulating layer 620 include conventional low-k materials such as SiO2, SiOC, SiOCN, or SiBCN. Typically, the thickness of the sidewall spacer 610 can vary from about 5 nm to about 20 nm and in the ranges in between.

[0043] With reference to Fig. Figures 7A to 7C show cross-sectional views of the semiconductor structure 100 after deepening the nanosheet fins 302 and forming internal spacer elements 720 according to an embodiment of the present disclosure. In this embodiment, Fig. 7A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 7B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 7C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0044] As experts know, the sidewall spacer 610 can be used as a mask to recess sections of the nanosheet fins 302 that are not covered by the sidewall spacer 610 and the dummy gate 410, as shown in Fig. Figure 7C illustrates this. For example, a RIE process can be used to deepen the sections of the nanosheet fins 302 that are not located below the sidewall spacer element 610 and the dummy gate 410. According to one embodiment, the nanosheet fins 302 can be deepened until an upper section of the lower dielectric insulating layer 620 is reached. As shown in Fig. 7A and Fig. As shown in Figure 7C, the deepening of the nanosheet fins 302 forms second openings (or source / drain depressions) 730 in the semiconductor structure 100.

[0045] Furthermore, with reference to Fig. In sections 7A to 7C, outer portions of each of the second sacrificial semiconductor layers 110 are selectively deepened, for example, by means of a selective etching process such as hydrogen chloride (HCl) gas etching. The selected etching process for deepening the second sacrificial semiconductor layers 110 is preferably capable of etching silicon-germanium without attacking silicon. The internal spacers 720 can be formed within a (not shown) indented cavity that is formed after etching the second sacrificial semiconductor layers 110. The internal spacers 720 can be formed, for example, by conformal deposition of a dielectric material for internal spacers that constricts the (not shown) indented cavity that is formed after deepening the second sacrificial semiconductor layers 110.The internal spacer elements 720 can be formed using any suitable dielectric material, such as silicon dioxide, silicon nitride, SiOC, SiOCN, or SiBCN, and can contain a single layer or multiple layers of dielectric materials. Subsequently, isotropic etching can be performed to remove excess material from the internal spacer elements from other areas of the semiconductor structure 100.

[0046] As in Fig. As shown in Figure 7C, the outer side walls of the inner spacer elements 720 are vertically aligned with the semiconductor channel layers 112 and consequently with upper sections of the side wall spacer element 610, which are located on opposite side walls of the dummy gate 410.

[0047] With reference to Fig. Figures 8A to 8C show cross-sectional views of the semiconductor structure 100 after forming a nanosheet protective layer 802 and structuring the backside contacts according to an embodiment of the present disclosure. In this embodiment, Fig. 8A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 8B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 8C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0048] According to one embodiment, the nanosheet protective layer 802 is located within the second openings 730 ( Fig. 6A to 6C) formed on opposite sides of the side wall spacer element 610, as shown in Fig. 8A and Fig. Figure 8C illustrates this. In an exemplary embodiment, the nanosheet protective layer 802 can consist of SiN, TiOx, AlOx, SiO2, SiOCN, SiC, and equivalent materials. An ALD deposition process followed by an anisotropic etching process can be used to form the nanosheet protective layer 802, as shown in Figure 8C. Fig. 8A and Fig. 8C configured. In particular, the nanosheet protective layer 802 is designed such that only sections of the nanosheet protective layer 802 remain perpendicular to the substrate 102 in the semiconductor structure 100. The thickness of the nanosheet protective layer 802 can vary from approximately 1 nm to approximately 3 nm and in ranges in between. As the name suggests, the nanosheet protective layer 802 can protect the integrity of the sidewall spacer element 610 and the nanosheet fins 302 during a subsequent etching process.

[0049] After the formation of the nanosheet protective layer 802, an organic planarization layer (OPL), or simply planarization layer 804, can be deposited onto the semiconductor structure 100. The planarization layer 804 can be made from any organic planarization material capable of effectively preventing damage to underlying layers during subsequent etching processes. The planarization layer 804 can contain an organic polymer with C, H, and N, but is not necessarily limited to this. In one embodiment, the organic planarization material can be free of silicon (Si). In another embodiment, the organic planarization material can be free of Si and fluorine (F).As defined herein, a material is free of an atomic element if the content of the atomic element in the material is at or below a trace level detectable by analytical methods available according to the state of the art. Non-restrictive examples of organic planarizing materials for forming the planarizing layer 804 may include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials. The planarizing layer 804 may be deposited, for example, by spin coating.

[0050] Furthermore, with reference to Fig. 8A to 8C, a lithography process is carried out, followed by an etching process on the semiconductor structure 100 to etch the planarization layer 804 and to remove a section of the first semiconductor layer 106 to form third openings 810, as shown in Fig. 8A and Fig. Figure 8C illustrates this. In some embodiments, the etching of the planarization layer 804 can be performed, for example, by an OPL-RIE including trace point detection. The removal of the portion of the first semiconductor layer 106 can be performed by the same or a different etching process that is selective with respect to the nanosheet protective layer 802, the STI regions 310, and the lower dielectric insulating layer 620.

[0051] In one or more embodiments, a position of the third openings 810 can be selected based on a desired position of subsequently formed rear metal contacts.

[0052] With reference to Fig. Figures 9A to 9C show cross-sectional views of the semiconductor structure 100 after sigma etching of the first semiconductor layer 106 according to an embodiment of the present disclosure. In this embodiment, Fig. 9A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 9B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 9C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0053] In the illustrated embodiment, a sigma etching process is performed on the first semiconductor layer 106, further increasing the size of the third openings 810 and exposing an upper section of the first sacrificial layer 104. As may be known to those skilled in the art, sigma etching is synonymous with the terms "crystallographic etching" and "anisotropic etching along crystal planes." Sigma etching incorporates the use of a chemical etchant. Examples of chemical etchants that can be used for sigma etching include, but are not limited to, potassium hydroxide, tetraethylammonium hydroxide, or an aqueous solution of ethylenediamine and catechol.

[0054] Sigma etching is an etching process that produces a sigma shape, cleaving a section of the first semiconductor layer 106. As in Fig. Figure 9C illustrates that after performing the sigma etching process, a sigma shape 902 is formed within the first semiconductor layer 106.

[0055] With reference to Fig. Figures 10A to 10C show cross-sectional views of the semiconductor structure 100 after the formation of a placeholder layer 1020 and the removal of the planarization layer 804 ( Fig. 9A to 9C) according to an embodiment of the present disclosure. In this embodiment, Fig. 10A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as in Fig. 1 shown; is Fig. Figure 10B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. Figure 10C shows a cross-sectional view of the semiconductor structure 100 along a line X-X', as shown in Fig. 1 shown.

[0056] According to one embodiment, a layer of any suitable material can be deposited within the third openings 810 to form the placeholder layer 1020. In one or more embodiments, the material forming the placeholder layer 1020 can, for example, contain SiGe, AlOx, TiOx, and the like. In particular, the material forming the placeholder layer 1020 essentially fills sigma-shaped third openings 810, as illustrated in the figures. In some embodiments, an upper surface of the placeholder layer 1020 can be coplanar with an upper surface of the lower dielectric insulating layer 620. The placeholder layer 1020, as indicated by its name, acts as a placeholder for subsequently formed rear-side metal contacts.

[0057] After the formation of the placeholder layer 1020, the planarization layer 804 can be removed from the semiconductor structure 100. Examples of techniques for removing the planarization layer 804 ( Fig. 9A to 9C) of the semiconductor structure 100 can be treated with an oxygen plasma, nitrogen plasma, hydrogen plasma, or other carbon removal or ashing process that causes minimal or no damage to the underlying layers. Removing the planarization layer 804 exposes the top surfaces of the lower dielectric insulating layer 620, the STI areas 310, and the nanosheet protective layer 802.

[0058] With reference to Fig. Figures 11A to 11C show cross-sectional views of the semiconductor structure 100 after removal of the nanosheet protective layer 802 ( Fig. 10A to 10C) according to an embodiment of the present disclosure. In this embodiment, Fig. 11A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 11B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. Figure 11C shows a cross-sectional view of the semiconductor structure 100 along a line X-X', as shown in Fig. 1 shown.

[0059] Examples of techniques for removing the nanosheet protective layer 802 ( Fig. 10A to 10C) of the semiconductor structure 100, selective wet or dry etching processes can be used, which cause minimal or no damage to the underlying layers, without being limited to them. The removal of the nanosheet protective layer 802 ( Fig. 10A to 10C) exposes the upper surfaces of the side wall spacer element 610, the lower dielectric insulating layer 620, the STI areas 310, the inner spacer elements 720 and the semiconductor channel layers 112, as shown in the figures.

[0060] With reference to Fig. Figures 12A to 12C show cross-sectional views of the semiconductor structure 100 after completion of front-end-of-line (FEOL) processing steps according to an embodiment of the present disclosure. In this embodiment, Fig. 12A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 12B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. 12C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0061] Known processes for manufacturing semiconductors have been used to form the semiconductor structure 100, as shown in Fig. Figures 12A to 12C illustrate this. Therefore, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may not be described in detail herein. Furthermore, the various tasks and process steps described herein may be integrated into a broader procedure or process with additional steps or functions not detailed here. In particular, several steps in the fabrication of semiconductor devices and ICs based on semiconductors are generally known, and therefore, for the sake of brevity, numerous conventional steps are only briefly mentioned or omitted entirely without providing the generally known details of the processes.

[0062] In general, source / drain regions 1220 can be formed in the semiconductor structure 100 during this step of the manufacturing process. As is known to experts, source / drain regions are formed within (in Fig. 1 NFET and PFET regions 12, 16 of the semiconductor structure 100 are formed. For example, the source / drain regions 1220 can be formed on the exposed ends of the semiconductor channel layers 112 using an epitaxial layer growth process.

[0063] The source / drain regions 1220 can be formed on opposite sides of the nanosheet fins 302 in direct contact with end sections of the semiconductor channel layers 112 and end sections of the inner spacer elements 720. An upper section of the source / drain regions 1220 can have a diamond shape resulting from the different growth rates during the epitaxial deposition process, which are characteristic of each crystallographic orientation plane of the material forming the source / drain regions 1220. In other embodiments, the source / drain regions 1220 can have a different shape than that shown in Fig. exhibit the diamond shape shown in 12A.

[0064] After the formation of the source / drain regions 1220, an interplane dielectric layer 1230 can be formed to fill voids in the semiconductor structure 100. The interplane dielectric layer 1230 can be formed, for example, by CVD of a dielectric material. Non-restrictive examples of dielectric materials for forming the interplane dielectric layer 1230 include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, low-k dielectrics based on silicon, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0065] As is known to experts, after the deposition of the interplane dielectric layer 1230, a planarization process (e.g., a CMP) can be performed on the semiconductor structure 100. This process can expose an upper surface of the dummy gate 410 in preparation for a replacement metal gate process, as described in detail below.

[0066] With reference to Fig. Figures 13A to 13C show cross-sectional views of the semiconductor structure 100 after performing a replacement metal gate process, middle-of-line (MOL) contact structuring and metallization, and forming a back-end-of-line (BEOL) interconnect plane 1320 and a support wafer 1322 according to an embodiment of the present disclosure. In this embodiment, Fig. 13A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 13B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. 13C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0067] According to one embodiment, the dummy gate 410 is removed from the semiconductor structure 100. As is known in the prior art, in a gate-last manufacturing process, the removed dummy gate 410 is subsequently replaced by a high-k metal gate structure, i.e., a replacement gate 1310. According to one embodiment, the second sacrificial semiconductor layers 110 ( Fig. 12A to 12B) are removed from the semiconductor structure 100 using known etching processes, including, for example, RIE, wet etching, or dry gas (HCl). The removal of the sacrificial semiconductor layers 110 ( Fig. 12A to 12B) creates (not shown) cavities between the inner spacer elements 720, which are subsequently filled with appropriate gate dielectric and exit work metals to form the high-k metal gate structure or the substitute gate 1310, as shown in Fig. Shown in sections 13B to 13C.

[0068] The replacement gate 1310 contains gate dielectrics such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium aluminum oxide (HfAlOx), hafnium lanthanum oxide (HfLaOx), etc., and one or more exit work metals, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and conductive metals, including, for example, aluminum (Al), tungsten (W), or cobalt (Co). As in Fig. As can be seen in Figure 13B, the replacement gate 1310 surrounds the (stacked) semiconductor channel layers 112. In one or more embodiments, a (not shown) gate cover can be formed over the replacement gate 1310.

[0069] After forming the replacement gate 1310, chemical-mechanical polishing (CMP) can be performed to remove excess material and polish the upper surfaces of the semiconductor structure 100.

[0070] In one or more embodiments, a gate-cutting process can be performed on the semiconductor structure 100 to isolate gate structures from different CMOS cells. During the process, a gate-cutting region 1315 can be formed either upstream of the replacement metal gate (RMG) or downstream of the RMG and subsequently filled with dielectrics such as SiO2, SiN, SiBCN, SiOCN, SiOC, SiC, and the like, as shown in Fig. 13B shown.

[0071] Furthermore, with reference to Fig. In embodiments 13A to 13C, a plurality of conductive structures, including metal contacts 1312, are formed in the semiconductor structure 100 to electrically connect FEOL units with subsequently formed metal planes. The process for forming the metal contacts 1312 is standard and generally known in the art. Typically, the process involves forming (not shown) trenches within the interplane dielectric layer 1230 and subsequently filling the trenches with a conductive material or a combination of conductive materials to form the metal contacts 1312. In one or more embodiments, the conductive material filling the metal contacts 1312 can be a silicide liner (e.g., titanium (Ti), nickel (Ni), a nickel-platinum (NiPt) alloy, etc.), a metal adhesion liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g.,Contains aluminium (Al), tungsten (W), copper (Co), ruthenium (Ru) or any combination thereof.

[0072] The conductive material can be deposited by any suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, for example, CMP, is performed to remove any conductive material from the top surfaces of the semiconductor structure 100. In particular, in the example shown, the metal contacts 1312 can be source / drain contacts (CA) extending to a top surface of the source / drain regions 1220, as shown in Fig. 13A and Fig. 13C is shown, and gate contacts (CB) to the replacement gate 1310 are included, as shown in Fig. 13B shown.

[0073] According to one embodiment, the BEOL interconnect layer 1320 is formed above and electrically connected to the FEOL unit layer 30 of the semiconductor structure 100. Although not shown in the figures, the BEOL interconnect layer 1320 typically includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-package connections, as may be known to those skilled in the art. As mentioned above, various steps in the fabrication of semiconductor units and ICs based on semiconductors are generally known, and therefore, for the sake of brevity, numerous conventional steps are only briefly mentioned here or omitted entirely without providing the generally known details of the processes.

[0074] According to one embodiment, after the formation of the BEOL interconnection plane 1320, the semiconductor structure 100 (i.e., the semiconductor wafer) is bonded to the support wafer (or an auxiliary substrate) 1322. The support wafer 1322 can act as a reinforcing substrate to provide mechanical strength during processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the support wafer 1322 can be achieved by a conventional wafer bonding process, such as dielectric-dielectric bonding or copper-copper bonding.

[0075] Accordingly, the carrier wafer 1322 can contain silicon oxide layers or SiCN layers or any other layers applicable to direct bonding technology used in prior art assembly techniques. Bonding of the unit wafer to the carrier wafer 1322 is carried out using such known direct bonding techniques, thereby achieving the Fig. The arrangement shown in 13A to 13C is obtained. Although this is not shown in the figures, the wafer is turned over after bonding the unit wafer to the carrier wafer 1322.

[0076] With reference to Fig. Figures 14A to 14C show cross-sectional views of the semiconductor structure 100 after removal of the substrate 102 ( Fig. 13A to 13C) according to an embodiment of the present disclosure. In this embodiment, Fig. 14A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 14B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. 14C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0077] In the illustrated embodiment, the substrate 102 ( Fig. 13A to 13C), after the wafer has been flipped (not shown), are removed by means of a conventional grinding, CMP, and selective etching process, including wet or dry etching techniques. In one or more embodiments, the grinding process is carried out until the substrate 102 has been substantially removed from the semiconductor structure 100, leaving only a few micrometers of Si. Thereafter, an optional CMP process can be used to further reduce the thickness variation, and finally, a highly selective Si etching process is used to remove the remaining substrate 102 from the semiconductor structure 100. In the illustrated embodiment, the first sacrificial layer 104 acts as an etch stop during the highly selective Si removal process, thus preventing excessive Si etching that could damage the replacement gate 1310 and the source / drain regions 1220.

[0078] With reference to Fig. Figures 15A to 15C show cross-sectional views of the semiconductor structure 100 after removal of the first sacrificial layer 104 and etching of sections of the first semiconductor layer 106 to expose the placeholder layer 1020, according to an embodiment of the present disclosure. In this embodiment, Fig. 15A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as in Fig. 1 shown; is Fig. Figure 15B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. Figure 15C shows a cross-sectional view of the semiconductor structure 100 along a line X-X', as shown in Fig. 1 shown.

[0079] In the illustrated embodiment, any suitable etching technique can be used to create the first sacrificial layer 104 ( Fig. 14A to 14C). In embodiments in which the first sacrificial layer 104 ( Fig. 14A to 14C) is made of SiGe, hot SCI etching or HCl dry etching can be used to remove the first sacrificial layer 104. In embodiments where the first sacrificial layer 104 ( Fig. 14A to 14C) is made from SiO2, a DHF wet etching can be used to remove the first sacrificial layer 104. As in Fig. 15A and Fig. As shown in 15C, some sections of the placeholder layer 1020 can also be etched during the removal of the sacrificial layer 104.

[0080] With reference to Fig. Figures 16A to 16C show cross-sectional views of the semiconductor structure 100 after removal of remaining Si-containing areas, i.e., the area in Fig. The first semiconductor layer 106 shown in 15A to 15C is illustrated according to an embodiment of the present disclosure. In this embodiment, Fig. 15A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as in Fig. 1 shown; is Fig. Figure 15B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. Figure 15C shows a cross-sectional view of the semiconductor structure 100 along a line X-X', as shown in Fig. 1 shown.

[0081] In this embodiment, a process similar to that described in Fig. 14A to 14C to remove the substrate 102 as described above are carried out to reveal the first semiconductor layer 106 ( Fig. 15A to 15C) from the semiconductor structure 100. Selective removal of the first semiconductor layer 106 ( Fig. 15A to 15C) exposes the placeholder layer 1020. As in Fig. 16A and Fig. 16C can be observed, a first or lower surface of the placeholder layer 1020 is in contact with a first or lower surface of the source / drain area 1220.

[0082] With reference to Fig. Figures 17A to 17C show cross-sectional views of the semiconductor structure 100 after the formation of a first backside interlayer dielectric (Figure) 1702 according to an embodiment of the present disclosure. In this embodiment, Fig. 17A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 17B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. 17C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0083] The first PICTURE 1702 is formed using standard procedures and materials such as those used to form the interplane dielectric layer 1230 described above with reference to Fig. have been described in sections 12A to 12C. As in Fig. As shown in Figures 17B to 17C, the first layer 1702 is arranged above the lower dielectric insulating layer 620. In an exemplary embodiment, the thickness of the first layer 1702 can vary between approximately 40 nm and approximately 300 nm, and in intermediate ranges. In one or more embodiments, a planarization process (e.g., a CMP) can be performed after the formation of the first layer 1702 on the semiconductor structure 100. After the planarization process, an exposed second or top surface of the placeholder layer 1020, opposite the first surface of the placeholder layer, is substantially coplanar with the first layer 1702 and the STI regions 310.

[0084] With reference to Fig. Figures 18A to 18C show cross-sectional views of the semiconductor structure 100 after selective removal of the placeholder layer 1020 ( Fig. 17A to 17C) according to an embodiment of the present disclosure. In this embodiment, Fig. 18A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 18B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. 18C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0085] Removing the placeholder layer 1020 ( Fig. 17A to 17C) creates fourth openings 1820 in the semiconductor structure 100. The fourth openings 1820 (i.e., back-side contact vias) expose one or more of the source / drain regions 1220, as shown in Fig. 18A and Fig. 18C is shown. Exemplary techniques for removing the placeholder layer 1020 ( Fig. 17A to 17C) of the semiconductor structure 100, can include HCl dry etching, which causes minimal or no damage to the underlying layers, without being limited to.

[0086] As in Fig. 18A and Fig. 18C can be observed, at least one of the fourth openings 1820 exposes an upper surface of a source / drain region 1220 adjacent to another source / drain region 1220 which is in electrical contact with a metal contact 1312.

[0087] With reference to Fig. Figures 19A to 19C show cross-sectional views of the semiconductor structure 100 after deposition of a back-side metal 1920 according to an embodiment of the present disclosure. In this embodiment, Fig. 19A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. Figure 19B shows a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as shown in Fig. 1 shown; and is Fig. 19C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0088] The rear metal 1920 fills the fourth openings 1820 ( Fig. 18A to 18C) essentially. A layer of the backside metal 1920 is further deposited over the filled fourth openings 1820, over the first image 1702 and over the STI areas 310, as shown in the figures. It should be noted that the backside metal 1920, which covers the fourth openings 1820 ( Fig. 18A to 18C) essentially fills, and provides rear metal contacts 1930 to the source / drain regions 1220. According to one embodiment, the rear contacts 1930 can electrically connect the semiconductor structure 100 to a subsequently formed rear busbar (BPR), as described in detail below.

[0089] The backside metal 1920 can be formed using similar conductive materials and comparable deposition processes to those used to form the metal contacts 1102. In some embodiments, the conductive metals used to form the backside metal 1920 can be selected according to the backside busbar structures subsequently formed. In such cases, the backside metal 1920 can be formed by depositing, for example, a silicide liner such as Ti, Ni, or NiPt, an adhesion metal liner such as TiN, and a layer of a low-resistance metal such as Ru, Co, W, or Cu.

[0090] The thickness of the backside material layer extending over the first image 1702 and the STI areas 310 can vary from about 30 nm to about 200 nm and in ranges in between.

[0091] In one or more embodiments, rear contacts 1930 can be provided between adjacent source / drain regions 1220, which are located within the NFET (i.e., in the N2N space) regions 12 ( Fig. 1) or the PFET (i.e., in P2P space) regions 16 ( Fig. 1) of the semiconductor structure 100. In the illustrated embodiment, the rear metal contact 1930 is formed in direct contact with the first or lower surface of at least one source / drain region 1220.

[0092] With reference to Fig. Sections 20A to 20C show cross-sectional views of the semiconductor structure 100 after structuring of backside busbars according to an embodiment of the present disclosure. In this embodiment, Fig. 20A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as in Fig. 1 shown; is Fig. 20B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 20C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0093] In the illustrated embodiment, rear busbars (BPRs) 2010, 2012 are formed in the semiconductor structure 100 by structuring the rear metal 1920 ( Fig. 19A to 19C) using subtractive metal etching. In particular, a hybrid Damascus and subtractive metal texturing can be used to form the back-side metal layer 1920 ( Fig. 19A to 19C) extending across the first FIGURE 1702 and the STI areas 310 to form the BPRs 2010, 2012, as shown in the figures. This allows the present embodiments to simultaneously form rear metal contacts (e.g., the rear contact 1930) and rear busbars (e.g., the BPRs 2010, 2012).

[0094] More precisely, in one embodiment, the semiconductor structure 100 contains an NFET unit. In such an embodiment, the BPR 2012 includes a VSS rail embedded in the NFET region of the semiconductor structure 100 to establish an electrical connection with an n-source / drain region 1220 via a rear contact 1930 (located between adjacent n-source / drain regions 1220). In other embodiments, the semiconductor structure 100 contains a PFET unit, in which the BPR 2010 may include a VDD rail embedded in the PFET region of the semiconductor structure 100, which is electrically connected to a (p-)source / drain region 1220 via a rear contact 1930 (located between adjacent p-source / drain regions 1220).

[0095] It should be noted that the source / drain regions 1220 wired to rear busbars (i.e., BPRs 2010, 2012) are not connected to the BEOL intermediate layer 1320. More precisely, as shown in the figures, at least one rear busbar (i.e., BPRs 2010, 2012) makes an electrical connection to a source / drain region 1220 of a transistor through the rear contact 1930, with the lower dielectric insulating layer 620, the first figure 1702, and / or the STI regions 310 being in contact with the remaining source / drain regions 1220 to electrically isolate the at least one rear busbar from the source / drain regions 1220 that are not electrically connected to the rear contact 1930.

[0096] After structuring the BPRs 2010 and 2012, voids within the semiconductor structure can be filled by depositing a dielectric material essentially similar to the first figure 1702. Therefore, for simplicity, another layer of the first figure 1702 is deposited within the semiconductor structure 100 to fill remaining voids and electrically insulate the BPRs 2010 and 2012, as shown in Fig. 21A to 21C are shown below. After the deposition of the next layer of the first FIGURE 1702, a planarization process can be carried out in the semiconductor structure 100.

[0097] With reference to Fig. Figures 21A to 21C show cross-sectional views of the semiconductor structure 100 after forming a backside power delivery network (BSPDN) 2130 according to an embodiment of the present disclosure. In this embodiment, Fig. 21A a cross-sectional view of the semiconductor structure 100 along Y1-Y1', as shown in Fig. 1 shown; is Fig. 21B a cross-sectional view of the semiconductor structure 100 along a line Y2-Y2', as in Fig. 1 shown; and is Fig. 21C a cross-sectional view of the semiconductor structure 100 along a line X-X', as in Fig. 1 shown.

[0098] In one or more embodiments, a structure of the BSPDN 2130 can be fabricated according to known techniques. Depending on the precise function of the transistor arrangement, a number of the source / drain regions 1220 can be connected to the rear power supply and ground via the rear contact 1930. As mentioned above, the rear contact 1930 is a metal surface area located between p-source / drain regions (N2N space) and between n-source / drain regions (N2N space), i.e., between source / drain regions of similar polarity. According to one embodiment, the rear contact 1930 is in contact with a lower surface of the BPR 2010 or 2012 (depending on the polarity of the unit) and is embedded in an intermediate STI region 310 (located between regions of the same polarity).

[0099] It should be noted that the BEOL interconnection level 1320 in the semiconductor structure 100, which is manufactured according to the disclosed technology, is separated from the BSPDN 2130, thereby increasing the conduction resources in the semiconductor structure 100 for signal wiring at the BEOL level.

[0100] According to the embodiment of the invention, by carrying out the sigma etching process, backside contact vias and consequently backside metal contacts 1930 exhibit a first (positive) taper profile which includes a first taper angle, according to which a first or upper critical dimension (CD1) of the backside metal contacts 1930 is smaller than a second or lower critical dimension (CD2) of the backside metal contacts 1930, as shown in Fig.21C is shown. Similarly, the BPRs 2010, 2012 are formed with a second (negative) taper profile that differs from the first taper profile of the rear metal contacts 1930. The second taper profile incorporates a second taper angle such that a third or upper critical dimension (CD3) of the BPRs 2010, 2012 is larger than a fourth or lower critical dimension (CD4) of each of the BPRs 2010, 2012.

[0101] Therefore, the embodiments described above provide a semiconductor unit comprising a field-effect transistor (FET) and a rear contact 1930. The rear contact 1930 is electrically connected to a source / drain region 1220 of the FET and to a rear busbar 2010, 2012. The rear contact 1930 has a first width adjacent to the source / drain region 1220 and a second width adjacent to the rear busbar 2010, 2012. The second width of the rear contact 1930 is larger than the first width of the rear contact 1930. According to one embodiment, the rear busbar 2010, 2012 has a third width adjacent to the rear contact 1930 and a fourth width on the opposite side of the rear contact 1930.The third width of the rear power rail 2010, 2012 is larger than the fourth width of the rear power rail 2010, 2012.

[0102] The process described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer as a raw wafer (that is, as a single wafer containing multiple unpackaged chips), as a bare chip, or in a package. In the latter case, the chip is placed in a single-chip package (such as on a plastic substrate with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as on a ceramic substrate with either surface interconnects, buried interconnects, or both). In each case, the chip is subsequently integrated with other chips, discrete circuit elements, and / or other signal processing units as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product containing integrated circuit chips, ranging from toys and other simple applications to sophisticated computer products that include a display, a keyboard or other input device, and a central processing unit.

[0103] The terminology used herein serves only to describe certain embodiments and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are to include the plural forms unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "has" and / or "having" when used in this description denote the presence of specified features, integers, steps, processes, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.“Optional” or “choice” means that the event or circumstance described below may occur and that the description includes cases in which the event occurs and cases in which it does not occur.

[0104] Spatially relative terms such as "inner," "outer," "under," "below," "lower," "above," "upper," "above," "below," and the like may be used herein for the sake of simplicity to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the unit in use or operation in addition to the orientation shown in the figures. For example, if the unit in the figures is reversed, elements described as "under" or "below" other elements or features would be oriented "above" them. Consequently, the exemplary term "below" can encompass an orientation both above and below.The unit can be oriented in other ways (rotated by 90 degrees or with other orientations) and the spatially relative descriptions used herein can be interpreted accordingly.

[0105] Approximate language, as used throughout this description and the claims, may be applied to modify any quantitative representation that could permissibly vary without altering the underlying function to which it refers. Accordingly, a value modified by a term or terms such as "approximately," "about," and "essentially" is not restricted to the precisely stated value. In at least some cases, the approximate language may correspond to the accuracy of an instrument used to measure the value. Here, and throughout this description and the claims, range boundaries may be combined and / or interchanged; such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise.“Approximately”, as applied to a particular value of a range, refers to both values ​​and, unless dependent on the accuracy of the instrument measuring the value, can indicate + / -10% of the stated value(s).

[0106] The descriptions of the various embodiments of the present invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Numerous modifications and variants are apparent to those skilled in the art without deviating from the scope of the described embodiments. The terminology used herein has been chosen to best explain the basic concepts of the embodiments, their practical application, or the technical improvements compared to technologies available on the market, or to enable other skilled persons to understand the embodiments disclosed herein.

Claims

[1] Semiconductor structure (100) which has: a plurality of source / drain regions (1220) within a field-effect transistor; a rear metal contact (1930) electrically connected to at least one source / drain region of the plurality of source / drain regions, wherein the rear metal contact includes a first tapered profile whose upper (CD1) and lower (CD2) dimensions are the upper and lower dimensions of the rear metal contact, respectively, and the upper dimension (CD1) is smaller than the lower dimension (CD2); and a rear busbar (1920) which is electrically connected to the at least one source / drain area by the rear metal contact, wherein the rear busbar includes a second tapered profile, the upper (CD3) and lower (CD4) dimensions of which are the upper and lower dimensions of the rear busbar respectively, and the upper dimension (CD3) of the rear busbar is larger than its lower dimension (CD4). [2] Semiconductor structure according to claim 1, further comprising: a front-end-of-line plane containing the field-effect transistor, wherein the front-end-of-line plane is electrically connected to a back-end-of-line interconnect plane (1320) located on a first side of the front-end-of-line plane; a plurality of areas (310) of a shallow trench insulation located between adjacent field-effect transistors; a rear-side interlayer dielectric (1702) surrounding the rear-side busbar and located on a second side of the front-end-of-line plane opposite the first side of the front-end-of-line plane; and a metal contact (1312) within an interplane dielectric layer (1230), wherein the metal contact is in electrical contact with an upper section of at least one further source / drain region. [3] Semiconductor structure according to claim 1, wherein the rear metal contact and the rear busbar consist of a conductive material containing Ru, Cu, Co, W and / or Al. [4] Semiconductor structure according to claim 1, further comprising: a power supply network via and in electrical contact with the rear busbar. [5] Semiconductor structure according to claim 4, further comprising: a carrier wafer (1322) in contact with a surface of the back-end-of-line interconnect plane that faces the majority of source / drain areas and the metal contact. [6] Semiconductor structure according to claim 1, wherein the field-effect transistor includes a p-field-effect transistor and / or an n-field-effect transistor and wherein the field-effect transistor includes a nanosheet field-effect transistor. [7] Method for forming a semiconductor structure which has: Forming a plurality of source / drain regions (1220) within a field-effect transistor; Forming a rear metal contact (1930) electrically connected to at least one source / drain region of the plurality of source / drain regions, wherein the rear metal contact includes a first tapered profile whose upper (CD1) and lower (CD2) dimensions are the upper and lower dimensions of the rear metal contact, respectively, and the upper dimension (CD1) is smaller than the lower dimension (CD2); and Forming a rear busbar (1920) which is electrically connected to the at least one source / drain area by the rear metal contact, wherein the rear busbar includes a second tapered profile, the upper (CD3) and lower (CD4) dimensions of which are the upper and lower dimensions of the rear busbar respectively, and the upper dimension (CD3) of the rear busbar being larger than its lower dimension (CD4). [8] The method of claim 7, further comprising: Forming a front-end-of-line plane containing the field-effect transistor, wherein the front-end-of-line plane is electrically connected to a back-end-of-line interconnect plane located on a first side of the front-end-of-line plane; Forming a plurality of areas (310) of shallow trench isolation between adjacent field-effect transistors; Forming a rear-side interlayer dielectric (1702) surrounding the rear-side busbar on a second side of the front-end-of-line plane opposite the first side of the front-end-of-line plane; and Forming a metal contact (1312) within an interplane dielectric layer (1230), wherein the metal contact is in electrical contact with an upper section of at least one further source / drain region. [9] Method according to claim 7, wherein the rear metal contact and the rear busbar consist of a conductive material containing Ru, Cu, Co, W and / or Al. [10] The method of claim 7, further comprising: Forming a power supply network via and in electrical contact with the rear busbar. [11] The method of claim 8, which further comprises: Forming a carrier wafer (1322) in contact with a surface of the back-end-of-line interconnect plane that faces the majority of source / drain areas and the metal contact. [12] Method according to claim 7, wherein the field-effect transistor includes a p-field-effect transistor and / or an n-field-effect transistor and wherein the field-effect transistor includes a nanosheet field-effect transistor. [13] Computer program comprising program code designed to perform the method steps of any one of claims 7 to 12 when the program is executed on a computer.

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