INTEGRATION OF WORD LINE CHARGES

Abstract

Methods, systems, and devices for integrating wordline charges are described. In some examples, a memory device may include a plurality of memory cells coupled to a wordline and respective bitlines. During a read operation, the wordline may be activated (e.g., brought to a voltage) and a subset of the respective bitlines may be activated (e.g., brought to a voltage) to begin integrating the charges of each of the memory cells. Before each bitline is activated, the wordline may be deactivated and the remaining bitlines may be activated (e.g., brought to a voltage) to begin integrating charges of the remaining memory cells coupled to the wordline. After each of the bitlines is selected, the respective sensing components may be activated to sense the charges associated with the memory cells.

Description

CROSS-REFERENCE

[0001] This patent application claims priority to U.S. Patent Application No. 18 / 528,451 by BEDESCHI et al., entitled "WORD LINE CHARGE INTEGRATION," filed December 4, 2023, and U.S. Provisional Patent Application No. 63 / 476,794 by BEDESCHI et al., entitled "WORD LINE CHARGE INTEGRATION," filed December 22, 2022, each of which is assigned to the assignee hereof and each of which is expressly incorporated herein by reference. TECHNICAL FIELD

[0002] The following statements concern one or more systems for memories, including the integration of word line charges. GENERAL STATE OF THE ART

[0003] Memory devices are commonly used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to different states. For example, binary memory cells can be programmed to one of two supported states, often denoted by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any one of which can be stored. To access stored information, a component can read a stored state of the memory device (e.g., capture, detect, retrieve, identify, determine, evaluate). To store information, a component can write the state to the memory device (e.g.,program, set, assign).

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selective memory, chalcogenide memory technologies, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can retain stored logical states for extended periods of time, even in the absence of an external power source.Memory cells configured in a volatile configuration can lose stored states when disconnected from an external power source. FeRAM can achieve densities similar to volatile memory, but can exhibit non-volatile properties due to the use of a ferroelectric capacitor as the storage device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example of a system that supports integration of wordline charges according to examples disclosed herein. Fig. 2 illustrates an example timing diagram supporting integration of wordline charges according to examples disclosed herein. Fig. 3A illustrates an example circuit diagram supporting integration of wordline charges according to examples disclosed herein. Fig. 3B illustrates an example timing diagram supporting integration of wordline charges according to examples disclosed herein. Fig. 4 illustrates a block diagram of a memory device supporting integration of wordline charges according to examples disclosed herein. Fig. 5 illustrates a flowchart showing one or more methods that support integration of wordline charges according to examples disclosed herein. DETAILED DESCRIPTION

[0005] A memory device may include memory cells coupled to access lines (e.g., word lines, bit lines, plate lines). A memory device may be, for example, a ferroelectric random access memory (FeRAM) or a dynamic random access memory (DRAM). The memory device may include a plurality of non-volatile memory cells (e.g., FeRAM) or volatile memory cells (e.g., DRAM) coupled to word lines and a respective bit line. In addition, some DRAM memory devices may utilize a feedback amplifier to bias the bit lines and integrate charges from respective memory cells onto a capacitor (e.g., an amp-cap). However, the duration of charge integration of memory cells may vary during access operations (e.g., read operations). If a word line is activated during a read operation (e.g.,Specifically, when a word line is driven by a voltage applied to the memory cell, memory cells at a first end of the word line (e.g., near the driver of the signal on the word line) may experience a longer charge integration duration than memory cells at a second end of the word line (e.g., away from the driver of the signal on the word line). The different charge integration durations may result in different electrical responses of the memory cells, which may impact overall memory performance and reliability. Accordingly, a memory device configured to mitigate the different charge integration durations of memory cells coupled to a word line is desirable.

[0006] This document describes a memory device configured to mitigate the varying duration of charge integration of memory cells coupled to a word line. In some examples, a memory device may include a plurality of FeRAM memory cells or DRAM memory cells coupled to a word line and respective bit lines. During a read operation, the word line may be activated (e.g., brought to a voltage) and a subset of the respective bit lines may be activated (e.g., brought to a voltage) to begin integrating the charges of each of the memory cells. Before each bit line is activated, the word line may be deactivated and the remaining bit lines may be activated (e.g., brought to a voltage) to begin integrating charges of the remaining memory cells coupled to the word line.After each of the bit lines is selected, the respective sense components can be activated to sense the charges associated with the memory cells. Accordingly, deactivating the word line before triggering the sense components can mitigate varying durations of charge integration of the memory cells, which can improve the overall performance and reliability of the memory device.

[0007] Features of the disclosure are first described in the context of systems and this with reference to Fig. 1. Features of the disclosure are described in conjunction with timing diagrams and circuit diagrams with reference to the Fig. 2, Fig. 3A and Fig. 3B. These and other features of the disclosure are further illustrated and described with reference to a device diagram and timing diagrams relating to wordline charge integration, as described with reference to Fig. 4 and Fig. 5 described.

[0008] Fig. 1 illustrates an example of a system 100 that supports wordline charge integration according to examples disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0009] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or another system. For example, system 100 may illustrate aspects of a computer, a laptop, a tablet computer, a smartphone, a mobile phone, a wearable device, an internet-connected device, a vehicle controller, or the like. Storage device 110 may be a component of system 100 operable to store data for one or more other components of system 100.

[0010] Portions of system 100 may be examples of host device 105. Host device 105 may be an example of a processor (e.g., a circuit, a processing circuit, a processing component) within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or other stationary or portable electronic device, among other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or any combination thereof that implements the functions of external memory controller 120.In some examples, the external storage controller 120 may be referred to as a host (e.g., a host device 105).

[0011] A storage device 110 may be an independent device or a component operable to provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, a storage device 110 may be configured to work with one or more different types of host devices. The signaling between the host device 105 and the storage device 110 may be operable to support one or more of the following: modulation schemes for modulating the signals, various contact configurations for communicating the signals, different form factors for the physical packaging of the host device 105 and the storage device 110, clock signaling and synchronization between the host device 105 and the storage device 110, timing conventions, or other features.

[0012] The storage device 110 may be operable to store data for the components of the host device 105. In some examples, the storage device 110 (e.g., operated as a secondary type device to the host device 105, operated as a dependent type of the host device 105) may respond to and execute commands provided by the host device 105 via the external storage controller 120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0013] Host device 105 may include one or more external memory controllers 120, a processor 125, a basic input / output system (BIOS) component 130, or other components, such as one or more peripheral components or one or more input / output controllers. The components of host device 105 may be coupled together via a bus 135.

[0014] Processor 125 may be operable to provide functionality (e.g., control functionality) to system 100 or host device 105. Processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), or SoC, among other examples.In some examples, the external memory controller 120 may be implemented by or be a part of the processor 125.

[0015] BIOS component 130 may be a software component including a BIOS operating as firmware that can initialize and execute various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and the various components of system 100 or host device 105. BIOS component 130 may include instructions (e.g., a program, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0016] The storage device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a capacity (e.g., a desired capacity, a fixed capacity) for data storage. Each memory die 160 (e.g., a memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). A memory array 170 may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, where each memory cell is operable to store one or more bits of data.A memory device 110 that includes two or more memory dies 160 may be referred to as a multi-die memory or multi-chip package, or as a multi-chip memory or multi-chip package.

[0017] As described herein, a memory array 170 may include one or more FeRAM memory cells or DRAM memory cells. Each type of memory cell may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor including a dielectric material to store a charge representative of the programmable state. In other memory architectures, other memory devices and components are possible. For example, nonlinear dielectric materials may be used. The memory cells may include a logic storage component, such as a capacitor, and a switching component (e.g., a cell select component). The capacitor may be an example of a dielectric capacitor or a ferroelectric capacitor.A node of the capacitor may be coupled to a voltage source, which may be the reference voltage of the cell plate, such as Vpl, or ground, such as Vss.

[0018] The device memory controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controllers 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0019] In some examples, storage device 110 may communicate information (e.g., data, commands, or both) with host device 105. For example, among other types of information communication, storage device 110 may receive a write command indicating that storage device 110 should store data received from host device 105 or receive a read command indicating that storage device 110 should provide data stored in a memory die 160 to host device 105.

[0020] A local memory controller 165 (e.g., local to a memory die 160) may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, a local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., receive or transmit data or commands, or both). In some examples, a memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. As such, a local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof.Examples of components that may be included in the device memory controller 155 or the local memory controllers 165, or both, may include receivers for receiving signals (e.g., from the external memory controller 120), transmitters for transmitting signals (e.g., to the external memory controller 120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other components operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0021] The external storage controller 120 may be operable to facilitate communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105, such as the processor 125 and the storage device 110). The external storage controller 120 may process (e.g., convert, translate) communications exchanged between the components of the host device 105 and the storage device 110. In some examples, the external storage controller 120 or other components of the system 100, the host device 105, or their functions described herein, may be implemented by the processor 125. For example, the external storage controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by the processor 125 or another component of the system 100 or the host device 105.While the external memory controller 120 is illustrated as being external to the memory device 110, in some examples, the external memory controller 120 or its functions described herein may be implemented by one or more components of a memory device 110 (e.g., a device memory controller 155, a local memory controller 165), or vice versa.

[0022] The components of the host device 105 can exchange information with the storage device 110 via one or more channels 115. The channels 115 can be operable to support communication between the external storage controller 120 and the storage device 110. Each channel 115 can be an example of a transmission medium that transmits information between the host device 105 and the storage device 110. Each channel 115 can include one or more signaling paths (e.g., transmission medium, a conductor) between ports associated with the components of the system 100. A signaling path can be an example of a conductive path operable to transmit a signal. For example, a channel 115 can be associated with a first port (e.g.,A first terminal (including one or more pins, including one or more pads) on the host device 105 and a second terminal on the memory device 110 may be associated. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to function as part of a channel.

[0023] Channels 115 (and the associated signaling paths and terminals) may be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling over channels 115 may be communicated using single data rate (SDR) signaling or double data rate (DDR) signaling. With SDR signaling, a modulation symbol (e.g., the signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g. signal levels) of a signal can be registered for each clock cycle (e.g.both on a rising and a falling edge of a clock signal).

[0024] In some examples, memory device 110 may include a plurality of FeRAM memory cells or DRAM memory cells coupled to a word line and respective bit lines. During a read operation, the word line may be activated (e.g., brought to a voltage) and a subset of the respective bit lines may be activated (e.g., brought to a voltage) to begin integrating the charges of each of the memory cells. Before each bit line is activated, the word line may be deactivated and the remaining bit lines may be activated (e.g., brought to a voltage) to begin integrating charges of the remaining memory cells coupled to the word line. After each of the bit lines is selected, the respective sensing components may be activated to sense the charges associated with the memory cells.Accordingly, deactivating the wordline before triggering the sense components (e.g., completing the read operation) may mitigate varying durations of charge integration of the memory cells, which may improve the overall performance and reliability of the memory device 110.

[0025] Fig. 2 illustrates an example timing diagram 200 that supports wordline charge integration according to examples disclosed herein. Timing diagram 200 may represent the voltage of a first node and a second node of a wordline at different times. For example, voltage 205 may represent a voltage of a first node at or near a first memory cell coupled to a wordline, and voltage 210 may represent a voltage of a second node at or near a second memory cell coupled to a wordline. As described herein, the first memory cell and the second memory cell may be located at different ends of the wordline (e.g., either closer to the driver of a signal on the wordline or farther from the driver).Voltage 205 shows the timing seen by a memory cell near the wordline signal driver. Voltage 210 shows the timing seen by the memory cell farther from the wordline signal driver. As illustrated, there may be a propagation delay for the wordline signal experienced by memory cells farther from the driver compared to memory cells closer to the driver. Voltage 205 and voltage 210 may illustrate deactivating the wordline before the end of the read operation (e.g., turning on the sense components during duration 245), which may mitigate varying charge integration durations of the memory cells and improve the overall performance and reliability of the associated memory device.

[0026] In some examples, voltage 205 may represent a voltage of a first node of a wordline located at or near a first memory cell. The first memory cell may represent a memory cell located relatively close to a voltage source coupled to the wordline. For example, the first memory cell may be a first memory cell coupled to the wordline and may be closer to the voltage source than any other memory cell coupled to the wordline. Accordingly, voltage 205 (e.g., the voltage of the first node) may rise relatively faster than the voltage of another node (e.g., the second node) of the wordline when the wordline is selected (e.g., driven to a voltage).

[0027] Additionally or alternatively, voltage 210 may represent a voltage of a second node of the wordline located at or near a second memory cell. The second memory cell may represent a memory cell located relatively far from a voltage source coupled to the wordline. For example, the second memory cell may be a last memory cell coupled to the wordline and may be farther from the voltage source than any other memory cell coupled to the wordline. Accordingly, voltage 210 (e.g., the voltage of the second node) may rise relatively more slowly than the voltage of another node (e.g., the first node) of the wordline when the wordline is selected (e.g., driven to a voltage).

[0028] Furthermore, although voltage 205 and voltage 210 are shown as increasing and decreasing relatively linearly, voltage 205 and voltage 210 may increase or decrease in any manner. For example, the voltages may not increase or decrease exponentially or generally in a sigmoidal fashion. Furthermore, each of the voltages may remain constant (or relatively constant) for a duration after the wordline is activated (e.g., driven to a voltage).

[0029] In some examples, a memory device associated with the word line (e.g., a memory device 110 as described with reference to Fig. 1) a read command from a host device (e.g., a host device 105 as described with reference to Fig. 1). The read command may be associated with reading the memory cells coupled to the word line. Upon receiving the read command, a memory controller (e.g., a device memory controller 155 as described with reference to Fig. 1) or another component of the memory device may initiate a read operation by activating the wordline. The read operation may occur during duration 215, and the wordline may be activated during duration 220. As described herein, the wordline may be activated by applying a voltage to the wordline. In some examples, the voltage may be applied by activating a switch (or other component) coupled to the voltage source and the wordline. After activating the wordline, voltage 205 may begin to rise.

[0030] After the voltage 205 rises, a charge associated with the first memory cell may be integrated. As used herein, "integration" or "charge integration" may refer to the process of providing a charge from a memory cell to a respective sensing component. For example, the first memory cell may be integrated during duration 225. Accordingly, during duration 225 (e.g., a first duration), a bitline coupled to the first memory cell may be selected, and a charge associated with the first memory cell may be integrated into a respective sensing component. In some cases, the charge associated with various memory cells may be integrated when the voltage of the wordline reaches a threshold voltage level. Due to the length of the wordline, different nodes of the wordline may reach the threshold voltage level at different times.

[0031] In some examples, a delay 230 may exist between the rise of voltage 205 and the rise of voltage 210. As described herein, delay 230 may occur due to the length of the word line and propagation delay of the signal traveling along the word line. After the rise of voltage 210, a charge associated with the second memory cell may be integrated. For example, the second memory cell may be integrated during duration 235. Accordingly, during duration 235, a bit line coupled to the second memory cell may be selected, and a charge associated with the second memory cell may be integrated into a respective sense component.

[0032] During duration 235 (e.g., the first duration), the wordline may be deactivated. As described herein, the wordline may be deactivated by removing the voltage from the wordline or driving the wordline to a different voltage (e.g., to ground). In some examples, the voltage may be removed by deactivating a switch (or other component) coupled to the voltage source and the wordline. After deactivating the wordline, voltage 205 may begin to decay.

[0033] By deactivating the wordline before completion of the read operation (e.g., before the end of 215), the integration time of the first memory cell and the second memory cell may be the same or similar. That is, duration 225 may be the same or a similar duration to duration 235. Furthermore, other memory cells coupled to the wordline (e.g., memory cells located between the first memory cell and the second memory cell) may experience the same or similar integration times. Additionally or alternatively, a delay 240 may exist between the drop in voltage 205 and the drop in voltage 210. Delay 230 and delay 240 may also be the same or similar due to deactivating the wordline before completion of the read operation.

[0034] After completion of the read operation (e.g., after duration 215), the sense components associated with the word line may be activated to sense the respective charges. For example, the first memory cell may be coupled to a first sense component, and the second memory cell may be coupled to a second sense component. The first sense component and the second sense component may be activated during a duration 245 to sense the charge associated with the first memory cell and the second memory cell, respectively. Other sense components (e.g., coupled to other memory cells of the word line) may be similarly activated during duration 245. Accordingly, deactivating the word line before completion of the read operation (e.g.,before the end of the duration 215) can mitigate different durations of charge integration of the memory cells, which can improve the overall performance and reliability of the associated memory device.

[0035] Fig. 3A illustrates an example of a circuit diagram 300-a that supports integration of wordline charges according to examples disclosed herein. In some examples, the circuit diagram 300-a may represent a detection circuit for a volatile memory device (e.g., a DRAM memory device). For example, a cascode circuit 320 may be depicted in the circuit diagram 300-a that is used to bias a bitline 330 to a voltage (e.g., a fixed voltage) to integrate a charge into a capacitor 325 (e.g., an amp-cap 325). In some examples, the wordline 345 may be biased prior to the end of a read operation (e.g., prior to the end of the duration 215 as described with reference to Fig. 2), which can mitigate different durations of charge integration of the memory cells, which can improve the overall performance and reliability of the associated memory device.

[0036] Circuit diagram 300-a may illustrate a voltage source 305 (e.g., a voltage pump 305, Vpump 305) coupled to a switch 310. The switch 310 may be coupled to a line 315 (e.g., qvnet 315) coupled to a capacitor 325 (e.g., an amp-cap 325). The line 315 may be coupled to a cascode 320 including one or more transistors. The cascode 320 may be coupled to a bitline 330, and the bitline 330 may be coupled to a capacitor 335 and a transistor 340. In some examples, the transistor 340 may be coupled to a wordline 345 and a capacitor 350 associated with a memory cell. In some cases, one plate of capacitor 350 may be coupled to a voltage source 355 (e.g., VSS).

[0037] During an access operation, word line 345 may be activated (e.g., brought to a voltage). Once word line 345 reaches a threshold voltage level, bit line 330 may be activated, and the charge stored in capacitor 350 may be integrated (e.g., provided) to capacitor 325. As described herein, word line 345 may be deactivated before completing the read operation. Accordingly, varying durations of charge integration of memory cells coupled to word line 345 may be mitigated, even though an initial voltage of qvnet 315 may be higher or lower than a voltage corresponding to a logic state of a memory cell.

[0038] Fig. 3B illustrates an example timing diagram 300-b that supports wordline charge integration according to examples disclosed herein. Timing diagram 300-b may illustrate example voltages of line 315 (e.g., qvnet 315), as described with reference to Fig. 3A. For example, voltage 360 ​​may represent a voltage of a first memory cell and voltage 365 may represent a voltage of a second memory cell, as described with reference to Fig. 2. Furthermore, voltage 360 ​​and voltage 365 may be illustrated relative to a reference voltage 370. Voltage 360 ​​and voltage 365 may illustrate deactivating a wordline before the end of a read operation (e.g., before the end of duration 375), which may mitigate varying durations of charge integration of the memory cells and improve the overall performance and reliability of the associated memory device.

[0039] As described herein, a read operation may occur during duration 375. During duration 375, a word line coupled to at least a first memory cell (e.g., a nearby memory cell) and a second memory cell (e.g., a remote memory cell) may be deactivated to mitigate different durations of charge integration of the memory cells. For example, a charge stored in a first memory cell may be integrated into capacitor 325 via line 315, as described with reference to Fig. 3A. If the capacitor (e.g., capacitor 350) of the first memory cell has stored a value associated with a first logic state (e.g., a logic "1"), then the voltage 360 ​​of line 315 may remain above the reference voltage 370, whereas if the capacitor of the first memory cell has stored a value associated with a second logic state (e.g., a logic "0"), the voltage 360 ​​of line 315 may fall below the reference voltage 370. It may be desirable for the difference 385 between the respective voltage values ​​to be relatively large to improve the reliability of a sensing operation.

[0040] Additionally or alternatively, a charge stored in a second memory cell may be integrated into the capacitor 325 via line 315, as described with reference to Fig. 3A. Due to the proximity of the second memory cell to the first memory cell, integration of the charge may begin after integration of the charge associated with the first memory cell has begun. If the capacitor (e.g., capacitor 350) of the second memory cell has stored a value associated with a first logic state (e.g., a logic "1"), then voltage 365 of line 315 may remain above reference voltage 370, whereas if the capacitor of the first memory cell has stored a value associated with a second logic state (e.g., a logic "0"), then voltage 365 of line 315 may fall below reference voltage 370.

[0041] By deactivating wordline 345 before the end of the read operation (e.g., before the end of duration 375), the difference 385 between the respective voltage values ​​of the first memory cell may be the same as or similar to those of the second memory cell. Having a similar difference 385 may improve the reliability of a subsequent sense operation. Accordingly, during a duration 380, respective sense amplifiers may be activated to sense the logic states associated with at least the first memory cell and the second memory cell. Deactivating the wordline before completing the read operation (e.g., before the end of duration 375) may mitigate different charge integration durations of the memory cells, which may improve the overall performance and reliability of the associated memory device.

[0042] Fig. 4 illustrates a block diagram 400 of a memory device 420 that supports wordline charge integration according to examples disclosed herein. The memory device 420 may be an example of aspects of a memory device as described with reference to Fig. 1 to 3. The memory device 420 or various components thereof may be an example of means for performing various aspects of wordline charge integration as described herein. For example, the memory device 420 may include an enable component 425, a disable component 430, a receive component 435, an integration component 440, or any combination thereof. Each of these components may communicate with another directly or indirectly (e.g., via one or more buses).

[0043] The activation component 425 may be configured as, or otherwise support, means for activating a wordline coupled to a plurality of memory cells. The deactivation component 430 may be configured as, or otherwise support, means for deactivating the wordline before activating sense components to sense charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells. In some examples, the activation component 425 may be configured as, or otherwise support, means for activating the sense components based at least in part on deactivating the wordline to sense charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells.

[0044] In some examples, the receiving component 435 may be configured as a means for receiving or otherwise supporting a read command, wherein activating the wordline is based at least in part on receiving the read command, and wherein the read command is completed based at least in part on activating the sensing components to sense the charge associated with the plurality of memory cells.

[0045] In some examples, the word line is deactivated before the read command is completed.

[0046] In some examples, a first charge of a first memory cell of the first subset of the plurality of memory cells is integrated for a first duration. In some examples, a second charge of a second memory cell of the second subset of the plurality of memory cells is integrated based at least in part on deactivating the wordline prior to activating the sense components for the first duration.

[0047] In some examples, a third memory cell included in the first subset of the plurality of memory cells is integrated based at least in part on disabling the wordline prior to enabling the sense components for the first duration.

[0048] In some examples, activating the word line occurs at a first time and deactivating the word line occurs at a second time after the first time.

[0049] In some examples, the duration between the first time and the second time is based at least in part on the type of memory cell of the plurality of memory cells.

[0050] In some examples, the plurality of memory cells each includes a volatile memory cell.

[0051] In some examples, the plurality of memory cells each includes a non-volatile memory cell.

[0052] Fig. 5 illustrates a flowchart showing a method 500 that supports integration of wordline charges according to examples disclosed herein. The operations of method 500 may be implemented by a memory device or its components as described herein. For example, the operations of method 500 may be performed by a memory device as described with reference to Fig. 1 to 4. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using specialized hardware.

[0053] At 505, the method may include activating a wordline coupled to a plurality of memory cells. The operations of 505 may be performed in accordance with examples disclosed herein. In some examples, aspects of the operations of 505 may be performed by an activation component 425, as described with reference to Fig. 4 described.

[0054] At 510, the method may include deactivating the wordline before activating sense components to sense charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells. The operations of 510 may be performed in accordance with examples disclosed herein. In some examples, aspects of the operations of 510 may be performed by a deactivation component 430, as described with reference to Fig. 4 described.

[0055] At 515, the method may include, based at least in part on deactivating the wordline, activating the sensing components to sense the charge associated with the first subset of the plurality of memory cells and the second subset of the plurality of memory cells. The operations of 515 may be performed in accordance with examples disclosed herein. In some examples, aspects of the operations of 515 may be performed by an activation component 425, as described with reference to Fig. 4 described.

[0056] In some examples, a device described herein may perform one or more methods, such as method 500. The device may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions), or any combination thereof, for performing the following aspects of the present disclosure:

[0057] Aspect 1: A method, apparatus, or non-transitory computer-readable medium including acts, features, circuits, logic, means, or instructions, or any combination thereof, for activating a wordline coupled to a plurality of memory cells; deactivating the wordline prior to activating sense components for sensing charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells; and activating the sense components for sensing charge associated with the first subset of the plurality of memory cells and the second subset of the plurality of memory cells based at least in part on deactivating the wordline.

[0058] Aspect 2: The method, device, or non-transitory computer-readable medium of aspect 1, further including acts, features, circuits, logic, means, or instructions, or any combination thereof, for receiving a read command, wherein activating the wordline is based at least in part on receiving the read command, and wherein the read command is completed based at least in part on activating the sensing components to sense the charge associated with the plurality of memory cells.

[0059] Aspect 3: The method, device, or non-transitory computer-readable medium of aspect 2, wherein deactivating the word line occurs before completing the read command.

[0060] Aspect 4: The method, device, or non-transitory computer-readable medium of any of aspects 1 to 3, wherein a first charge of a first memory cell of the first subset of the plurality of memory cells is integrated for a first duration and a second charge of a second memory cell of the second subset of the plurality of memory cells is integrated based at least in part on deactivating the wordline prior to activating the sense components for the first duration.

[0061] Aspect 5: The method, device, or non-transitory computer-readable medium of aspect 4, wherein a third memory cell included in the first subset of the plurality of memory cells is integrated based at least in part on disabling the wordline prior to enabling the sense components for the first duration.

[0062] Aspect 6: The method, device, or non-transitory computer-readable medium of any of aspects 1 to 5, wherein activating the wordline occurs at a first time and deactivating the wordline occurs at a second time after the first time.

[0063] Aspect 7: The method, device, or non-transitory computer-readable medium of aspect 6, wherein the duration between the first time and the second time is based at least in part on the type of memory cell of the plurality of memory cells.

[0064] Aspect 8: The method, device, or non-transitory computer-readable medium of any of aspects 1 to 7, wherein the plurality of memory cells each includes a volatile memory cell.

[0065] Aspect 9: The method, device, or non-transitory computer-readable medium of any of aspects 1 to 8, wherein the plurality of memory cells each includes a non-volatile memory cell.

[0066] It should be noted that the methods described in this document describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0067] The information and signals described in this document may be represented using a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols for signaling referred to in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0068] The terms "electronic communication," "conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating with each other (e.g., in conductive contact with each other, connected with each other, coupled with each other) if there is an electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, a conductive path between components that are in electronic communication with each other (e.g., in conductive contact with each other, connected with each other, or coupled with each other) can be an open circuit or a closed circuit, based on the operation of the device that includes the connected components.A conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be temporarily interrupted, for example, using one or more intermediate components such as switches or transistors.

[0069] The term "coupling" refers to a transition from an open circuit between components, where signals cannot currently be transmitted across a conductive path between the components, to a closed circuit between components, where signals can be transmitted across the conductive path between components. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components across a conductive path that previously did not allow signal flow.

[0070] The term "isolated" refers to a relationship between components in which no signals can currently flow between the components. Components are isolated from each other if an open circuit exists between them. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller causes a change that prevents signals from flowing between the components via a conductive path that previously allowed signals to flow.

[0071] The devices discussed in this document, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate or portions of the substrate may be controlled by doping using various chemicals, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other dopant.

[0072] A switching component (e.g., a transistor) discussed in this document may represent a field-effect transistor (FET) and may comprise a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a drain terminal). The terminals may be connected to other electronic components through conductive materials (e.g., metals, alloys). The source and drain may be conductive and may comprise a doped (e.g., highly doped, degenerate) semiconductor region. The source and drain may be separated by a doped (e.g., lightly doped) semiconductor region or channel. If the channel is n-type (e.g., most of the charge carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most of the charge carriers are holes), the FET may be referred to as a p-type FET.The channel may be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to conduct. A transistor can be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor can be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0073] The description set forth in this document, together with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or that fall within the scope of the claims. As used in this document, the term "exemplary" means "serving as an example, instance, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order not to obscure the concepts of the described examples.

[0074] In the accompanying figures, similar components or features may have the same reference numeral. Furthermore, different components of the same type may be distinguished by following the reference numeral with a hyphen and a second designation that distinguishes the similar components. If only the first reference numeral is used in the description, the description applies to each of the similar components with the same first reference numeral, regardless of the second reference numeral.

[0075] The functions described in this document may be implemented in hardware, in software executed by a processor, in firmware, or in a combination thereof. The functions, if implemented in software executed by a processor, may be stored on a computer-readable medium or transferred thereto as one or more instructions (e.g., code). Other examples and implementations are within the scope of the disclosure and the appended claims. Due to the nature of software, the functions described in this document may be implemented, for example, using software executed by a processor, hardware, firmware, hardwiring, or combinations thereof.Features that implement functions may also be physically located at different positions, including being distributed such that portions of functions are implemented at different physical locations.

[0076] For example, the various illustrative blocks and modules described in connection with the present disclosure may be implemented or executed with a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, another programmable logic device, or any combination thereof, to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0077] As used in this specification, including in the claims, "or" in a list of items (e.g., in a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, means a list of at least one of A, B, or CA, or B, or C, or AB, or AC, or BC, or ABC (i.e., A, B, and C). Also, the phrase "based on," as used in this specification, is not intended to be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on Condition A" may be based on both Condition A and Condition B without departing from the scope of the present disclosure. In other words, as used in this specification, the phrase "based on" is to be construed in the same manner as the phrase "based at least in part on."

[0078] Computer-readable media includes both non-transitory computer storage media and communications media, including any media that facilitates the transfer of a computer program from one location to another. A non-transitory storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can include: RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk-ROM (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer or processor.Furthermore, each connection is aptly referred to as a computer-readable medium. For example, if the software is sent from a website, server, or other remote source over a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then that coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray Disc, with disks typically reproducing data magnetically, while discs reproducing data optically using lasers. Combinations of the foregoing are also included within the scope of computer-readable media.

[0079] The description in this specification is provided to enable a person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be apparent to those skilled in the art, and the general principles defined in this specification may be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not limited to the examples and designs described in this specification, but is to be to the widest extent consistent with the principles and novel features disclosed in this specification. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 528,451

[0001] US 63 / 476,794

[0001]

Claims

[1] Method comprising: activating a word line coupled to a plurality of memory cells; Deactivating the word line before activating sense components to sense a charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells; and Activating the sensing components based at least in part on deactivating the wordline to sense the charge associated with the first subset of the plurality of memory cells and the second subset of the plurality of memory cells. [2] The method of claim 1, further comprising: Receiving a read command, wherein activating the wordline is based at least in part on receiving the read command, and wherein the read command is at least partially completed based on activating the sensing components to sense the charge associated with the plurality of memory cells. [3] The method of claim 2, wherein deactivating the word line occurs before completing the read command. [4] The method of claim 1, wherein: a first charge of a first memory cell of the first subset of the plurality of memory cells is integrated for a first duration; and a second charge of a second memory cell of the second subset of the plurality of memory cells is integrated based at least in part on disabling the word line prior to enabling the sense components for the first duration. [5] The method of claim 4, wherein a third memory cell included in the first subset of the plurality of memory cells is integrated based at least in part on disabling the wordline prior to enabling the sense components for the first duration. [6] The method of claim 1, wherein activating the word line occurs at a first time and deactivating the word line occurs at a second time after the first time. [7] The method of claim 6, wherein the duration between the first time and the second time is based at least in part on the type of memory cell of the plurality of memory cells. [8] The method of claim 1, wherein the plurality of memory cells each comprises a volatile memory cell. [9] The method of claim 1, wherein the plurality of memory cells each comprises a non-volatile memory cell. [10] A device comprising: a controller associated with a storage device, the controller configured to cause the device to: activating a word line coupled to a plurality of memory cells; Deactivating the word line before activating sense components to sense a charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells; and Activating the sensing components based at least in part on deactivating the wordline to sense the charge associated with the first subset of the plurality of memory cells and the second subset of the plurality of memory cells. [11] The device of claim 10, wherein the controller is further configured to cause the device to: Receiving a read command, wherein activating the wordline is based at least in part on receiving the read command, and wherein the read command is at least partially completed based on activating the sensing components to sense the charge associated with the plurality of memory cells. [12] The device of claim 11, wherein deactivating the word line occurs before completing the read command. [13] Device according to claim 10, wherein: a first charge of a first memory cell of the first subset of the plurality of memory cells is integrated for a first duration; and a second charge of a second memory cell of the second subset of the plurality of memory cells is integrated based at least in part on disabling the word line prior to enabling the sense components for the first duration. [14] The device of claim 13, wherein a third memory cell included in the first subset of the plurality of memory cells is integrated based at least in part on disabling the wordline prior to enabling the sense components for the first duration. [15] The device of claim 10, wherein the activation of the word line occurs at a first time and the deactivation of the word line occurs at a second time after the first time. [16] The device of claim 15, wherein the duration between the first time and the second time is based at least in part on the type of memory cell of the plurality of memory cells. [17] The device of claim 10, wherein the plurality of memory cells each comprises a volatile memory cell. [18] The device of claim 10, wherein the plurality of memory cells each comprises a non-volatile memory cell. [19] A non-transitory computer-readable medium storing code, the code comprising processor-executable instructions to: activating a word line coupled to a plurality of memory cells; Deactivating the word line before activating sense components to sense a charge associated with a first subset of the plurality of memory cells and a second subset of the plurality of memory cells; and Activating the sensing components based at least in part on deactivating the wordline to sense the charge associated with the first subset of the plurality of memory cells and the second subset of the plurality of memory cells. [20] The non-transitory computer-readable medium of claim 19, wherein the instructions are further executable by the processor to: Receiving a read command, wherein activating the wordline is based at least in part on receiving the read command, and wherein the read command is at least partially completed based on activating the sensing components to sense the charge associated with the plurality of memory cells.

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