THIN FILM CAPACITOR AND CIRCUIT BOARD WITH THE SAME

Abstract

Provision of a thin-film capacitor capable of reducing the connection resistance between a terminal electrode and a capacitance electrode. A thin-film capacitor 1 comprises: unit capacitors C1 to C3 stacked one above the other by an insulating layer 31; and via conductors 11 and 12. The unit capacitor C1 has: a capacitance electrode 111 and a dummy electrode 112 provided on one surface of a dielectric layer 100, and a capacitance electrode 121 and a dummy electrode 122 provided on the other surface of the dielectric layer 100. The via conductor 11 penetrates a stacking body S such that it contacts the dummy electrodes 122, 222, 322 and the capacitance electrodes 111, 211, and 311. The via conductor 12 penetrates the stack body S in such a way that it contacts the dummy electrodes 121, 221, 321 and the capacitance electrodes 112, 212 and 312.

Description

[Technical area]

[0001] The present disclosure relates to a thin-film capacitor and a printed circuit board containing the same. [Technical background]

[0002] Patent document 1 discloses a stacked thin-film capacitor obtained by stacking a plurality of thin-film capacitors. [Citation list][Patent document]

[0003] [Patent Document 1] JP 2019-140312A [Disclosure of the invention][Problem to be solved by the invention]

[0004] The thin-film capacitor described in patent document 1 has a structure in which a terminal electrode contacts the side surface of a capacitance electrode.

[0005] The present disclosure describes a thin-film capacitor suitable for reducing the connection resistance between the terminal electrode and the capacitance electrode. [Means to solve the problem]

[0006] A thin-film capacitor according to one aspect of the present disclosure comprises: a plurality of unit capacitors stacked one above the other by a first insulating layer; and first and second via conductors. Each of the plurality of unit capacitors contains a dielectric layer with opposing first and second surfaces, a first capacitance electrode and a first dummy electrode provided on the first surface of the dielectric layer, and a second capacitance electrode and a second dummy electrode provided on the second surface of the dielectric layer. The first capacitance electrode overlaps with the second capacitance electrode and the second dummy electrode. The second capacitance electrode overlaps with the first capacitance electrode and the first dummy electrode.The first via conductor penetrates the majority of unit capacitors and the first insulating layer to contact the first capacitance electrode and the second dummy electrode in each of the majority of unit capacitors, and the second via conductor penetrates the majority of unit capacitors and the first insulating layer to contact the second capacitance electrode and the first dummy electrode in each of the majority of unit capacitors. [Advantageous effects of the invention]

[0007] According to the present disclosure, a thin-film capacitor is provided which is suitable for reducing a connection resistance between the terminal electrode and the capacitance electrode. [Brief description of the drawings] [ Fig. 1] Fig. Figure 1A is a schematic top view of a thin-film capacitor 1 according to a first embodiment of the technology described herein, viewed from the side of the upper surface. Fig. Figure 1B is a schematic cross-sectional view of the thin-film capacitor 1. Fig. 1C is a schematic underside view of the thin-film capacitor 1 as seen from the side of the lower surface. [ Fig. 2] Fig. Figures 2A to 2D are process views to illustrate a manufacturing process for the thin-film capacitor 1 according to the first embodiment. [ Fig. 3] Fig. Figures 3A to 3C are process views to explain a manufacturing process for the thin-film capacitor 1 according to the first embodiment. [ Fig. 4] Fig. Figure 4 is a schematic cross-sectional view of a thin-film capacitor 1A according to a first modification of the first embodiment. [ Fig. 5] Fig. Figure 5 is a schematic cross-sectional view of a thin-film capacitor 1B according to a second modification of the first embodiment. [ Fig. 6] Fig. Figure 6A is a schematic cross-sectional view of a thin-film capacitor 1C according to a third modification of the first embodiment. Fig. Figure 6B is a schematic diagram showing an example where solders 25 and 26 are provided on a thin-film capacitor 1C. [ Fig. 7] Fig. Figure 7A is a schematic top view of a thin-film capacitor 2 according to a second embodiment of the technology described herein, viewed from the side of the upper surface. Fig. Figure 7B is a schematic cross-sectional view of the thin-film capacitor 2. Fig. 7C is a schematic underside view of the thin-film capacitor 2 as seen from the side of the lower surface. [ Fig. 8] Fig. Figures 8A to 8D are process views to explain a manufacturing process for the thin-film capacitor 2 according to the second embodiment. [ Fig. 9] Fig. Figures 9A to 9D are process views to explain a manufacturing process for the thin-film capacitor 2 according to the second embodiment. [ Fig. 10] Fig. Figure 10A is a schematic top view of a thin-film capacitor 3 according to a third embodiment of the technology described herein, as seen from the side of the upper surface. Fig. Figure 10B is a schematic cross-sectional view of the thin-film capacitor 3. Fig. Figure 10C is a schematic underside view of the thin-film capacitor 3 as seen from the side of the lower surface. [ Fig. 11] Fig. Figure 11 is a schematic cross-sectional view of a thin-film capacitor 4 according to a fourth embodiment of the technology described herein. [ Fig. 12] Fig. 12A and Fig. Figure 12B shows views to illustrate the structure of the unit capacitor C1 according to a first example. Fig. Figure 12A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 12B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the top surface. [ Fig. 13] Fig. 13A and Fig. Figure 13B shows views to explain the structure of the unit capacitor C1 according to a second example. Fig. Figure 13A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 13B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface. [ Fig. 14] Fig. 14A and Fig. Figure 14B shows views illustrating the structure of the unit capacitor C1 according to a third example. Fig. Figure 14A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 14B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the top surface. [ Fig. 15] Fig. 15A and Fig. Figure 15B shows views to explain the structure of the unit capacitor C1 according to a fourth example. Fig. Figure 15A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 15B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface. [ Fig. 16] Fig. 16A and Fig. Figure 16B shows views illustrating the structure of the unit capacitor C1 according to a fifth example. Fig. Figure 16A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 16B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface. [ Fig. 17] Fig. 17A and Fig. 17B are views to explain the structure of the unit capacitor C1 according to a sixth example. Fig. Figure 17A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 17B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface. [ Fig. 18] Fig. Figure 18A is a schematic cross-sectional view to illustrate the structure of a printed circuit board 6 with the thin-film capacitor 1 according to the first embodiment. Fig. Figure 18B is a schematic cross-sectional view to illustrate the structure of a printed circuit board 6A with the thin-film capacitor 1 according to the first embodiment. [ Fig. 19] Fig. Figure 19A is a schematic cross-sectional view to illustrate the structure of a printed circuit board 6B with the thin-film capacitor 1 according to the first embodiment. Fig. Figure 19B is a schematic cross-sectional view to illustrate the construction of a printed circuit board 6C with the thin-film capacitor 1 according to the first embodiment. [Method of implementation of the invention]

[0008] Preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. <Erste Ausführungsform>

[0009] Fig. Figure 1A is a schematic top view of a thin-film capacitor 1 according to a first embodiment of the technology described herein, viewed from the side of the upper surface. Fig. Figure 1B is a schematic cross-sectional view of the thin-film capacitor 1. Fig. 1C is a schematic underside view of the thin-film capacitor 1 as seen from the side of the lower surface.

[0010] As in the Fig. As shown in Figures 1A to 1C, the thin-film capacitor 1 according to the first embodiment has a structure in which three unit capacitors C1 to C3 are stacked on top of each other by an insulating layer 31. A terminal electrode 21 is provided on a surface 31a in the stacking direction of a stack body S, which is formed from the insulating layer 31 and the unit capacitors C1 to C3. A terminal electrode 22 is located on the other surface 31b in the stacking direction of the stack body S. The insulating layer 31 is made of a resin material and may contain a core material such as glass fabric.

[0011] The unit capacitors C1 to C3 have the same structure. Unit capacitor C1 comprises a dielectric layer 100, a capacitance electrode 111 located on one surface 101 of the dielectric layer 100, and a capacitance electrode 121 located on the other surface 102 of the dielectric layer 100. The capacitance electrode 111 can be a stacked structure consisting of a lower layer conductor 1111, which contacts the dielectric layer 100 and is made, for example, of nickel (Ni), copper (Cu), or a rare-earth metal, and an upper layer conductor 1112, which is stacked on top of the lower layer conductor 1111 and is made of a different material than that of the lower layer conductor 1111, selected from the group consisting, for example, of nickel (Ni), copper (Cu), or a rare-earth metal. The capacitance electrode 111 is sometimes also referred to as the upper electrode.The capacitance electrode 121 can be a stacked body consisting of a lower layer conductor 1211, which contacts the dielectric layer 100 and is made, for example, of nickel (Ni), a nickel alloy, or copper, and an upper layer conductor 1212, which is stacked on top of the lower layer conductor 1211 and is made of a different material than the lower layer conductor 1211, for example, copper (Cu). The capacitance electrode 121 is sometimes also referred to as the lower electrode.

[0012] Similarly, the unit capacitor C2 comprises a dielectric layer 200, a capacitance electrode 211 located on one surface 201 of the dielectric layer 200, and a capacitance electrode 221 located on the other surface 202 of the dielectric layer 200. The unit capacitor C3 comprises a dielectric layer 300, a capacitance electrode 311 located on one surface 301 of the dielectric layer 300, and a capacitance electrode 321 located on the other surface 302 of the dielectric layer 300. The capacitance electrodes 211 and 311 can be made of the same material and have the same layer configuration as the capacitance electrode 111. The capacitance electrodes 221 and 321 can be made of the same material and have the same layer structure as the capacitance electrode 121.

[0013] The dielectric layers 100, 200, and 300 are, for example, formed from a dielectric perovskite material. Examples of dielectric perovskite materials include ferroelectric materials or paraelectric materials with a perovskite structure, such as BaTiO3 (barium titanate), (Ba 1-x Sr x )TiO3 (barium strontium titanate), (Ba 1-x Cax)TiO3, PbTiO3, Pb (Zr x Ti 1-x )O3, (ST 1-x Approx x ), (Ti 1-Y Zr Y )O3, Ba (Mg 1 / 3 Ta 2 / 3 ), a composite ferroelectric material of the perovskite relaxer type, represented by Pb (Mg 1 / 3 Note 2 / 3 )O3, and the like, a bismuth layer compound, represented by Bi4Ti3O 12 , and SrBi2Ta2O9, a ferroelectric material of the tungsten bronze type, represented by (Sr 1-x Ba x) Nb₂O₆ and PbNb₂O₆. In the perovskite structure described above, the perovskite relaxer-type ferroelectric material, the bismuth layer compound, and the tungsten bronze-type ferroelectric material, the ratio of A-site to B-site is generally an integer ratio, but it can be intentionally deviated from this integer ratio to improve the properties. To control the properties of dielectric layers 100, 200, and 300, the dielectric layers 100, 200, and 300 can appropriately contain an additive as a partial component. The relative dielectric constant (ε) rThe dielectric strength of dielectric layers 100, 200, and 300 is, for example, 10 or more. The higher the dielectric strength of dielectric layers 100, 200, and 300, the better, and there is no particular upper limit for this value. Similarly, the higher the relative permittivity of dielectric layers 100, 200, and 300, the better, and there is no particular upper limit for this value. The thickness of dielectric layers 100, 200, and 300 ranges, for example, from approximately 10 nm to approximately 6000 nm.

[0014] On the same layer as the capacitance electrode 111 is a dummy electrode 112 made of the same material and with the same layer structure as the capacitance electrode 111. The dummy electrode 112 is separate from the capacitance electrode 111 and is smaller than the capacitance electrode 111. The dummy electrode 112 can be a stacked structure consisting of a lower layer conductor 1121 and an upper layer conductor 1122. On the same layer as the capacitance electrode 121, a dummy electrode 122 made of the same material and with the same layer configuration as the capacitance electrode 121 is provided. The dummy electrode 122 is separate from the capacitance electrode 121 and is smaller than the capacitance electrode 121. The dummy electrode 122 can be a stacked structure consisting of a lower layer conductor 1221 and an upper layer conductor 1222.

[0015] On the same layer as the capacitance electrode 211 is a dummy electrode 212 made of the same material and with the same layer structure as the capacitance electrode 211. The dummy electrode 212 is separated from the capacitance electrode 211 and is smaller than the capacitance electrode 211. On the same layer as the capacitance electrode 221 is a dummy electrode 222, which is made of the same material and has the same layer configuration as the capacitance electrode 221. The dummy electrode 222 is separated from the capacitance electrode 221 and is smaller than the capacitance electrode 221.

[0016] On the same layer as the capacitance electrode 311 is a dummy electrode 312 made of the same material and with the same layer structure as the capacitance electrode 311. The dummy electrode 312 is separated from the capacitance electrode 311 and is smaller than the capacitance electrode 311. On the same layer as the capacitance electrode 321 is a dummy electrode 322, which is made of the same material and has the same layer configuration as the capacitance electrode 321. The dummy electrode 322 is separated from the capacitance electrode 321 and is smaller than the capacitance electrode 321.

[0017] The adjacent unit capacitors C1 and C2 are arranged such that the capacitance electrodes 121 and 221 face each other through the insulating layer 31, and that the dummy electrodes 122 and 222 face each other through the insulating layer 31. The adjacent unit capacitors C2 and C3 are arranged such that the capacitance electrodes 211 and 311 face each other through the insulating layer 31, and that the dummy electrodes 212 and 312 face each other through the insulating layer 31.

[0018] Capacitance electrode 111 overlaps capacitance electrode 121 and dummy electrode 122 through the dielectric layer 100. Capacitance electrode 121 overlaps capacitance electrode 111 and dummy electrode 112 through the dielectric layer 100. Dummy electrodes 112 and 122 do not overlap each other.

[0019] Capacitance electrode 211 overlaps capacitance electrode 221 and dummy electrode 222 through the dielectric layer 200. Capacitance electrode 221 overlaps capacitance electrode 211 and dummy electrode 212 through the dielectric layer 200. Dummy electrodes 212 and 222 do not overlap each other.

[0020] Capacitance electrode 311 overlaps capacitance electrode 321 and dummy electrode 322 through the dielectric layer 300. Capacitance electrode 321 overlaps capacitance electrode 311 and dummy electrode 312 through the dielectric layer 300. Dummy electrodes 312 and 322 do not overlap each other.

[0021] The area where capacitance electrodes 111 and 121 overlap, the area where capacitance electrodes 211 and 221 overlap, and the area where capacitance electrodes 311 and 321 overlap form an effective area A that generates capacitance. In the present embodiment, capacitance electrodes 111, 211, and 311 have a larger area than capacitance electrodes 121, 221, and 321. In a top view, capacitance electrodes 121, 221, and 321 overlap with capacitance electrodes 111, 211, and 311 on three sides each. Thus, the area of ​​the effective area A depends significantly on the areas of capacitance electrodes 121, 221, and 321.

[0022] The dummy electrodes 122, 222, and 322 overlap each other in the top view, viewed in the stacking direction. In the stack body S, which consists of the insulating layer 31 and the unit capacitors C1 to C3, a via 11A is formed such that it penetrates the dummy electrodes 122, 222, and 322 and the capacitance electrodes 111, 211, and 311. The area where the dummy electrodes 122, 222, and 322 and the capacitance electrodes 111, 211, and 311 overlap forms a blind region B1 in which no capacitance is generated. The via 11A is filled with a via conductor 11. The via conductor 11 thus contacts the dummy electrodes 122, 222 and 322 and the capacitance electrodes 111, 211 and 311.Although the via hole 11A does not have to be completely filled with the via conductor 11, the via conductor 11 is located at least on the inner wall of the via hole 11A and in the central area of ​​the via hole 11A in a radial direction.

[0023] The dummy electrodes 112, 212, and 312 overlap each other in a top view viewed in the stacking direction. In the stack body S, which consists of the insulating layer 31 and the unit capacitors C1 to C3, a via 12A is formed such that it penetrates the dummy electrodes 112, 212, and 312 and the capacitance electrodes 121, 221, and 321. The area where the dummy electrodes 112, 212, and 312 and the capacitance electrodes 121, 221, and 321 overlap forms a blind region B2 in which no capacitance is generated. The via 12A is filled with a via conductor 12. The via conductor 12 thus contacts the dummy electrodes 112, 212 and 312 and the capacitance electrodes 121, 221 and 321.Although the via hole 12A does not have to be completely filled with the via conductor 12, the via conductor 12 is located at least on the inner wall of the via hole 12A and in the central area of ​​the via hole 12A in a radial direction.

[0024] An end section of the via conductor 11 contacts the terminal electrode 21, which is located on surface 31a (an outer surface of the stack body S) of the insulating layer 31. The terminal electrode 21 faces the capacitance electrode 111 through the insulating layer 31. An insulating layer 32 is located on surface 31b (the other outer surface of the stack body S) of the insulating layer 31 and contacts the other end section of the via conductor 11. An end section of the via conductor 12 contacts the terminal electrode 22, which is located on surface 31b (the other outer surface of the stack body S) of the insulating layer 31. The terminal electrode 22 faces the capacitance electrode 321 through the insulating layer 31.An insulating layer 33 is provided on the surface 31a (an outer surface of the stack body S) of the insulating layer 31 to contact the other end section of the via conductor 12. The insulating layers 32 and 33 can be formed from a resin material.

[0025] As a result, three unit capacitors C1 to C3 are connected in parallel between the terminal electrodes 21 and 22. As in the Fig. 1A and Fig. As shown in Figure 1C, the via conductors 11 and 12 can each be provided in numerical multiples. In this case, the majority of the via conductors 11 are connected to the terminal electrode 21, and the majority of the via conductors 12 are connected to the terminal electrode 22. Therefore, if the via conductors 11 and 12 are each provided in multiples, the connection resistances between the unit capacitors C1 to C3 and the terminal electrodes 21 and 22 can be reduced.

[0026] As described above, the unit capacitors C1 to C3 in the thin-film capacitor 1 according to the present embodiment each have the effective area A and blind areas B1 and B2, and the vias 11 and 12 are configured to penetrate the blind areas B1 and B2, respectively. This means that the effective area A, which has no via, is unlikely to be damaged by the formation of the via holes 11A and 12A or by the formation of the vias 11 and 12. Furthermore, external stresses are hardly transmitted to the effective area A through the vias 11 and 12. In addition, the effective area A is located between the blind areas B1 and B2 in the top view, which increases the moisture resistance of the effective area A and thus improves the reliability of the product.

[0027] Furthermore, the via conductors 11 and 12 are used to connect the terminal electrodes 21 and 22 and the unit capacitors C1 to C3, thereby also reducing the connection resistances between the terminal electrodes 21 and 22 and the unit capacitors C1 to C3. In addition, in the present embodiment, the via holes 11A and 12A are each filled with the via conductors 11 and 12, so that the resistance values ​​of the via conductors 11 and 12 themselves are also reduced.

[0028] Furthermore, in the present embodiment, the capacitance electrodes 121 and 221, both connected to the terminal electrode 22, face each other through the insulating layer 31, and the capacitance electrodes 211 and 311, both connected to the terminal electrode 21, face each other through the insulating layer 31, so that no high electric field is applied to the insulating layer 31, which is arranged between the adjacent capacitance electrodes in the stacking direction. In addition, the capacitance electrode 111, connected to the terminal electrode 21, faces the terminal electrode 21 through the insulating layer 31, and the capacitance electrode 321, connected to the terminal electrode 22, faces the terminal electrode 22 through the insulating layer 31. This suppresses the generation of stray capacitance through the insulating layer 31 in order to achieve stable control at a high frequency.The same applies to the dummy electrode. That is, the capacitance electrodes 122 and 222, which are both connected to the terminal electrode 21, face each other through the insulating layer 31, and the capacitance electrodes 212 and 312, which are both connected to the terminal electrode 22, face each other through the insulating layer 31, so that the generation of stray capacitance is suppressed.

[0029] Furthermore, in the present embodiment, the capacitance electrodes 111, 211, and 311 are each exposed on three sides by the insulating layer 31, and the capacitance electrodes 121, 221, and 321 are each exposed on one side by the insulating layer 31. That is, the three sides of each of the capacitance electrodes 111, 211, and 311, and one side of each of the capacitance electrodes 121, 221, and 321, are exposed by the side faces of the stack body S. This allows the heat generated inside the thin-film capacitor 1 to be efficiently dissipated to the outside.

[0030] Fig. 2A to 2D and Fig. Figures 3A to 3C are process views to explain a manufacturing process for the thin-film capacitor 1 according to the first embodiment.

[0031] As in Fig. As shown in Figure 2A, the unit capacitors C1 to C3 are stacked through the insulating layer 31 to form the stack body S. At this point, the surface 31b (the other outer surface of the stack body S) of the insulating layer 31 is covered with a conductor pattern 22a. Subsequently, as shown in Fig. As shown in Figure 2B, a laser beam is directed from the side of surface 31a of the insulating layer 31 onto the stack body S to form the via hole 11A, which penetrates the dummy electrodes 122, 222 and 322 and the capacitance electrodes 111, 211 and 311, and the via hole 12A, which penetrates the dummy electrodes 112, 212 and 312 and the capacitance electrodes 121, 221 and 321. During the fabrication of the via holes 11A and 12A, the conductor pattern 22a acts as a stopper. Subsequently, as shown in Fig. 2C shows that a currentless plating is applied to form a nucleation layer 13 on the surface 31a of the insulating layer 31 and the inner walls of the via holes 11A and 12A, and then an electrolytic plating is applied to coat the nucleation layer 13, as shown in Fig. The diagram is shown in 2D. This fills the via holes 11A and 12A with via conductors 11 and 12, respectively, and forms the terminal electrode 21 on the surface 31a of the insulating layer 31. Furthermore, the conductor pattern 22a formed on the surface 31b of the insulating layer 31 is grown by plating to form the terminal electrode 22.

[0032] Then, as in Fig. Figure 3A shows resist patterns R1 and R2 being formed on the surfaces of the terminal electrodes 21 and 22, respectively, and unnecessary parts of the terminal electrodes 21 and 22 being removed by etching with the resist patterns R1 and R2 as masks, as shown in Fig. As shown in 3B, removed, thereby separating the terminal electrode 21 and the terminal electrode 22 from the via conductor 12 and the via conductor 11, respectively. Consequently, as shown in Fig. 3C shows that after removing the resist patterns R1 and R2, the insulating layers 31 and 32 are formed by screen printing or similar methods, followed by singulation of the thin-film capacitor 1 to complete the thin-film capacitor 1 according to the present embodiment.

[0033] As described above, in the manufacturing process of the thin-film capacitor 1 according to the present embodiment, the via holes 11A and 12A are formed such that they penetrate the stack body S; however, the via holes 11A and 12A are each formed in the blind areas B1 and B2, so that the effective area A is not damaged when forming the via holes 11A and 12A.

[0034] Fig. Figure 4 is a schematic cross-sectional view of a thin-film capacitor 1A according to a first modification of the first embodiment.

[0035] The in Fig. The thin-film capacitor 1A shown in Figure 4 differs from the thin-film capacitor 1 according to the diagram in Figure 4. Fig. In the first embodiment shown in Figures 1A to 1C, the insulating layers 32 and 33 are arranged partially overlapping on the outer surfaces of the respective terminal electrodes 22 and 21, as viewed in the stacking direction. When the terminal electrodes 22 and 21 are partially covered with the insulating layers 32 and 33, it is unlikely that the terminal electrodes 21 and 22 will detach.

[0036] Fig. Figure 5 is a schematic cross-sectional view of a thin-film capacitor 1B according to a second modification of the first embodiment.

[0037] The in Fig. The thin-film capacitor 1B shown in Figure 5 differs from the thin-film capacitor 1 according to the diagram in Figure 5. Fig. In the first embodiment shown in Figures 1A to 1C, the planar positions of the edges of the capacitance electrodes 111, 211, and 311 within the stack body S differ from one another, and the planar positions of the edges of the capacitance electrodes 121, 221, and 321 within the stack body S also differ from one another. In this configuration, the stress acting on the edges of the capacitance electrodes 111, 211, and 311 is distributed, even under external stress on the thin-film capacitor 1B, and the stress acting on the edges of the capacitance electrodes 121, 221, and 321 is also distributed. This makes it unlikely that the capacitance electrodes will be damaged by external stresses.

[0038] Fig. Figure 6A is a schematic cross-sectional view of a thin-film capacitor 1C according to a third modification of the first embodiment.

[0039] The in Fig. The thin-film capacitor 1C shown in Figure 6A differs from the thin-film capacitor 1 according to the figure shown in Figure 6A. Fig. In the first embodiment shown in Figures 1A to 1C, the connection electrodes 21 and 23 are connected to both ends of the via conductor 11, and the connection electrodes 22 and 24 are connected to both ends of the via conductor 12. The connection electrode 23 is located on surface 31b of the insulating layer 31 instead of the insulating layer 32. The connection electrode 24 is located on surface 31a of the insulating layer 31 instead of the insulating layer 33. This allows access from both sides in the stacking direction. Alternatively, as shown in Fig. Figure 6B shows that surface mounting on a substrate is facilitated if a solder 25 is provided on one side face of the stacking body S to contact the terminal electrodes 21 and 23, and a solder 26 is provided on the other side face of the stacking body S to contact the terminal electrodes 22 and 24. <Zweite Ausführungsform>

[0040] Fig. Figure 7A is a schematic top view of a thin-film capacitor 2 according to a second embodiment of the technology described herein, seen from the top. Fig. Figure 7B is a schematic cross-sectional view of the thin-film capacitor 2. Fig. 7C is a schematic underside view of the thin-film capacitor 2 as seen from the side of the lower surface.

[0041] The thin-film capacitor 2 according to the second embodiment, shown in the Fig. 7A to 7C differs from the thin-film capacitor 1 according to the first embodiment in that the via conductors 11 and 12 are each provided on the inner walls of the via holes 11A and 12A, and that the central regions of the via holes 11A and 12A, which are surrounded by the via conductors 11 and 12, are filled with a resin portion 34. Other basic configurations are the same as those of the thin-film capacitor 1 according to the first embodiment, so that the same elements are designated with the same reference numerals and a corresponding description is omitted.

[0042] The resin part 34 can have insulating or conductive properties. Furthermore, the resin part 34 can consist solely of a synthetic resin material or be produced by adding an inorganic filler such as silicon dioxide to a synthetic resin material. According to the present embodiment, the coefficients of thermal expansion in the via holes 11A and 12A can be adjusted by the material or volume of the resin part 34, thereby improving the connection reliability of the via conductors 11 and 12.

[0043] Fig. 8A to 8D and Fig. Figures 9A to 9D are process views to explain a manufacturing process for the thin-film capacitor 2 according to the second embodiment.

[0044] As in Fig. As shown in Figure 8A, the unit capacitors C1 to C3 are stacked through the insulating layer 31 to form the stack body S. At this point, the surface 31b (the other outer surface of the stack body S) of the insulating layer 31 can be covered with a conductor pattern 22a. Subsequently, as shown in Fig. As shown in Figure 8B, a laser beam is directed onto the stacked body S to form the via hole 11A, which penetrates the dummy electrodes 122, 222, and 322 and the capacitance electrodes 111, 211, and 311, and the via hole 12A, which penetrates the capacitance electrodes 121, 221, and 321 and the dummy electrodes 112, 212, and 312. Since the surface 31b of the insulating layer 31 is covered with the conductor pattern 22a, the via holes 11A and 12A penetrate the conductor pattern 22a. Subsequently, as shown in Fig. 8C shows a currentless plating applied to form a nucleation layer 13 on the surfaces 31a and 31b of the insulating layer 31 and the inner walls of the via holes 11A and 12A, and then the via holes 11A and 12A are filled with the resin part 34 as shown in Fig. Figure 8D illustrates this. An additional electroless plating process is then performed to form the nucleation layer 13 on the surfaces of the resin part 34 exposed at the end sections of the via holes 11A and 12A. The nucleation layer 13 formed on the inner walls of the via holes 11A and 12A forms the via conductors 11 and 12. After the formation of the nucleation layer 13, electrolytic plating can be performed to increase the layer thickness of the via conductors 11 and 12.

[0045] Then, as in Fig. Figure 9A shows the resist patterns R3 and R4 being formed in the areas where the insulating layers 32 and 33 are to be formed. Then, as shown in Fig. As shown in Figure 9B, an electrolytic plating process is carried out using resist patterns R3 and R4 as masks for the coating growth of the nucleation layer 13, thereby forming the terminal electrodes 21 and 22 on the surface 31a and 31b, respectively, of the insulating layer 31. Subsequently, after removal of resist patterns R3 and R4, unnecessary areas of the nucleation layer 13 are removed, as shown in Figure 9B. Fig. 9C is shown. As a result, the terminal electrode 21 and the via conductor 12 are separated from each other, and the terminal electrode 22 and the via conductor 11 are separated from each other. Then, as shown in Fig. 9D shown, the insulating layers 32 and 33 are formed by screen printing or similar, followed by the singulation of the thin-film capacitor 2 to complete the thin-film capacitor 2 according to the present embodiment.

[0046] As described above, in the manufacturing process of the thin-film capacitor 2 according to the present embodiment, the via holes 11A and 12A are formed in the blind areas B1 and B2, respectively, so that the effective area A is not damaged during the formation of the via holes 11A and 12A. Furthermore, the via holes 11A and 12A do not need to be completely filled with the via conductors 11 and 12, respectively, so that electrolytic plating is not required over a longer period. <Dritte Ausführungsform>

[0047] Fig. Figure 10A is a schematic top view of a thin-film capacitor 3 according to a third embodiment of the technology described herein, as seen from the side of the upper surface. Fig. Figure 10B is a schematic cross-sectional view of the thin-film capacitor 3. Fig. Figure 10C is a schematic underside view of the thin-film capacitor 3 as seen from the side of the lower surface.

[0048] The thin-film capacitor 3 according to the one described in the Fig. The third embodiment shown in Figures 10A to 10C differs from the thin-film capacitor according to the first embodiment in that the capacitance electrodes 111, 121, 211, 221, 311, and 321 are embedded in the insulating layer 31 without being exposed, and that the dummy electrodes 112, 122, 212, 222, 312, and 322 are exposed on three sides of the insulating layer 31. That is, the capacitance electrodes 111, 121, 211, 221, 311, and 321 are not exposed on the side faces of the stack body S, while the dummy electrodes 112, 122, 212, 222, 312, and 322 are exposed on three sides of the stack body S. Other basic configurations are the same as those of the thin-film capacitor 1 according to the first embodiment, so that the same reference numerals are used for the same elements and a matching description is omitted.

[0049] In the present embodiment, it is unlikely that the capacitance electrodes 111, 121, 211, 221, 311, and 321 will be damaged during the singulation of the thin-film capacitor 3, thereby increasing the reliability of the moisture resistance of the effective area A. In the present embodiment, the capacitance electrodes 111, 211, and 311 overlap on three sides of the capacitance electrodes 121, 221, and 321, respectively. Therefore, the area of ​​the effective area A depends substantially on the areas of the capacitance electrodes 111, 211, and 311. <Vierte Ausführungsform>

[0050] Fig. Figure 11 is a schematic cross-sectional view of a thin-film capacitor 4 according to a fourth embodiment of the technology described herein.

[0051] The thin-film capacitor 4 according to the in Fig. The fourth embodiment shown in Figure 11 has four stacked unit capacitors C1 to C4. Unit capacitor C4 comprises a dielectric layer 400, a capacitance electrode 411, and a dummy electrode 412, which are provided on one surface of the dielectric layer 400, and a capacitance electrode 421 and a dummy electrode 422, which are provided on the other surface of the dielectric layer 400. The via hole 11A is configured to penetrate the dummy electrodes 122, 222, 322, and 422 and the capacitance electrodes 111, 211, 311, and 411. The via hole 11B is shaped to penetrate the dummy electrodes 112, 212, 312 and 412 and the capacitance electrodes 121, 221, 321 and 421.The via conductor 11 is formed on the inner wall of the via hole 11A, and the central part of the via hole 11A, surrounded by the via conductor 11, is filled with the resin part 34. The via conductor 12 is formed on the inner wall of the via hole 12A, and the central region of the via hole 12A, surrounded by the via conductor 12, is filled with the resin part 34.

[0052] Furthermore, in the thin-film capacitor 4 according to the fourth embodiment, both end sections of each of the via conductors 11 and 12 are covered with the insulating layer 31. An internal wiring pattern 41 is provided between the surface 31a of the insulating layer 31 and the unit capacitor C1. The internal wiring pattern 41 is connected to the capacitance electrode 111 via a via conductor 51. An internal wiring pattern 42 is provided between the surface 31b of the insulating layer 31 and the unit capacitor C4. The internal wiring pattern 42 is connected to a dummy electrode 412 via a via conductor 53. The terminal electrode 21 is connected to the internal wiring pattern 41 via a via conductor 52, and the terminal electrode 22 is connected to the internal wiring pattern 42 via a via conductor 54.Other basic configurations are the same as those of the thin-film capacitor 2 according to the second embodiment, so that the same elements are designated with the same reference numerals and a matching description is omitted.

[0053] As the thin-film capacitor 4 according to the fourth embodiment shows, the terminal electrodes 21 and 22 do not have to be in direct contact with the via conductors 11 and 12 respectively, but can be connected, for example, via the Fig. The internal wiring pattern shown in Figure 11 is connected to these. In this configuration, the voltage to be transmitted to the via conductors 11 and 12 is attenuated even when an external voltage is applied to the terminal electrodes 21 and 22.

[0054] Fig. 12A and Fig. Figure 12B shows views to illustrate the structure of the unit capacitor C1 according to a first example. Fig. Figure 12A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 12B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the top surface.

[0055] In the first example, which is in the Fig. 12A and Fig. As shown in Figure 12B, the capacitance electrode 111 and the dummy electrode 112 are separated by a slot 131, and the capacitance electrode 121 and the dummy electrode 122 are separated by a slot 132. The slots 131 and 132 are straight. Three via conductors 12 connected to the capacitance electrodes 121 are assigned to the dummy electrode 112, and three via conductors 11 connected to the capacitance electrodes 111 are assigned to the dummy electrode 122. The capacitance electrode and the dummy electrode can thus be separated by a straight slot.

[0056] Fig. 13A and Fig. Figure 13B shows views to explain the structure of the unit capacitor C1 according to a second example. Fig. Figure 13A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 13B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface.

[0057] The second, in the Fig. 13A and Fig. The example shown in Figure 13B corresponds to the first example with respect to the number and position of the via conductors 11 and 12, but differs in that the dummy electrodes 112 are individually assigned to the via conductors 12 and the dummy electrodes 122 to the via conductors 11. In the second example, the three dummy electrodes 112 have a rectangular, planar shape and are connected to the corresponding via conductors 12 at their substantially central sections. The capacitance electrode 111 and the dummy electrode 112 are separated from each other by a substantially U-shaped slot 133. Similarly, the three dummy electrodes 122 have a rectangular, planar shape and are connected to the corresponding via conductors 11 at their substantially central sections. The capacitance electrode 121 and the dummy electrode 122 are separated from each other by a substantially U-shaped slot 134.

[0058] In the second example, part of the capacitance electrode 111 is positioned between the adjacent dummy electrodes 112, and part of the capacitance electrode 121 is positioned between the adjacent dummy electrodes 122, thus increasing the effective area A compared to the first example. As described above, the capacitance can be increased by reducing the size of the dummy electrodes 112 and 122 and by positioning the capacitance electrodes 111 and 121 so that they surround the dummy electrodes 112 and 122.

[0059] Fig. 14A and Fig. Figure 14B shows views illustrating the structure of the unit capacitor C1 according to a third example. Fig. Figure 14A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 14B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the top surface.

[0060] The third in the Fig. 14A and Fig. The example shown in Figure 14B differs from the second example in that the dummy electrodes 112 and 122 have a circular, planar shape and are connected to the corresponding via conductors 12 and 11 at their essentially central sections. Thus, the planar shapes of the dummy electrodes 112 and 122 do not necessarily have to be rectangular, but can also be circular. This allows the areas of the capacitance electrodes 111 and 121 to be increased, thereby achieving a greater capacitance.

[0061] Fig. 15A and Fig. Figure 15B shows views to explain the structure of the unit capacitor C1 according to a fourth example. Fig. Figure 15A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 15B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface.

[0062] The in the Fig. 15A and Fig. The fourth example shown in Figure 15B differs from the third example in that the dummy electrodes 112 and 122 are provided sequentially in large numbers. When the dummy electrodes 112 and 122 are present in large numbers, the number of via conductors 11 and 12 increases accordingly, so that the combined resistance of the via conductors 11 and 12 can be reduced.

[0063] Fig. 16A and Fig. Figure 16B shows views illustrating the structure of the unit capacitor C1 according to a fifth example. Fig. Figure 16A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 16B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the top.

[0064] In the fifth example, which is in the Fig. 16A and Fig. As shown in Figure 16B, there are numerous vias 11 and 12, a dummy electrode 112 is assigned to each of these numerous vias 12, and a dummy electrode 122 is assigned to each of the numerous vias 11. This reduces the area allocated to a slot 135 for separating the capacitance electrode 111 and the dummy electrode 112, and the area allocated to a slot 136 for separating the capacitance electrode 121 and the dummy electrode 122, thus ensuring sufficient capacitance while simultaneously reducing the combined resistance of the vias 11 and 12.

[0065] Fig. 17A and Fig. 17B are views to explain the structure of the unit capacitor C1 according to a sixth example. Fig. Figure 17A is a schematic top view showing the planar shapes of the capacitance electrode 111 and the dummy electrode 112. Fig. Figure 17B is a schematic transparent top view of the planar shapes of the capacitance electrode 121 and the dummy electrode 122 as seen from the side of the upper surface.

[0066] In the sixth example, which is in the Fig. 17A and Fig. As shown in Figure 17B, four dummy electrodes 112 are provided, each with three via conductors 12, and four dummy electrodes 122, each with three via conductors 11. This allows a larger capacitance to be achieved than in the fifth example.

[0067] Fig. Figure 18A is a schematic cross-sectional view to illustrate the structure of a printed circuit board 6 with the thin-film capacitor 1 according to the first embodiment.

[0068] The in Fig. The printed circuit board 6 shown in Figure 18A has a DBC (Direct Bonded Copper) substrate 7 and the thin-film capacitor 1 mounted on the DBC substrate 7. The DBC substrate 7 has a substrate body part 7A formed from an insulating material with high thermal conductivity, such as Al₂O₃, AlN, or Si₃N₄, and metallic conductor patterns 7B and 7C formed on the front and back of the substrate body part 7A. The conductor patterns 7B and 7C are, for example, made of copper (Cu). In the Fig. In the example shown in Figure 18A, the thin-film capacitor 1 is mounted on the DBC substrate 7 such that the terminal electrode 22 of the thin-film capacitor 1 is connected to the conductor pattern 7B of the DBC substrate 7.

[0069] The surfaces of the terminal electrodes 21 and 22 of the thin-film capacitor 1 are each covered with surface treatment films 61 and 62, respectively, containing gold (Au), tin (Sn), and the like. The surface treatment film 62 of the thin-film capacitor 1 and the conductor pattern 7B of the DBC substrate 7 are bonded together by a solder 72. Examples of the solder 72 material include AuSn, AgSn, PbSn, SnSb, SnCu, SnCuNi, SnCuAg, SnCuBiIn, SnNiPCuGa, SmAgBiCu, SnAgBiCuIn, SnInAgBi, SnZn, SnZnBi, SnIn, and SnBi. The surface treatment film 61 of the thin-film capacitor 1 is connected to a bond wire 70. When the thin-film capacitor 1 is mounted on the DBC substrate 7 in this way, the heat generated by the thin-film capacitor 1 is efficiently dissipated through the DBC substrate 7.

[0070] Fig. Figure 18B is a schematic cross-sectional view to illustrate the structure of a printed circuit board 6A with the thin-film capacitor 1 according to the first embodiment.

[0071] The in Fig. The circuit board 6A shown in 18B differs from the one in Fig. The printed circuit board 6 shown in Figure 18A is modified by using a metal block 8, e.g., made of copper (Cu), instead of the DBC substrate 7. The surface treatment film 62 of the thin-film capacitor 1 and the metal block 8 are connected to each other by the solder 72. As shown, it is possible to replace the DBC substrate 7 with the metal block 8, made of, for example, copper (Cu), on which the thin-film capacitor 1 is mounted.

[0072] Fig. Figure 19A is a schematic cross-sectional view to illustrate the construction of a printed circuit board 6B with the thin-film capacitor 1 according to the first embodiment.

[0073] The in Fig. The circuit board 6B shown in 19A differs from the one in Fig. The circuit board 6 shown in Figure 18A is modified by using a metal column 81 instead of the bonding wire 70. The metal column 81 and the surface treatment film 61 on the terminal electrode 21 are connected to each other by a solder 82. As described above, the metal column 81 can be used instead of the bonding wire 70.

[0074] Fig. Figure 19B is a schematic cross-sectional view to illustrate the construction of a printed circuit board 6C with the thin-film capacitor 1 according to the first embodiment.

[0075] The in Fig. The circuit board 6C shown in 19B differs from the one in Fig. The printed circuit board 6B shown in Figure 19A is distinguished by the use of the metal block 8 instead of the DBC substrate 7. Similarly, when using the metal column 81, it is also possible to use the metal block 8 formed from copper (Cu) instead of the DBC substrate 7.

[0076] Although the preferred embodiment of the present disclosure has been described, the present disclosure is not limited to the above embodiment, and various modifications may be made within the scope of the present disclosure, and all such modifications are included in the present disclosure.

[0077] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.

[0078] A thin-film capacitor according to one aspect of the present disclosure comprises: a plurality of unit capacitors connected to one another by a first insulating layer; and first and second via conductors. Each of the plurality of unit capacitors includes a dielectric layer with opposing first and second surfaces, a first capacitance electrode and a first dummy electrode provided on the first surface of the dielectric layer, and a second capacitance electrode and a second dummy electrode provided on the second surface of the dielectric layer. The first capacitance electrode overlaps with the second capacitance electrode and the second dummy electrode. The second capacitance electrode overlaps with the first capacitance electrode and the first dummy electrode.The first via conductor penetrates the majority of the unit capacitors and the first insulating layer to contact the first capacitance electrode and the second dummy electrode contained in each of the unit capacitors, and the second via conductor penetrates the majority of the unit capacitors and the first insulating layer to contact the second capacitance electrode and the first dummy electrode contained in each of the unit capacitors. This configuration makes it possible to increase the capacitance according to the number of unit capacitors and to design an effective area where the first and second capacitance electrodes overlap, making damage unlikely.

[0079] In the thin-film capacitor described above, the first capacitance electrodes contained in the adjacent unit capacitors in the stack direction can face each other. This suppresses the generation of stray capacitance.

[0080] In the thin-film capacitor mentioned above, the edges of the first capacitance electrodes, which lie next to each other in the stacking direction in unit capacitors, can deviate from each other in their planar position. This makes it unlikely that the first capacitance electrodes will be damaged by external influences.

[0081] The thin-film capacitor described above can further comprise a first terminal electrode positioned on one surface of the first insulating layer such that it is connected to an end section of the first via conductor, and a second terminal electrode positioned on the other surface of the first insulating layer such that it is connected to an end section of the second via conductor. As a result, the first capacitance electrode and the first terminal electrode are connected to each other with low resistance, and the second capacitance electrode and the second terminal electrode are connected to each other with low resistance.

[0082] In the thin-film capacitor described above, each of the first and second via conductors can be provided in multiples, the majority of the first via conductors can be connected to the first terminal, and the majority of the second via conductors can be connected to the second terminal. This can reduce the connection resistance between the unit capacitors and the first and second terminals.

[0083] The thin-film capacitor described above can further comprise a second insulating layer, provided on the other outer surface of the first insulating layer such that it contacts the other end section of the first via conductor, and a third insulating layer, provided on one outer surface of the first insulating layer such that it contacts the other end section of the second via conductor. This allows the other end sections of the first and second via conductors to be isolated.

[0084] In the thin-film capacitor mentioned above, part of the second insulating layer can be positioned on the outer surface of the second terminal electrode such that it overlaps the second terminal electrode in the stacking direction, and part of the third insulating layer can be positioned on the outer surface of the first terminal electrode such that it overlaps the first terminal electrode in the stacking direction. This can prevent the first and second terminal electrodes from separating.

[0085] In the thin-film capacitor described above, the first terminal electrode can contact either end of the first via conductor, and the second terminal electrode can contact either end of the second via conductor. This allows access to the first and second terminal electrodes from both sides in the stacking direction.

[0086] In the thin-film capacitor mentioned above, the first and second capacitance electrodes can overlap at a point between the first and second via conductors when viewed from above. This improves the moisture resistance of the effective area where the first and second capacitance electrodes overlap, thus increasing product reliability.

[0087] In the thin-film capacitor mentioned above, the first and second vias can be filled with via holes that penetrate the majority of unit capacitors and the first insulating layer. This reduces the resistance values ​​of the first and second vias.

[0088] In the thin-film capacitor described above, the first and second via conductors can be located on the inner walls of via holes, each penetrating the majority of the unit capacitors and the first insulating layer. The central sections of the via holes, surrounded by the first and second via conductors, can be filled with a resin. This allows the coefficient of thermal expansion within the via hole to be adjusted by the material or volume of the resin.

[0089] In the thin-film capacitor mentioned above, the first and second capacitance electrodes can be embedded in the first insulating layer without being exposed by it. This makes it unlikely that the first and second capacitance electrodes will be damaged during singulation.

[0090] In the thin-film capacitor mentioned above, the first dummy electrode can be surrounded by the first capacitance electrode in at least three directions, and the second dummy electrode can be surrounded by the second capacitance electrode in at least three directions. This allows the surface areas of the first and second capacitance electrodes to be increased.

[0091] A printed circuit board according to one aspect of the present disclosure comprises: a substrate with surfaces from which a metal element is exposed, and the thin-film capacitor described above. The thin-film capacitor is mounted on the substrate such that the first terminal electrode is connected to the metal part. This allows the heat generated by the thin-film capacitor to be efficiently dissipated through the substrate. [List of reference symbols] 1-4, 1A, 1B, 1C thin film capacitor 6, 6A, 6B, 6C circuit board 7 DBC substrate 7A Substrate body part 7B, 7C conductor pattern 8 metal blocks 11, 12 over ladder 11A, 12A via hole 13 Germinal layer 21-24 Connection electrode 22a Conductor pattern 25, 26 Soldering 31-33 Insulation layer 31a, 31b Surface 34 resin part 41, 42 internal wiring pattern 51-54 via ladder 61, 62 Surface treatment film 70 Bond wire 72 Lot 81 metal column 82 Lot 100, 200, 300, 400 dielectric layer 101, 102, 201, 202, 301, 302 Surface 111, 121, 211, 221, 311, 321, 411, 421 Capacitance electrode 112, 122, 212, 222, 312, 322, 412, 422 Blind electrode 131-136 Slot 1111, 1121, 1211, 1221 Lower Shift Supervisor 1112, 1122, 1212, 1222 Senior Shift Supervisor An effective area B1, B2 Blind area C1-C4 unit capacitor R1-R4 resist pattern S stacking body QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-140312A

[0003]

Claims

[1] Thin-film capacitor, comprising: a plurality of unit capacitors connected to each other by a first insulating layer; and first and second through-hole conductors, wherein each of the plurality of unit capacitors has a dielectric layer with opposing first and second surfaces, a first capacitance electrode and a first dummy electrode provided on the first surface of the dielectric layer, and a second capacitance electrode and a second dummy electrode provided on the second surface of the dielectric layer, where the first capacitance electrode overlaps with the second capacitance electrode and the second dummy electrode, where the second capacitance electrode overlaps with the first capacitance electrode and the first dummy electrode, wherein the first via conductor penetrates the plurality of unit capacitors and the first insulating layer to contact the first capacitive electrode and the second dummy electrode contained in each of the plurality of unit capacitors, and wherein the second via conductor penetrates the plurality of unit capacitors and the first insulating layer to contact the second capacitive electrode and the first dummy electrode contained in each of the plurality of unit capacitors. [2] Thin-film capacitor according to claim 1, wherein the first capacitance electrodes contained in the unit capacitors which are adjacent in a stacking direction are facing each other. [3] Thin-film capacitor according to claim 2, wherein the edges of the first capacitance electrodes contained in the unit capacitors which are adjacent in the stack direction differ from each other in their planar position. [4] Thin-film capacitor according to claim 1, further comprising: a first terminal electrode provided on a surface of the first insulating layer such that it is connected to an end section of the first via conductor; and a second terminal electrode which is provided on the other surface of the first insulating layer in such a way that it is connected to an end section of the second via conductor. [5] Thin-film capacitor according to claim 4, where each of the first and second through-hole conductors is present in a plurality, wherein the majority of the first via conductors are connected together with the first terminal electrode, and where the majority of the second via conductors are connected together with the second terminal electrode. [6] Thin-film capacitor according to claim 4, further comprising: a second insulating layer provided on the other outer surface of the first insulating layer such that it contacts the other end section of the first via conductor; and a third insulating layer which is provided on one outer surface of the first insulating layer in such a way that it contacts the other end section of the second via conductor. [7] Thin-film capacitor according to claim 6, wherein part of the second insulating layer is provided on an outer surface of the second terminal electrode such that it overlaps the second terminal electrode in a stacking direction, and wherein part of the third insulating layer is provided on an outer surface of the first terminal electrode, so that it overlaps the first terminal electrode in the stacking direction. [8] Thin-film capacitor according to claim 4, wherein the first terminal electrode contacts both one and the other end section of the first via conductor, and wherein the second terminal electrode contacts both one and the other end section of the second via conductor. [9] Thin-film capacitor according to claim 1, wherein the first and the second capacitance electrode overlap at a point between the first and the second via conductor in the top view. [10] Thin-film capacitor according to claim 1, wherein the first and second via conductors are filled in via holes which each penetrate the plurality of unit capacitors and the first insulating layer. [11] Thin-film capacitor according to claim 1, wherein the first and second via conductors are provided on inner walls of via holes, each penetrating the majority of unit capacitors and the first insulating layer, and wherein middle sections of the via holes, which are surrounded by the first and second via conductors, are filled with a resin part. [12] Thin-film capacitor according to claim 1, wherein the first and the second capacitance electrode are embedded in the first insulating layer without being exposed by the first insulating layer. [13] Thin-film capacitor according to claim 1, wherein the first dummy electrode is surrounded by the first capacitive electrode in at least three directions, and wherein the second dummy electrode is surrounded by the second capacitive electrode in at least three directions. [14] Printed circuit board comprising: a substrate with surfaces from which a metal element is exposed; and the thin-film capacitor according to one of claims 4 to 7, wherein the thin-film capacitor is mounted on the substrate in such a way that the first terminal electrode is connected to the metal part.

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