Semiconductor device and method for manufacturing a semiconductor device

Abstract

The generation of a high impulse voltage is suppressed. A semiconductor device comprises a trench extending from the upper surface of a base layer such that it reaches a first impurity layer and further the interior of a first pillar layer, a first gate electrode located within the trench and surrounded by a first insulating film, and a second gate electrode arranged such that it is in contact with a collector layer sandwiched between a buffer layer and a second impurity layer, with a second insulating film between them, and such that it does not reach the first pillar layer, and the first pillar layer and the second pillar layers are arranged alternately in a direction intersecting a depth direction of the first pillar layer.

Description

TECHNICAL AREA

[0001] The technology disclosed in the description of the present application relates to a semiconductor technology. BACKGROUND TECHNOLOGY

[0002] In some prior art semiconductor devices, a super junction structure (a structure in which a columnar p-type layer and a columnar n-type layer are arranged alternately) is arranged in a drift region (see, for example, patent document 1). DOCUMENTS ACCORDING TO THE STATE OF THE TECHNOLOGY PATENT DOCUMENT(S)

[0003] [Patent Document 1] Published Japanese patent application Official Gazette No. 2002-26320 SUMMARY: PROBLEM TO BE SOLVED BY THE INVENTION

[0004] Since a state-of-the-art structure has a thinned super-junction structure (a voltage-holding part), in some cases, when a recovery current is high, the voltage-holding part becomes completely depleted, generating a high impulse voltage.

[0005] The technique disclosed in the description of the present application is intended to solve the problem described above and is a technique to suppress the generation of a high impulse voltage in a semiconductor device with a super-junction structure. MEANS TO SOLVE THE PROBLEM

[0006] A first aspect of the technology disclosed in the description of the present application is intended for a semiconductor device, and the semiconductor device comprises a first pillar layer of a first conductivity type, a plurality of second pillar layers, each of a second conductivity type, arranged from an upper surface of the first pillar layer at a depth extending into the interior of the first pillar layer, a first impurity layer of the first conductivity type arranged on the upper surface of the first pillar layer, a base layer of the second conductivity type arranged in a surface layer of an upper surface of the first impurity layer, a trench arranged from an upper surface of the base layer such that it reaches the first impurity layer and further into the interior of the first pillar layer, and a first gate electrode arranged within the trench.wherein it is surrounded by a first insulating film, a source layer of the first conductivity type arranged in a part of a surface layer of the upper surface of the base layer, being in contact with the first insulating film, a first intermediate film arranged to cover a part of the source layer and the first gate electrode, an emitter electrode arranged to cover the base layer, the source layer and the first intermediate film, a buffer layer of the first conductivity type arranged on a lower surface of the first column layer, a collector layer of the second conductivity type arranged in a surface layer of a lower surface of the buffer layer, a second impurity layer of the first conductivity type arranged in a part of a surface layer of a lower surface of the collector layer, a second gate electrode,which is arranged so that it is in contact with the collector layer sandwiched between the buffer layer and the second impurity layer, with a second insulating film arranged between them, and so that it does not reach the first pillar layer, a second intermediate film arranged to cover the second gate electrode, and a collector electrode arranged to cover the collector layer and the second intermediate film, and in the semiconductor device the first pillar layer and the second pillar layers are arranged alternately in a direction intersecting a depth direction of the first pillar layer. EFFECTS OF INVENTION

[0007] According to at least the first aspect of the technique disclosed in the description of the present application, it is possible in the semiconductor device with a super-junction structure to suppress the generation of a high impulse voltage.

[0008] These and other objectives, features, aspects and advantages of the technology disclosed in the description of the present application will become more apparent from its detailed description below when it is taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. 1] is a top view showing an exemplary structure of a semiconductor device according to a preferred embodiment; [ Fig. 2] is a cross-sectional view showing an exemplary structure of an AB cross-section of an element area in the in Fig. The structure shown in 1 represents; [ Fig. Figure 3] is a cross-sectional view showing another exemplary structure of the AB cross-section of the element area in the Fig. The structure shown in 1 represents; [ Fig. Figure 4] is a representation that conceptually depicts an exemplary configuration of the semiconductor device according to the preferred embodiment; [ Fig. 5] is a view that represents a state in which the in Fig. 4 semiconductor devices shown are connected in series; [ Fig. [6] is a table that provides an example of the distinction between current modes in a case where a by means of a in Fig. The current detected by the current detection device shown in section 4 is determined using a current mode determination device; [ Fig. [7] is a graphical representation showing exemplary gate signals according to a current mode of a collector current; [ Fig. Figure 8] is a graphical representation that illustrates an exemplary determination of a high-current range and a low-current range in a case where one polarity of the collector current is positive; [ Fig. [9] is a diagram that conceptually represents an exemplary configuration of the semiconductor device according to the preferred embodiment; [ Fig.

[10] is a table that provides an example of the differentiation of voltage modes in a case where a voltage is applied by means of a voltage in Fig. The voltage detected by the voltage detection device shown in Figure 9 is determined using a voltage mode determination device; [ Fig.

[11] is a graphical representation that provides an exemplary determination of a high-voltage range and a low-voltage range in a case where one polarity of a collector-emitter voltage is positive; [ Fig.

[12] is a top view showing an exemplary structure of the semiconductor device according to the preferred embodiment; [ Fig. Figure 13] is a cross-sectional view showing an exemplary structure of an AB cross-section across the element area and a termination area in the Fig. The structure shown in 12 represents; [ Fig.

[14] is a cross-sectional view, which is a variant of the one in Fig. The structure shown in section 13 represents; and [ Fig.

[15] is a cross-sectional view, which is another variant of the in Fig. The structure shown in section 13 is represented. DESCRIPTION OF THE FORM(S)

[0009] The preferred embodiments are described below with reference to the accompanying drawings. While detailed features and the like are presented for the purpose of describing the technology, they are illustrated for illustrative purposes only, and not all features are always necessary to achieve the preferred embodiments.

[0010] Furthermore, the figures are presented schematically, and for the sake of clarity, some components may be omitted or a structure simplified. Moreover, the correlation in size and position of a structure or the like, depicted in different figures, is not always accurately represented but may be altered. Even in figures other than a cross-sectional view, such as a top view or the like, hatching is sometimes used in preferred embodiments to facilitate understanding of the content.

[0011] Furthermore, in the following description, identical component elements are represented by the same reference symbols and each has the same name and function. Therefore, in some cases, their detailed description is omitted to avoid repetition.

[0012] Furthermore, in the description presented in the description of the present application, when it is described that something “comprises”, “contains”, “has”, or the like a component element, this description is not such an exclusive expression as to indicate that there is no other component element unless otherwise stated.

[0013] Furthermore, in the description presented in the description of the present application, even in a case where any number of ordinal numbers such as "first", "second" and the like is used, these words are used for convenience in order to make the contents of the preferred embodiments easy to understand, and the contents are not limited to the sequence or the like represented by these ordinal numbers.

[0014] Furthermore, in the description presented in the present application, even in cases where any of the words used in the description such as "upper", "lower", "left", "right", "side", "bottom or underside", "front", "rear" and the like are used, which signify specific positions and directions, they are used for convenience to make the contents of the preferred embodiments easy to understand and do not have any relation to actual positions or directions used when any of the preferred embodiments are carried out.

[0015] Furthermore, in the description presented in the present application, in a case where any expression such as "an upper surface of...", "a lower surface of...", and the like is used, these expressions encompass not only the upper surface itself or the lower surface itself of a target component element, but also a state in which any other component element is formed on the upper surface or the lower surface of the target component element. Specifically, in a case where, for example, "B arranged on an upper surface of A" is described, this expression does not preclude a state in which another component element "C" is present between A and B. <Erste bevorzugte Ausführungsform>

[0016] In the following, a semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. <Struktur einer Halbleitervorrichtung>

[0017] Fig. Figure 1 is a top view illustrating an exemplary structure of a semiconductor device according to the present preferred embodiment. As in the exemplary structure of Fig. As shown in Figure 1, the semiconductor device comprises an element area 12 and a termination area 14 surrounding the element area 12 in plan view.

[0018] Fig. Figure 2 is a cross-sectional view showing an exemplary structure of an AB cross-section of element area 12 in the Fig. 1 represents the structure shown.

[0019] As in the exemplary structure of Fig. As shown in Figure 2, the element area 12 comprises an n-type column layer 22 and a plurality of p-type column layers 24, each of which extends from an upper surface of the n-type column layer 22 to a predetermined depth within the n-type column layer 22. A structure in which the n-type column layer 22 and the p-type column layers 24 are arranged alternately in a direction intersecting a depth direction is also referred to as a stress-retaining part.

[0020] Furthermore, the element area 12 comprises an n-type buffer layer 26 arranged on a lower surface of the n-type column layer 22 and an n-type emitter-side layer 28 arranged on the upper surface of the n-type column layer 22.

[0021] Furthermore, the element area 12 comprises a collector layer 30 of p-type arranged in a surface layer on one side of a lower surface of the buffer layer 26 of n-type and a base layer 32 of p-type arranged in a surface layer on one side of an upper surface of the emitter-side layer 28 of n-type.

[0022] Furthermore, the element area 12 includes a trench 50 extending from a lower surface of the p-type collector layer 30 to the interior of the n-type buffer layer 26, and a trench 52 extending from an upper surface of the p-type base layer 32 to the emitter-side layer 28 of the n-type and further to the interior of the n-type column layer 22. The trench 50 has an insulating film 54 arranged along a bottom surface and a side surface within the trench 50, and a collector-side gate electrode 58 located inside the trench 50 and surrounded by the insulating film 54. The trench 52 contains an insulating film 56 arranged along a bottom surface and a side surface inside the trench 52 and an emitter-side gate electrode 60 arranged inside the trench 52, which is surrounded by the insulating film 56.The collector-side gate electrode 58 is in contact with the p-type collector layer 30, which is sandwiched between the n-type buffer layer 26 and a collector-side n-type layer 34, with the insulating film 54 positioned between them. The collector-side gate electrode 58 is positioned such that it does not reach the n-type column layer 22.

[0023] Furthermore, the element region 12 includes the collector-side layer 34 of n-type, which is arranged in part of a surface layer on one side of a lower surface of the collector layer 30 of p-type, in contact with the insulating film 54, and an n-type source layer 36, which is arranged in part of a surface layer on one side of an upper surface of the base layer 32 of p-type, in contact with the insulating film 56. Hereinafter, the source layer 36 of n-type, the base layer 32 of p-type, the insulating film 56, and the emitter-side gate electrode 60 are collectively referred to as an emitter-side channel subregion. Furthermore, the collector-side layer 34 of n-type, the collector layer 30 of p-type, the insulating film 54, and the collector-side gate electrode 58 are collectively referred to as a collector-side channel subregion.

[0024] Furthermore, the element area 12 includes an interlayer film 38 arranged to cover part of the collector-side n-type layer 34 and the collector-side gate electrode 58, a collector electrode 42 arranged to cover the p-type collector layer 30, the n-type collector-side layer 34 and the interlayer insulating film 38, an interlayer insulating film 40 arranged to cover part of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 arranged to cover the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.

[0025] The emitter-side n-type layer 28 is formed between the p-type base layer 32 and the voltage-holding portion, being flatter or less deep than the bottom or underside of the emitter-side gate electrode 60. The voltage-holding portion, consisting of the n-type column layer 22 and the p-type column layers 24, is also referred to as a superjunction structure.

[0026] The peak defect concentration of the source layer 36 of the n-type, for example, is not less than 1×10 18 cm -3 and not higher than 1×10 21 cm -3 Furthermore, the peak defect concentration of the base layer 32 of p-type is, for example, 1×10 17 cm -3 .

[0027] The peak defect concentration of the emitter-side layer 28 of n-type, for example, is not less than 1×10 15 cm -3 and not higher than 1×10 17 cm -3Furthermore, the peak defect concentration of the buffer layer 26 of n-type, for example, is not less than 1×10 15 cm -3 and not higher than 1×10 18 cm -3 .

[0028] The peak defect concentration of the p-type collector layer 30, for example, is not less than 1×10 17 cm -3 and not higher than 1×10 19 cm -3 Moreover, the peak defect concentration of the collector-side layer 34 of n-type, for example, is not less than 1×10 18 cm -3 and not higher than 1×10 21 cm -3 .

[0029] If the part holding a tensile stress is formed by a drift layer of n-type, its impurity concentration is approximately 1×10 14 cm -3However, if the part holding one of the standing stresses has the superjunction structure described above, the impurity concentration of the column layer 22 of n-type and the column layers 24 of p-type is approximately 1×10 15 cm -3 .

[0030] The interval of a repeated arrangement (emitter-side gate distance) of the emitter-side gate electrode 60 does not have to be the same as the interval of a repeated arrangement (collector-side gate distance) of the collector-side gate electrode 58.

[0031] Fig. Figure 3 is a cross-sectional view showing another exemplary structure of the AB cross-section of element area 12 in the Fig. 1 represents the structure shown.

[0032] As in the exemplary structure of Fig. As shown in Figure 3, the element area 12 comprises the n-type column layer 22, the p-type column layers 24, an n-type buffer layer 26A arranged on the lower surface of the n-type column layer 22, and the n-type emitter-side layer 28.

[0033] Furthermore, the element area 12 comprises an n-type collector layer 30A, which is arranged in part of a surface layer on one side of a lower surface of the n-type buffer layer 26A, the p-type base layer 32 and the trench 52. The trench 52 contains the insulating film 56 and the emitter-side gate electrode 60.

[0034] Furthermore, the element area 12 contains a collector-side layer 34A of n-type, which is arranged in part of a surface layer on one side of a lower surface of the collector layer 30A of p-type, and the source layer 36 of n-type.

[0035] The element area 12 further comprises an insulating film 54A, arranged to cover part of the p-type collector layer 30A, the n-type collector-side layer 34A, and the exposed n-type buffer layer 26A; a collector-side gate electrode 58A, arranged to cover the insulating film 54A; an intermediate film 38A, arranged to cover the collector-side electrode 58A; the collector electrode 42, arranged to cover the p-type collector layer 30A and the intermediate film 38A; the intermediate film 40; and the emitter electrode 44. The collector-side gate electrode 58A is in contact with the collector layer 30A, which is sandwiched between the n-type buffer layer 26A and the n-type collector-side layer 34A. p-type, with the insulating film 54A positioned between them.The collector-side electrode 58A is then arranged in such a way that it does not reach the column layer 22 of the n-type.

[0036] In a backward conducting state, a positive voltage is applied to the collector-side gate electrode 58, and in the collector-side channel part area, the collector-side layer 34 of n-type and the part holding a withstand voltage are electrically connected to each other.

[0037] In this case, when the emitter-side gate electrode 60 is brought into an ON state (a state in which a positive voltage is applied to it), unipolar operation is achieved, and when the emitter-side gate electrode 60 is brought into an OFF state (a state in which no positive voltage is applied to it), bipolar operation is achieved. Unipolar operation here refers to an operation in which electrons from the collector-side n-type layer 34 are transported through the channel, flowing in the voltage-holding portion to reach the n-type source layer 36. Furthermore, bipolar operation refers to an operation in which electrons from the collector-side n-type layer 34 are transported through the channel, flowing in the voltage-holding portion to reach the p-type base layer 32, and then holes are injected from the p-type base layer 32.

[0038] In a reverse recovery (which is also referred to as recovery in the following), which is a transition process from the reverse conducting state to a blocking or switching-off state, the electrons and holes are discharged into the collector-side layer 34 of the n-type or the base layer 32 of the p-type and a depletion layer is extended from both sides of the part holding a voltage.

[0039] If the voltage-holding portion is thinned due to the superjunction structure, it will become more easily depleted during bipolar recovery. Since a recovery current is abruptly interrupted or switched off when the voltage-holding portion is completely depleted, a high surge voltage will be generated if a high recovery current is being transmitted when the voltage-holding portion is completely depleted.

[0040] Since hole injection from the p-type base layer 32 is reduced during the reverse conduction of the bipolar in a case where the emitter-side layer 28 is n-type, it is possible to reduce carrier accumulation on the emitter side. During the bipolar's recovery, this promotes depletion from the emitter side. Depletion from the collector side is then suppressed, thus preventing the generation of a high surge voltage due to complete depletion.

[0041] Thus, according to the semiconductor device of the present preferred embodiment, it is possible to avoid a high surge voltage during the recovery of the bipolar. Therefore, it is possible to transport the current bidirectionally while suppressing any electromagnetic noise or breakdown due to the high surge voltage. <Die zweite bevorzugte Ausführungsform>

[0042] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Furthermore, in the following description, components identical to those shown in the preferred embodiment described above are represented by the same reference numerals, and their detailed description is omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0043] Fig. Figure 4 is a diagram that conceptually illustrates an exemplary configuration of the semiconductor device according to the present preferred embodiment. As in the exemplary configuration of Fig. As shown in Figure 4, the semiconductor device comprises a collector-side gate drive 102 for driving the Fig. 2 collector-side gate electrode 58 shown, an emitter-side gate control device 104 for controlling the in Fig. 2 emitter-side gate electrode 60 shown, a PWM (pulse width modulation) control device 106 for supplying a control signal to the collector-side gate control device 102 and the emitter-side gate control device 104, a current detection device 108 for detecting the collector current (load current) and a current mode determination device 110 for determining a current mode on the basis of a current value detected by means of the current detection device 108.

[0044] Fig. 5 is a view that represents a state in which the in Fig. The 4 semiconductor devices shown are connected in series.

[0045] Fig. Table 6 is an example of a distinction between current modes in a case where the current is determined by means of the in Fig. The current detected by the current detection device 108 shown in Figure 4 is determined by means of the current mode determination device 110.

[0046] As in the exemplary case of Fig. As shown in Figure 6, when the collector current, whose polarity is positive, is detected by the current detection device 108, the current mode determiner 110 interprets an emitter-side gate signal as a PWM control signal (specifically, based on a determination result obtained by the current mode determiner 110, the PWM control signal is output from the PWM control device 106 to the emitter-side gate drive device 104). Furthermore, in this case, if a collector current value is higher than a predetermined threshold, the current mode determiner 110 switches off a collector-side gate signal (i.e., a signal to drive the collector-side gate electrode 58), and if the collector current value is lower than the predetermined threshold, the current mode determiner 110 switches the collector-side gate signal on.

[0047] As in the exemplary case of Fig. As shown in Figure 6, when the collector current, which has a negative polarity, is detected by the current detection device 108, the current mode determiner 110 switches on the collector-side gate signal. Furthermore, in this case, if the collector current value is lower than the predetermined threshold, the current mode determiner 110 designates the emitter-side gate signal as the PWM control signal, and if the collector current value is higher than the predetermined threshold, the current mode determiner 110 switches off the PWM control signal in order to prevent the emitter-side gate signal from being output.

[0048] Fig. Figure 7 is a graphical representation showing exemplary gate signals according to a current mode of the collector current. As in the exemplary case of Fig. As shown in Figure 7, if the polarity of the collector current is positive and its collector current value is higher (i.e., a high current range), the collector-side gate signal is switched off to bring about bipolar operation.

[0049] As in the exemplary case of Fig. As shown in Figure 7, if the polarity of the collector current is positive and its collector current value is lower (i.e., a low current range), the collector-side gate signal is switched on to bring about unipolar operation.

[0050] Furthermore, as in the exemplary case of Fig. Figure 7 shows that when the polarity of the collector current is negative and its collector current value is lower, the collector-side gate signal is switched on to bring about unipolar operation.

[0051] As in the exemplary case of Fig. As shown in Figure 7, if the polarity of the collector current is negative and its collector current value is higher, the PWM control signal of the emitter-side gate is switched off and the collector-side gate signal is switched on to bring about bipolar operation.

[0052] Fig. Figure 8 is a graphical representation that shows an exemplary determination of the high current range and the low current range in a case where the polarity of the collector current is positive. Fig. Figure 8 shows a collector current X1 in a case where the collector-side gate signal is turned on, and a collector current X2 in a case where the collector-side gate signal is turned off. Furthermore, in Fig. 8 the vertical axis represents the magnitude of the collector current and the horizontal axis represents the magnitude of a voltage between the collector electrode and the emitter electrode.

[0053] As in the exemplary case of Fig. As shown in Figure 8, both the collector current X1 and the collector current X2 increase with increasing voltage between the collector electrode and the emitter electrode. Furthermore, in a region where the voltage between the collector electrode and the emitter electrode is low, the collector current X2 is lower than the collector current X1, and in a region where the voltage between the collector electrode and the emitter electrode is high, the collector current X2 is higher than the collector current X1.

[0054] A value of the collector current at a time when the relationship between the collector current X1 and the collector current X2 is reversed can be determined as a limit between the high current range and the low current range.

[0055] Although the collector current state (polarity, high / low) changes during inverter operation to (positive, high), (positive, low), (negative, low), (negative, high), (negative, low), (positive, low), (positive, high), (positive, low), ... in that sequence, the operating mode (current mode) does not change before and after the collector current polarity reversal. Therefore, it is unnecessary to measure the current (measure the current from 0 A) at the point of a collector current polarity reversal.

[0056] Thus, according to the semiconductor device of the present preferred embodiment, it is not necessary to detect the current of 0 A, which is difficult to detect due to noise.

[0057] Therefore, it is possible to transport the current bidirectionally in the semiconductor device, while preventing the breakdown of the semiconductor device due to a false detection of the current of 0 A. <Die dritte bevorzugte Ausführungsform>

[0058] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Furthermore, in the following description, components identical to those depicted in the preferred embodiments described above are represented by the same reference numerals, and their detailed description is omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0059] Fig. Figure 9 is a diagram that conceptually illustrates an exemplary configuration of the semiconductor device according to the present preferred embodiment. As in the exemplary configuration of Fig. As shown in Figure 9, the semiconductor device comprises the collector-side gate drive 102 for driving the Fig. 2 collector-side gate electrode 58 shown, the emitter-side gate control means 104 for controlling the in Fig. 2 the emitter-side gate electrode 60 shown, the PWM control means 106 for supplying a control signal to the collector-side gate control means 102 and the emitter-side gate control means 104, a voltage detection means 112 for detecting a collector-emitter voltage and a voltage mode determination means 114 for determining a voltage mode on the basis of a voltage value detected by means of the voltage detection means 112.

[0060] The semiconductor devices described above are as described in Fig. 5 are shown connected in series.

[0061] Fig. Table 10 is an example of a distinction between voltage modes in a case where one is determined by means of the in Fig. The voltage detected by the voltage detection device 112 shown in Figure 9 is determined using the voltage mode determination device 114.

[0062] As in the exemplary case of Fig. As shown in Figure 10, when the collector-emitter voltage, whose polarity is positive, is detected by the voltage detection device 112, the voltage mode determiner 114 identifies the emitter-side gate signal as the PWM control signal (specifically, based on a determination result obtained by the voltage mode determiner 114, the PWM control signal is output from the PWM control device 106 to the emitter-side gate drive device 104). Furthermore, in this case, if the collector-emitter voltage is higher than a predetermined threshold, the voltage mode determiner 114 switches off the collector-side gate signal (i.e., the signal for driving the collector-side gate electrode 58), and if the collector current value is lower than the predetermined threshold, the voltage mode determiner 114 switches on the collector-side gate signal.

[0063] Furthermore, as in the exemplary case of Fig. As shown in Figure 10, when the collector current, which has a negative polarity, is detected by the voltage detection device 112, the voltage mode determiner 114 activates the collector-side gate signal. Furthermore, in this case, if the collector-emitter voltage is lower than the predetermined threshold, the voltage mode determiner 114 identifies the emitter-side gate signal as the PWM control signal, and if the collector-emitter voltage is higher than the predetermined threshold, the voltage mode determiner 114 switches off the PWM control signal to prevent the emitter-side gate signal from being output.

[0064] If the polarity of the collector-emitter voltage is positive and the collector-emitter voltage is higher, the collector-side gate is switched off to bring about bipolar operation.

[0065] If the polarity of the collector-emitter voltage is positive and the collector-emitter voltage is lower, the collector-side gate is switched on to bring about unipolar operation.

[0066] If the polarity of the collector-emitter voltage is negative and the collector-emitter voltage is lower, the collector-side gate is switched on to bring about unipolar operation.

[0067] If the polarity of the collector-emitter voltage is negative and the collector-emitter voltage is higher, the PWM control signal of the emitter-side gate is switched off and the collector-side gate is switched on to bring about bipolar operation.

[0068] Fig. Figure 11 is a graphical representation that provides an exemplary determination of the high voltage range and the low voltage range in a case where the polarity of the collector-emitter voltage is positive. Fig. Figure 11 shows a collector current Y1 in a case where the collector-side gate signal is turned on, and a collector current Y2 in a case where the collector-side gate signal is turned off. Furthermore, in Fig. 11 the vertical axis represents the magnitude of the collector current and the horizontal axis represents the magnitude of the voltage between the collector electrode and the emitter electrode.

[0069] As in the exemplary case of Fig. As shown in Figure 11, both the collector current Y1 and the collector current Y2 increase with increasing voltage between the collector electrode and the emitter electrode. Furthermore, in a region where the voltage between the collector electrode and the emitter electrode is low, the collector current Y2 is lower than the collector current Y1, and in a region where the voltage between the collector electrode and the emitter electrode is high, the collector current Y2 is higher than the collector current Y1.

[0070] A value of the collector-emitter voltage at a time when the relationship between the collector current Y1 and the collector current Y2 is reversed can be determined as a limit between the high-voltage range and the low-voltage range.

[0071] Although the collector-emitter voltage state (polarity, high / low) changes during inverter operation to (positive, high), (positive, low), (negative, low), (negative, high), (negative, low), (positive, low), (positive, high), (positive, low), ... in that sequence, the operating mode (voltage mode) does not change before and after the collector-emitter voltage polarity reversal. Therefore, it is unnecessary to measure the voltage (meaning the voltage drops from 0 V) ​​at the time of a collector-emitter voltage polarity reversal.

[0072] Thus, according to the semiconductor device of the present preferred embodiment, it is not necessary to detect the voltage of 0 V, which is difficult to detect due to noise.

[0073] Therefore, it is possible to transport the current bidirectionally in the semiconductor device, while preventing the breakdown of the semiconductor device due to a false detection of the voltage of 0 V. <Die vierte bevorzugte Ausführungsform>

[0074] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Furthermore, in the following description, components identical to those shown in the preferred embodiments described above are represented by the same reference numerals, and their detailed description is omitted where appropriate. <Struktur einer Halbleitervorrichtung>

[0075] Fig. Figure 12 is a top view illustrating an exemplary structure of the semiconductor device according to the present preferred embodiment. As in the exemplary structure of Fig. As shown in Figure 12, the semiconductor device comprises an element area 12 and a termination area 14A surrounding the element area 12 in plan view.

[0076] Fig. Figure 13 is a cross-section that shows an exemplary structure of an AB cross-section over the element area 12 and the termination area 14A in the Fig. The structure shown in 12 represents the structure.

[0077] As in the exemplary structure of Fig. As shown in Figure 13, the element area 12 and the termination area 14A comprise the n-type column layer 22 and the plurality of p-type column layers 24.

[0078] Furthermore, element area 12 and termination area 14A comprise the n-type buffer layer 26. In addition, element area 12 contains the emitter-side n-type layer 28, which is arranged on the upper surface of the n-type column layer 22.

[0079] Furthermore, the element area 12 contains the collector layer 30 of p-type, which is located in the surface layer on the side of the lower surface of the buffer layer 26 of n-type, and the base layer 32 of p-type, which is located in the surface layer on the side of the upper surface of the emitter-side layer 28 of n-type.

[0080] The termination region 14A further comprises an n-type cathode layer 62 arranged in the surface layer on the side of the lower surface of the n-type base layer 26, and a plurality of p-type trough layers 64, each of which is arranged above the p-type column layer 24 in a surface layer on one side of an upper surface of the n-type column layer 22. Herein, the peak defect concentration of the n-type cathode layer 62 is, for example, not less than 1 × 10 18 cm -3 and not higher than 1×10 21 cm -3 .

[0081] Furthermore, element area 12 contains trench 50 and trench 52. Trench 50 contains insulating film 54 and collector-side gate electrode 58. Trench 52 contains insulating film 56 and emitter-side gate electrode 60.

[0082] Furthermore, element area 12 contains the collector-side layer 34 of n-type and the source layer 36 of n-type.

[0083] Furthermore, the element area 12 includes the interlayer film 38, the collector electrode 42, the interlayer film 40 and the emitter electrode 44.

[0084] The termination area 14A further comprises an interlayer film 66 arranged to cover part of the p-type trough layer 64, an interlayer film 68 arranged to cover part of the p-type trough layer 64 and the p-type column layer 24, an interlayer film 70 arranged to cover part of the p-type trough layer 64 and the n-type column layer 22, an electrode 72 arranged to cover part of the interlayer film 66, part of the interlayer film 68 and the exposed p-type trough layer 64, and an electrode 74 arranged to cover part of the interlayer film 68, part of the interlayer film 70 and the exposed p-type trough layer 64. In addition, part of the interlayer film 66 is covered with the emitter electrode 44.Furthermore, the collector electrode 42 is arranged such that it covers the n-type cathode layer 62.

[0085] Although the termination area 14A has an FLR (field-limiting ring) structure in Fig. 12 and Fig. As shown in Figure 13, the termination area 14A can have a RESURF structure (Reduced Surface Electric Field) or a VLD structure (Variation of Lateral Doping).

[0086] In termination region 14A, a pn diode is formed, consisting of the p-type layer (p-type pillar layer 24, p-type boat layer 64) on one side of a front surface of the n-type pillar layer 22 and the n-type cathode layer 62 on one side of a back surface of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, thus suppressing the breakdown of the semiconductor device. <Variante 1 >

[0087] Fig. Figure 14 is a cross-sectional view, which is a variant of the one shown in Fig. The structure shown in section 13 is represented.

[0088] As in the exemplary structure of Fig. As shown in Figure 14, the column layer 22 of n-type and the plurality of column layers 24 of p-type are arranged in an element area 12B and a termination area 14B.

[0089] Furthermore, the n-type buffer layer 26 is arranged in element area 12B and the termination area 14B. In addition, element area 12B contains the emitter-side layer 28 of n-type, which is arranged on the upper surface of the column layer 22 of n-type.

[0090] The element area 12B also contains a collector layer 30B of the p-type, which is arranged in a part of the surface layer on the side of the lower surface of the buffer layer 26 of the n-type, and the base layer 32 of the p-type, which is arranged in the surface layer on the side of the upper surface of the emitter-side layer 28 of the n-type.

[0091] Furthermore, the termination region 14B contains an n-type cathode layer 62B arranged in the surface layer on the side of the lower surface of the n-type buffer layer 26, and the plurality of p-type trough layers 64, each of which is arranged above the p-type column layer 24 in the surface layer on the side of the upper surface of the n-type column layer 22. The n-type cathode layer 62B is also arranged in a portion of the surface layer on the side of the lower surface of the n-type buffer layer 26 in element region 12B. The n-type cathode layer 62B arranged in element region 12B and the cathode layer 62B arranged in termination region 14B may be continuous or interrupted. In other words, the n-type cathode layer 62B located in element area 12B can be arranged discretely or individually in element area 12B.

[0092] In element area 12B, trench 50 and trench 52 are also arranged. The insulating film 54 and the collector-side gate electrode 58 are arranged in trench 50. The insulating film 56 and the emitter-side gate electrode 60 are arranged in trench 52.

[0093] Furthermore, in element area 12B, the collector-side layer 34 of n-type and the source layer 36 of n-type are arranged.

[0094] Furthermore, the interlayer film 38, the collector electrode 42, the interlayer film 40, and the emitter electrode 44 are arranged in element area 12B. The collector electrode 42 is also arranged such that it covers the p-type collector layer 30B and the n-type cathode layer 62B.

[0095] In the termination area 14B, the interlayer film 66, the interlayer film 68, the interlayer film 70, the electrode 72 and the electrode 74 are also arranged. Furthermore, part of the interlayer film 66 is covered by the emitter electrode 44.

[0096] In termination region 14B, a pn diode is formed, consisting of the p-type layer (p-type pillar layer 24, p-type boat layer 64) on the front surface of the n-type pillar layer 22 and the n-type cathode layer 62B on the back surface of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, thus suppressing the breakdown of the semiconductor device. <Variante 2>

[0097] Fig. 15 is a cross-sectional view, which is another variant of the in Fig. The structure shown in section 13 is represented.

[0098] As in the exemplary structure of Fig. As shown in Figure 15, the column layer 22 of n-type and the plurality of column layers 24 of p-type are arranged in an element area 12C and a termination area 14C.

[0099] Furthermore, the n-type buffer layer 26 is arranged in element area 12C and the termination area 14C. In addition, element area 12C contains the emitter-side layer 28 of n-type, which is arranged on the upper surface of the column layer 22 of n-type.

[0100] The element area 12C further contains the collector layer 30B of p-type arranged in a part of the surface layer on the side of the lower surface of the buffer layer 26 of n-type and the base layer 32 of p-type arranged in the surface layer on the side of the upper surface of the emitter-side layer 28 of n-type.

[0101] Furthermore, the termination region 14C contains an n-type cathode layer 62C arranged in the surface layer on the side of the lower surface of the n-type buffer layer 26, and a plurality of p-type trough layers 64, each of which is arranged above the p-type column layer 24 in the surface layer on the side of the upper surface of the n-type column layer 22. The n-type cathode layer 62C is also arranged in a portion of the surface layer on the side of the lower surface of the n-type buffer layer 26 in element region 12C. The n-type cathode layer 62C arranged in element region 12C and the n-type cathode layer 62C arranged in termination region 14C may be continuous or discontinuous. In other words, the n-type cathode layer 62C arranged in element region 12C may be arranged separately within element region 12C.Furthermore, at least one of the impurity concentrations and the depth of the n-type cathode layer 62C is the same as that of the n-type collector layer 34. Moreover, the same impurity concentration or the same depth encompasses at least the same value, differing by, for example, a few percent within a measurement error range.

[0102] Furthermore, trenches 50 and 52 are arranged in element area 12C. The insulating film 54 and the collector-side gate electrode 58 are arranged in trench 50. The insulating film 56 and the emitter-side gate electrode 60 are arranged in trench 52.

[0103] Furthermore, in element area 12C, the collector-side layer 34 is of n-type and the source layer 36 is of n-type.

[0104] In addition, the interlayer film 38, the collector electrode 42, the interlayer film 40 and the emitter electrode 44 are arranged in element area 12C.

[0105] In the termination area 14C, the interlayer film 66, the interlayer film 68, the interlayer film 70, the electrode 72 and the electrode 74 are also arranged. In addition, part of the interlayer film 66 is covered by the emitter electrode 44.

[0106] As a method for producing the in Fig. In the structure shown in Figure 15, the column layer 22 of n-type and the column layers 24 of p-type are initially arranged in element region 12C and the end region 14C. Here, the column layer 24 of p-type is arranged from the upper surface of the column layer 22 of n-type at a depth that extends into the interior of the column layer 22 of n-type. The column layer 22 of n-type and the column layers 24 of p-type are formed alternately in a direction that intersects a depth direction of the column layer 22 of n-type.

[0107] Next, in element region 12C, the emitter-side layer 28 of n-type is formed on the upper surface of the column layer 22 of n-type, and the base layer 32 of p-type is placed in the surface layer of the upper surface of the emitter-side layer 28 of n-type. Next, in element region 12C, the source layer 36 of n-type is placed in a portion of the surface layer of the upper surface of the base layer 32 of p-type.

[0108] In element area 12C, the trench 52, which extends from the upper surface of the p-type base layer 32 so that it reaches the emitter-side layer 28 of the n-type and further the interior of the n-type column layer 22, is arranged so that it comes into contact with the n-type source layer 36, and the emitter-side gate electrode 60, surrounded by the insulating film 56, is arranged inside the trench 52.

[0109] Next, in element area 12C, the interlayer film 40 is arranged so that it covers part of the n-type source layer 36 and the emitter-side gate electrode 60, and the emitter electrode 44 is arranged so that it covers the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.

[0110] On the other hand, in element area 12C and the termination area 14C, the n-type buffer layer 26 is arranged on the lower surface of the n-type column layer 22.

[0111] In element area 12C, the next step is to arrange the p-type collector layer 30B in a part of the surface layer of the lower surface of the n-type buffer layer 26.

[0112] In element area 12C, the n-type cathode layer 62C is next arranged in another part of the surface layer of the lower surface of the n-type buffer layer 26, and the n-type collector-side layer 34 is arranged in a part of the surface layer of the lower surface of the p-type collector layer 30B, and at the same time in the termination area 14C, the n-type cathode layer 62C is arranged in the surface layer of the lower surface of the n-type buffer layer 26.

[0113] In element area 12C, the collector-side gate electrode 58 is next arranged such that it comes into contact with the p-type collector layer 30B, which is sandwiched between the n-type buffer layer 26 and the n-type collector-side layer 34, with the insulating film 54 positioned between them, and such that it does not reach the n-type column layer 22. Fig.In element area 12C, the trench 50 extends from the lower surface of the p-type collector layer 30B in such a way that it reaches the interior of the n-type buffer layer 26 and does not reach the n-type column layer 22, and is arranged in such a way that it comes into contact with the n-type collector-side layer 34, and the collector-side electrode 58, surrounded by the insulating film 54, is arranged within the trench 50.

[0114] Next, in element region 12C, the interlayer film 38 is positioned so that it covers the collector-side gate electrode 58. In element region 12C and the termination region 14C, the collector electrode 42 is then positioned so that it covers the p-type collector layer 30B, the interlayer film 38, and the n-type cathode layer 62C.

[0115] In termination region 14C, a pn diode is formed by the p-type layer (p-type pillar layer 24, p-type boat layer 64) on the front surface of n-type pillar layer 22 and the n-type cathode layer 62C on the back surface of n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, thus suppressing the breakdown of the semiconductor device. <Durch die oben beschriebenen bevorzugten Ausführungsformen erzeugte Effekte>

[0116] Next, exemplary effects produced by the multitude of preferred embodiments described above are described. Furthermore, although the effects are described in the following description based on the specific configurations exemplified in the multitude of preferred embodiments described above, the configurations can be replaced by any other specific configuration exemplified in the description of the present application, provided that the same effects are produced. In other words, although there is sometimes a case where, for the sake of expediency, only one of the corresponding specific configurations is described representatively below, the representatively described specific configuration can be replaced by any other corresponding specific configuration.

[0117] Furthermore, this substitution can be made across the multitude of preferred embodiments. In other words, the respective configurations exemplified in the various preferred embodiments can be combined to produce the same effects.

[0118] According to the embodiments described above, the semiconductor device comprises the first pillar layer of the first conductivity type (n-type), the plurality of second pillar layers of the second conductivity type (p-type), the first impurity layer of n-type, the base layer of p-type, the trench 52, the first gate electrode, the source layer of n-type, the first interlayer film, the emitter electrode 44, the buffer layer of n-type, the collector layer of p-type, the second impurity layer, the second gate electrode, the second interlayer film, and the collector electrode 42. Here, the first pillar layer corresponds, for example, to pillar layer 22 of n-type or the like. Furthermore, the second pillar layer corresponds, for example, to pillar layer 24 of p-type or the like. The first impurity layer corresponds, for example, to the emitter-side layer 28 of n-type or the like.The base layer corresponds, for example, to p-type base layer 32 or the like. The first gate electrode corresponds, for example, to emitter-side gate electrode 60 or the like. The source layer corresponds, for example, to n-type source layer 36 or the like. The first interlayer film corresponds, for example, to interlayer film 40 or the like. The buffer layer corresponds, for example, to n-type buffer layer 26, n-type buffer layer 26A, or the like. The collector layer corresponds, for example, to p-type collector layer 30, p-type collector layer 30A, p-type collector layer 30B, or the like. The second impurity layer corresponds, for example, to n-type collector layer 34, n-type collector layer 34A, or the like.The second gate electrode corresponds, for example, to the collector-side gate electrode 58, the collector-side gate electrode 58A, or the like. The second interlayer film corresponds, for example, to the interlayer film 38, the interlayer film 38A, or the like. The p-type column layer 24 extends from the upper surface of the n-type column layer 22 to a depth reaching into the interior of the n-type column layer 22. The n-type emitter-side layer 28 is located on the upper surface of the n-type column layer 22. The p-type base layer 32 is located in the surface layer of the upper surface of the n-type emitter-side layer 28. The trench 52 is arranged such that it extends from the upper surface of the p-type base layer 32 to the n-type emitter-side layer 28 and further into the interior of the n-type column layer 22.The emitter-side gate electrode 60 is arranged within the trench 52, surrounded by the first insulating film. The first insulating film corresponds, for example, to the insulating film 56 or the like. The n-type source layer 36 is arranged in a portion of the surface layer of the upper surface of the p-type base layer 32, in contact with the insulating film 56. The intermediate film 40 is arranged to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60. The emitter electrode 44 is arranged to cover the p-type base layer 32, the n-type source layer 36, and the intermediate film 40. The n-type buffer layer 26 is arranged on the lower surface of the n-type column layer 22. The p-type collector layer 30 is arranged in the surface layer of the lower surface of the n-type buffer layer 26.The collector-side layer 34 of n-type is arranged in a portion of the surface layer of the lower surface of the collector layer 30 of p-type. The collector-side gate electrode 58 is arranged such that it is in contact with the collector layer 30 of p-type, which is sandwiched between the buffer layer 26 of n-type and the collector-side layer 34 of n-type, with the second insulating film positioned between them, and such that it does not reach the column layer 22 of n-type. The second insulating film corresponds, for example, to insulating film 54, insulating film 54A, or the like. The intermediate layer film 38 is arranged such that it covers the collector-side gate electrode 58. The collector electrode 42 is arranged such that it covers the collector layer 30 of p-type and the intermediate layer film 38.The column layer 22 of n-type and the column layers 24 of p-type are arranged alternately in a direction that crosses the depth direction of the column layer 22 of n-type.

[0119] According to this structure, it is possible to suppress the generation of a high surge voltage in the semiconductor device with a superjunction structure. Specifically, since the emitter-side layer 28 is n-type, hole injection from the p-type base layer 32 is reduced during the reverse conduction of the bipolar. Therefore, it is possible to reduce carrier accumulation on the emitter side. During the bipolar recovery, this promotes depletion from the emitter side. Depletion from the collector side is then suppressed, and thus it is possible to suppress the generation of a high surge voltage due to complete depletion.

[0120] If any other component element, illustrated by way of example in the description of the present application, is added to the one described above, in other words, if any other component element, not referred to as the structure described above and illustrated by way of example in the description of the present application, is added, the same effects can be produced.

[0121] Furthermore, according to the preferred embodiments described above, the semiconductor device includes the current detection unit and the control unit. In this context, the current detection unit corresponds, for example, to the current detection device 108 or the like. The control unit also corresponds, for example, to the current mode determiner 110 and the PWM control device 106 or the like. The current detection device 108 detects the collector current delivered via the collector electrode 42. The control unit controls the voltage to be applied to the emitter-side gate electrode 60 and the collector-side gate electrode 58 based on the polarity and current value of the collector current detected by the current detection device 108.According to such a configuration, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector current in order to suitably utilize either the bipolar operation or the unipolar operation of the semiconductor device, it is possible to suppress the generation of a high impulse voltage.

[0122] According to the preferred embodiments described above, if the collector current polarity is positive and the collector current value is higher than the predetermined threshold, the control unit sets the emitter-side gate electrode 60 to an ON state and sets the collector-side gate electrode 58 to an OFF state. Furthermore, if the collector current polarity is positive and the collector current value is lower than the predetermined threshold, the control unit sets the emitter-side gate electrode 60 to an ON state and sets the collector-side gate electrode 58 to an ON state. If the collector current polarity is negative and the collector current value is lower than the predetermined threshold, the control unit sets the emitter-side gate electrode 60 to an ON state and sets the collector-side gate electrode 58 to an ON state.If the collector current polarity is negative and the collector current value is higher than the predetermined threshold, the control unit switches the emitter-side gate electrode 60 to an OFF state and the collector-side gate electrode 58 to an ON state. According to this configuration, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector current, in order to suitably utilize either bipolar or unipolar operation of the semiconductor device, it is possible to suppress the generation of a high surge voltage.

[0123] According to the preferred embodiments described above, the semiconductor device further comprises the voltage detection unit and the control unit. The voltage detection unit corresponds, for example, to the voltage detection device 112 or the like. The control unit corresponds, for example, to the voltage mode determiner 114 and the PWM control device 106 or the like. The voltage detection device 112 detects the interelectrode voltage, which is a voltage applied between the collector electrode 42 and the emitter electrode. The control unit controls the voltage to be applied to the emitter-side gate electrode 60 and the collector-side gate electrode 58 based on the polarity and voltage value of the interelectrode voltage detected by the voltage detection device 112.According to such a configuration, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector-emitter voltage in order to suitably utilize either the bipolar operation or the unipolar operation of the semiconductor device, it is possible to suppress the generation of a high surge voltage.

[0124] According to the preferred embodiments described above, if the polarity of the interelectrode voltage is positive and the voltage value is higher than the predetermined threshold, the control unit sets the emitter-side gate electrode 60 to an ON state and sets the collector-side gate electrode 58 to an OFF state. Furthermore, if the polarity of the interelectrode voltage is positive and the voltage value is lower than the predetermined threshold, the control unit sets both the emitter-side gate electrode 60 and the collector-side gate electrode 58 to an ON state.If the polarity of the interelectrode voltage is negative and the voltage value is lower than the predetermined threshold, the control unit sets the emitter-side gate electrode 60 to an ON state and sets the collector-side gate electrode 58 to an ON state. If the polarity of the interelectrode voltage is negative and the voltage value is higher than the predetermined threshold, the control unit sets the emitter-side gate electrode 60 to an OFF state and sets the collector-side gate electrode 58 to an ON state.According to such a configuration, by switching the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 according to the detected collector-emitter voltage in order to suitably utilize either the bipolar operation or the unipolar operation of the semiconductor device, it is possible to suppress the generation of a high surge voltage.

[0125] According to the preferred embodiments described above, the semiconductor device further comprises the element area 12 (or element area 12B, element area 12C) and the termination area 14A (or termination area 14B, termination area 14C), which surrounds the element area 12 in plan view. In the element area 12 and the termination area 14A, the n-type column layer 22, the p-type column layers 24, and the n-type buffer layer 26 are arranged. In the termination area 14A, the semiconductor device includes the n-type cathode layer arranged in the surface layer of the lower surface of the n-type buffer layer 26. Furthermore, the cathode layer corresponds, for example, to the n-type cathode layer 62, the n-type cathode layer 62B, the n-type cathode layer 62C, or the like. In the termination area 14A, the collector electrode 42 is arranged so that it covers the n-type cathode layer 62.According to this structure, a pn diode is formed in termination region 14A, consisting of the p-type layer (p-type pillar layer 24, p-type boat layer 64) on the front surface of the n-type pillar layer 22 and the n-type cathode layer 62 on the back surface of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, thus suppressing the breakdown of the semiconductor device.

[0126] According to the preferred embodiments described above, the n-type cathode layer 62B (or the n-type cathode layer 62C) is further arranged in a portion of the surface layer of the lower surface of the n-type buffer layer 26 in element region 12B (or element region 12C). The p-type collector layer 30B is arranged in another portion of the surface layer of the lower surface of the n-type buffer layer 26. In element region 12B and the termination region 14B (or termination region 14C), the collector electrode 42 is arranged such that it covers the p-type collector layer 30B and the n-type cathode layer 62B (or the n-type cathode layer 62C).According to this structure, a pn diode is formed in termination region 14B, consisting of the p-type layer (p-type pillar layer 24, p-type boat layer 64) on the front surface of the n-type pillar layer 22 and the n-type cathode layer 62B on the back surface of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, thus suppressing the breakdown of the semiconductor device.

[0127] Furthermore, according to the preferred embodiments described above, since the n-type cathode layer 62C and the n-type collector-side layer 34 are formed in the same process, these layers exhibit the same impurity concentration or depth. According to such a structure, since the n-type collector-side layer 34 is formed in the elemental region 12C and the n-type cathode layer 62C is formed in the elemental region 12C and the termination region 14C in the same process, the number of steps in the manufacturing process is reduced compared to the case where these layers are formed separately in different processes.

[0128] According to the embodiments described above, in the method for manufacturing the semiconductor device, the semiconductor device comprises the element region 12C and the termination region 14C surrounding the element region 12C in plan view. Within the element region 12C and the termination region 14C, the n-type column layer 22 and the plurality of p-type column layers 24, which extend from the upper surface of the n-type column layer 22 to a depth reaching into the interior of the n-type column layer 22, are arranged alternately in a direction intersecting the depth direction of the n-type column layer 22. Within the element region 12C, the emitter-side layer 28 of n-type is arranged on the upper surface of the n-type column layer 22, and the p-type base layer 32 is arranged in the surface layer of the upper surface of the emitter-side layer 28 of n-type.In element region 12C, the n-type source layer 36 is positioned in a portion of the surface layer of the upper surface of the p-type base layer 32. In element region 12C, the trench 52, extending from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further into the interior of the n-type column layer 22, is positioned so that it comes into contact with the source layer 36, and the emitter-side gate electrode 60, surrounded by the insulating film 56, is positioned inside the trench 52. In element area 12C, the interlayer film 40 is arranged so that it covers part of the n-type source layer 36 and the emitter-side gate electrode 60, and the emitter electrode 44 is arranged so that it covers the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.In element area 12C and the termination area 14C, the n-type buffer layer 26 is arranged on the lower surface of the n-type column layer 22. In element area 12C, the p-type collector layer 30B is arranged in a portion of the surface layer of the lower surface of the buffer layer 26. In element area 12C, the n-type cathode layer 62C is arranged in another portion of the surface layer of the lower surface of the n-type buffer layer 26, and the collector-side layer 34, n-type, is arranged in a portion of the surface layer of the lower surface of the p-type collector layer 30B. Simultaneously, in termination area 14C, the n-type cathode layer 62C is arranged in the surface layer of the lower surface of the n-type buffer layer 26.In element region 12C, the collector-side gate electrode 58 is positioned so that it comes into contact with the p-type collector layer 30B, which is sandwiched between the n-type buffer layer 26 and the n-type collector-side layer 34, with the insulating film 54 (or insulating film 54A) positioned between them, and so that it does not reach the n-type column layer 22. In element region 12C, the intermediate film 38 is positioned so that it covers the collector-side gate electrode 58. In element region 12C and the termination region 14C, the collector electrode 42 is then positioned so that it covers the p-type collector layer 30B, the intermediate film 38, and the n-type cathode layer 62C.

[0129] According to such a structure, it is possible to suppress the generation of a high impulse voltage in the semiconductor device with a superjunction structure. Furthermore, since the collector-side layer 34 of n-type in the 12C element region and the cathode layer 62C of n-type in the 12C element region and the termination region 14C are formed in the same process, the number of steps in the manufacturing process is reduced compared to the case where these layers are formed separately in different processes.

[0130] Unless there are specific restrictions, the order in which the respective processes are carried out can also be changed.

[0131] If any other component element of the configuration described above, which is illustrated by way of example in the description of the present application, is added, in other words, even if any other component element not referred to as the configuration described above and which is illustrated by way of example in the description of the present application is added, the same effects can be achieved. <Varianten der oben beschriebenen bevorzugten Ausführungsformen>

[0132] In the multitude of preferred embodiments described above, the material quality, material, size, shape, relative arrangement relationship, implementation or design condition, or the like of each component element are described in some cases, but these are only examples in all aspects and not limiting.

[0133] Therefore, an indefinite number of modifications, variants, and equivalents, not illustrated by way of example, are assumed or presupposed within the scope of the technology disclosed in the description of this application. These modifications, variants, and equivalents include, for example, cases in which at least one component is deformed, added, or omitted, and furthermore, cases in which at least one component is extracted in at least one preferred embodiment and combined with a component in any other preferred embodiment.

[0134] If, in at least one of the preferred embodiments described above, a material name or the like is described without being particularly specified, the material includes the same containing any other additive, such as an alloy or the like, unless otherwise stated.

[0135] If each of the preferred embodiments described above describes that it contains "one" component element, it may contain "one or more" component elements, as long as there is no contradiction.

[0136] Furthermore, in the preferred embodiments described above, each component element is a conceptual unit and the scope of the technology disclosed in the description of the present application includes cases in which a component element is formed by a plurality of structural objects, in which a component element corresponds to a part of a structural object and in which, furthermore, a plurality of component elements are contained in a structural object.

[0137] Each component element in the preferred embodiments described above further comprises any structural object with any other structure or shape, as long as it can perform the same function.

[0138] Furthermore, the description in the description of the present application can be applied to all purposes relating to the present technology and is not recognized as prior art. EXPLANATION OF THE REFERENCE SYMBOLS

[0139] 12 Element area, 12B Element area, 12C Element area, 14 Termination area, 14A Termination area, 14B Termination area, 14C Termination area, 22 n-type column layer, 24 p-type column layer, 26 n-type buffer layer, 26A n-type buffer layer, 28 n-type emitter layer, 30 p-type collector layer, 30A p-type collector layer, 30B p-type collector layer, 32 p-type base layer, 34 n-type collector layer, 34A n-type collector layer, 36 n-type source layer, 38 Interlayer film, 38A Interlayer film, 40 Interlayer film, 42 Collector electrode, 44 Emitter electrode, 50 Trench, 52 Trench, 54 Insulating film 54A Insulating film, 56 Insulating film, 58 Collector-side gate electrode, 58A Collector-side gate electrode, 60 Emitter-side gate electrode, 62 n-type cathode layer, 62B n-type cathode layer, 62C n-type cathode layer, 64 p-type well layer, 66 Interlayer film, 68 Interlayer film,70 Intermediate film, 72 Electrode, 74 Electrode, 102 Collector-side gate driving device, 104 Emitter-side gate driving device, 106 PWM control device, 108 Current detection device, 110 Current mode determination device, 112 Voltage detection device, 114 Voltage mode determination device, X1 Collector current, X2 Collector current, Y1 Collector current, Y2 Collector current QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2002-26320

[0003]

Claims

[1] Semiconductor device comprising: a first column layer of a first conductivity type; a plurality of second column layers, each of a second conductivity type, arranged from an upper surface of the first column layer to a depth extending into the interior of the first column layer; a first defect layer of the first conductivity type, which is arranged on the upper surface of the first column layer; a base layer of the second conductivity type, which is arranged in a surface layer of an upper surface of the first defect layer; a trench which is arranged from an upper surface of the base layer in such a way that it reaches the first fault layer and further the interior of the first columnar layer; a first gate electrode located inside the trench, surrounded by a first insulating film; a source layer of the first conductivity type, which is arranged in part of a surface layer of the upper surface of the base layer, being in contact with the first insulating film; a first intermediate layer film arranged to cover part of the source layer and the first gate electrode; an emitter electrode arranged to cover the base layer, the source layer and the first intermediate film; a buffer layer of the first conductivity type, which is arranged on a lower surface of the first column layer; a collector layer of the second conductivity type, which is arranged in a surface layer of a lower surface of the buffer layer; a second defect layer of the first conductivity type, which is located in part of a surface layer of a lower surface of the collector layer; a second gate electrode arranged in such a way that it is in contact with the collector layer sandwiched between the buffer layer and the second impurity layer, with a second insulating film arranged between them, and in such a way that it does not reach the first column layer; a second intermediate film arranged to cover the second gate electrode; and a collector electrode arranged to cover the collector layer and the second intermediate layer film, wherein the first column layer and the second column layers are arranged alternately in a direction that crosses a depth direction of the first column layer. [2] Semiconductor device according to claim 1, further comprising: a current detection unit for detecting a collector current emitted via the collector electrode; and a control unit for controlling a voltage to be applied to the first gate electrode and the second gate electrode on the basis of a polarity and a current value of the collector current detected by means of the current detection unit. [3] Semiconductor device according to claim 2, wherein The control unit switches the first gate electrode to an ON state and the second gate electrode to an OFF state when the polarity of the collector current is positive and the value of the collector current is higher than a predetermined threshold. The control unit brings the first gate electrode into an ON state and brings the second gate electrode into an ON state when the polarity of the collector current is positive and the current value of the collector current is lower than the predetermined threshold. The control unit brings the first gate electrode into an ON state and brings the second gate electrode into an ON state when the polarity of the collector current is negative and the current value of the collector current is lower than the predetermined threshold, and The control unit switches the first gate electrode to an OFF state and the second gate electrode to an ON state when the polarity of the collector current is negative and the current value of the collector current is higher than the predetermined threshold. [4] Semiconductor device according to claim 1, further comprising: a voltage detection unit for detecting an interelectrode voltage, which is a voltage applied between the collector electrode and the emitter electrode; and a control unit for controlling a voltage to be applied to the first gate electrode and the second gate electrode on the basis of a polarity and a voltage value of the inter-electrode voltage detected by the voltage detection unit. [5] Semiconductor device according to claim 4, wherein The control unit switches the first gate electrode to an ON state and the second gate electrode to an OFF state when the polarity of the interelectrode voltage is positive and the voltage value of the interelectrode voltage is higher than a predetermined threshold. The control unit brings the first gate electrode into an ON state and brings the second gate electrode into an ON state when the polarity of the interelectrode voltage is positive and the voltage value of the interelectrode voltage is lower than the predetermined threshold. The control unit brings the first gate electrode into an ON state and brings the second gate electrode into an ON state when the polarity of the interelectrode voltage is negative and the voltage value of the interelectrode voltage is lower than the predetermined threshold, and The control unit switches the first gate electrode to an OFF state and the second gate electrode to an ON state when the polarity of the inter-electrode voltage is negative and the voltage value of the inter-electrode voltage is higher than the predetermined threshold. [6] Semiconductor device according to any one of claims 1 to 5, comprising: an element area and a finishing area surrounding the element area in plan view, wherein the first column layer, the second column layer and the buffer layer are arranged in the element area and the termination area, the semiconductor device further comprises: a cathode layer of the first conductivity type, which is arranged in the surface layer of the lower surface of the buffer layer in the termination region, wherein the collector electrode is arranged such that it covers the cathode layer in the termination region. [7] Semiconductor device according to claim 6, wherein the cathode layer is located in a part of the surface layer of the lower surface of the buffer layer in the element area, the collector layer is located in another part of the surface layer of the lower surface of the buffer layer and The collector electrode is arranged so that it covers the collector layer and the cathode layer in the element area and the termination area. [8] Semiconductor device according to claim 6 or 7, wherein the cathode layer and the second impurity layer are formed in the same process. [9] Semiconductor device according to claim 8, wherein at least one of the impurity concentrations and depths of the cathode layer is the same as that of the second impurity layer. [10] Method for manufacturing a semiconductor device comprising an element region and a termination region surrounding the element region in plan view, comprising: Arranging a first column layer of a first conductivity type and a plurality of second column layers, each of a second conductivity type, arranged from an upper surface of the first column layer to a depth extending into the interior of the first column layer, alternating in a direction intersecting a depth direction of the first column layer in the element area and the termination area; Arranging a first defect layer of the first conductivity type on the upper surface of the first column layer and a base layer of the second conductivity type in a surface layer of an upper surface of the first defect layer in the element area; Arranging a source layer of the first conductivity type in a part of a surface layer of an upper surface of the base layer in the element area; Arranging a trench extending from the upper surface of the base layer to reach the first defect layer and further the interior of the first column layer to come into contact with the source layer in the element region, and arranging a first gate electrode surrounded within the trench by a first insulating film; Arranging a first interlayer film so that it covers part of the source layer and the first gate electrode in the element region, and arranging an emitter electrode so that it covers the base layer, the source layer and the first interlayer film; Arranging a buffer layer of the first conductivity type on a lower surface of the first column layer in the element area and the termination area; Arranging a collector layer of the second conductivity type in a part of a surface layer of a lower surface of the buffer layer in the element area; Arranging a cathode layer of the first conductivity type in another part of the surface layer of the lower surface of the buffer layer in the element region and arranging a second defect layer of the first conductivity type in a part of a surface layer of a lower surface of the collector layer in the element region and simultaneously arranging the cathode layer in the surface layer of the lower surface of the buffer layer in the termination region; Arranging a second gate electrode so that it is aligned with the one formed by the buffer layer and the second defect layer comes into contact with the sandwich-like surrounded collector layer, with a second insulating film arranged between them, and does not reach the first column layer in the element area; Arranging a second interlayer film so that it covers the second gate electrode in the element region; and Arrange a collector electrode so that it covers the collector layer, the second interlayer film and the cathode layer in the element area and the termination area.

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