SUBSTRATES WITH A GLASS CORE AND GLASS LAYERS

Abstract

Substrates with a glass core and glass superstructure layers, as well as methods for their formation, are described here. In one example, a substrate includes a glass core, glass layers above and below the glass core, conductive traces in the glass core and in at least some of the glass layers, and conductive contacts on a surface of the substrate.

Description

[0001] This application claims priority over US patent application no. 18 / 194,550, filed on March 31, 2023, entitled “SUBSTRATES WITH A GLASS CORE AND GLASS BUILDUP LAYERS”, which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] The demand for miniaturized computing device form factors and increasing integration to achieve high performance is driving the development of sophisticated package approaches in the semiconductor industry. Minimizing electrical input / output (I / O) interconnects is one of the most important drivers for improved performance. However, for microbump-based interconnects, reducing the bump pitch beyond 10 micrometers (µm) presents a significant technical challenge. Consequently, other interconnect technologies with better scalability have gained importance, such as hybrid bonding, a combination of dielectric bonding and direct copper-to-copper bonding. Hybrid bonding is used for silicon-to-silicon bonding, for example, to connect multiple silicon chips, wafers, and so on.However, interconnects between silicon chips and package substrates are still mainly implemented using microbumps. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a glass package substrate for hybrid-bonded silicon chips. Fig. Figures 2A-J illustrate a process flow for forming a glass package substrate for hybrid-bonded silicon chips. Fig. Figure 3 illustrates a package with an embedded chip in a glass substrate. Fig. Figures 4A-I illustrate a process flow for forming a package with an embedded chip in a glass substrate. Fig. Figure 5 illustrates a package for embedded chips in a glass substrate with silicon vias. Fig. Figures 6A-I illustrate a process flow for forming a package with an embedded chip in a glass substrate using silicon vias. Fig. Figures 7A-C illustrate various embodiments of glass substrates and housings with microbumps. Fig. Figure 8 illustrates a flowchart for the formation of a package for an integrated circuit (IC) on a substrate with a glass core and glass buildup layers. Fig. Figure 9 is a top view of a wafer and chips that may be enclosed in a microelectronic assembly. Fig. Figure 10 is a cross-sectional side view of an integrated circuit device that can be enclosed in a microelectronic assembly. Fig. Figure 11 is a cross-sectional side view of an integrated circuit device that may include a microelectronic assembly. Fig. Figure 12 is a block diagram of an exemplary electrical device that may include a microelectronic assembly. DETAILED DESCRIPTION

[0003] Competition in high-performance computing has intensified over the past decade. The demand for miniaturized form factors of computing devices and increasing integration to achieve high performance is driving the development of sophisticated package approaches in the semiconductor industry.

[0004] Minimizing electrical input / output (I / O) interconnects is a major driver of improved performance. However, reducing the bump pitch below 10 micrometers (µm) for microbump-based interconnects presents a significant technical challenge. Consequently, other interconnect technologies are gaining ground. For example, direct copper-to-copper bonding (e.g., without solder) is a promising alternative to microbumps for reducing the bump pitch below 10 µm. Another promising alternative is hybrid bonding, a combination of dielectric bonding and copper-to-copper bonding.

[0005] Current hybrid bonding technology is limited to silicon-to-silicon bonding, such as wafer-to-wafer, chip-to-wafer, chip-to-chip / chip stack, etc. However, package substrates are typically made of materials other than silicon. Therefore, interconnects between silicon chips and (non-silicon) package substrates are still primarily implemented using microbumps.

[0006] Package substrates are typically made from organic materials or a combination of glass and organic materials. Organic substrates generally include an organic core with multiple organic build-up layers, and glass substrates typically include a glass core with multiple organic build-up layers. For both types of substrates, the organic build-up layers are usually formed using an organic film such as Ajinomoto Build-up Film (ABF) and polyimide (PI). However, organic materials have a high coefficient of thermal expansion (CTE), causing them to expand significantly at high temperatures. Therefore, these substrates are unsuitable for hybrid bonding because the organic materials within them expand, creating stresses in the package and potentially leading to defects.

[0007] Accordingly, this disclosure presents embodiments of all-glass (or predominantly glass) substrates suitable for both microbump bonding and hybrid chip substrate bonding (e.g., copper-copper dielectric bonding). Current glass-based substrates use only glass in the substrate core, while the buildup layers are formed from organic materials (e.g., ABF, PI), making them poor candidates for hybrid bonding. However, the glass substrates in this disclosure include a glass core and glass buildup layers, thereby fully exploiting the electrical and mechanical advantages of glass.

[0008] These glass substrates can be formed by starting with a glass core and replacing the conventional organic buildup layers with glass layers, e.g. by forming silicon oxide layers on the glass core using chemical vapor deposition (CVD), physical vapor deposition (PVD) or other similar processes.

[0009] Processes that are normally only applied to the glass core - such as the formation of vias (TGV) using laser-based etching techniques (e.g., laser-induced selective etching (LISE)) and conductive seeding and plating (e.g., titanium / copper seeding with copper plating) - can also be applied to the glass buildup layers to form the electrical interconnects.

[0010] The rear end of the substrate can feature microbumps for traditional chip attachment via thermal compression bonding and mass reflow, or alternatively, it can feature recessed Cu bumps within the glass layers (e.g., silicon oxidation) for direct hybrid bonding with silicon chips.

[0011] These glass substrates offer several advantages. For example, organic build-up layers are replaced by glass layers that can be precisely adapted to the glass core. This provides greater flexibility in substrate design, which was previously limited by manufacturing capabilities.

[0012] This all-glass substrate utilizes the mechanical and electrical advantages of glass more effectively than conventional glass-based substrates that only use glass in the core. The resulting glass substrate exhibits, for example, improved electrical and mechanical properties such as lower dielectric loss, higher bandwidth, lower CTE, reduced warpage, etc.

[0013] Furthermore, this all-glass design can be used for both microbump bonding and hybrid bonding. In particular, this design enables a hybrid connection between the chip and the substrate for communication with lower latency and higher bandwidth. For example, the mechanical properties of the glass layers can be tuned to match those of silicon for hybrid bonding. Direct copper-to-copper bonding between a monolithic chip or chip stack and a substrate offers significant performance advantages. Moreover, this all-glass substrate can be fabricated and hybrid-bonded to silicon chips at the panel or wafer level.

[0014] Fig. Figure 1 illustrates a glass package substrate 100 for hybrid-bonded silicon chips. In some embodiments, the glass substrate 100 can, for example, be used in an integrated circuit package in which one or more integrated circuit chips are hybrid-bonded to the glass substrate 100.

[0015] The glass substrate 100 encloses a glass core 102 with glass superstructure layers 104 above and below the core. In various embodiments, the glass core 102 can be a glass substrate consisting of any suitable (e.g., amorphous) glass material, including, without limitation, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica), fused silica, alkali glass, non-alkali glass, borosilicate glass, floated borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, quartz, and / or any other type of glass.

[0016] The glass core 102 can thus consist in various embodiments of materials that include elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g. with or without dopants such as boron, phosphorus, titanium and / or zinc), calcium carbonate (CaCO3) and sodium carbonate (Na2CO3).

[0017] The glass structure layers 104 can be dielectric layers made of any suitable glass materials, including, but not limited to, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica, quartz glass), spin-on glass (e.g., glass materials such as silicon dioxide (SiO2) with dopants such as boron, phosphorus, titanium, and / or zinc), and so on. Thus, in some embodiments, the glass structure layers 104 can consist of materials incorporating elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layers 104 (e.g.,the CTE) are adjusted to match those of silicon for hybrid bonding with silicon chips.

[0018] The housing substrate 100 also includes conductive traces 106 incorporated into the glass core 102 and the glass buildup layers 104, including vias in the glass core 102 and the glass layers 104, as well as horizontal traces in the glass layers 104. In some embodiments, the conductive traces may be made of metal 106 (e.g., copper and / or titanium).

[0019] The conductive traces 106 electrically couple the recessed pads 108 on the top surface of the housing substrate 100 to the bumps 110 on the underside of the substrate. The recessed pads 108 and the bumps 110 are conductive contacts used to electrically couple other components to the housing substrate 100. The recessed pads 108 can be copper pads slightly recessed beneath the dielectric glass layers 104, and the bumps 110 can be solder balls, bumps, or microbumps. The housing substrate 100 also includes a solder mask layer 109 on the underside of the substrate where the bumps 110 are located.

[0020] In some embodiments, for example, one or more integrated circuit chips (not shown) can be coupled to the top surface of the housing substrate 100 and hybrid-connected to the recessed pads 108 (e.g., via a combination of dielectric and copper-to-copper bonding). Furthermore, the housing substrate 100 can be coupled to a printed circuit board (e.g., a mainboard, motherboard, etc.) or another integrated circuit package (not shown) via the protrusions 110 on the underside of the housing substrate 100.

[0021] Fig. 2A-J illustrate a process flow for forming the glass housing substrate 100 from Fig. 1. The described process flow can be used in particular for the production of glass substrates for hybrid-bonded silicon chips at the panel or wafer level (e.g., substrate-chip hybrid bonding). However, this process flow is only one example of a method for producing such substrates.

[0022] In Fig. 2A An amorphous glass plate (or wafer) of a suitable thickness is used as the substrate core 102. In some embodiments, the glass plate can have a thickness of 100 micrometers (µm) to 1000 µm or 1 millimeter (mm). Depending on the process requirements, a variety of glass compositions can be used, including, but not limited to, alkali glass, non-alkali glass, borosilicate glass, floated borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, and / or quartz.

[0023] In Fig. 2B, through-holes 103 are formed in the glass core 102. In some embodiments, the through-holes 103 are formed using laser-based methods, such as laser-induced selective etching (LISE). LISE is a two-stage process in which the glass is locally modified with an ultrafast laser pulse, and the modified areas are then etched away using wet chemical etching methods (e.g., an etching bath containing hydrogen fluoride (HF), potassium hydroxide (KOH), or sodium hydroxide (NaOH)). The laser-treated area exhibits a significantly faster etch rate compared to the untreated area, enabling the formation of through-holes 103 with a high aspect ratio.

[0024] In Fig. In step 2C, metallization and coating are performed to form electrically conductive paths 106 through and above / below the core 102. For example, titanium and copper can be deposited on the surfaces of the core 102 and the through-holes 103 to form nucleation layers, and copper can be deposited on the nucleation layers to form glass through-holes (TGVs) 106 in the core 102 (e.g., by filling the through-holes 103) and conductive layers 106 above and below the core 102. The surface of the conductive layers on the core 102 can be planarized using polishing processes (e.g., grinding, chemical-mechanical planarization (CMP)).

[0025] In Fig. In 2D, the conductive layers on the top and bottom surfaces of the core 102 are structured into conductive traces 106 by etching away the unwanted metal. In some embodiments, conventional lithographic methods can be used to etch away the unwanted metal, e.g., lamination with dry film resist (DFR), photoexposure, photoresist development, and copper etching.

[0026] In Fig. 2E glass buildup layers 104 are formed above and below the core 102. Instead of laminating organic buildup layers onto the core (e.g. using ABF film), glass layers 104 of a suitable thickness (e.g. 10-50 µm) are formed above and below the core 102 by applying a material suitable for glass formation.

[0027] In some embodiments, the glass layers 104 can be silicon oxide layers formed by depositing a silicon oxide (SiOx), such as silicon dioxide (SiO2) (also known as silica), onto the core 102 by chemical vapor deposition (CVD) or physical vapor deposition (PVD), which solidifies to form glass. Various dopants and concentrations can be carefully selected to modify the silicon oxide formers and modifiers and to achieve the desired electrical and mechanical properties of the resulting glass layers 104.

[0028] Subsequently, the surfaces of the glass layers 104 can be smoothed using polishing processes (e.g. grinding, chemical-mechanical planarization (CMP)).

[0029] In Fig. 2F through-holes 105 are formed in the glass layers 104. Instead of, for example, forming conventional through-holes in organic buildup layers (e.g., ABF) by laser drilling, the through-holes 105 are formed in the glass buildup layers 104. Therefore, the through-holes 105 in the glass layers 104 can be formed using the same LISE process as the through-holes 103 in the glass core 102. Fig. 2B, which means that the same equipment can be used.

[0030] In Fig. 2G will have a second set of vias / conductive layers 106 on the glass layers 104 above and below the core 102 using similar metallization and surface planarization techniques as the first set of vias / conductive layers in Fig. 2C formed.

[0031] Similarly, in Fig. 2H the conductive layers 106 on the top and bottom using the same etching techniques as in Fig. 2D to conductor tracks 106 structured.

[0032] In Fig. 2I the steps from Fig. 2E-H is repeated to form another set of glass buildup layers 104 and conductive buildup layers 106 on the top and bottom surfaces. These steps can be repeated until the appropriate number of glassy / conductive buildup layers for the specific substrate has been formed.

[0033] In Fig. 2J a further glass layer 104 is formed on the underside and planarized (e.g. flush with the layer of conductor tracks 106), a solder mask layer 109 is formed on the glass layer 104, and solder bumps or microbumps 110 are formed on the conductor tracks 106 to create the interconnect of the second layer.

[0034] Another glass layer 104 is also formed on the top surface—slightly raised above the conductor layer 106—and then planarized (e.g., with CMP) to form an extremely flat dielectric glass surface 104, with the copper pads 108 slightly recessed below the surface 104 (e.g., by 5–20 nm). The recessed copper pads 108 form the first-level interconnect for hybrid bonding with one or more silicon chips (not shown). In some embodiments, the hybrid bonding can be performed at the plate level between a plate of glass substrates 100 and the silicon chip(s). As mentioned previously, the properties of the dielectric glass layers 104, such as the CTE, can be fine-tuned to closely match those of silicon by adding silicon formers, exchangers, and / or modifiers.This allows the glass substrate 100 to be hybridly connected to the silicon chips without causing stress or damage to the substrate 100.

[0035] The illustrated example describes the process flow at a high level. Certain steps are omitted for the sake of simplicity and / or may differ from those described herein without exceeding the scope of the described embodiments. For the sake of simplicity, only a limited number of glass-like / conductive build-up layers 104, 106 in the substrate 100 are shown. In specific embodiments, the number of build-up layers can be up to 20 layers or more. Furthermore, the number of build-up layers above and below the core need not necessarily be the same.

[0036] Compared to substrates with a glass core and organic build-up layers, the all-glass (or predominantly glass) substrates described here offer numerous advantages. For example, the described embodiments support hybrid bonding between a glass substrate and a silicon chip, enabling higher interconnect density and a shorter interconnect distance between the substrate and the chip compared to microbump interconnects. Since the materials used for the glass build-up layers can be very similar to those of the glass core, these glass substrates also offer various mechanical and structural advantages, such as reduced warpage, which increases yield. The described embodiments also require fewer tooling components for fabrication, resulting in significant cost savings.

[0037] Fig. Figure 3 shows a package 300 with an embedded chip in a glass substrate 301. The package 300 with embedded chips is a package for integrated circuits with silicon chips 312 embedded in the glass substrate 301.

[0038] In the illustrated embodiment, the glass substrate 301 includes a glass core 302, which may be a glass substrate made of any suitable (e.g., amorphous) glass material, including, without limitation, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica), fused silica, alkali glass, non-alkali glass, borosilicate glass, floated borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, quartz, and / or any other type of glass. The glass core 302 can thus consist in various embodiments of materials that include elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g. with or without dopants such as boron, phosphorus, titanium and / or zinc), calcium carbonate (CaCO3) and sodium carbonate (Na2CO3).

[0039] Furthermore, the glass core 302 encloses several cavities 307 with embedded silicon chips 312, which are attached to the bottom of the respective cavities 307 by means of die attach film (DAF) 311.

[0040] The glass substrate 301 also includes glass buildup layers 304 above and below the glass core 302. The glass buildup layers 304 can be dielectric layers made of any suitable glass materials, including, but not limited to, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica, quartz glass), spin-on glass (e.g., glass materials such as silicon dioxide (SiO2) with dopants such as boron, phosphorus, titanium, and / or zinc), and so on. Thus, in some embodiments, the glass buildup layers 304 can consist of materials that include elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).Furthermore, in some embodiments the properties of the glass layers 304, such as the CTE, can be adjusted to correspond to those of silicon (e.g. for hybrid bonding with silicon chips).

[0041] The substrate 301 also includes conductive traces 306 incorporated into the glass core 302 and the glass buildup layers 304, including vias in the glass core 302 and in the glass layers 304, as well as horizontal conductive traces in the glass layers 304. In some embodiments, the conductive traces 306 may be made of metal (e.g., copper and / or titanium).

[0042] The conductive traces 306 electrically couple the embedded chips 312, the recessed pads 308 on the top surface of the substrate 301, and the bumps 310 on the bottom surface of the substrate 301. The recessed pads 308 and the bumps 310 are conductive contacts that serve to electrically couple other components to the substrate 301. The recessed pads 308 can be copper pads slightly recessed beneath the dielectric glass layers 304, and the bumps 310 can be solder balls, bumps, or microbumps. The substrate 301 also includes a layer of solder mask 309 on the bottom surface where the bumps 310 are located.

[0043] In some embodiments, for example, one or more additional silicon chips (not shown) on the top surface of the substrate 301 can be hybrid-connected to the recessed pads 308 (e.g., via a combination of dielectric and copper-copper bonding). Furthermore, the substrate 301 can be coupled to a printed circuit board (e.g., a mainboard, motherboard, etc.) or another package for integrated circuits (not shown) via the bumps 310 on the underside of the substrate 301.

[0044] For simplicity, the embedded chips 312 are shown only on the top side of the core 302. In other embodiments, however, passive components (e.g., conductor tracks 306) and active silicon chips 312 can be embedded on both sides of the core 302 or in the glass buildup layers 304 (e.g., using embedded multi-chip interconnects / bridges), or both across the core 302 and across the glass buildup layers 304.

[0045] Fig. 4A-I show a process flow for forming the package with embedded chip 300 of Fig. 3. The described process flow is used in particular to embed active chips and passive components (e.g., conductor tracks / bridges / interconnects) in a glass substrate. However, this process flow is only one example of a method for manufacturing such packages.

[0046] In Fig. 4A A glass plate (or wafer) of a suitable thickness is used as the substrate core 302 (e.g. similar to that in Fig. 2A).

[0047] In Fig. 4B cavities 307 for silicon chips are formed in the core 302 (e.g. using LISE methods).

[0048] In Fig. In step 4C, silicon chips 312 are attached to the bottom of the cavities 307 using die-attach films (DAF) 311 with precise alignment and tilt control. The chips 312 enclose pads 314 on their upper surface for interconnects to other components.

[0049] In Fig. In 4D, a glass layer 304 is formed by silicon oxidation to fill the gaps above the chips 312, and the glass layer 304 is planarized (e.g. by grinding and / or CMP).

[0050] In Fig. 4E through holes 303 are formed in the glass core 302 and through holes 305 are formed in the glass layer 304 to the pads 314 on the silicon chip 312 (e.g. using LISE methods).

[0051] In Fig. In step 4F, metal seeding and coating are performed to form conductive paths 306 through the core 302, to the silicon chips 312, and above and below the core 302 (e.g., on the glass layer 304). For example, through-holes (TGVs) 306 are formed in the core 302 by filling the through-holes 303 with metal, through-holes 306 are formed in the glass layer 304 by filling the through-holes 305 with metal, and conductive layers 306 are formed above / below the core 302 by depositing metal below the core 302 and above the core 302 on the glass layer 304.

[0052] The remaining steps in Fig. 4G, Fig. 4H and Fig. 4I are similar to those in Fig. 2H, Fig. 2I or 2J.

[0053] Fig. Figure 5 illustrates a package 500 for embedded chips in a glass substrate with silicon vias. The package 500 with embedded chips is, for example, a package for integrated circuits in a glass substrate 501 with embedded silicon chips 512, which have silicon vias (TSVs) 513.

[0054] In the illustrated embodiment, the glass substrate 501 encloses a glass core 502, which may be a glass substrate made of any suitable (e.g., amorphous) glass material, including, without limitation, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica), fused silica, alkali glass, non-alkali glass, borosilicate glass, floated borosilicate glass (e.g., BOROFLOAT®), alkali borosilicate glass, quartz, and / or any other type of glass. The glass core 502 can be composed of materials in various embodiments that include elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g. with or without dopants such as boron, phosphorus, titanium and / or zinc), calcium carbonate (CaCO3) and sodium carbonate (Na2CO3).

[0055] Furthermore, the glass core 502 encloses several cavities 507 containing embedded silicon chips 512, which are attached to the bottom of the respective cavities 507 by means of die-attach film (DAF) 511. The embedded silicon chips 512 enclose silicon vias (TSV) 513 to electrically couple the chips 512 to conductive traces 506 above and below the chips 512 in the substrate 501.

[0056] The glass substrate 501 also includes glass buildup layers 504 above and below the glass core 502. The glass buildup layers 504 can be dielectric layers made of any suitable glass materials, including, but not limited to, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica, quartz glass), spin-on glass (e.g., glass materials such as silicon dioxide (SiO2) with dopants such as boron, phosphorus, titanium, and / or zinc), and so on. Thus, in some embodiments, the glass buildup layers 504 can consist of materials that include elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).Furthermore, in some embodiments the properties of the glass layers 504, such as the CTE, can be adjusted to correspond to those of silicon (e.g. for hybrid bonding with silicon chips).

[0057] The substrate 501 also includes conductive traces 506 incorporated into the glass core 502 and the glass buildup layers 504, including vias in the glass core 502 and in the glass layers 504, as well as horizontal conductive traces in the glass layers 504. In some embodiments, the conductive traces 506 may be made of metal (e.g., copper and / or titanium).

[0058] The conductive traces 506 electrically couple the embedded chips 512, the recessed pads 508 on the top surface of the substrate 501, and the bumps 510 on the bottom surface of the substrate 501. The recessed pads 508 and the bumps 510 are conductive contacts that serve to electrically couple other components to the substrate 501. The recessed pads 508 can be copper pads slightly recessed beneath the dielectric glass layers 504, and the bumps 510 can be solder balls, bumps, or microbumps. The substrate 501 also includes a layer of solder mask 509 on the underside of the substrate where the bumps 510 are located.

[0059] In some embodiments, for example, one or more additional silicon chips (not shown) on the top side of the substrate 501 can be hybrid-connected to the recessed pads 508 (e.g., via a combination of dielectric and copper-copper bonding). Furthermore, the substrate 501 can be coupled to a printed circuit board (e.g., a mainboard, motherboard, etc.) or another package for integrated circuits (not shown) via the bumps 510 on the underside of the substrate 501.

[0060] For simplicity, the embedded chips 512 are shown only on the top side of the core 502. In other embodiments, however, passive components (e.g., conductor tracks 506) and active silicon chips 512 can be embedded on both sides of the core 502 or in the glass build-up layers 504 (e.g., using embedded multi-chip interconnects / bridges), or both across the core 502 and across the glass build-up layers 504.

[0061] Fig. 6A-I show a process flow for forming the package with embedded chip 500 of Fig. 5. This process flow is just one example of a methodology for manufacturing such housings.

[0062] The in Fig. The process flow shown in 6A-I for the 500 housing with embedded chip is similar to the one in Fig. 4A-I for housing 300 with embedded chip, except as specified below.

[0063] In Fig. 6C enclose the chips 512 mounted in the cavities 507 silicon vias (TSV) 513 which are connected to pads 514 on the top and bottom of the chips 512.

[0064] In Fig. 6E through-holes 505 are formed in the glass core 502 to the chip pads 514 on the underside of the embedded chips 512 (e.g., in addition to the through-holes 505 in the glass layer 504 to the chip pads 514 on the top side of the chips 512 and the through-holes 503 in the glass core 502). Furthermore, the chip mounting film 511 on the lower chip pads 514 is removed (e.g., with lasers) to establish an electrical connection between the lower chip pads 514 and the subsequently formed vias.

[0065] Fig. Figures 7A-C illustrate various embodiments of glass substrates and housings with microbumps. In particular, they show Fig. 7A, Fig. 7B and Fig. 7C the embodiments of Fig. 1, Fig. 3, Fig. 5, where the first-level interconnect on the top surface is formed by microbumps rather than recessed pads for hybrid bonding. This allows one or more silicon chips (or other packages for integrated circuits / components) to be attached to the microbumps on the top surface.

[0066] For example, it illustrates Fig. 7A a glass housing substrate 100' with microbumps 108' on the top side, Fig. 7B illustrates a glass package with embedded chips 300' with microbumps 308' on the top, and Fig. Figure 7C illustrates a glass package with embedded chips 500' with silicon vias 513 in the embedded chips 512 and microbumps 508' on the top side.

[0067] The embodiments in Fig. 7A, Fig. 7B and Fig. 7C can be produced using similar processes as those described in Fig. 2A-J, 4A-I, and 6A-I are described. However, in the final stage of the process, solder mask and bumps are applied to both sides of the glass substrates, not just the underside. Conventional bumping technologies can be used to form the bumps for the first-level interconnect (top) and the second-level interconnect (bottom). In this way, conventional bump / microbump bonding is applied to all-glass substrates—rather than organic or pure glass core substrates—to fully exploit the electrical and mechanical advantages of glass.

[0068] In the embodiments shown and described in this disclosure (e.g. substrates / housings 100, 100', 300, 300', 500, 500'), other types of conductive pads may be used instead of or in addition to those shown, including, without limitation, metal pads (e.g. recessed or non-recessed copper pads), metal bumps / microbumps (e.g. C2 / C4 copper bumps), solder balls / bumps and solder paste, among other examples.

[0069] Furthermore, the glass substrates described here can be "all-glass" or "predominantly glass" substrates in various embodiments, meaning that the core is made of glass and all or some of the dielectric buildup layers are made of glass. In some embodiments, for example, the glass core can be made of solid glass (and may be equipped with various integrated circuits) rather than glass fabric or material. Furthermore, in some embodiments, all dielectric buildup layers can be glass layers, while in other embodiments, a combination of glass buildup layers and non-glass buildup layers may be present, with the non-glass buildup layers being made of other dielectric materials, such as organic materials (e.g., ABF, solder mask).Furthermore, the glass core and / or the glass / dielectric layers can be structured with various features, including but not limited to vias / conductor tracks, conductive contact surfaces (e.g. pads, bumps), recesses, cavities, embedded silicon chips, and so on.

[0070] Furthermore, the described glass substrates can be used as substrate materials for any type of electronic device, including integrated circuit enclosures, printed circuit boards (e.g. printed circuit boards), and so on.

[0071] Fig. Figure 8 illustrates a flowchart 800 for forming a package for an integrated circuit (IC) on a substrate with a glass core and glass buildup layers. In light of this revelation, it becomes clear that flowchart 800 is only one example of a method for obtaining an IC package on a substrate with a glass core and glass buildup layers.

[0072] The steps of Flowchart 800 can be performed using any suitable semiconductor fabrication process. For example, patterning and removal—such as interconnect patterning, via orifice formation, and shaping—can be performed using any suitable technique, such as lithographic patterning / masking and / or etching. Furthermore, layer deposition, layer infill (e.g., removed sections), and via orifice filling can be performed using any suitable deposition technique, including electroless deposition, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or physical vapor deposition (PVD).

[0073] The flowchart begins in block 802 with the receipt of a glass plate (or wafer) used as the core of a substrate for the IC package. The glass core can be made of any type of glass. Thus, in various embodiments, the glass core can consist of materials including elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0074] The flowchart then proceeds to block 804 to form traces within the glass core and above / below the glass core. For example, through-holes can be created in the glass core and filled with a conductive material (e.g., metal) to form through-holes across the glass core. Furthermore, conductive layers can be formed above and below the core and etched into a suitable pattern of conductive traces. In some embodiments, the conductive material used to form the conductive traces can include a metal such as copper, titanium, tin, silver, gold, nickel, aluminum, tungsten, and / or alloys thereof.

[0075] The flowchart then continues with block 806 to form glass layers above and below the glass core. Furthermore, in some embodiments, the properties of the glass layers, such as the CTE, can be matched to those of the glass core and / or the silicon (e.g., for hybrid bonding with silicon chips).

[0076] The glass structure layers can be dielectric layers made of any suitable glass materials, including, but not limited to, silicon oxides (SiOx) (e.g., silicon dioxide (SiO2), also known as silica, quartz glass), spin-on glass (e.g., glass materials such as silicon dioxide (SiO2) with dopants such as boron, phosphorus, titanium, and / or zinc), and so on. Thus, the glass core in various embodiments can consist of materials incorporating elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including, without limitation, silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0077] The flowchart then continues with block 808 to form traces in the glass layers above and below the core, including through holes and horizontal traces.

[0078] Blocks 806 and 808 can be repeated any number of times to form the corresponding number of glass buildup layers structured with conductor tracks above and below the core.

[0079] The flowchart then continues with block 810 to form conductive contact surfaces on one or more surfaces of the substrate (e.g., on the upper and / or lower glass layers and coupled to the conductor tracks), such as metal pads (e.g., recessed or non-recessed copper pads), metal bumps / microbumps (e.g., C2 / C4 copper bumps), solder balls / bumps, and solder paste, among other examples.

[0080] In some embodiments, recessed pads (e.g., for hybrid bonding) or microbumps for first-level interconnection with one or more integrated circuit chips can be formed on the top surface of the glass substrate. Furthermore, bumps for second-level interconnection to a printed circuit board (e.g., a motherboard, mainboard, etc.) or other integrated circuit package can be formed on the underside of the glass substrate.

[0081] In this way, the finished housing substrate includes a glass core, glass structure layers above and below the glass core, conductive tracks incorporated into the glass core and the glass structure layers, and conductive contacts on the surface(s) of the substrate for the first and / or second level interconnects.

[0082] The flowchart then proceeds to block 812 to mount one or more integrated circuit (IC) chips onto the substrate. In some embodiments, for example, one or more chips can be mounted on the top surface of the glass substrate, such as by hybrid bonding the chips to recessed copper pads on the substrate surface or by mounting the chips to microbumps on the substrate surface. Alternatively, in some embodiments, one or more cavities can be formed in the glass core and / or in the glass layers during earlier processing steps, and one or more silicon chips can be embedded in the cavities and connected to the conductive traces structured in the glass buildup layers.

[0083] The integrated chip(s) may include any suitable type of circuitry, including but not limited to processing circuitry, communication circuitry, and / or memory / mass storage circuitry. In some embodiments, the integrated chip(s) may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a visual processing unit (VPU), a microprocessor, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an input / output (I / O) controller, a network interface controller (NIC), a controller, and / or solid-state memory, among other examples.

[0084] The finished IC package can then be attached to or enclosed within a printed circuit board, another substrate or integrated circuit housing, or an electronic device (e.g., the electronic device 1200).

[0085] In some embodiments, the IC package can be enclosed in an electronic device such as a mobile phone, a portable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit, or a household appliance, among other examples.

[0086] At this point, the flowchart may be complete. However, in some embodiments, the flowchart may restart and / or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 802 to form another package for an integrated circuit with the same or a similar design. Example of embodiments of an integrated circuit

[0087] Fig. Figure 9 is a top view of a wafer 900 and chips 902, which may be included in any of the embodiments disclosed herein. The wafer 900 may be made of semiconductor material and may include one or more chips 902 with integrated circuit structures formed on a surface of the wafer 900. The individual chips 902 may be a repeating unit of an integrated circuit, including any suitable integrated circuit. After completion of the fabrication of the semiconductor product, the wafer 900 may be subjected to a singulation process in which the chips 902 are separated from one another to provide discrete “chips” of the integrated circuit product. The chip 902 may be any of the chips described herein. The chip 902 may include one or more transistors (e.g., some of the transistors 1040 of Fig. 10, see below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal lines, resistors, capacitors, or inductors), and / or other components of the integrated circuit. In some embodiments, the wafer 900 or the chip 902 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a conductive-bridging RAM (CBRAM), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Several of these devices may be combined on a single chip 902.For example, a memory array formed by multiple memory devices can be represented on the same chip 902 as a single processor unit (e.g., the processor unit 1202 of . Fig. 12) or other logic configured for storing information in the storage devices or executing instructions stored in the storage array. Several of the microelectronic assemblies disclosed herein can be fabricated using a chip-to-wafer assembly technique in which some chips are attached to a wafer 900, which has other chips, and the wafer 900 is subsequently singulated.

[0088] Fig. Figure 10 is a cross-sectional side view of an integrated circuit device 1000, which may be included in any of the embodiments disclosed herein (e.g., in any of the chips). One or more of the integrated circuit devices 1000 may be contained in one or more chips 902 ( Fig. 9) be included. The integrated circuit device 1000 can be mounted on a chip substrate 1002 (e.g., the wafer 900 made of Fig. 9) and can be formed in a chip (e.g. the 902 chip from Fig. 9) The chip substrate 1002 may be a semiconductor substrate consisting of semiconductor material systems, for example, n-type or p-type material systems (or a combination of both). The chip substrate 1002 may, for example, include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the chip substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon, including, among others, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the chip substrate 1002.Although some examples of materials from which the chip substrate 1002 can be formed are described herein, any material that can serve as a basis for an integrated circuit device 1000 can be used. The chip substrate 1002 can be part of a discrete chip (e.g., the chips 902 from ). Fig. 9) or a wafer (e.g., wafer 900 from Fig. 9) be.

[0089] The integrated circuit device 1000 can have one or more device layers 1004 arranged on the chip substrate 1002. The device layer 1004 can have features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the chip substrate 1002. The transistors 1040 can, for example, have one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling current flow between the S / D regions 1020, and one or more S / D contacts 1024 for conducting electrical signals to / from the S / D regions 1020. The transistors 1040 can have additional features, not shown for clarity, such as isolation regions, gate contacts, and the like. The 1040 transistors are not suitable for the one in Fig. The type and configuration shown are limited and can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as dual-gate or tri-gate transistors, and wrap-around or all-around-gate transistors, such as nanoband, nanoplate, or nanowire transistors.

[0090] With renewed reference to Fig. 10. A transistor 1040 can have a gate 1022 formed from at least two layers, a gate dielectric and a gate electrode. The gate dielectric can have a single layer or a stack of layers. The one or more layers can have silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material.

[0091] The high-k dielectric material can contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate. In some embodiments, a tempering process can be performed on the gate dielectric to improve its quality when a high-k material is used.

[0092] The gate electrode can be formed on the gate dielectric and, depending on whether the transistor 1040 is to be a p-type metal-oxide semiconductor (PMOS) transistor or an n-type metal-oxide semiconductor (NMOS) transistor, can have at least one p-type or one n-type exit metal. In some implementations, the gate electrode can consist of a stack of two or more metal layers, where one or more metal layers are exit metal layers and at least one metal layer is a filler metal layer. Additional metal layers may be included for other purposes, such as acting as a barrier layer.

[0093] In a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (for example, ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (for example, for work function tuning). In an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (for example, for work function tuning).

[0094] In some embodiments, the gate electrode, viewed as a cross-section of the transistor 1040 along the source-channel-drain direction, can consist of a U-shaped structure comprising a lower portion that is substantially parallel to the surface of the chip substrate 1002 and two sidewall portions that are substantially perpendicular to the upper surface of the chip substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode can simply be a planar layer that is substantially parallel to the upper surface of the chip substrate 1002 and has no sidewall portions that are substantially perpendicular to the upper surface of the chip substrate 1002. In still other embodiments, the gate electrode can consist of a combination of U-shaped structures and planar, non-U-shaped structures.For example, the gate electrode can consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0095] In some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers can be made of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally involve deposition and etching processes. In some embodiments, multiple pairs of spacers can be used; for example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0096] The S / D regions 1020 can be formed within the chip substrate 1002 adjacent to the gate 1022 of individual transistors 1040. The S / D regions 1020 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the chip substrate 1002 to form the S / D regions 1020. The ion implantation process can be followed by a annealing process, which activates the dopants and causes them to diffuse further into the chip substrate 1002. In the latter process, the chip substrate 1002 can first be etched to create depressions at the locations of the S / D regions 1020. An epitaxial deposition process can then be performed to fill the depressions with material used to fabricate the S / D areas 1020.In some implementations, the S / D regions 1020 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1020 can be formed using one or more alternative semiconductor materials such as germanium or a material or alloy from Group III-V. In other embodiments, one or more layers of metal and / or metal alloys can be used to form the S / D regions 1020.

[0097] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from the devices (e.g., transistors 1040) of the device layer 1004 through one or more interconnection layers arranged on the device layer 1004 (in Fig. 10 illustrated as interconnection layers 1006-1010). For example, electrically conductive features of the device layer 1004 (e.g., the gate 1022 and the S / D contacts 1024) can be electrically coupled to the interconnection structures 1028 of the interconnection layers 1006 to 1010. The one or more interconnection layers 1006-1010 can form a metallization stack (also referred to as an "ILD stack") 1019 of the integrated circuit device 1000.

[0098] The interconnect structures 1028 can be arranged within the interconnect layers 1006-1010 to conduct electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the one shown in Fig. The special configuration of intermediate connection structures shown in section 10 is limited to 1028. Even if in Fig. 10 where a specific number of interconnect layers 1006-1010 is shown, embodiments of the present disclosure include IC devices with more or fewer interconnect layers than shown.

[0099] In some embodiments, the interconnection structures 1028 may include traces 1028a and / or vias 1028b filled with an electrically conductive material, such as a metal. The traces 1028a may be arranged to transmit electrical signals in a direction along a plane that is substantially parallel to a surface of the chip substrate 1002 on which the device layer 1004 is formed. For example, from the perspective of Fig. The vias 1028b conduct electrical signals in one direction into and out of the side and / or in one direction across the side. They can be arranged to conduct electrical signals in one direction along a plane that is substantially perpendicular to the surface of the chip substrate 1002 on which the device layer 1004 is formed. In some embodiments, the vias 1028b can electrically couple conductors 1028a of different interconnection layers 1006 to 1010.

[0100] The intermediate interconnection layers 1006-1010 can have a dielectric material 1026 arranged between the intermediate interconnection structures 1028, as shown in Fig. Figure 10 shows. In some embodiments, the dielectric material 1026 arranged between the interconnection structures 1028 in different interconnection layers 1006 to 1010 can have different compositions; in other embodiments, the composition of the dielectric material 1026 can be the same between different interconnection layers 1006 to 1010. The device layer 1004 can have a dielectric material 1026 that is also arranged between the transistors 1040 and a lower layer of the metallization stack.The dielectric material 1026 contained in the device layer 1004 may have a different composition than the dielectric material 1026 contained in the intermediate compound layers 1006 to 1010; in other embodiments, the composition of the dielectric material 1026 in the device layer 1004 may be the same as that of a dielectric material 1026 contained in any of the intermediate compound layers 1006 to 1010.

[0101] A first interconnection layer 1006 (designated as metal 1 or "M1") can be formed directly on the device layer 1004. In some embodiments, the first interconnection layer 1006 can include conductors 1028a and / or vias 1028b, as shown. The conductors 1028a of the first interconnection layer 1006 can be coupled to contacts (e.g., S / D contacts 1024) of the device layer 1004. The vias 1028b of the first interconnection layer 1006 can be coupled to the conductors 1028a of a second interconnection layer 1008.

[0102] The second interconnect layer 1008 (designated as metal 2 or “M2”) can be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 can include a via 1028b to couple the leads 1028 of the second interconnect layer 1008 to the leads 1028a of a third interconnect layer 1010. Although the leads 1028a and the vias 1028b are structurally separated by a line in individual interconnect layers for clarity, in some embodiments the leads 1028a and the vias 1028b can be structurally and / or materially related (for example, by being filled simultaneously during a dual-damascene process).

[0103] The third interconnect layer 1010 (designated as Metal 3 or “M3”) (and, if required, additional interconnect layers) can be subsequently formed on the second interconnect layer 1008 according to similar techniques and configurations described in connection with the second interconnect layer 1008 or the first interconnect layer 1006. In some embodiments, the interconnect layers located “higher up” (i.e., farther away from the device layer 1004) in the metallization stack 1019 of the integrated circuit device 1000 can be thicker than the interconnect layers located lower down in the metallization stack 1019, with the conductors 1028a and vias 1028b in the higher interconnect layers being thicker than those in the lower interconnect layers.

[0104] The integrated circuit device 1000 can have a solder mask material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interlinking layers 1006-1010. Fig. Figure 10 illustrates the conductive contacts 1036 as taking the form of bond contact patches. The conductive contacts 1036 can be electrically coupled to the interconnection structures 1028 and configured to conduct the electrical signals of the transistor(s) 1040 to external devices. For example, solder bonds can be formed on one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit chip comprising the integrated circuit device 1000 to another component (e.g., a printed circuit board). The integrated circuit device 1000 can have additional or alternative structures to conduct the electrical signals from the interconnection layers 1006 to 1010, where, for example, the conductive contacts 1036 can have other analogous features (e.g., pillars) that conduct the electrical signals to external components.The conductive contacts 1036 can serve as any of the conductive contacts described in the entire present disclosure.

[0105] In some embodiments where the integrated circuit device 1000 is a double-sided chip, the integrated circuit device 1000 may have another (not shown) metallization stack on the opposite side of the device layer(s) 1004. This metallization stack may have several interconnection layers, as discussed above with reference to interconnection layers 1006 to 1010, to provide conductive paths (e.g., including conductive traces and vias) between the device layer(s) 1004 and (not shown) additional conductive contacts on the side of the IC device 1000 opposite the conductive contacts 1036. These additional conductive contacts may be any of the conductive contacts described throughout this disclosure.

[0106] In other embodiments, where the integrated circuit device 1000 is a double-sided chip, the integrated circuit device 1000 may have one or more silicon vias (TSVs) through the chip substrate 1002; these TSVs may make contact with the device layer(s) 1004 and may provide conductive paths between the device layer(s) 1004 and additional conductive contacts (not shown) on the side of the integrated circuit device 1000 opposite the conductive contacts 1036. These additional conductive contacts may be any of the conductive contacts described throughout this disclosure.In some embodiments, TSVs extending through the substrate can be used to conduct power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1000 from the conductive contacts 1036 to the transistors 1040 and any other components integrated in the chip 1000, and the metallization stack 1019 can be used to conduct I / O signals from the conductive contacts 1036 to the transistors 1040 and any other components integrated in the chip 1000.

[0107] Multiple integrated circuit devices (ICDs) can be stacked with one or more interconnects (TSVs) in each stacked device, providing a connection between any one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit chips can be stacked on a base integrated circuit chip, and the TSVs in the HBM chips can provide a connection between the individual HBM chip and the base integrated circuit chip. Conductive contacts can provide additional connections between adjacent integrated circuit chips in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (micro-bumps).

[0108] Fig. Figure 11 is a cross-sectional side view of an assembly with an integrated circuit device 1100, which may include any of the embodiments disclosed herein. For example, any suitable component of the integrated circuit device 1100 may include one or more of the glass substrates / housings 100, 300, 500 disclosed herein. In some embodiments, the integrated circuit device assembly 1100 may be a microelectronic assembly. The integrated circuit device assembly 1100 has a number of components arranged on a printed circuit board 1102 (which may be a motherboard, a system board, a main board, etc.). The IC device assembly 1100 has components arranged on a first surface 1140 of the printed circuit board 1102 and an opposing second surface 1142 of the printed circuit board 1102. where components can generally be arranged on one or both surfaces 1140 and 1142.Any of the integrated circuit components discussed below with reference to the integrated circuit device assembly 1100 can take the form of any suitable embodiment of the microelectronic assemblies 100 disclosed herein.

[0109] In some embodiments, the circuit board 1102 can be a printed circuit board (PCB) comprising several metal layers (or interconnect layers) separated from one another by layers of a dielectric material and connected to one another by electrically conductive vias. The individual metal layers include conductive traces. Any number of the metal layers can be formed in a desired circuit structure to transmit electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1102. In other embodiments, the circuit board 1102 can be a non-PCB substrate. The in Fig. Figure 11 illustrates an integrated circuit device assembly 1100 that has a package-on-interposer structure 1136 coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1116. The coupling components 1116 can electrically and mechanically couple the package-on-interposer structure 1136 to the printed circuit board 1102 and can be solder balls (as shown in Figure 11). Fig. 11 shown), pins (for example, as part of a pin grid arrangement (PGA)), contacts (for example, as parts of a contact patch arrangement (LGA)), plug and socket sections of a socket, an adhesive, a backing material, and / or any other suitable electrical and / or mechanical coupling structure. The coupling components 1116 may optionally be the coupling components illustrated or described for any of the substrate assembly or substrate assembly components described herein.

[0110] The package-on-interposer structure 1136 can include an integrated circuit component 1120 coupled to an interposer 1104 by coupling components 1118. The coupling components 1118 can take any shape suitable for the application, such as the shapes discussed above with reference to the coupling components 1116. Although a single integrated circuit component 1120 in Fig. As shown in Figure 11, several integrated circuit components can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an intermediate substrate that is used to form a bridge between the printed circuit board 1102 and the integrated circuit component 1120.

[0111] The integrated circuit component 1120 can be a packaged or unpackaged integrated circuit product containing one or more integrated circuit chips (e.g., the 902 chip from Fig. 9, the integrated circuit device 1000 from Fig. 10) and / or includes one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit chips mounted on a package substrate, wherein the integrated circuit chips and the package substrate are encapsulated in an encapsulation material such as metal, plastic, glass, or ceramic. In an example of an unencapsulated integrated circuit component 1120, a single monolithic integrated circuit chip comprises solder pad prongs attached to contacts on the chip. The solder pad prongs allow the chip to be mounted directly to the interposer 1104. The integrated circuit component 1120 can include one or more computing system components, such as one or more processor units (e.g.,The integrated circuit component 1120 may include a system-on-a-chip (SoC), a processor core, a graphics processing unit (GPU), an accelerator, a chipset processor, an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 1120 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0112] In embodiments where the integrated circuit component 1120 comprises several integrated circuit chips, the chips can be of the same type (a homogeneous multi-chip integrated circuit component) or of two or more different types (a heterogeneous multi-chip integrated circuit component). A multi-chip integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

[0113] In addition to containing one or more processor units, the integrated circuit component 1120 can include additional components such as embedded DRAM, high-bandwidth stacked memory (HBM), shared cache memory, input / output (I / O) controls, or memory controls. Any of these additional components can be placed on the same integrated circuit chip as a processor unit or on one or more separate integrated circuit chips that are distinct from the integrated circuit chips containing the processor units. These separate integrated circuit chips can be referred to as "chiplets."In embodiments where an integrated circuit component comprises multiple integrated circuit chips, interconnections between the chips can be provided through the package substrate, through one or more silicon interposers, through one or more silicon bridges embedded in the package substrate (such as embedded multi-chip interconnect bridges (EMIBs: Intel® Embedded Multi-Chip Interconnect Bridges)), or combinations thereof.

[0114] In general, the interposer 1104 can spread connections to a wider grid spacing or redirect one connection to another. For example, the interposer 1104 can couple the integrated circuit component 1120 to a set of conductive ball grid array (BGA) contacts of the coupling components 1116 for coupling to the printed circuit board 1102. In the Fig. In the illustrated embodiment, the integrated circuit component 1120 and the printed circuit board 1102 are mounted on opposite sides of the interposer 1104; in other embodiments, the integrated circuit component 1120 and the printed circuit board 1102 may be mounted on the same side of the interposer 1104. In some embodiments, three or more components may be interconnected using the interposer 1104.

[0115] In some embodiments, the interposer 1104 can be formed as a PCB comprising several metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1104 can be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1104 can be formed from alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other materials of Groups III-V and IV.The interposer 1104 can have metal interconnections 1108 and vias 1110, including vias 1110-1 (extending from a first face 1150 of the interposer 1104 to a second face 1154 of the interposer 1104), blind vias 1110-2 (extending from the first or second face 1150 or 1154 of the interposer 1104 to an internal metal layer) and buried vias 1110-3 (connecting internal metal layers).

[0116] In some embodiments, the interposer 1104 can comprise a silicon interposer. The silicon vias (TSVs) extending through the silicon interposer can connect links on a first face of the silicon interposer to an opposite second face of the silicon interposer. In some embodiments, an interposer 1104 comprising a silicon interposer can further comprise one or more relay layers to relay connections on a first face of the interposer 1104 to an opposite second face of the interposer 1104.

[0117] The interposer 1104 can further comprise embedded devices 1114, which may include both passive and active devices. Such devices may include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 1104. The package-on-interposer structure 1136 can take the form of any package-on-interposer structure known in the prior art. In embodiments where the interposer is a non-printed circuit board,

[0118] The integrated circuit device assembly 1100 can comprise an integrated circuit component 1124, which is coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1122. The coupling components 1122 can take the form of any of the embodiments discussed above with reference to the coupling components 1116, and the integrated circuit component 1124 can take the form of any of the embodiments discussed above with reference to the integrated circuit component 1120.

[0119] The in Fig. Figure 11 illustrates the integrated circuit device assembly 1100, which has a case-on-case structure 1134 coupled to the second surface 1142 of the printed circuit board 1102 by coupling components 1128. The case-on-case structure 1134 can include an integrated circuit component 1126 and an integrated circuit component 1132, which are coupled to each other by coupling components 1130 such that the integrated circuit component 1126 is located between the printed circuit board 1102 and the integrated circuit component 1132. The coupling components 1128 and 1130 can take the form of any embodiment of the coupling components 1116 discussed above, and the integrated circuit components 1126 and 1132 can take the form of any embodiment of the integrated circuit component 1120 discussed above.The case-on-case structure 1134 can be configured according to any of the case-on-case structures known in the prior art.

[0120] Fig. Figure 12 is a block diagram of an exemplary electrical device 1200, which may have one or more of the embodiments disclosed herein. For example, all suitable components of the electrical device 1200 may include one or more of the glass substrates / housings 100, 100', 300, 300', 500, 500' disclosed herein, assemblies of integrated circuit devices 1100, components of integrated circuits 1120, integrated circuit devices 1000, or integrated circuit chips 902. A number of components are shown in Figure 12. Fig. Figure 12 illustrates the electrical device 1200 as containing components, but any or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components contained in the electrical device 1200 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components may be fabricated on a single system-on-a-chip (SoC) chip.

[0121] In addition, the electrical device 1200 may, in various embodiments, have one or more in Fig.The electrical device 1200 may not include the components shown in Figure 12; however, it may include an interface circuit for coupling with one or more of the components. For example, the electrical device 1200 may not include a display device 1206, but it may include a display device interface circuit (e.g., a connector and a driver circuit) to which a display device 1206 can be coupled. In another set of examples, the electrical device 1200 may not include an audio input device 1224 or an audio output device 1208, but it may include an audio input or output device interface circuit (e.g., a connector and a support circuit) to which an audio input device 1224 or an audio output device 1208 can be coupled.

[0122] The electrical device 1200 can include one or more processor units 1202 (for example, one or more processor units). As used herein, the terms "processor unit," "processing unit," or "processor" can refer to any device or any part of a device that processes electronic data from registers and / or memory to convert such electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1202 can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g.,Graphics accelerators, compression accelerators, AI accelerators), cryptoprocessors of a controller (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit can be referred to as an XPU (or xPU).

[0123] The electrical device 1200 can include a memory 1204, which in turn can include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based voltage-free phase-change memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1204 can include memory located on the same integrated circuit chip as the processor unit 1202. This memory can be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last-Level Cache (LLC)) and can include embedded dynamic random access memory (eDRAM) or magnetic spin transfer torque random access memory (STT-MRAM).

[0124] In some embodiments, the electrical device 1200 may comprise one or more processor units 1202 that are heterogeneous or asymmetric with respect to another processor unit 1202 in the electrical device 1200. There may be a multitude of differences between the processing units 1202 in a system with respect to a spectrum of quality metrics, exhibiting architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1202 in the electrical device 1200.

[0125] In some embodiments, the electrical device 1200 may include a communication component 1212 (for example, one or more communication components). For example, the communication component 1212 may manage wireless communications for the transfer of data to and from the electrical device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term "wireless" does not imply that the devices associated with it contain no wires whatsoever, although in some embodiments they may not.

[0126] The 1212 communication component can implement any number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) Project along with all changes, updates, and / or revisions (e.g., Advanced LTE Project, Ultra Mobile Broadband (UMB) Project (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a certification mark for products that pass compliance and interoperability tests according to IEEE 802.16 standards.The 1212 communication component can operate according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The 1212 communication component can also operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 1212 communication component can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as all other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the 1212 communication component can operate according to other wireless protocols.The electrical device 1200 can have an antenna 1222 to enable wireless communication and / or to receive other wireless communication (such as AM or FM radio transmissions).

[0127] In some embodiments, the communication component 1212 can manage wired communications, such as electrical, optical, or any other suitable communication protocols (for example, IEEE 802.3 Ethernet standards). As mentioned above, the communication component 1212 can include multiple communication components. For example, a first communication component 1212 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 1212 can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1212 can be dedicated to wireless communications, and a second communication component 1212 can be dedicated to wired communications.

[0128] The electrical device 1200 can include a battery / power circuit 1214. The battery / power circuit 1214 can include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit arrangement for coupling components of the electrical device 1200 to a power source separate from the electrical device 1200 (e.g., AC mains power).

[0129] The electrical device 1200 may include a display device 1206 (or a corresponding interface circuit as discussed above). The display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a field-of-view display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0130] The electrical device 1200 may include an audio output device 1208 (or a corresponding interface circuit as discussed above). The audio output device 1208 may include any embedded, wired, or wirelessly connected external device that produces an acoustic indicator, such as a loudspeaker, headphones, or earphones.

[0131] The electrical device 1200 may include an audio input device 1224 (or a corresponding interface circuit as discussed above). The audio input device 1224 may include any embedded, wired, or wirelessly connected device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1200 may include a global navigation satellite system (GNSS) device 1218 (or a corresponding interface circuit as discussed above), such as a global positioning system (GPS) device.The GNSS device 1218 can communicate with a satellite-based system and can determine a geographic location of the electrical device 1200 based on information received from one or more GNSS satellites, as is known in the prior art.

[0132] The electrical device 1200 may include one or more other output devices 1210 (or a corresponding interface circuit, as discussed above). Examples of the one or more other output devices 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional mass storage device.

[0133] The electrical device 1200 may include one or more other input devices 1220 (or a corresponding interface circuit, as discussed above). Examples of the one or more other input devices 1220 may include an accelerometer, a gyroscope, a compass, an image acquisition device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touch panel, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick-response (QR) code reader, an electrocardiogram (ECG) sensor, a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0134] The 1200 electrical device can have any desired form factor, such as a handheld or mobile electrical device (for example, a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a convertible 2-in-1 computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.).), an electrical desktop device, a server, a rack-level computing solution (for example, blade, tray, or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a home gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, an electrical wearable device, or an embedded computing system (for example, computing systems that are part of a vehicle, a smart home appliance, a consumer electronics product or equipment, or manufacturing equipment). In some embodiments, the electrical device 1200 can be any other electronic device that processes data. In some embodiments, the electrical device 1200 can comprise several discrete physical components.In view of the variety of devices that the electrical device 1200 can manifest itself in in different embodiments, the electrical device 1200 can be referred to as a calculating device or calculating system in some embodiments. Exemplary embodiments

[0135] Illustrative examples of the technologies described in this entire disclosure are provided below. Embodiments of these technologies may include one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components shown in one or more of the preceding figures may be configured to perform one or more operations, one or more techniques, one or more processes, and / or one or more methods, as set forth in the following examples.

[0136] Example 1 includes a substrate comprising: a glass core; a plurality of glass layers on the glass core, wherein some of the glass layers are located above the glass core and some of the glass layers are located below the glass core; a plurality of conductive traces, wherein the conductive traces are located in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate.

[0137] Example 2 includes the substrate of Example 1, wherein the conductor tracks comprise: a plurality of vias, wherein the vias are located in the glass core and at least some of the glass layers; and a plurality of horizontal conductor tracks, wherein the horizontal conductor tracks are located in at least some of the glass layers.

[0138] Example 3 includes the substrate from one of Examples 1-2, wherein at least some of the conductive contacts are to be electrically coupled to a printed circuit board or an integrated circuit housing.

[0139] Example 4 includes the substrate from one of Examples 1 to 3, wherein at least some of the conductive contacts are to be electrically coupled to a chip of the integrated circuit.

[0140] Example 5 includes the substrate of Example 4, wherein the conductive contact surfaces to be electrically coupled to the chip of the integrated circuit comprise a plurality of microbumps or a plurality of contact surfaces.

[0141] Example 6 includes the substrate of Example 5, with the pads being recessed relative to the glass layers.

[0142] Example 7 includes the substrate from one of Examples 1-6, where the glass core has a thickness of approximately 100-1000 microns.

[0143] Example 8 includes the substrate from one of Examples 1-7, wherein at least some of the glass layers have a thickness of about 10-50 micrometers.

[0144] Example 9 includes the substrate from one of Examples 1-8, wherein at least some of the glass layers comprise silicon and oxygen.

[0145] Example 10 includes the substrate from one of Examples 1-9, wherein the conductor tracks comprise at least one of copper or titanium.

[0146] Example 11 comprises an integrated circuit package comprising: an integrated circuit chip; and a package substrate electrically coupled to the integrated circuit chip, the package substrate comprising: a glass core; a plurality of glass layers on the glass core, wherein some of the glass layers are located above the glass core and some of the glass layers are located below the glass core; a plurality of conductive traces, wherein the conductive traces are located in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the package substrate.

[0147] Example 12 includes the housing with integrated circuit from Example 11, wherein at least some of the conductive contacts are electrically connected to a printed circuit board or another housing with integrated circuit.

[0148] Example 13 includes the housing of an integrated circuit according to one of Examples 11-12, wherein at least some of the conductive contacts are electrically contacted with the chip of the integrated circuit.

[0149] Example 14 includes the package of an integrated circuit according to one of Examples 11-12, wherein the chip of the integrated circuit is embedded in a cavity of the package substrate.

[0150] Example 15 includes the integrated circuit package from one of Examples 11-14, wherein the integrated circuit chip comprises a processing circuit, a communication circuit or a memory chip.

[0151] Example 16 comprises an electronic device comprising: a printed circuit board; and an integrated circuit housing electrically coupled to the printed circuit board, the integrated circuit housing comprising: one or more integrated circuit chips; and a housing substrate electrically coupled to the one or more integrated circuit chips, the housing substrate comprising: a glass core; a plurality of glass layers on the glass core, some of the glass layers being above the glass core and some of the glass layers being below the glass core; a plurality of conductive traces, the conductive traces being in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the housing substrate.

[0152] Example 17 includes the electronic device from Example 16, wherein the electronic device is a mobile phone, a portable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit or a device.

[0153] Example 18 comprises a method comprising: receiving a glass core; forming a plurality of glass layers on the glass core, with some of the glass layers being formed above the glass core and some of the glass layers being formed below the glass core; forming a plurality of conductive traces in the glass core and at least some of the glass layers; and forming a plurality of conductive contacts on one or more surfaces of the glass layers.

[0154] Example 19 includes the procedure of Example 18, which further includes: attaching a chip of the integrated circuit to at least some of the conductive contacts.

[0155] Example 20 comprises the method of Example 18, which further comprises: forming a cavity in the glass core and / or in at least some of the glass layers and embedding an integrated circuit chip in the cavity.

[0156] While the concepts of the present disclosure are open to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are described in detail herein. It is understood, however, that the intention is not to limit the concepts of the present disclosure to the specific disclosed forms, but rather, on the contrary, to cover all modifications, equivalents, and alternatives that are consistent with the present disclosure and the appended claims.

[0157] In the drawings, certain structural or process features may be depicted in specific arrangements and / or sequences. However, it is understood that such specific arrangements and / or sequences are not required. Rather, in some embodiments, such features may be arranged in a different manner and / or sequence than shown in the illustrative figures. Furthermore, the inclusion of a structural or process feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments it may be omitted or combined with other features. It is also understood that the various embodiments shown in the figures are for illustrative purposes only and are not necessarily drawn to scale.

[0158] Furthermore, the illustrations and / or descriptions of various embodiments may be simplified or approximated for ease of understanding, and as a result, they may not necessarily reflect the level of accuracy or variation that may be present in actual embodiments. For example, while some figures generally show straight lines, right angles, and smooth surfaces, actual implementations of the disclosed embodiments may not have perfectly straight lines and right angles, and some features may have surface topography or otherwise be uneven due to real limitations of manufacturing processes. Likewise, illustrations and / or descriptions of how components are arranged may be simplified or approximated for ease of understanding and may differ in actual embodiments (e.g.,(due to manufacturing processes, etc.) they may vary by a certain margin of error.

[0159] Unless otherwise stated, the use of the ordering adjectives 'first', 'second', 'third', etc., to describe a common object merely indicates different instances of the same object being referred to, and is not intended to imply that the objects so described must be in any given sequence, whether temporally, spatially, in rank, or in any other way.

[0160] The terms "essentially", "close", "approximately", "near", and "about" generally refer to a deviation of + / - -10% from a target value (unless otherwise specified). Similarly, terms describing spatial relationships, such as "perpendicular", "orthogonal", or "coplanar", can refer to the fact that they lie substantially within the described spatial relationships (e.g., within + / - 10 degrees of orthogonality).

[0161] Furthermore, certain terminology in the preceding description may be used merely for reference purposes and is therefore not intended to be restrictive. For example, terms such as "upper," "lower," "above," "below," "below," and "above" refer to directions in the drawings being referenced. Terms such as "front," "rear," "back," and "side" describe the orientation and / or position of parts of the component within a consistent but arbitrary frame of reference, which is clarified by referring to the text and the associated drawings describing the component under discussion. This terminology may include the words specifically mentioned above, derivatives thereof, and words with similar meanings.

[0162] The terms "above," "between," "next to," "to," and "on" used here can refer to the relative position of a layer or component in relation to other layers or components. For example, a layer can be "above" or "on" another layer, "adjacent" to another layer, or "connected" to another layer and be in direct contact with that layer, or it can have one or more intermediate layers. A layer "between" layers can be in direct contact with the layers or it can have one or more intermediate layers.

[0163] The meaning of "ein / e" and "der / die / das" includes plural references. The meaning of "in" includes "in" and "auf".

[0164] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” is synonymous with (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0165] The term "package" generally refers to a self-contained carrier for one or more chips, where the chips are attached to the package substrate and may be encapsulated for protection, with integrated or wired connections between the chips and traces, pins, or protrusions located on the external parts of the package substrate. The package may contain a single chip or multiple chips that perform a specific function. The package is typically mounted on a printed circuit board and interconnected with other integrated circuits and discrete components to form a larger circuit.

[0166] The term "core" generally refers to the substrate of an integrated circuit package, mounted on a circuit board, card, or wafer, and comprised of a rigid, inflexible material. Typically, a small printed circuit board (PCB) is used as the core, onto which the integrated circuit and discrete passive components can be soldered. The core usually features vias extending from one side to the other, allowing circuit assemblies on one side of the core to be directly connected to circuit assemblies on the opposite side. The core can also serve as a platform for layering conductors and dielectric materials.

[0167] The term "coreless" generally refers to an integrated circuit package substrate that lacks a core. The absence of a core enables higher-density package architectures because the vias have relatively large dimensions and spacings compared to high-density connections.

[0168] The term "terminal face," when used herein, generally refers to the side of the substrate or package of the integrated circuit that is closest to the plane of attachment to a printed circuit board, mainboard, or other enclosure. This is in contrast to the term "chip face," which refers to the side of the substrate or package of the integrated circuit on which the chip or chips are mounted.

[0169] The term “dielectric” generally refers to any number of non-electrically conductive materials that form the structure of a package substrate. For the purposes of this disclosure, dielectric material can be incorporated into a package for integrated circuits in the form of layers of laminate film or as a resin cast over the integrated circuit chip mounted on the substrate.

[0170] The term "metallization" generally refers to metal layers formed over and through the dielectric material of the package substrate. These metal layers are typically structured to form metal structures such as conductor tracks and bond pads. The metallization of a package substrate may be limited to a single layer or consist of multiple layers separated by dielectric layers.

[0171] The term "bond pad" generally refers to metallization structures that terminate integrated circuit traces and vias in integrated circuit packages and chips. The term "solder pad" may occasionally be used instead of "bond pad" and has the same meaning.

[0172] The term "solder contact bump" generally refers to a layer of solder formed on a bond pad. This solder layer typically has a round shape, hence the name "solder bump".

[0173] The term "substrate" generally refers to a planar platform that includes dielectric and / or metallization structures. The substrate can mechanically support and electrically couple one or more IC chips on a single platform, with the one or more IC chips being encapsulated by a malleable dielectric material. The substrate may include solder bumps (or other conductive contacts) as interconnects on one or both sides. One side of the substrate, generally referred to as the "chip side," may include solder bumps for chip or die bonding. The opposite side of the substrate, generally referred to as the "land side," may include solder bumps for bonding the package to a printed circuit board.

[0174] The term "assembly" generally refers to a grouping of parts into a single functional unit. The parts may be separate and mechanically assembled into a functional unit, and the parts may be removable. In other cases, the parts may be permanently bonded together. In some cases, the parts are connected to each other.

[0175] The terms “coupled” or “connected” mean a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluidic connection between the things that are connected, or an indirect connection through one or more passive or active intermediate devices.

[0176] The term "circuit" or "module" can refer to one or more passive and / or active components designed to work together to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 194,550

[0001]

Claims

[1] Substrate comprising the following: a glass core; a multitude of glass layers on the glass core, with some of the glass layers being located above the glass core and some of the glass layers being located below the glass core; a multitude of conductive traces, wherein the conductive traces are located in the glass core and in at least some of the glass layers; and a large number of conductive contacts on one or more surfaces of the substrate. [2] Substrate according to claim 1, wherein the conductor tracks comprise: a multitude of through holes, wherein the through holes are located in the glass core and at least some of the glass layers; and a multitude of horizontal bands, wherein the horizontal bands are located in at least some of the glass layers. [3] Substrate according to one of claims 1 to 2, wherein at least some of the conductive contacts are to be electrically coupled to a printed circuit board or a housing for integrated circuits. [4] Substrate according to one of claims 1 to 3, wherein at least some of the conductive contacts are to be electrically coupled to a chip of an integrated circuit. [5] Substrate according to claim 4, wherein the conductive contacts to be electrically coupled to the chip of the integrated circuit comprise: a multitude of microbumps; or a variety of pads. [6] Substrate according to claim 5, wherein the pads are recessed relative to the glass layers. [7] Substrate according to any one of claims 1 to 6, wherein the glass core has a thickness in the range of about 100 to 1000 microns. [8] Substrate according to any one of claims 1 to 7, wherein at least some of the glass layers have a thickness of about 10 to 50 micrometers. [9] Substrate according to any one of claims 1-8, wherein at least some of the glass layers comprise silicon and oxygen. [10] Substrate according to any one of claims 1 to 9, wherein the conductive conductors comprise at least one of the elements copper or titanium. [11] Device comprising the following: a chip with an integrated circuit; and a package substrate that is electrically coupled to the chip of the integrated circuit, wherein the package substrate comprises the following: a glass core; a multitude of glass layers on the glass core, with some of the glass layers being located above the glass core and some of the glass layers being located below the glass core; a multitude of conductive traces, wherein the conductive traces are located in the glass core and in at least some of the glass layers; and a large number of conductive contacts on one or more surfaces of the housing substrate. [12] Device according to claim 11, wherein at least some of the conductive contacts are electrically coupled to the chip of the integrated circuit, the conductive contacts which are electrically coupled to the chip of the integrated circuit comprising microbumps or pads. [13] Device according to claim 12, wherein the pads are recessed relative to the glass layers. [14] Device according to one of claims 11-13, wherein the chip of the integrated circuit is embedded in a cavity of the housing substrate. [15] Device according to one of claims 11-14, wherein the glass core has a thickness in the range of about 100 to 1000 micrometers. [16] Device according to one of claims 11-15, wherein at least some of the glass layers have a thickness in the range of about 10 to 50 microns. [17] Device according to one of claims 11-16, wherein at least some of the glass layers comprise silicon and oxygen. [18] Device according to one of claims 11-17, wherein the conductive conductors comprise at least one of the elements copper or titanium. [19] Device according to one of claims 11-18, wherein the chip with integrated circuit comprises a processing circuit, a communication circuit or a storage circuit. [20] Device according to one of claims 11-19, further comprising a housing for an integrated circuit, wherein the housing for the integrated circuit comprises the chip for the integrated circuit and the housing substrate. [21] Device according to claim 20, further comprising a printed circuit board, wherein the housing of the integrated circuit is electrically coupled to the printed circuit board. [22] Device according to claim 21, wherein the device is a mobile phone, a portable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit or a device. [23] Method comprising the following: Receiving a glass core; Forming a multitude of glass layers on the glass core, with some of the glass layers being formed above the glass core and some of the glass layers being formed below the glass core; Forming a multitude of conductive pathways in the glass core and at least some of the glass layers; and Forming a multitude of conductive contacts on one or more surfaces of the glass layers. [24] The method of claim 23, further comprising: Attaching a chip with an integrated circuit to at least some of the conductive contacts. [25] The method of claim 23, further comprising: Forming a cavity in the glass core and / or at least some of the glass layers; and Embedding a chip with an integrated circuit into the cavity.

Images