Display panel and display device

Abstract

A display field and a display device. The display field comprises a pixel driver circuit, the pixel driver circuit comprising a second transistor. The display field further comprises a base substrate, an auxiliary layer, and an active layer, the auxiliary layer being located on one side of the base substrate and connected to a first signal; the active layer being located on the side of the auxiliary layer facing away from the base substrate, and the active layer comprising a second active section, the second active section being used to form a channel region of the second transistor, and the orthographic projection of the auxiliary layer onto the base substrate covering the orthographic projection of the second active section onto the base substrate.In the display field, a provided auxiliary layer can prevent free charges in a lower layer from diffusing into a channel area of ​​a second transistor at high temperature, thus avoiding the influence of the free charges on the properties of the second transistor and improving an abnormal display of the display field caused by the diffusion of free charges after a high-temperature reliability test.

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of display technology and in particular to a display panel and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) is an active light-emitting display device and offers advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness and thinness, and flexibility. Currently, the application of OLED displays is becoming increasingly widespread. However, OLED displays have been found to have a color shift issue, as demonstrated in reliability tests.

[0003] It should be noted that the information disclosed in the above background section is only intended to deepen the understanding of the background of the present disclosure and may therefore contain information of a related nature not known to the person skilled in the art in this field. SUMMARY

[0004] One objective of the present disclosure is to overcome the aforementioned shortcomings of the prior art and to provide a display field and a display device.

[0005] According to one aspect of the present disclosure, a display field is provided; the display field comprises a pixel driver circuit, the pixel driver circuit comprises a second transistor and a driver transistor, and a first electrode of the second transistor is connected to a gate of the driver transistor; the display field further comprises: a base substrate; an auxiliary layer located on one side of the base substrate and connected to a first signal; and an active layer located on a side of the auxiliary layer facing away from the base substrate, comprising: a second active section configured to form a channel region of the second transistor; and a third active section configured to form a channel region of the driver transistor;wherein an orthographic projection of the auxiliary layer on the base substrate covers an orthographic projection of the second active section on the base substrate and an orthographic projection of the third active section on the base substrate.

[0006] In an exemplary embodiment of the present disclosure, the display field comprises several pixel driver circuits distributed in an array along a row direction and a column direction, the auxiliary layer comprises several auxiliary units distributed in an array along the row direction and the column direction, an auxiliary unit is provided corresponding to a pixel driver circuit, the second active section comprises a third active subsection and a fourth active subsection, and the auxiliary unit comprises: a first auxiliary section whose orthographic projection on the base substrate covers the orthographic projection of the third active section on the base substrate;and a second auxiliary section, the orthographic projection of which on the base substrate covers an orthographic projection of the third active subsection on the base substrate and an orthographic projection of the fourth active subsection on the base substrate.

[0007] In an exemplary embodiment of the present disclosure, the active layer further comprises: a tenth active section connected between the third active subsection and the fourth active subsection; wherein the orthographic projection of the second auxiliary section on the base substrate does not overlap with an orthographic projection of the tenth active section on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the active layer further comprises: a tenth active section connected between the third active subsection and the fourth active subsection; wherein the second auxiliary section comprises a first auxiliary subsection and a second auxiliary subsection, an orthographic projection of the first auxiliary subsection on the base substrate covers the orthographic projection of the third active subsection on the base substrate and the orthographic projection of the fourth active subsection on the base substrate, and an orthographic projection of the second auxiliary subsection on the base substrate covers an orthographic projection of the tenth active section on the base substrate.

[0009] In an exemplary embodiment of the present disclosure, the display field further comprises: a second conductive layer located on a side of the active layer facing away from the base substrate, wherein the second conductive layer comprises a first conductive block, an orthographic projection of the first conductive block on the base substrate is arranged on the orthographic projection of the tenth active section on the base substrate; a second source-drain metal layer located on a side of the second conductive layer facing away from the base substrate, wherein the second source-drain metal layer comprises a first current line, an orthographic projection of the first current line on the base substrate extends along the column direction, and the first current line is coupled to the first conductive block by a third through-hole;wherein the orthographic projection of the second auxiliary subsection on the base substrate further covers an orthographic projection of the third through-hole on the base substrate.

[0010] In an exemplary embodiment of the present disclosure, the active layer further comprises a first active section connected to a side of the second active section, wherein the first active section is configured to form a channel region of the first transistor; and the auxiliary unit further comprises a fourth auxiliary section connected to the second auxiliary section, wherein an orthographic projection of the fourth auxiliary section on the base substrate covers an orthographic projection of the first active section on the base substrate.

[0011] In an exemplary embodiment of the present disclosure, the first active section comprises a first active subsection and a second active subsection; and the active layer further comprises a ninth active section connected between the first active subsection and the second active subsection; wherein the orthographic projection of the fourth auxiliary section on the base substrate further covers an orthographic projection of the ninth active section on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a fourth transistor; the active layer further comprises a fourth active section configured to form a channel region of the fourth transistor; the auxiliary unit further comprises: a third interconnect section connected between two auxiliary units adjacent in the column direction, wherein an orthographic projection of the third interconnect section on the base substrate extends along the column direction; and a sixth auxiliary section connected to the third interconnect section, wherein an orthographic projection of the sixth auxiliary section on the base substrate extends along the row direction and covers an orthographic projection of the fourth active section on the base substrate.

[0013] In an exemplary embodiment of the present disclosure, the auxiliary unit further comprises: a third connecting section that is connected between two auxiliary units adjacent in the column direction, and an orthographic projection of the third connecting section on the base substrate extends along the column direction; and a first connecting section that is connected in the column direction to a side of the second auxiliary section facing away from the first auxiliary section, wherein in two auxiliary units adjacent in the column direction, a third connecting section of an auxiliary unit in a previous row is connected to a first connecting section of an auxiliary unit in a subsequent row, and an orthographic projection of the first connecting section on the base substrate does not overlap with an orthographic projection of the first active section on the base substrate.

[0014] In an exemplary embodiment of the present disclosure, the first active section comprises a first active subsection and a second active subsection; and the active layer further comprises a ninth active section connected between the first active subsection and the second active subsection; wherein the orthographic projection of the first connecting section on the base substrate does not overlap with an orthographic projection of the ninth active section on the base substrate.

[0015] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a fourth transistor; the active layer further comprises a fourth active section, and the fourth active section is configured to form a channel region of the fourth transistor; and the auxiliary unit further comprises: a third interconnect section connected between two auxiliary units adjacent in the column direction, and an orthographic projection of the third interconnect section on the base substrate extends along the column direction; and a sixth auxiliary section connected to the third interconnect section, and an orthographic projection of the sixth auxiliary section on the base substrate extends along the row direction and covers an orthographic projection of the fourth active section on the base substrate.

[0016] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a first transistor, and a second electrode of the first transistor is connected to the gate of the driver transistor; the active layer further comprises a first active section connected to one side of the second active section, and the first active section is configured to form a channel region of the first transistor; and the auxiliary unit further comprises: a second interconnect section connected to the first auxiliary section and the second auxiliary section respectively, wherein an orthographic projection of the second interconnect section on the base substrate runs along the line direction, and two auxiliary units adjacent in the line direction are connected by the second interconnect section;a third connecting section that is connected between two auxiliary units adjacent in the column direction, and an orthographic projection of the third connecting section on the base substrate runs along the column direction;and a first connecting section or a fourth auxiliary section connected to a side of the second auxiliary section facing away from the first auxiliary section in the column direction, wherein in two auxiliary units adjacent in the column direction, a third connecting section of an auxiliary unit in a previous row is connected to a first connecting section or a fourth auxiliary section of an auxiliary unit in a next row, wherein an orthographic projection of the first connecting section on the base substrate does not overlap with an orthographic projection of the first active section on the base substrate, and an orthographic projection of the fourth auxiliary section on the base substrate covers the orthographic projection of the first active section on the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the display field further comprises a first source-drain metal layer and / or a second source-drain metal layer located on a side of the active layer facing away from the base substrate, and the first source-drain metal layer and / or the second source-drain metal layer comprises a second current line and / or a first current line whose orthographic projection runs along the column direction, and in a non-display area of ​​the display field, the second current line and / or the first current line is connected to the auxiliary layer via a through-hole.

[0018] In an exemplary embodiment of the present disclosure, the display field further comprises: a second conductive layer located on a side of the active layer facing away from the base substrate, wherein the second conductive layer comprises a first initialization signal line and a second initialization signal line, an orthographic projection of the first initialization signal line on the base substrate extending along the line direction, and an orthographic projection of the second initialization signal line on the base substrate extending along the line direction;and a first source-drain metal layer located on a side of the second conductive layer facing away from the base substrate, wherein the first source-drain metal layer comprises a third initialization signal line and / or a fourth initialization signal line, an orthographic projection of the third initialization signal line on the base substrate runs along the column direction, the third initialization signal line is connected to the first initialization signal line through a first through-hole, an orthographic projection of the fourth initialization signal line on the base substrate runs along the column direction, and the fourth initialization signal line is connected to the second initialization signal line through a second through-hole.

[0019] In an exemplary embodiment of the present disclosure, the display field comprises a first pixel column and a second pixel column, which are distributed sequentially and alternately in the row direction; the orthographic projection of the third initialization signal line on the base substrate is located at least partially in an area where the second pixel column is located, the orthographic projection of the fourth initialization signal line on the base substrate is located in an area where the first pixel column is located, and both the first through-hole and the second through-hole are located in the first pixel column.

[0020] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a storage capacitor, a first electrode of the storage capacitor being connected to the gate of the driver transistor, and a second electrode of the storage capacitor being connected to a second power supply terminal; and the display field further comprises: a first conductive layer located on a side of the active layer facing away from the base substrate, the first conductive layer comprising a second conductive block, an orthographic projection of the second conductive block on the base substrate covering the orthographic projection of the third active section on the base substrate, and the second conductive block being configured to form the first electrode of the storage capacitor;a second conductive layer located on a side of the first conductive layer facing away from the base substrate, the second conductive layer comprising a third conductive block and a first conductive block, an orthographic projection of the third conductive block on the base substrate arranged on the orthographic projection of the second conductive block on the base substrate, the third conductive block configured to form the second electrode of the storage capacitor, an orthographic projection of the first conductive block on the base substrate arranged on the orthographic projection of the tenth active section on the base substrate;and a first source-drain metal layer located on a side of the second conductive layer facing away from the base substrate, the first source-drain metal layer comprising a first power transmission line and a second power transmission line, the first power transmission line being connected to the third conductive block via a through-hole and further connected to a first conductive block in an adjacent pixel driver circuit via a through-hole, the second power transmission line being connected to the third conductive block via a through-hole, and an extent length of an orthographic projection of the second power transmission line on the base substrate along the column direction being greater than an extent length of the first power transmission line on the base substrate along the column direction.

[0021] In an exemplary embodiment of the present disclosure, the first power transmission line comprises a first transmission section, a second transmission section and a third transmission section, both an orthographic projection of the first transmission section on the base substrate and an orthographic projection of the third transmission section on the base substrate extending along the column direction, an orthographic projection of the second transmission section on the base substrate extending along the row direction, and the first transmission section and the third transmission section being connected by the second transmission section;and the first transmission section is connected to the third conductive block and the first power line via a through-hole, and the third transmission section is located in another pixel driver circuit adjacent in the line direction and is connected to the first conductive block via a through-hole.

[0022] In an exemplary embodiment of the present disclosure, the auxiliary unit further comprises a second connecting section, which is connected to the first auxiliary section and the second auxiliary section respectively, an orthographic projection of the second connecting section on the base substrate extends along the line direction, and two auxiliary units adjacent in the line direction are connected by the second connecting section; wherein an orthographic projection of the second transmission section on the base substrate partially overlaps with an orthographic projection of the second connecting section on the base substrate.

[0023] In an exemplary embodiment of the present disclosure, the first conductive layer further comprises a gate signal line, the gate signal line comprising a main extension section and an additional section, an orthographic projection of the main extension section on the base substrate extending along the row direction and covering the orthographic projection of the third active subsection on the base substrate, an orthographic projection of the additional section on the base substrate extending along the column direction and covering the orthographic projection of the fourth active subsection on the base substrate, and a substructure of the gate signal line configured to form a gate of the second transistor; the second conductive layer further comprises a first initialization signal line, and an orthographic projection of the first initialization signal line on the base substrate extending along the row direction;and the first source-drain metal layer further comprises a third initialization signal line, an orthographic projection of the third initialization signal line on the base substrate running along the column direction, and the third initialization signal line being connected to the first initialization signal line via a through-hole; wherein a first overlap area is provided between the orthographic projection of the third transmission section on the base substrate and the orthographic projection of the main extension section on the base substrate, a second overlap area is provided between the orthographic projection of the third initialization signal line on the base substrate and the orthographic projection of the auxiliary section on the base substrate, and the orthographic projection of the second auxiliary section on the base substrate covers the first overlap area and the second overlap area.

[0024] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a fifth transistor, a gate of the fifth transistor is connected to an enable signal line, a first electrode of the fifth transistor is connected to a first power supply terminal, and a second electrode of the fifth transistor is connected to a second electrode of the driver transistor; the active layer further comprises: a fifth active section configured to form a channel region of the fifth transistor; a sixteenth active section connected between the fifth active section and the third active section and configured to form the second electrode of the fifth transistor and the second electrode of the driver transistor;and a seventeenth active section connected to a side of the fifth active section facing away from the sixteenth active section and configured to form the first electrode of the fifth transistor; and, the first conductive layer further comprising an enable signal line, an orthographic projection of the enable signal line on the base substrate running along the line direction and covering an orthographic projection of the fifth active section on the base substrate, and a substructure of the enable signal line configured to form the gate of the fifth transistor; wherein the seventeenth active section is connected to the first current line via a through-hole.;

[0025] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a fourth transistor and a sixth transistor, a gate of the second transistor is connected to a gate signal terminal, and a second electrode of the second transistor is connected to the first electrode of the driver transistor, a gate of the fourth transistor is connected to a second reset signal terminal, a first electrode of the fourth transistor is connected to the second electrode of the driver transistor, a second electrode of the fourth transistor is connected to the second electrode of the fifth transistor, a gate of the sixth transistor is connected to the enable signal terminal, a first electrode of the sixth transistor is connected to the first electrode of the driver transistor, and a second electrode of the sixth transistor is connected to an anode of a light-emitting device;The active layer further comprises: a sixteenth active section connected to one side of the third active section and configured to form the second electrode of the driver transistor and the second electrode of the fifth transistor; a fourteenth active section connected via a through-hole to a second bridge section located in a first source-drain metal layer, the second bridge section further connected via a through-hole to the sixteenth active section, and the fourteenth active section configured to form the first electrode of the fourth transistor; a fourth active section connected to the fourteenth active section and configured to form a channel region of the fourth transistor;a fifteenth active section connected to a side of the fourth active section facing away from the fourteenth active section, the fifteenth active section being configured to form the second electrode of the fourth transistor; a fifth active section configured to form a channel region of the fifth transistor; a sixth active section configured to form a channel region of the sixth transistor; a seventh active section configured to form a channel region of the seventh transistor; and the first conductive layer further comprising: a first reset signal line, the orthographic projection of which on the base substrate covers an orthographic projection of the first active section on the base substrate, and a substructure of the first reset signal line configured to form a gate of the first transistor;a gate signal line whose orthographic projection on the base substrate covers the orthographic projection of the second active section on the base substrate, and a substructure of the gate signal line is configured to form the gate of the second transistor; an enable signal line whose orthographic projection on the base substrate covers an orthographic projection of the fifth active section on the base substrate and an orthographic projection of the sixth active section on the base substrate, a substructure of the enable signal line is configured to form the gate of the fifth transistor, and a substructure of the enable signal line is configured to form the gate of the sixth transistor;and a second reset signal line, the orthographic projection of which on the base substrate covers an orthographic projection of the fourth active section on the base substrate and an orthographic projection of the seventh active section on the base substrate, a substructure of the second reset signal line is configured to form the gate of the fourth transistor, and a substructure of the second reset signal line is configured to form a gate of the seventh transistor; wherein the orthographic projection of the first reset signal line on the base substrate, the orthographic projection of the gate signal line on the base substrate, the orthographic projection of the enable signal line on the base substrate, and the orthographic projection of the second reset signal line on the base substrate all extend along the row direction and are sequentially spaced in the column direction;and the orthographic projection of the gate signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate are located on both sides of the orthographic projection of the third active section on the base substrate.

[0026] In an exemplary embodiment of the present disclosure, the display field comprises a pixel driver circuit, the pixel driver circuit comprising a second transistor and a driver transistor, a first electrode of the second transistor is connected to a gate of the driver transistor, and the display field further comprises: a base substrate comprising an organic layer; an auxiliary layer located on one side of the base substrate; an active layer located on a side of the auxiliary layer facing away from the base substrate, and the active layer comprising a second active section configured to form a channel region of the second transistor, and a third active section configured to form a channel region of the driver transistor;wherein an orthographic projection of the auxiliary layer on the base substrate covers an orthographic projection of the second active section on the base substrate and an orthographic projection of the third active section on the base substrate.

[0027] In an exemplary embodiment of the present disclosure, the display field comprises a plurality of pixel driver circuits distributed in an array along a row direction and a column direction, the auxiliary layer comprises a plurality of auxiliary units distributed in an array along the row direction and the column direction, an auxiliary unit is provided corresponding to a pixel driver circuit, and the second active section comprises a third active subsection and a fourth active subsection;and the auxiliary unit comprises a first auxiliary section and a second auxiliary section; an orthographic projection of the first auxiliary section on the base substrate covers the orthographic projection of the third active section on the base substrate; an orthographic projection of the second auxiliary section on the base substrate covers an orthographic projection of the third active subsection on the base substrate and an orthographic projection of the fourth active subsection on the base substrate.

[0028] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a first transistor, and a second electrode of the first transistor is connected to the gate of the driver transistor; the active layer further comprises a first active section connected to one side of the second active section, and the first active section is configured to form a channel region of the first transistor;and the auxiliary unit further comprises a second connecting section and a fourth auxiliary section, the second connecting section being connected to the first auxiliary section and the second auxiliary section respectively, an orthographic projection of the second connecting section on the base substrate runs along the line direction, and two auxiliary units adjacent in the line direction are connected by the second connecting section, the fourth auxiliary section is connected to the second auxiliary section, and an orthographic projection of the fourth auxiliary section on the base substrate covers an orthographic projection of the first active section on the base substrate.

[0029] According to another aspect of the present disclosure, a display device is also provided which includes the display field according to any embodiment of the present disclosure.

[0030] In the display field provided by the present disclosure, the auxiliary layer is provided at the lower end of the active layer, the auxiliary layer is connected to a first signal, and the orthographic projection of the auxiliary layer on the base substrate covers the orthographic projection of the second active section on the base substrate, that is, the auxiliary layer forms a structure to cover the channel region of the second transistor at the lower end of the active layer, so that it can be prevented from free charges in the lower layer diffusing into the channel region of the second transistor at high temperature, thereby avoiding the influence of the free charges on the properties of the second transistor and improving the problem of abnormal display of the display field caused by the diffusion of free charges after a high-temperature reliability test and a copper rod friction test.

[0031] It should be understood that both the foregoing general description and the following detailed description are merely exemplary and explanatory and do not constitute a limitation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which form part of and are incorporated into the description, illustrate embodiments that conform to the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description represent some embodiments of the present disclosure, and other drawings can be derived from these drawings by a person skilled in the art without inventive step. Fig. Figure 1 is a schematic representation of a circuit structure of a pixel driver circuit in a display field according to an embodiment of the present disclosure; Fig. Figure 2 is a time sequence diagram of each node in a control method for the pixel driver circuit in Fig. 1; Fig. 3 is a structural layout of a display field according to an embodiment of the present disclosure; Fig. 4 is a structural layout of the auxiliary layer in Fig. 3; Fig. 5 is a structural layout of the active layer in Fig. 3; Fig. 6 is a stacked layout of the auxiliary layer and the active layer in Fig. 3; Fig. 7 is a schematic representation of connections of the auxiliary layer along the row direction and the column direction in Fig. 3; Fig. 8 is a structural layout of the auxiliary layer in Fig. 3 according to another embodiment; Fig. 9 is a schematic representation of an auxiliary layer for blocking charge according to an embodiment of the present disclosure; Fig. 10 is a structural layout of a display field according to another embodiment of the present disclosure; Fig. 11 is a structural layout of the auxiliary layer in Fig. 10; Fig. 12 is a stacked layout of the auxiliary layer and the active layer in Fig. 10; Fig. Figure 13 is a stacked layout of the auxiliary layer, the active layer, and the second conductive layer in Fig. 10; Fig. Figure 14 is a structural layout of a display field according to another embodiment of the present disclosure; Fig. 15 is a structural layout of the auxiliary layer in Fig. 14; Fig. 16 is a stacked layout of the auxiliary layer and the active layer in Fig. 14; Fig. Figure 17 is a schematic representation of connections of the auxiliary layer along the row direction and the column direction in Fig. 14; Fig. 18 is a structural layout of a display field according to another embodiment of the present disclosure; Fig. 19 is a structural layout of the auxiliary layer in Fig. 18; Fig. 20 is a stacked layout of the auxiliary layer and the active layer in Fig. 18; Fig. 21 is a structural layout of a display field according to another embodiment of the present disclosure; Fig. 22 is a structural layout of the auxiliary layer in Fig. 21; Fig. 23 is a stacked layout of the auxiliary layer and the active layer in Fig. 21; Fig. Figure 24 is a stacked layout of the auxiliary layer, the active layer, and the second conductive layer in Fig. 21; Fig. 25 to Fig. 34 are the auxiliary layer and stack layouts of the auxiliary layer and the active layer according to other embodiments of the present disclosure; Fig. 35 is a structural layout of an auxiliary layer according to another embodiment of the present disclosure; Fig. 36 is a structural layout of the first conductive layer in Fig. 3; Fig. Figure 37 is a structural layout of the second conductive layer in Fig. 3; Fig. 38 is a structural layout of the first source-drain metal layer in Fig. 3; Fig. 39 is a structural layout of the second source-drain metal layer in Fig. 3; Fig. 40 is a stacked layout of the auxiliary layer, the active layer, and the first source-drain metal layer in Fig. 3; Fig. 41 is a stacked layout of the auxiliary layer, the first conductive layer, and the first source-drain metal layer in Fig. 3; Fig. 42 is a cross-sectional image along line AA in Fig. 3. DETAILED DESCRIPTION

[0033] Exemplary embodiments are now described in more detail with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in a multitude of forms and should not be interpreted as limited to those presented here. On the contrary, these embodiments are provided to ensure that this disclosure is comprehensive and complete, and that the concepts of the exemplary embodiments are fully conveyed to the person skilled in the art in this field. The same reference numerals in the figures denote the same or similar structures, which is why their detailed description is omitted. Furthermore, the figures are merely schematic representations of the present disclosure and are not necessarily drawn to scale.

[0034] Fig. Figure 1 is a schematic representation of a circuit structure of a pixel driver circuit in a display field according to an embodiment of the present disclosure. The pixel driver circuit can comprise a first transistor T1, a second transistor T2, a driver transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C.Among these, a first electrode of the first transistor T1 is connected to a first initialization signal terminal Vinit1, a second electrode of the first transistor T1 is connected to a first node N1, and a gate of the first transistor T1 is connected to a first reset signal terminal Reset (N); a first electrode of the second transistor T2 is connected to a gate of the driver transistor T3, a second electrode of the second transistor T2 is connected to a first electrode of the driver transistor, and a gate of the second transistor T2 is connected to a gate signal terminal Gate; the gate of the driver transistor T3 is connected to the first node N1; a second electrode of the fourth transistor T4 is connected to a data signal terminal V. Dataconnected, a first electrode of the fourth transistor T4 is connected to the second electrode of the driver transistor T3, and a gate of the fourth transistor T4 is connected to the gate signal terminal Gate; a second electrode of the fifth transistor T5 is connected to the second electrode of the driver transistor T3, a first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, and a gate of the fifth transistor T5 is connected to an enable signal terminal EM; a first electrode of the sixth transistor T6 is connected to the first electrode of the driver transistor T3, and a gate of the sixth transistor T6 is connected to the enable signal terminal EM;A first electrode of the seventh transistor T7 is connected to a second initialization signal terminal Vinit2, a second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6, and a gate of the seventh transistor T7 is connected to a second reset signal terminal Reset (n+1); a first electrode of the storage capacitor C is connected to the first node N1, and a second electrode of the storage capacitor C is connected to the first power supply terminal VDD. The pixel driver circuit can be connected to a light source OLED to drive the light source OLED to illuminate, and the light source OLED can be connected between the second electrode of the sixth transistor T6 and a second power supply terminal VSS. Among these, each transistor in the present disclosure can be a P-type transistor.For example, the first transistor T1 through the seventh transistor T7 can each be a P-type low-temperature polycrystalline transistor. The P-type low-temperature polycrystalline transistor exhibits relatively high charge carrier mobility, which facilitates the implementation of a display array with high resolution, high response speed, high pixel density, and high aperture. Depending on the actual situation, the same or different voltage signals can be output from the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2.

[0035] It should be noted that the transistors used in the embodiments of the present disclosure can all be thin-film transistors or field-effect transistors, or other devices with the same properties. In the present description, the first electrode can be a drain electrode, the second electrode can be a source electrode; or the first electrode can be a source electrode, and the second electrode can be a drain electrode.

[0036] Fig. 2 is a time sequence diagram of each node in the control method for the pixel driver circuit in Fig. 1. As in Fig. In Figure 2, Gate represents the time sequence of the gate signal terminal Gate, Re1 represents the time sequence of the first reset signal terminal Reset (n), Re2 represents the time sequence of the second reset signal terminal Reset (n+1), EM represents the time sequence of the enable signal terminal EM, and Da represents the time sequence of the data signal terminal V DataThe control method for the pixel driver circuit can comprise a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light emission stage t4. In the first reset stage t1, a low-level signal is output from the first reset signal terminal Reset (n), the first transistor T1 is switched on, and a first initialization signal is input from the first initialization signal terminal Vinit1 to the first node N1. In the compensation stage t2, a low-level signal is output from the gate signal terminal Gate, the second transistor T2 and the fourth transistor T4 are switched on, and a data signal is input from the data signal terminal V Data output to calculate the voltage Vdata+Vth (i.e., the sum of the voltages V Dataand the voltage Vth) to the first node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the driver transistor T3. In the second reset stage t3, a low-level signal is output from the second reset signal terminal Reset (n+1), the seventh transistor T7 is switched on, and a second initialization signal is input from the second initialization signal terminal Vinit2 to the second electrode of the sixth transistor T6. In the light emission stage t4, a low-level signal is output from the enable signal terminal EM, the sixth transistor T6 and the fifth transistor T5 are switched on, and the driver transistor T3 provides a drive current under the influence of the voltage Vdata+Vth stored in the storage capacitor C, so that the light-emitting device OLED emits light.

[0037] According to the output current formula for the driver transistor I = (µWCox / 2L) (Vgs-Vth)2 , where µ is the charge carrier mobility, Cox is the gate storage capacity per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the voltage difference between the gate and source of the driver transistor, and Vth is the threshold voltage of the driver transistor, the output current of the driver transistor in the pixel driver circuit of the present disclosure is I = (µWCox / 2L) (Vdata+Vth-Vdd-Vth) 2 In the pixel driver circuit, the influence of the change in the threshold voltage of the driver transistor on the output current of the driver transistor can be avoided.

[0038] In the prior art, the light emission efficiency of the light-emitting device is always higher to meet the requirements for a longer lifespan and lower power consumption of the display device. However, excessively high light emission efficiency makes the light-emitting device more sensitive to the characteristic changes of the TFT, and the properties of the TFT in the display field can be affected after a reliability test. Furthermore, since the light emission efficiency of each device varies, the problem of color shift in the display field arises because the charge migrates into the active layer poly after a reliability test or a copper rod friction test.Additionally, when a user uses an end product such as a mobile phone, static electricity can accumulate on the display panel. If the user uses the screen frequently and for extended periods, this static charge can affect the TFT's properties, potentially causing a local color shift defect at the point where the static electricity is collected. The display panel described in this disclosure is used to address these problems.

[0039] The display array provided by the present disclosure can comprise a plurality of pixel driver circuits distributed in an array along a row direction X and a column direction Y. The pixel driver circuit is configured to drive the light-emitting device to emit light. The row direction X intersects the column direction Y. The pixel driver circuit can include a second transistor T2 and a driver transistor T3, and a first electrode of the second transistor T2 is connected to a gate of the driver transistor T3. The pixel driver circuit can be configured as shown in Fig. Figure 1 is shown. However, in other exemplary embodiments, the pixel driver circuit in the display field may also have a different structure, such as a structure of 8T1C, 9T1C or the like. Fig. Figure 3 is a structural layout of a display field according to an embodiment of the present disclosure, Fig. 4 is a structural layout of the auxiliary layer in Fig. 3, Fig. 5 is a structural layout of the active layer in Fig. 3, Fig. 6 is a stacked layout of the auxiliary layer and the active layer in Fig. 3, Fig. 7 is a schematic representation of connections of the auxiliary layer along the row direction and the column direction in Fig. 3, and Fig. 8 is a structural layout of the auxiliary layer in Fig. 3 according to another embodiment. As in Fig. 3 to Fig. As shown in Figure 8, the display field can further comprise a base substrate, an auxiliary layer BSM, and an active layer Poly; wherein the auxiliary layer BSM is located on one side of the base substrate and the auxiliary layer BSM may or may not be connected to a first signal; the active layer Poly is located on a side of the auxiliary layer BSM facing away from the base substrate, the active layer Poly comprises a second active section POL2 and a third active section POL3, the second active section POL2 is configured to form a channel region of the second transistor T2, and the third active section POL3 is configured to form a channel region of the driver transistor T3; and an orthographic projection of the auxiliary layer BSM on the base substrate covers an orthographic projection of the second active section POL2 on the base substrate and an orthographic projection of the third active section POL3 on the base substrate.

[0040] In the display field provided by the present disclosure, the auxiliary layer BSM is provided at the lower end of the active layer Poly, and the orthographic projection of the auxiliary layer BSM on the base substrate covers the orthographic projection of the second active section POL2 on the base substrate, that is, the auxiliary layer BSM forms a structure for covering the channel region of the second transistor T2 at the lower end of the active layer Poly, so that it can be prevented from free charges in the lower layer diffusing into the channel region of the second transistor T2 at high temperature, thereby avoiding the influence of the free charges on the properties of the second transistor T2 and improving the problem of abnormal display of the display field caused by the diffusion of free charges after a high-temperature reliability test and a copper rod friction test.

[0041] The base substrate of the present disclosure can be a flexible base substrate; for example, the base substrate can be a flexible substrate made of a PI material. A large amount of free charges is present in the flexible base substrate, and after the temperature rise, the free charges can diffuse into the channel region of the transistor, leading to a forward drift of the transistor's threshold voltage. In the example of the transistor described in Fig. In the pixel driver circuit shown, after a forward drift of the threshold voltage of the second transistor T2, the voltage at the first node N1 can be reduced, thus correspondingly reducing the gate-source voltage of the driver transistor T3 and increasing the drive current provided by the pixel driver circuit. This results in a brighter screen than before the reliability test. Furthermore, since the light emission efficiency of the G-subpixel is highest, the brighter display after a friction test is generally described as a greenish display after the test. This phenomenon is more easily perceptible to the human eye during low grayscale displays; that is, the phenomenon is more obvious during low grayscale levels.

[0042] The orthographic projection of a certain structure A on the base substrate, which covers the orthographic projection of the other structure B on the base substrate in the present disclosure, can be understood as meaning that the contour of the projection of structure B on the plane of the base substrate lies completely within the contour of the projection of structure A on the same plane. In the present disclosure, the orthographic projection of the auxiliary layer BSM on the base substrate covers the orthographic projection of the second active section POL2 on the base substrate; that is, the contour of the orthographic projection of the second active section POL2 on the base substrate lies completely within the contour of the orthographic projection of the auxiliary layer BSM on the base substrate.In this way, the auxiliary layer BSM forms a structure to cover the channel area of ​​the second transistor T2 at the lower end of the active layer Poly. As shown in . Fig. As shown in Figure 9, the free charge can be trapped by the auxiliary layer BSM and cannot diffuse into the active layer Poly, thus ensuring the channel stability of the second transistor T2 and avoiding the problem of forward drift of the threshold voltage of the second transistor T2, thereby reducing the characteristic difference of the transistor after the high-temperature reliability test and improving the problem of abnormal display of the display field after the high-temperature reliability test.

[0043] For example, the orthographic projection of the auxiliary layer BSM on the base substrate, which covers the orthographic projection of the second active section POL2 on the base substrate, corresponds to the presence of an auxiliary layer structure beneath the second active section POL2. This auxiliary layer structure lies opposite the second active section POL2 and has a larger area than the second active section POL2. That is, the boundary of the auxiliary layer structure extends beyond the boundary of the second active section POL2. Clearly, the auxiliary layer structure can block the diffusion of free charge to the second active section POL2, thereby reducing the characteristic difference of the second transistor T2 before and after the high-temperature reliability test and preventing the problem of abnormal readings after the reliability test.

[0044] It should be noted that whether or not the auxiliary layer BSM is connected to the first signal in the present disclosure, it can prevent free charges from entering the channel region of the transistor. If the auxiliary layer BSM is not connected to the first signal, since it has no potential, it will not form a parasitic effect with other electrical conductors, and thus the transistor will not be affected. If the auxiliary layer BSM is connected to the first signal, it forms an equipotential surface, so the barrier effect on the free charge can be improved.Secondly, the transistor's threshold voltage in the pixel circuit can drift after prolonged operation. This threshold voltage can be corrected and restored by setting the auxiliary layer and connecting it to a voltage signal, thus also improving the display effect of the display field. Among these signals, the first signal can be a constant voltage signal. For example, the first signal could be a voltage signal coming from the first power supply terminal, VDD. Fig. 1 is provided, or can be an initialization signal that is supplied from the first initialization signal terminal Vinit1 or the second initialization signal terminal Vinit2 in Fig. 1 is provided.

[0045] Furthermore, the auxiliary layer BSM in the present disclosure can be a metallic auxiliary layer formed from a metallic material, such as at least one of silver, copper, molybdenum, titanium, aluminum, or the like. The auxiliary layer BSM can also be a transparent conductive layer, such as at least one of indium tin oxide (ITO), cadmium stannate (TCO), graphene, metal nanowires, carbon nanotubes, or the like. Alternatively, the auxiliary layer BSM can also be an auxiliary layer formed after a conduction treatment of a semiconductor material layer, for example, a semiconductor material such as doped polysilicon or amorphous silicon, etc. Alternatively, the auxiliary layer BSM can be a semiconductor material, such as monocrystalline silicon, amorphous silicon, polysilicon, microcrystalline silicon, or the like. The material of the auxiliary layer BSM is not particularly limited in the present disclosure.

[0046] The solution to the present disclosure is further described below with reference to the accompanying drawings.

[0047] As in Fig. 3 and Fig. As shown in Figure 5, the active layer Poly can comprise a first active section POL1 through a nineteenth active section POL19. The first active section POL1 can be configured to form a channel region of the first transistor T1, the second active section POL2 can be configured to form a channel region of the second transistor T2, the third active section POL3 can be configured to form a channel region of the driver transistor T3, and the fourth active section POL4 through the seventh active section POL7 are each configured to form channel regions of the fourth transistor T4 through the seventh transistor T7. The active layer Poly in the present disclosure can form the various transistors in the pixel driver circuit with the third active section POL3 at its center.The active layer Poly in the present disclosure can be formed from a polysilicon semiconductor material, and accordingly the transistor in the display field of the present disclosure can be a P-type low-temperature polysilicon thin-film transistor.

[0048] In the exemplary embodiment, the first transistor T1 and the second transistor T2 can have dual-gate structures. Therefore, the first active section POL1 can comprise a first active subsection POL1-1 and a second active subsection POL1-2. The first active subsection POL1-1 and the second active subsection POL1-2 are configured to each form two channel regions of the first transistor T1, and the first active subsection POL1-1 and the second active subsection POL1-2 are connected by the ninth active section POL9. That is, the ninth active section POL9 is configured to connect the two channels of the first transistor T1, thereby forming a conduction structure T1M between the two channels of the first transistor T1.The second active section POL2 can include a third active subsection POL2-3 and a fourth active subsection POL2-4. The third active subsection POL2-3 and the fourth active subsection POL2-4 are each configured to form two channel regions of the second transistor T2. The third active subsection POL2-3 and the fourth active subsection POL2-4 can be connected by the tenth active section POL10. That is, the tenth active section POL10 is configured to connect the two channels of the second transistor T2, thereby forming a conduction structure T2M between the two channels of the second transistor T2.

[0049] The eleventh active section, POL11, is connected between the first active subsection, POL1-1, and the fourth active subsection, POL2-4, and can be configured to form the second electrode of the first transistor, T1, and the first electrode of the second transistor, T2. The eleventh active section, POL11, can be connected via a through-hole to the first bridge section 31 of the first source-drain metal layer, SD1, to connect the second electrode of the first transistor, T1, and the first electrode of the second transistor, T2, to the gate of the driver transistor, T3, through the first bridge section 31.

[0050] The twelfth active section, POL12, can be configured to form the second electrode of the first transistor, T1. In an exemplary embodiment, the display field can comprise a first pixel column, P1, and a second pixel column, P2, distributed sequentially and alternately along the row direction, X. In each pixel driver circuit of the first pixel column, P1, the twelfth active section, POL12, can be connected via a through-hole to the third initialization signal line, Vinit3, in the first source-drain metal layer, SD1, to connect the twelfth active section, POL12, to the first initialization signal line, Vinit1, via the third initialization signal line, Vinit3.In each pixel driver circuit of the second pixel column P2, the twelfth active section POL12 can be connected via a through hole to the third bridge section 33 in the first source-drain metal layer SD1 in order to connect the twelfth active section POL12 through the third bridge section 33 to the first initialization signal line Vinit1.

[0051] The thirteenth active section, POL13, is connected between the third active subsection, POL2-3, and the third active section, POL3. The thirteenth active section, POL13, can be configured to form the second electrode of the second transistor, T2, the first electrode of the sixth transistor, T6, and the first electrode of the driver transistor, T3.

[0052] The sixteenth active section, POL16, is connected between the fifth active section, POL5, and the third active section, POL3. The sixteenth active section, POL16, can be configured to form the second electrode of the driver transistor, T3, and the second electrode of the fifth transistor, T5.

[0053] The seventeenth active section POL17 is connected to the side of the fifth active section POL5 facing away from the sixteenth active section POL16, and the seventeenth active section POL17 can be configured to form the first electrode of the fifth transistor T5. The seventeenth active section POL17, which is located in each pixel driver circuit of the first pixel column P1, can be connected via a through-hole to the first power transmission line VDDL1 in the first source-drain metal layer SD1, in order to be connected via the first power transmission line VDDL1 to the first power transmission line VDD in the second source-drain metal layer SD2.The seventeenth active section POL17, located in the second pixel column P2, can be connected via a through hole to the second power transmission line VDDL2 in the first source-drain metal layer SD1, in order to be connected via the second power transmission line VDDL2 to the first power line VDD in the second source-drain metal layer SD2, so that the first electrode of the fifth transistor T5 is connected via the first power transmission line VDDL1 and the second power transmission line VDDL2 respectively to the first power supply terminal.

[0054] The fourteenth active section POL14 and the fifteenth active section POL15 are connected to both sides of the fourth active section POL4. The fourteenth active section POL14 can be configured to form the first electrode of the fourth transistor T4, and the fifteenth active section POL15 can be configured to form the second electrode of the fourth transistor T4. The fourteenth active section POL14 can be connected via a through-hole to the second bridge section 32 in the first source-drain metal layer SD1 to connect the first electrode of the fourth transistor T4 to the second electrode of the driver transistor T3 via the second bridge section 32.The fifteenth active section POL15 can be connected via a through hole to a data transmission section VdataL located in the first source-drain metal layer SD1, in order to be connected via the data transmission section VdataL to the data signal line Vdata in the second source-drain metal layer SD2, thereby connecting the second electrode of the fourth transistor T4 to the data signal terminal.

[0055] The eighteenth active section POL18 is connected between the sixth active section POL6 and the seventh active section POL7. The eighteenth active section POL18 can be configured to form the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The eighteenth active section POL18 can be connected via a through-hole to the anode transfer section 35 in the first source-drain metal layer SD1 to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the anode of the light-emitting device via the anode transfer section 35.

[0056] The nineteenth active section POL19 is connected to the other side of the seventh active section POL7, the nineteenth active section POL19 can be configured to form the first electrode of the seventh transistor T7, and the nineteenth active section POL19 can be connected via a through hole to the second initialization signal line Vinit2 in the second conductive layer Gate2 to connect the first electrode of the seventh transistor T7 to the second initialization signal terminal.

[0057] As in Fig. 3 and Fig. As shown in Figure 4, in an exemplary embodiment the auxiliary layer BSM can comprise a plurality of auxiliary units BSMO, the plurality of auxiliary units BSMO are distributed along the row direction and the column direction in an array, and a pixel driver circuit is accordingly equipped with an auxiliary unit BSMO.

[0058] As in Fig. As shown in Figure 4, the auxiliary unit BSMO can include a second auxiliary section B2. The second auxiliary section B2 can be arranged corresponding to the second active section POL2, that is, the second auxiliary section B2 is arranged below the second active section POL2. As described above, the second transistor T2 in the display field of this disclosure can have a double-gate structure. As shown in Fig. As shown in Figure 6, the orthographic projection of the second auxiliary section B2 on the base substrate can cover both the orthographic projection of the third active subsection POL2-3 and the orthographic projection of the fourth active subsection POL2-4 on the base substrate. In this way, the channel region of the second transistor T2 can be isolated from the free charge in the lower layer by the second auxiliary section B2. Furthermore, in this exemplary embodiment, the orthographic projection of the second auxiliary section B2 on the base substrate does not overlap with the orthographic projection of the tenth active section POL10 on the base substrate; that is, the second auxiliary section B2 does not block the tenth active section POL10.In other words, the auxiliary unit BSMO only blocks the channel area of ​​the second transistor T2, but does not block the conduction structure T2M between the two channels of the second transistor T2. For example, as in . Fig. As shown in Figure 4, the second auxiliary section B2 is provided with a recess B0, and the orthographic projection of the tenth active section POL10 on the base substrate is within the orthographic projection of the recess B0 on ​​the base substrate, so that the second auxiliary section B2 does not block the tenth active section POL10.

[0059] As in Fig. 4 and Fig. As shown in Figure 6, in the exemplary embodiment, the auxiliary unit BSMO can further comprise a first auxiliary section B1, which is connected to the second auxiliary section B2, and the first auxiliary section B1 is positioned corresponding to the third active section POL3. The orthographic projection of the first auxiliary section B1 onto the base substrate can cover the orthographic projection of the third active section POL3 onto the base substrate. That is, the auxiliary layer BSM is further provided with a metal insulation structure at the position corresponding to the channel area of ​​the driver transistor T3, which blocks the channel area of ​​the driver transistor T3. In this way, the auxiliary layer BSM can prevent charge generated by friction from entering the third active section POL3, thus avoiding the problem of a brighter display after a copper rod friction test and a high-temperature reliability test.

[0060] It is to be understood that the orthographic projection of a certain structure A on the base substrate, which covers the orthographic projection of the other structure B on the base substrate in the present disclosure, can be understood as meaning that the contour of the projection of structure B on the plane of the base substrate is completely within the contour of the projection of structure A on the same plane.

[0061] As in Fig. As shown in Figure 4, in an exemplary embodiment, the auxiliary unit BSMO can further comprise a first connecting section B11 to a third connecting section B13. The first connecting section B11 is connected to the side of the second auxiliary section B2 facing away from the first auxiliary section B1 along the column direction, and the orthographic projection of the first connecting section B11 on the base substrate does not overlap with the orthographic projection of the first active section POL1 on the base substrate. That is, the area covered by the orthographic projection of the first connecting section B11 on the base substrate is avoided by the area covered by the orthographic projection of the first active section POL1 on the base substrate. In other words, no auxiliary layer structure is provided beneath the first active section POL1.

[0062] The second connecting section B12 is connected to the side of the first auxiliary section B1 in the row direction, and the orthographic projection of the second connecting section B12 on the base substrate can extend along the row direction. The third connecting section B13 is connected to the side of the first auxiliary section B1 facing away from the second auxiliary section B2 in the column direction, and the orthographic projection of the third connecting section B13 on the base substrate runs along the column direction. As in Fig. As shown in Figure 7, in two auxiliary units BSMO adjacent in the row direction, the second connection section B12 in one auxiliary unit BSMO is connected to the first auxiliary section B1 in the other auxiliary unit BSMO; that is, the two auxiliary units BSMO adjacent in the row direction are connected by the second connection section B12. In the two auxiliary units BSMO adjacent in the column direction, the third connection section B13 in the previous row is connected to the first connection section B11 in the next row; that is, the two auxiliary units BSMO adjacent in the column direction are connected by the third connection section B13. Therefore, the various auxiliary units BSMO in the auxiliary layer BSM form a crisscrossing lattice structure, and the lattice structure can reduce the IR drop of the first signal connected to the lattice structure, thereby reducing the voltage drop loss.Furthermore, an equipotential surface is formed in the grid structure created by the auxiliary layer BSM, so that the auxiliary effect on the free charge in the active layer can be improved, which is advantageous for the characteristic stability of each transistor in the pixel driver circuit.

[0063] Furthermore, in an exemplary embodiment, the auxiliary layer BSM may not be connected to the first signal. For example, as in Fig. As shown in Figure 8, the auxiliary unit BSMO cannot include a connecting section; that is, each auxiliary section in the auxiliary unit BSM can be an isolated structure. For example, in Fig. 8. The first auxiliary section B1 and the second auxiliary section B2 are not connected to each other, two adjacent auxiliary units BSMO are also not connected to each other, and the free charge can also be prevented from passing through the independent auxiliary sections into the transistors at the corresponding positions. Furthermore, it is to be understood that in Fig. Figure 8 only describes that the auxiliary section is provided below the second transistor T2 and the driver transistor T3, and the auxiliary unit BSMO may further include more isolated auxiliary sections to block the various transistors, which is not explained in detail here.

[0064] A particular structure A, extending along the B-direction as described in the present disclosure, refers to A comprising a main section and a sub-section connected to the main section; the main section being a body in the form of a line, a line segment, or a strip; the main section extending along the B-direction; and the length of the main section extending along the B-direction being greater than the length of the sub-section extending along other directions.

[0065] Fig. 10 is a structural layout of a display field according to another embodiment of the present disclosure; Fig. 11 is a structural layout of the auxiliary layer in Fig. 10; Fig. 12 is a stacked layout of the auxiliary layer and the active layer in Fig. 10; and Fig. Figure 13 is a stacked layout of the auxiliary layer, the active layer, and the second conductive layer in Fig. 10. The active layer Poly to the second source-drain metal layer SD2 in the in Fig. The 10 display fields shown are equipped with all the features that define the active layer Poly up to the second source-drain metal layer SD2 in the display field. Fig. 3 correspond. Furthermore, it should be understood that the in Fig. 13 The through-hole shown is an insulating layer provided on the second conductive layer Gate2, and the metal structure corresponding to the through-hole position in the Gate2 layer is connected through the through-hole to a corresponding structure in the first source-drain metal layer SD1.

[0066] Based on the above embodiments, as described in Fig. 10 and Fig. As shown in Figure 11, in the exemplary embodiment, the second auxiliary section B2 comprises a first auxiliary subsection B21 and a second auxiliary subsection B22. The orthographic projection of the first auxiliary subsection B21 on the base substrate covers the orthographic projection of the third active subsection POL2-3 on the base substrate and the orthographic projection of the fourth active subsection POL2-4 on the base substrate. The orthographic projection of the second auxiliary subsection B22 on the base substrate covers the orthographic projection of the tenth active section POL10 on the base substrate. That is, a corresponding auxiliary subsection is also present under the conduction structure T2M between the two channels of the second transistor T2 for charge blocking.Therefore, in the exemplary embodiment, the second auxiliary section B2 not only blocks the two channels of the second transistor T2, but also blocks the conduction structure T2M between the two channels of the second transistor T2, so that the auxiliary unit BSM0 can further prevent charge from entering the conduction structure T2M, which is connected between the two channels of the second transistor T2. Since the second transistor T2 is switched on in the data write stage, it has a significant influence on the drive current provided by the drive circuit.Therefore, in the exemplary embodiment, by providing the second auxiliary subsection B22, the overall stability of the second transistor T2 can be further improved, and the characteristic shift of the second transistor T2 before and after the high-temperature reliability test and the copper rod friction test can be avoided, thereby further ensuring that the problem of color shift of the display field before and after the test cannot occur.

[0067] Furthermore, as in Fig. As shown in Figure 13, in an exemplary embodiment the second conductive layer Gate2 is generally provided with a first conductive block 21, the first conductive block 21 is located above the tenth active section POL10, and the first conductive block 21 is connected via the third through-hole H3 in the interlayer dielectric layer to the first current line VDD in the second source-drain metal layer SD2 in order to provide the first conductive block 21 with a stable voltage source through the first current line VDD, thereby enabling voltage stabilization for the tenth active section POL10 to be carried out by the first conductive block 21.Based on this, the orthographic projection of the second auxiliary subsection B22 on the base substrate further covers the orthographic projection of the third through-hole H3 on the base substrate. That is, the area covered by the orthographic projection of the third through-hole H3 on the base substrate lies entirely within the area covered by the orthographic projection of the second auxiliary subsection B22 on the base substrate. This ensures a flat auxiliary layer structure beneath the third through-hole H3, thus preventing any thickness step difference beneath the third through-hole H3 and avoiding deformation of the third through-hole H3. If the third through-hole H3 is deformed, a change in the capacitance of the auxiliary layer BSM and the second conductive layer Gate2 at the conduction structure T2M of the second transistor T2 can occur.Therefore, if the third through-hole H3 is deformed due to process variations, a problem of display striping between different subpixels can occur due to a capacitance difference between the conducting structure T2M of the second transistor T2 and the second conductive layer Gate2. In the exemplary embodiment, the area covered by the orthographic projection of the third through-hole H3 on the base substrate is entirely within the area covered by the orthographic projection of the second auxiliary subsection B22 on the base substrate, in order to avoid the Mura display defect caused by different capacitances of the auxiliary layer BSM and the second conductive layer Gate2 at the tenth active section POL10 between different subpixels.

[0068] Fig. 14 is a structural layout of a display field according to another embodiment of the present disclosure, Fig. 15 is a structural layout of the auxiliary layer in Fig. 14, Fig. 16 is a stacked layout of the auxiliary layer and the active layer in Fig. 14, and Fig. 17 is a schematic diagram of connections of the auxiliary layer along the row direction and the column direction in Fig. 14. The active layer Poly to the second source-drain metal layer SD2 in the in Fig. The 14 display fields shown are equipped with all the features that the active layer Poly up to the second source-drain metal layer SD2 in the display field in Fig. 3 correspond.

[0069] Based on the foregoing embodiments, as described in Fig. 14, Fig. 15 and Fig. 17 shown, the difference to the one in Fig. The layout structure shown in Figure 3 consists in the fact that, in the exemplary embodiment, the auxiliary unit BSMO can further comprise a fourth auxiliary section B4, which is provided corresponding to the first active section POL1. The fourth auxiliary section B4 is connected to the second auxiliary section B2, and an orthographic projection of the fourth auxiliary section B4 onto the base substrate can cover an orthographic projection of the first active section POL1 onto the base substrate. That is, the auxiliary unit BSMO in the exemplary embodiment is not provided with a first connecting section B11.In this structure, in two auxiliary units BSM0 adjacent in the column direction, the third connecting section B13 in the previous row is connected to the fourth auxiliary section B4 in the next row, so that the different auxiliary units BSMO in the same column are sequentially connected, and simultaneously the different auxiliary units BSMO in the same row are also sequentially connected. Therefore, the auxiliary layer BSM in the in . Fig. The layout structure shown in 14 also features a cross-patterned grid structure.

[0070] As described above, the first active section POL1 can comprise the first active subsection POL1-1 and the second active subsection POL1-2. As in Fig. 14 and Fig. As shown in Figure 16, in the exemplary embodiment, the orthographic projection of the fourth auxiliary section B4 on the base substrate can, in particular, cover the orthographic projection of the first active subsection POL1-1 on the base substrate and the orthographic projection of the second active subsection POL1-2 on the base substrate. That is, an area covered by the orthographic projection of the first active subsection POL1-1 on the base substrate and the orthographic projection of the second active subsection POL1-2 on the base substrate is entirely within an area covered by the orthographic projection of the fourth auxiliary section B4 on the base substrate.Therefore, the auxiliary layer BSM blocks the first active section POL1 with the fourth auxiliary section B4 to prevent free charge from entering the first active section POL1 and thus ensure that the characteristics of the first transistor T1 remain stable before and after the high-temperature reliability test and the copper rod friction test. It is known that after free charge enters the channel region of the first transistor T1, a forward shift in the threshold voltage of the first transistor T1 can result. This forward shift in the threshold voltage of the first transistor T1 can also lead to an increase in the drive current, and the increased drive current can result in a higher display brightness than before the reliability test.Therefore, in the exemplary embodiment, by providing the fourth auxiliary section B4 on the auxiliary layer BSM, the stability of the first transistor T1 can be maintained, thereby further avoiding the problem of the display error of the display field before and after the high temperature reliability test, such as a brighter display.

[0071] Based on the preceding embodiment, Fig. 18 a structural layout of a display field according to a further embodiment of the present disclosure, Fig. 19 is a structural layout of the auxiliary layer in Fig. 18, and Fig. 20 is a stacked layout of the auxiliary layer and the active layer in Fig. 18. The active layer Poly to the second source-drain metal layer SD2 in the in Fig. The 18 display fields shown are equipped with all the features that define the active layer Poly up to the second source-drain metal layer SD2 in the display field. Fig. 3 correspond.

[0072] As in Fig. 18 to Fig. As shown in 20, in an exemplary embodiment the difference to the one in Fig. The layout structure shown in Figure 14 consists in the fact that the orthographic projection of the fourth auxiliary section B4 on the base substrate can further cover the orthographic projection of the ninth active section POL9 on the base substrate. As described above, the first transistor T1 is a dual-channel transistor, and the characteristic change of the first transistor T1 can lead to a change in the drive current. In the exemplary embodiment, the orthographic projection of the ninth active section POL9 on the base substrate lies within the orthographic projection of the fourth auxiliary section B4 on the base substrate, so that the fourth auxiliary section B4 also blocks the ninth active section POL9; that is, the fourth auxiliary section B4 also blocks the conduction structure T1M between the two channels of the first transistor T1.Therefore, the fourth auxiliary section B4 can further prevent free charge in the lower layer from entering the conduction structure T1M between the two channels of the first transistor T1, which is advantageous for maintaining the stability of the properties of the first transistor T1 by further avoiding the threshold voltage drift of the first transistor T1, thus avoiding the defect problem of a brighter display of the display field before and after the high temperature reliability test and before and after the copper rod friction test.

[0073] Based on the above embodiments, Fig. 21 a structural layout of a display field according to a further embodiment of the present disclosure; Fig. 22 is a structural layout of the auxiliary layer in Fig. 21; Fig. 23 is a stacked layout of the auxiliary layer and the active layer in Fig. 21; and Fig. Figure 24 is a stacked layout of the auxiliary layer, the active layer, and the second conductive layer in Fig. 21. The active layer Poly to the second source-drain metal layer SD2 in the in Fig. The 21 display fields shown are equipped with all the features that define the active layer Poly up to the second source-drain metal layer SD2 in the display field. Fig. 3 correspond.

[0074] As in Fig. 21 and Fig. As shown in Figure 22, in the exemplary embodiment the second auxiliary section B2 can comprise both the first auxiliary subsection B21 and the second auxiliary subsection B22, and the auxiliary unit BSMO can further comprise a fourth auxiliary section B4. That is, the auxiliary unit BSMO blocks the first transistor T1 while blocking the conduction structure T2M between the two channels of the second transistor T2. Similar to the one shown in Fig. In the layout structure shown in Figure 10, the second auxiliary subsection B22 is connected to the second auxiliary section B2, and the orthographic projection of the second auxiliary subsection B22 on the base substrate covers the orthographic projection of the tenth active section POL10 on the base substrate. That is, the second auxiliary subsection B22 is also provided under the conduction structure T2M between the two channels of the second transistor T2 for charge blocking. Furthermore, as shown in Figure 10, the second auxiliary subsection B22 covers the second auxiliary subsection B22. Fig. As shown in Figure 24, the orthographic projection of the second auxiliary subsection B22 onto the base substrate further corresponds to the orthographic projection of the third through-hole H3 onto the base substrate; that is, an area covered by the orthographic projection of the third through-hole H3 onto the base substrate lies entirely within an area covered by the orthographic projection of the second auxiliary subsection B22 onto the base substrate. Therefore, in the exemplary embodiment, the second auxiliary subsection B22 can perform the same function as the second auxiliary subsection B22 in the one shown in Fig. The layout structure shown in 10 is present.

[0075] Furthermore, as in Fig. 21 and Fig. Figure 22 shows that the fourth auxiliary section B4 is connected to the second auxiliary section B2 in the exemplary embodiment, and the orthographic projection of the fourth auxiliary section B4 on the base substrate can cover the orthographic projection of the first active section POL1 on the base substrate. That is, the fourth auxiliary section B4 can cover the Fig. 14 exhibit the layout structure shown, and accordingly, the advantageous effect of the fourth auxiliary section B4 in the Fig. The layout structure shown in Figure 14 can be used. Alternatively, the orthographic projection of the fourth auxiliary section B4 on the base substrate can cover both the orthographic projection of the first active section POL1 on the base substrate and the orthographic projection of the ninth active section POL9 on the base substrate. That is, the fourth auxiliary section B4 can cover the layout structure shown in Figure 14. Fig. 18 exhibit the layout structure shown, and accordingly the advantageous effect of the fourth auxiliary section B4 can be seen in the Fig. The layout structure shown in section 18 is included. Details will not be described again here.

[0076] Furthermore, based on the foregoing embodiments, the auxiliary unit BSMO can further comprise a sixth auxiliary section B6, the sixth auxiliary section B6 is connected to the third connecting section B13, the sixth auxiliary section B6 is provided corresponding to the fourth active section POL4, and the orthographic projection of the sixth auxiliary section B6 on the base substrate extends along the line direction and covers the orthographic projection of the fourth active section POL4 on the base substrate.

[0077] For example, in some embodiments the auxiliary unit BSMO can be used in Fig. 25 layout structure shown based on the one in Fig. The layout structure shown in section 4 forms the active layer Poly up to the second source-drain metal layer SD2, and all features are provided that define the active layer Poly up to the second source-drain metal layer SD2 in the display field in Fig. 3 correspond. The stack layout of the auxiliary layer BSM and the active layer Poly is as in Fig. 26 shown.

[0078] In some other embodiments, the auxiliary unit BSMO can also perform the functions described in Fig. 27 layout structure shown based on the one in Fig. The layout structure shown in Figure 11 forms the active layer Poly up to the second source-drain metal layer SD2, and all features are provided that define the active layer Poly up to the second source-drain metal layer SD2 in the display field in Figure 11. Fig. 10 correspond. The stack layout of the auxiliary layer BSM and the active layer Poly is as in Fig. 28 shown.

[0079] In some other embodiments, the auxiliary unit BSMO can also perform the functions described in Fig. 29 layout structure shown based on the one in Fig. The layout structure shown in Figure 15 forms the active layer Poly up to the second source-drain metal layer SD2, and all features are provided that the active layer Poly up to the second source-drain metal layer SD2 in the display field in Fig. 14 correspond. The stack layout of the auxiliary layer BSM and the active layer Poly is as in Fig. 30 shown.

[0080] In other embodiments, the auxiliary unit BSMO can also perform the functions described in Fig. 31 layout structure shown based on the one in Fig. The layout structure shown in Figure 19 forms the active layer Poly up to the second source-drain metal layer SD2, and all features are provided that define the active layer Poly up to the second source-drain metal layer SD2 in the display field in Figure 19. Fig. 18 correspond. The stack layout of the auxiliary layer BSM and the active layer Poly is as in Fig. 32 shown.

[0081] In several other embodiments, the auxiliary unit BSMO can also perform the functions described in Fig. 33 Layout structure shown based on the one in Fig. The layout structure shown in Figure 22 forms the active layer Poly up to the second source-drain metal layer SD2, and all features are provided that define the active layer Poly up to the second source-drain metal layer SD2 in the display field in Figure 22. Fig. 21 corresponds to the stack layout of the auxiliary layer BSM and the active layer Poly as in Fig. 34 shown.

[0082] However, in other embodiments of the present disclosure, the orthographic projection of the auxiliary unit BSMO onto the base substrate can also cover the orthographic projections of all transistors in the corresponding pixel driver circuit on the base substrate. For example, as in Fig. Figure 35 shows that the orthographic projection shape of the auxiliary unit BSMO in the auxiliary layer BSM on the base substrate is similar to the orthographic projection shape of the active layer structure in the corresponding pixel driver circuit on the base substrate, and the orthographic projection of the active layer structure of a pixel driver circuit on the base substrate is located within the orthographic projection of the auxiliary unit BSMO at the corresponding position on the base substrate, so that the auxiliary unit BSMO can form a barrier for all transistors under the corresponding pixel driver circuit, thereby further improving the barrier effect on the free charge.

[0083] In the present disclosure, the display field can further comprise a first conductive layer Gate1, a second conductive layer Gate2, a first source-drain metal layer SD1, and a second source-drain metal layer SD2, which are stacked and provided on a side of the active layer Poly facing away from the base substrate. The first conductive layer Gate1 can be a first gate metal layer, the second conductive layer Gate2 can be a second gate metal layer, and an insulating layer can be provided between two adjacent conductive layers.For example, a first gate insulating layer can be provided between the first conductive layer Gate1 and the active layer Poly, a second gate insulating layer can be provided between the second conductive layer Gate2 and the first conductive layer Gate1, an intermediate dielectric layer can be provided between the first source-drain metal layer SD1 and the second conductive layer Gate2, and a passivation layer and a planarization layer, etc., can be provided between the second source-drain metal layer SD2 and the first source-drain metal layer SD1.

[0084] Fig. 36 is a structural layout of the first conductive layer in Fig. 3; Fig. Figure 37 is a structural layout of the second conductive layer in Fig. 3; Fig. Figure 38 is a structural layout of the first source-drain metal layer in Fig. 3; Fig. 39 is a structural layout of the second source-drain metal layer in Fig. 3; Fig. 40 is a stacked layout of the auxiliary layer, the active layer, and the first source-drain metal layer in Fig. 3; and Fig. 41 is a stacked layout of the auxiliary layer, the first conductive layer, and the first source-drain metal layer in Fig. 3.

[0085] As in Fig. 3 and Fig. As shown in Figure 36, in an exemplary embodiment, the first conductive layer Gate1 can comprise a second conductive block 12, a first reset signal line Reset (n), a gate signal line Gate, an enable signal line EM, and a second reset signal line Reset (n+1). Orthographic projections of the first reset signal line Reset (n), the gate signal line Gate, the second conductive block 12, the enable signal line EM, and the second reset signal line Reset (n+1) onto the base substrate can all extend along the row direction and are spaced at intervals along the column direction. The first reset signal line Reset (n) and the gate signal line Gate are located on the same side of the second conductive block 12, and the enable signal line EM and the second reset signal line Reset (n+1) are located on the opposite side of the second conductive block 12.

[0086] The orthographic projection of the second conductive block 12 on the base substrate can cover the orthographic projection of the third active section POL3 on the base substrate, and the second conductive block 12 can be configured to form the gate of the driver transistor T3 and the first electrode of the storage capacitor Cst. In this way, in the layout structure, the first reset signal line Reset (n) and the gate signal line Gate are located on the same side of the driver transistor T3, and the enable signal line EM and the second reset signal line Reset (n+1) are located on the other side of the driver transistor T3.

[0087] The first reset signal line (n) can be configured to be the first reset signal connection in Fig. 1 to provide, and the orthographic projection of the first reset signal line Reset (n) on the base substrate can cover the orthographic projection of the first active subsection POL1-1 on the base substrate and the orthographic projection of the second active subsection POL1-2 on the base substrate, so that a substructure of the first reset signal line Reset (n) is configured to form the gate of the first transistor T1, and the first transistor T1 forms a double-gate structure.

[0088] The gate signal line can be configured to connect the gate signal in Fig. To provide 1, the orthographic projection of the gate signal line Gate on the base substrate can cover the orthographic projection of the second active section POL2 on the base substrate, and a substructure of the gate signal line Gate forms the gate of the second transistor T2. In the exemplary embodiment, the second active section POL2 in the active layer Poly can include a third active subsection POL2-3 and a fourth active subsection POL2-4, that is, the second transistor T2 comprises two channel regions.The gate signal line Gate can include a main extension section Gate-0 and an additional section Gate-1, the orthographic projection of the main extension section Gate-0 on the base substrate can cover the orthographic projection of the third active subsection POL2-3 on the base substrate, and the orthographic projection of the additional section Gate-1 on the base substrate can cover the orthographic projection of the fourth active subsection POL2-4 on the base substrate, so that the second transistor T2 forms a double-gate structure.

[0089] The release signal line EM can be configured to connect to the release signal port. Fig. 1. To provide the orthographic projection of the enable signal line EM on the base substrate, each can cover the orthographic projection of the fifth active section POL5 on the base substrate and the orthographic projection of the sixth active section POL6 on the base substrate. A substructure of the enable signal line EM can be configured to form the gate of the fifth transistor T5, and a substructure of the enable signal line EM can be configured to form the gate of the sixth transistor T6.

[0090] The second reset signal line (n+1) can be configured to connect to the second reset signal port. Fig. 1. To provide the orthographic projection of the second reset signal line Reset (n+1) on the base substrate, the orthographic projection of the seventh active section POL7 on the base substrate can be covered, and a substructure of the second reset signal line Reset (n+1) can be configured to form the gate of the seventh transistor T7.

[0091] In the display field of the present disclosure, the first conductive layer Gate 1 can be used as a mask to perform a conduction treatment of the active layer Poly, that is, the active layer Poly covered by the first conductive layer Gate1 forms the channel region of the transistor, and the region not covered by the first conductive layer Gate1 forms a conduction structure.

[0092] As in Fig. 3 and Fig. As shown in Figure 37, in an exemplary embodiment, the second conductive layer Gate2 can comprise a third conductive block 23, as well as a first initialization signal line Vinit1 and a second initialization signal line Vinit2, which extend along the row direction and are located on the same side of the third conductive block 23. The orthographic projection of the third conductive block 23 on the base substrate can be on an orthographic projection of the second conductive block 12 on the base substrate, and the third conductive block 23 can be configured to form the second electrode of the storage capacitor Cst.

[0093] As in Fig. As shown in Figure 37, in an exemplary embodiment the third conductive block 23 can be connected via a through-hole to the power transmission line VDDL located in the first source-drain metal layer SD1, and then connected via the power transmission line VDDL to the first power line VDD in the second source-drain metal layer SD2, so that the third conductive block 23 is connected to the first power line VDD.

[0094] As in Fig. As shown in Figure 37, in an exemplary embodiment, two third conductive blocks 23 adjacent in the line direction can be connected by a connecting line 24, such that the first current line VDD forms a crisscrossing grid structure through the laterally extending third conductive block 23. The first current line VDD of the grid structure can reduce the resistance of the first current line VDD, thereby reducing the RC load of the first current line VDD and reducing the power consumption of the display field.

[0095] As in Fig. As shown in Figure 37, in an exemplary embodiment the first initialization signal line Vinit1 can comprise a main signal line Vinit10 and an auxiliary section Vinit11, the main signal line Vinit10 can extend along the row direction, the auxiliary section Vinit11 can be connected to the side of the main signal line in the column direction, and the auxiliary section Vinit11 can be connected via a through-hole to the third initialization signal line Vinit3, which is located in the first source-drain metal layer SD1, in order to connect the first initialization signal line Vinit1 through the third initialization signal line Vinit3 to the twelfth active section POL12 in the active layer Poly, thereby connecting the first electrode of the first transistor T1 to the first initialization signal line Vinit1.Simultaneously, the third initialization signal line, Vinit3, extends along the column direction and is connected to the first initialization signal line, Vinit1, in each row, so that the first initialization signal line, Vinit1, forms a crisscrossing grid structure. This reduces the resistance of the first initialization signal line, Vinit1, thus lowering its RC load and reducing power consumption.On the other hand, in the non-display area, the third initialization signal line, Vinit3, can be connected to the auxiliary layer BSM via a through-hole. This allows the third initialization signal line, Vinit3, to be configured to provide the first signal to the auxiliary layer BSM, thus ensuring that the display field maintains stable display characteristics before and after the high-temperature reliability test and the copper rod test. However, in other embodiments, in the non-display area, the first initialization signal line, Vinit1, can be directly connected to the auxiliary layer BSM via a through-hole. For example, the first initialization signal line, Vinit1, can form a loop in the non-display area and then be connected to the auxiliary layer BSM via a through-hole.

[0096] As in Fig. As shown in Figure 37, in an exemplary embodiment, the second initialization signal line Vinit2 can be connected via the second through-hole H2 to the fourth initialization signal line Vinit4, which is located in the first source-drain metal layer SD1, in order to be connected via the fourth initialization signal line Vinit4 to the nineteenth active section POL19 in the active layer Poly, thereby connecting the first electrode of the seventh transistor T7 to the second initialization signal line Vinit2. Similarly, on the one hand, the second initialization signal line Vinit2 forms a crisscrossing lattice structure via the fourth initialization signal line Vinit4; on the other hand, in the non-display region, the fourth initialization signal line Vinit4 can be connected to the auxiliary layer BSM to provide the first signal for the auxiliary layer BSM.Similarly, in other embodiments in the non-display area, the second initialization signal line Vinit2 can be directly connected to the auxiliary layer BSM via the through-hole, and details are not described again here.

[0097] As in Fig. As shown in Figure 37, in an exemplary embodiment, the second conductive layer Gate2 can further comprise a first conductive block 21. The orthographic projection of the first conductive block 21 on the base substrate can be located on an orthographic projection of the tenth active section POL10 on the base substrate. That is, the first conductive block 21 can cover the conduction structure between the two channel regions of the second transistor T2. Furthermore, the first conductive block 21 can be connected via the third through-hole H3 to the current transfer line VDDL located in the first source-drain metal layer SD1, in order to connect the first conductive block 21 via the current transfer line VDDL to the first current transfer line VDD in the second source-drain metal layer SD2.In this way, the first conductive block 21 has a voltage stabilization effect on the tenth active section POL10, that is, the first conductive block 21 can be used to stabilize the voltage of the conduction structure connected to the two channel areas of the second transistor T2, so that the leakage of the second transistor T2 can be reduced and the interference of the AC voltage on the data signal line Vdata on the tenth active section POL10 can be supported, thereby reducing the voltage fluctuation of the driver transistor T3 in the light emission stage of the pixel driver circuit to improve image quality.It should be noted that the third through-hole H3 here refers to a through-hole formed in the insulating layer between the first conductive block 21 and the power transmission line VDDL; that is, a through-hole through which the first conductive block 21 is connected to the power transmission line VDDL. The power transmission line VDDL may be connected to the first power line VDD in the second source-drain metal layer SD2 through the through-hole at other locations; that is, the position of a through-hole through which the first power line VDD is connected to the power transmission line VDDL may differ from the position of the third through-hole H3. However, in other embodiments, the first power line VDD may also be connected to the power transmission line VDDL at a position corresponding to the third through-hole H3.

[0098] Furthermore, as in Fig. 3 and Fig. As shown in Figure 37, in an exemplary embodiment, due to the presence of the first conductive block 21, a third through-hole H3 is formed in the interlayer dielectric layer located on the second conductive layer Gate2, in order to be connected via the third through-hole H3 to the current transmission line VDDL in the first source-drain metal layer SD1. Based on this, the orthographic projection of the auxiliary unit BSMO in the auxiliary layer BSM on the base substrate can also cover the orthographic projection of the third through-hole H3 on the base substrate. In particular, as shown in Fig. 37 and Fig. As shown in Figure 40, the second auxiliary section B2 in the auxiliary layer BSM comprises the first auxiliary subsection B21 and the second auxiliary subsection B22, and the orthographic projection of the second auxiliary subsection B22 on the base substrate can cover the orthographic projection of the first conductive block 21 on the base substrate and the orthographic projection of the third through-hole H3 on the base substrate, thus preventing the area under the through-hole in the interlayer dielectric layer from being unflat due to process variations. It should be noted that if the area under the through-hole is unflat, this can lead to deformation of the through-hole and result in display errors such as the display band between different subpixels.Therefore, in the exemplary embodiment, by completely covering the third through-hole H3 with the auxiliary layer BSM, it is possible to prevent the deformation of the third through-hole H3 and thus avoid the defect of the display strip caused by the deformation of the through-hole on the interlayer dielectric layer.

[0099] As in Fig. 3, Fig. 38 and Fig. As shown in Figure 40, in an exemplary embodiment, the first source-drain metal layer SD1 can comprise a third initialization signal line Vinit3 and a fourth initialization signal line Vinit4. Both the third initialization signal line Vinit3 and the fourth initialization signal line Vinit4 can extend along the column direction. The third initialization signal line Vinit3 can be connected to the first initialization signal line Vinit1 via the first through-hole H1 to form a parallel structure to the first initialization signal line Vinit1. This allows the third initialization signal line Vinit3 to be further extended into the non-display area by extending along the column direction and connected to the auxiliary layer BSM to provide the first signal for the auxiliary layer BSM.The fourth initialization signal line, Vinit4, can be connected to the second initialization signal line, Vinit2, via the second through-hole to form a parallel structure to the second initialization signal line, Vinit2. This parallel structure can then be further extended through the fourth initialization signal line, Vinit4, into the non-display area and connected to the auxiliary layer, BSM, to provide the first signal for the auxiliary layer, in the exemplary embodiment. That is, in the exemplary embodiment, the first signal for the auxiliary layer, BSM, can be provided by the first initialization signal line, Vinit1, or the first signal for the auxiliary layer, BSM, can be provided by the second initialization signal line, Vinit2.

[0100] As in Fig. 38 and Fig. As shown in Figure 40, in an exemplary embodiment the display field can comprise a first pixel column P1 and a second pixel column P2, which are distributed sequentially and alternately along the row direction. The third initialization signal line Vinit3 can be located in the second pixel column P2, the fourth initialization signal line Vinit4 can be located in the first pixel column P1, and the first through-hole H1 and the second through-hole H2 are both located in the first pixel column P1. Furthermore, in the exemplary embodiment, the pixel driver circuit located in the first pixel column P1 can be a first pixel driver circuit, and the pixel driver circuit located in the second pixel column P2 can be a second pixel driver circuit. The display field can comprise a plurality of repeating units distributed in an array along the row and column direction.A repeating unit comprises a first pixel driver circuit and a second pixel driver circuit adjacent to the first pixel driver circuit along the row direction. It is understood that a particular structure A located in a particular pixel column B, as described in the present disclosure, can be understood as having the orthographic projection of structure A onto the base substrate located within the area where pixel column B is located.

[0101] For example, as in Fig. Figure 38 shows that the third initialization signal line, Vinit3, comprises a first main body section, Vinit30, a first extension section, Vinit31, and a second extension section, Vinit32. The first main body section, Vinit30, can be located in the second pixel column, P2, and the first extension section, Vinit31, can be connected between the first main body section, Vinit30, and the second extension section, Vinit32. One end of the second extension section, Vinit32, is connected to the first initialization signal line, Vinit1, via the first through-hole, H1, and the other end is connected to the twelfth active section, POL12, via another through-hole. Therefore, the third initialization signal line, Vinit3, is connected to the first initialization signal line, Vinit1, on one side and to the first electrode of the first transistor, T1, in the first pixel column, P1, on the other.At the same time, the first source-drain metal layer SD1 can further include a third bridge section 33, and the third bridge section 33 is located in the second pixel column P2 to connect the first electrode of the first transistor T1 to the first initialization signal line Vinit1 in the second pixel column P2.

[0102] As in Fig. As shown in Figure 38, the fourth initialization signal line Vinit4 can comprise a second main body section Vinit40, a third extension section Vinit43, and a fourth extension section Vinit44. The third extension section Vinit43 is connected between the second main body section Vinit40 and the fourth extension section Vinit44. One end of the fourth extension section Vinit44 is connected to the second initialization signal line Vinit2 via the second through-hole H2, and the other end is connected to the nineteenth active section POL19 via another through-hole. Therefore, the fourth initialization signal line Vinit4 is connected to the second initialization signal line Vinit2 on one side and also to the first electrode of the seventh transistor T7 in the first pixel column P1 on the other.Simultaneously, the first source-drain metal layer SD1 can further comprise a fourth bridge section 34, the fourth bridge section 34 being located in the second pixel column P2, and the orthographic projection of the fourth bridge section 34 onto the base substrate can extend along the column direction. The fourth bridge section 34 can each be connected via through-holes to the nineteenth active section POL19 and the second initialization signal line Vinit2, such that the first electrode of the seventh transistor T7 in the second pixel column P2 is connected to the second initialization signal line Vinit2 through the fourth bridge section 34.

[0103] It is evident that in the exemplary embodiment, in the same repeating unit, the first initialization signal line Vinit1 is connected via the third initialization signal line Vinit3 to the first electrode of the first transistor T1 in the first pixel driver circuit and via the third bridge section 33 to the first electrode of the first transistor T1 in the second pixel driver circuit. The second initialization signal line Vinit2 is connected via the fourth initialization signal line Vinit4 to the first electrode of the seventh transistor T7 in the first pixel driver circuit and via the fourth bridge section 34 to the first electrode of the seventh transistor T7 in the second pixel driver circuit.

[0104] As in Fig. 38 and Fig. As shown in Figure 40, in an exemplary embodiment, the first source-drain metal layer SD1 can further comprise a power transmission line VDDL. The power transmission line VDDL can comprise a first transmission section VDDL-1, a second transmission section VDDL-2, and a third transmission section VDDL-3. For example, the first power transmission line VDDL1 can comprise three transmission sections: the first transmission section VDDL1-1, the second transmission section VDDL1-2, and the third transmission section VDDL1-3; and the second power transmission line VDDL2 can comprise three transmission sections: the first transmission section VDDL2-1, the second transmission section VDDL2-2, and the third transmission section VDDL2-3.The orthographic projection of the first transmission section VDDL-1 on the base substrate and the orthographic projection of the third transmission section VDDL-3 on the base substrate both extend along the column direction, the orthographic projection of the second transmission section VDDL-2 on the base substrate extends along the row direction, and the first transmission section VDDL-1 and the third transmission section VDDL-3 are connected by the second transmission section VDDL-2. That is, the current transmission line VDDL is provided in a curved configuration, with one substructure located in the present pixel driver circuit and another substructure located in the adjacent pixel driver circuit along the row direction.Therefore, the power transmission line VDDL is connected to the third conductive block 23 and the first power line VDD by a first transmission section VDDL-1 located in the present pixel driver circuit, and to the first conductive block 21 in the adjacent pixel column by a third transmission section VDDL-3 located in the adjacent pixel driver circuit, so that the third conductive block 23 in the present pixel driver circuit and the first conductive block 21 in the adjacent pixel column are connected to the first power line VDD in the second source-drain metal layer SD2.

[0105] Furthermore, as described above, the display field can comprise a first pixel column P1 and a second pixel column P2, alternately distributed along the row direction. Based on this, the power transmission line VDDL can comprise a first power transmission line VDDL1 and a second power transmission line VDDL2, with the first power transmission line VDDL1 located in the first pixel column P1 and the second power transmission line VDDL2 located in the second pixel column P2. The first power transmission line VDDL1 in the first pixel column P1 can be connected via a through-hole to the third conductive block 23 in the second conductive layer Gate2 and can be connected via a through-hole to the first power transmission line VDD in the second source-drain metal layer SD2, thereby connecting the second electrode of the storage capacitor Cst to the first power transmission line VDD.Furthermore, after crossing the third conductive block 23 in the first pixel column P1, the first power transmission line VDDL1 is bent in a direction near the second pixel column P2, so that the first power transmission line VDDL1 in the first pixel column P1 is connected through the through hole to the first conductive block 21 in the second pixel column P2 in the same repeating unit, thereby connecting the first conductive block 21 in the second pixel column P2 in the same repeating unit to the first power line VDD.

[0106] The second power transmission line VDDL2 in the second pixel column P2 can be connected via a through hole to the third conductive block 23 in the second conductive layer Gate2 and can be connected via a through hole to the first power line VDD in the second source-drain metal layer SD2 to connect the second electrode of the storage capacitor Cst in the second pixel column to the first power line VDD.Furthermore, after crossing the third conductive block 23 in the second pixel column P2, the second power transmission line VDDL2 is bent in a direction near another repeating unit adjacent in the row direction to be connected via a through hole to the first conductive block 21 in the first pixel column P1 in another repeating unit adjacent in the row direction, thereby connecting the first conductive block 21 in the first pixel column P1 in the repeating unit adjacent in the row direction to the first power line VDD.

[0107] Furthermore, as in Fig. As shown in Figure 38, in the exemplary embodiment, the extent length of the orthographic projection of the second power transmission line VDDL2 on the base substrate along the column direction is greater than the extent length of the orthographic projection of the first power transmission line VDDL1 on the base substrate along the column direction. Fig. As can be seen in Figure 38, the first power transmission line VDDL1 is an isolated structure; that is, the first power transmission lines VDDL1 located in the same column in different pixel driver circuits are not connected to each other. The second power transmission line VDDL2 is a continuous structure; that is, the second power transmission lines VDDL2 located in the same column in different pixel driver circuits are connected to each other to form a continuous structure. Therefore, the extent length of the orthographic projection of the second power transmission line VDDL2 on the base substrate along the column direction is greater than the extent length of the orthographic projection of the first power transmission line VDDL1 on the base substrate along the column direction.Furthermore, in the non-display area of ​​the display field, the second power transmission line VDDL2 can be connected to the auxiliary layer BSM through the through-hole to provide the first signal for the auxiliary layer BSM. As described above, the power transmission line in a pixel driver circuit can comprise a multitude of transmission segments. Orthographic projections of partial transmission segments extend along the column direction, and orthographic projections of partial transmission segments extend along the row direction. Therefore, the extension length of the orthographic projection of a given power transmission line on the base substrate along the column direction can be understood as the sum of the extension lengths of the various segments that extend along the column direction in the orthographic projection of the power transmission line on the base substrate.In this way, the extension length of the second power transmission line VDDL2 along the column direction is greater than the extension length of the first power transmission line VDDL1 along the column direction, such that the sum of the extension lengths of different sections extending along the column direction in the orthographic projection of the second power transmission line VDDL2 is greater than the sum of the extension lengths of different sections extending along the column direction in the orthographic projection of the first power transmission line VDDL1.

[0108] As in Fig. 38 and Fig. As shown in Figure 41, in the exemplary embodiment, the orthographic projection of the second transmission section VDDL-2 on the base substrate can overlap at least partially with the orthographic projection of the second connection section B12 in the auxiliary layer BSM on the base substrate. With respect to the first power transmission line VDDL1, as shown in Figure 41, the orthographic projection of the second transmission section VDDL-2 on the base substrate can overlap at least partially with the orthographic projection of the second connection section B12 in the auxiliary layer BSM on the base substrate. Fig. Figure 41 shows that, within the dashed frame M in the figure, the orthographic projection of the second transmission section VDDL-2 of the first power transmission line VDDL1 on the base substrate partially overlaps with the orthographic projection of the second connection section B12 on the base substrate, and the second connection section B12 is located beneath the second transmission section VDDL-2 of the first power transmission line VDDL1. The overlapping arrangement of the second transmission section VDDL-2 and the second connection section B12 allows all the space occupied by cabling at this position in the layout to be saved, and this saved space can be used to improve light transmission.

[0109] Furthermore, the orthographic projection of the connecting line 24 in the second conductive layer Gate2 for connecting the third conductive blocks 23 in the two adjacent pixel driver circuits can be located within the orthographic projection of the second transmission section VDDL-2 on the base substrate. In this way, the second connecting section B12 in the auxiliary layer BSM, the connecting line 24 in the second conductive layer Gate2, and the second transmission section VDDL-2 in the first source-drain metal layer SD1 are arranged to overlap at this position.Furthermore, the connecting line 24 in the second conductive layer Gate2 is equipotent with the second transmission section VDDL-2 in the first source-drain metal layer SD1, and no signal crosstalk can be formed, so that the space occupied by the cabling at this position can be further saved by the overlapping arrangement of the three structures and the light transmission can be improved.

[0110] In some other embodiments, the orthographic projection of the second connecting section B12 on the base substrate can further cover the orthographic projection of the second transmission section VDDL-2 on the base substrate. That is, the second connecting section B12 underneath completely blocks the connecting line 24 and the second transmission section VDDL-2. Compared to the partially overlapping arrangement, the space occupied by the cabling can be further saved, and light transmission is improved.

[0111] In relation to Fig. 38 and Fig. 41 In the exemplary embodiment, a first overlap region S1 is provided between the orthographic projection of the third transmission section VDDL-3, located in the first source-drain metal layer SD1, and the orthographic projection of the main extension section Gate-0 of the gate signal line Gate in the first conductive layer Gate1 on the base substrate; and a second overlap region S2 is provided between the orthographic projection of the third initialization signal line Vinit3 in the first source-drain metal layer SD1 and the orthographic projection of the auxiliary section Gate-1 of the gate signal line Gate in the first conductive layer Gate1 on the base substrate. The orthographic projection of the second auxiliary section B2 on the base substrate can cover the first overlap region S1 and the second overlap region S2.This means that both the first overlap region S1 and the second overlap region S2 are located within the orthographic projection of the second auxiliary section B2 on the base substrate, which means that by enlarging the second auxiliary section B2, the two overlap regions can be covered, so that the coupling capacitance of the auxiliary layer BSM is consistent at the positions of the two channels of the second transistor T2, thus eliminating display errors due to coupling capacitance differences.

[0112] As in Fig. 38 and Fig. As shown in Figure 40, in an exemplary embodiment, the first source-drain metal layer SD1 can further comprise a first bridge section 31. The first bridge section 31 can extend along the column direction, and one end of the first bridge section 31 can be connected via a through-hole to the eleventh active section POL11 to connect to the second electrode of the first transistor T1 and the first electrode of the second transistor T2. The other end of the first bridge section 31 can be connected via a through-hole to the second conductive block 12 to connect to the gate of the driver transistor T3. In this way, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the gate of the driver transistor T3 via the first bridge section 31.

[0113] As in Fig. 38 and Fig. As shown in Figure 40, in an exemplary embodiment the first source-drain metal layer SD1 can further comprise an anode transfer section 35. One end of the anode transfer section 35 can be connected via a through-hole to the eighteenth active section POL18 to connect to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7; and the other end of the anode transfer section 35 can be connected via a through-hole to the anode terminal section 41 in the second source-drain metal layer SD2 to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the anode of the light-emitting device via the anode terminal section 41.

[0114] As in Fig. 3 and Fig. As shown in Figure 39, in an exemplary embodiment, the second source-drain metal layer SD2 can comprise a first power line VDD and a data signal line Vdata. The orthographic projection of the first power line VDD onto the base substrate and the orthographic projection of the data signal line Vdata onto the base substrate can both extend along the column direction, with the first power line VDD being configured to have the first power supply connection in Fig. 1, and the first current line VDD can be connected via a through-hole to the current transmission line VDDL in the first source-drain metal layer SD1, in order to be connected via the current transmission line VDDL to the second electrode of the storage capacitor Cst and the first electrode of the fifth transistor T5. Furthermore, in the exemplary embodiment, in the non-display area of ​​the display field, the first current line VDD can be connected via a through-hole to the auxiliary layer to provide the first signal for the auxiliary layer. In some other embodiments of the present disclosure, the display field can further comprise a second current line located in the first source-drain metal layer SD1; and in the non-display area, the second current line can be connected via a through-hole to the auxiliary layer to provide the first signal for the auxiliary layer.For example, the second power line can be the VDDL power transmission line described in the preceding embodiments, and the VDDL power transmission line is connected to the auxiliary layer via a through hole after extension into the non-display area.

[0115] It is understood that in the present disclosure, the auxiliary layer can alternatively be connected to one of the first initialization signal lines Vinit1, the second initialization signal line Vinit2, the first power line VDD, or the second power line. That is to say, in the present disclosure, the first signal for the auxiliary layer can be provided by the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first power line VDD, or the second power line.

[0116] The data signal line Vdata can be configured to connect to the data signal port in Fig. 1 to provide, and the data signal line Vdata can be connected via a through hole to the data transmission section VdataL in the first source-drain metal layer SD1, in order to be connected via the data transmission section VdataL to the second electrode of the fourth transistor T4.

[0117] As in Fig. As shown in Figure 39, the second source-drain metal layer SD2 can further comprise an anode connection section 41 and an anode flat section 42. The orthographic projection of the anode connection section 41 on the base substrate is located above the orthographic projection of the anode transfer section 35 on the base substrate. The anode connection section 41 is located below the anode of the light-emitting device and is connected to the anode. In this way, the anode of the light-emitting device can be connected via the anode connection section 41 to the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. Due to the presence of the anode connection section 41, there is a slight protrusion below the anode.On this basis, by additionally providing the anode flat section 42 in the second source-drain metal layer SD2, the protrusion height of the anode terminal section 41 can be compensated by the anode flat section 42 in order to avoid one side being higher and the other side lower under the anode, thus preventing the anode from being tilted and ensuring a normal display of the light emission device.

[0118] It is understood that the terms “first”, “second”, “third” or the like are used in the present revelation only as designations and serve to distinguish names of different structures, neither limiting the number of objects nor indicating a sequential relationship.

[0119] Fig. 41 is a cross-sectional image along the AA direction in Fig.3. The display field can further comprise a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, a passivation layer 77 and a second dielectric layer 77, wherein the base substrate 71, the auxiliary layer BSM, the buffer layer 72, the active layer Poly, the first insulating layer 73, the first conductive layer Gate1, the second insulating layer 74, the second conductive layer Gate2, the first dielectric layer 75, the first source-drain metal layer SD1, the passivation layer 76, the second dielectric layer 77 and the second source-drain metal layer SD2 are stacked and arranged in sequential order.The first insulating layer 73 can be an organic insulating layer; the second insulating layer 74 can be silicon oxide; the first dielectric layer 75 and the second dielectric layer 77 can be silicon nitride layers; and the material of the passivation layer 77 and the buffer layer 72 can be silicon oxide, silicon nitride, or the like. The base substrate 71 can comprise a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The material of the first conductive layer Gate1 and the second conductive layer Gate2 can be one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy, or a molybdenum / titanium alloy, or a laminated layer.The material of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 can include a metallic material such as molybdenum, aluminum, copper, titanium and niobium, an alloy, a molybdenum / titanium alloy or laminated layer, or a titanium / aluminium / titanium laminated layer, etc.

[0120] The present disclosure further provides a display device which may include the display field described in one of the embodiments mentioned above.

[0121] Other embodiments of the present disclosure will be apparent to a person skilled in the art from considering the description and practice of the invention disclosed herein. The present application is intended to cover all variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge and conventional technical means not disclosed herein. The description and embodiments are to be considered merely as examples, the actual scope and meaning of the present disclosure being specified by the following claims.

Claims

[1] Display panel comprising a pixel driver circuit, wherein the pixel driver circuit comprises a second transistor and a driver transistor, a first electrode of the second transistor is connected to a gate of the driver transistor, and the display panel further comprises: a base substrate; an auxiliary layer located on one side of the base substrate and connected to a first signal; and an active layer located on the side of the auxiliary layer facing away from the base substrate and comprising: a second active section configured to form a channel area of ​​the second transistor; and a third active section configured to form a channel area of ​​the driver transistor; where an orthographic projection of the auxiliary layer on the base substrate covers an orthographic projection of the second active section on the base substrate and an orthographic projection of the third active section on the base substrate. [2] Display field according to claim 1, wherein the display field comprises a plurality of pixel driver circuits distributed in an array along a row direction and a column direction, the auxiliary layer comprises a plurality of auxiliary units distributed in an array along the row direction and the column direction, an auxiliary unit corresponding to a pixel driver circuit is provided, and the second active section comprises a third active subsection and a fourth active subsection; wherein the auxiliary unit comprises: a first auxiliary section, wherein an orthographic projection of the first auxiliary section on the base substrate covers the orthographic projection of the third active section on the base substrate; and a second auxiliary section, wherein an orthographic projection of the second auxiliary section on the base substrate covers an orthographic projection of the third active subsection on the base substrate and an orthographic projection of the fourth active subsection on the base substrate. [3] Display field according to claim 2, wherein the active layer further comprises: a tenth active section connected between the third active subsection and the fourth active subsection; where the orthographic projection of the second auxiliary section on the base substrate does not overlap with an orthographic projection of the tenth active section on the base substrate. [4] Display field according to claim 2, wherein the active layer further comprises: a tenth active section connected between the third active subsection and the fourth active subsection; wherein the second auxiliary section comprises a first auxiliary subsection and a second auxiliary subsection, an orthographic projection of the first auxiliary subsection on the base substrate covers the orthographic projection of the third active subsection on the base substrate and the orthographic projection of the fourth active subsection on the base substrate, and an orthographic projection of the second auxiliary subsection on the base substrate covers an orthographic projection of the tenth active section on the base substrate. [5] Display field according to claim 4, wherein the display field further comprises: a second conductive layer located on the side of the active layer facing away from the auxiliary layer and comprising: a first conductive block, wherein an orthographic projection of the first conductive block on the base substrate is located on the orthographic projection of the tenth active section on the base substrate; a second source-drain metal layer located on a side of the second conductive layer facing away from the base substrate and comprising: a first power line, wherein an orthographic projection of the first power line on the base substrate runs along the column direction, and the first power line is coupled to the first conductive block via a third through-hole; wherein the orthographic projection of the second auxiliary subsection on the base substrate further covers an orthographic projection of the third through-hole on the base substrate. [6] Display field according to claim 1, wherein the active layer further comprises: a first active section connected to one side of the second active section, the first active section being configured to form a channel area of ​​the first transistor; the auxiliary unit further comprises: a fourth auxiliary section connected to the second auxiliary section, an orthographic projection of the fourth auxiliary section onto the base substrate, and an orthographic projection of the first active section onto the base substrate. [7] Display field according to claim 6, wherein the first active section comprises a first active subsection and a second active subsection; and the active layer also includes: a ninth active section connected between the first active subsection and the second active subsection; wherein the orthographic projection of the fourth auxiliary section on the base substrate further covers an orthographic projection of the ninth active section on the base substrate. [8] Display field according to claim 7, wherein the pixel driver circuit further comprises a fourth transistor; the active layer also includes: a fourth active section configured to form a channel area of ​​the fourth transistor; The aid unit also includes: a third connecting section that is connected between two auxiliary units adjacent in the column direction, wherein an orthographic projection of the third connecting section on the base substrate runs along the column direction; and a sixth auxiliary section connected to the third connecting section, wherein an orthographic projection of the sixth auxiliary section on the base substrate runs along the line direction and covers an orthographic projection of the fourth active section on the base substrate. [9] Display field according to claim 1, wherein the auxiliary unit further comprises: a third connecting section, which is connected between two auxiliary units adjacent in the column direction, and an orthographic projection of the third connecting section on the base substrate runs along the column direction; and a first connecting section that is connected to a side of the second auxiliary section facing away from the first auxiliary section in the column direction, wherein in two auxiliary units adjacent in the column direction a third connecting section of an auxiliary unit in a previous row is connected to a first connecting section of an auxiliary unit in a next row, and an orthographic projection of the first connecting section on the base substrate does not overlap with an orthographic projection of the first active section on the base substrate. [10] Display field according to claim 9, wherein the first active section comprises a first active subsection and a second active subsection; and the active layer also includes: a ninth active section connected between the first active subsection and the second active subsection; where the orthographic projection of the first connection section on the base substrate does not overlap with an orthographic projection of the ninth active section on the base substrate. [11] Display field according to claim 9, wherein the pixel driver circuit further comprises a fourth transistor; the active layer further comprises a fourth active section, and the fourth active section is configured to form a channel region of the fourth transistor; and The aid unit also includes: a third connecting section, which is connected between two auxiliary units adjacent in the column direction, and an orthographic projection of the third connecting section on the base substrate runs along the column direction; and a sixth auxiliary section connected to the third connecting section, and an orthographic projection of the sixth auxiliary section on the base substrate runs along the line direction and covers an orthographic projection of the fourth active section on the base substrate. [12] Display field according to claim 1, wherein the pixel driver circuit further comprises a first transistor, and a second electrode of the first transistor is connected to the gate of the driver transistor; the active layer also includes: a first active section connected to one side of the second active section, the first active section being configured to form a channel area of ​​the first transistor; The aid unit also includes: a second connecting section, each connected to the first auxiliary section and the second auxiliary section, wherein an orthographic projection of the second connecting section on the base substrate runs along the line direction, and two auxiliary units adjacent in the line direction are connected by the second connecting section; a third connecting section, which is connected between two auxiliary units adjacent in the column direction, and an orthographic projection of the third connecting section on the base substrate runs along the column direction; and a first connecting section or a fourth auxiliary section connected to a side of the second auxiliary section facing away from the first auxiliary section in the column direction, wherein in two auxiliary units adjacent in the column direction a third connecting section of an auxiliary unit in a previous row is connected to a first connecting section or a fourth auxiliary section of an auxiliary unit in a next row, an orthographic projection of the first connecting section on the base substrate does not overlap with an orthographic projection of the first active section on the base substrate, and an orthographic projection of the fourth auxiliary section on the base substrate covers the orthographic projection of the first active section on the base substrate. [13] Display field according to claim 1, wherein the display field further comprises: a first source-drain metal layer and / or a second source-drain metal layer located on a side of the active layer facing away from the base substrate and comprising: a second power line and / or a first power line, wherein an orthographic projection of the second power line and / or the first power line runs along the column direction, and in a non-display area of ​​the display field the second power line and / or the first power line is connected to the auxiliary layer via a through hole. [14] Display field according to claim 1, wherein the display field further comprises: a second conductive layer located on the side of the active layer facing away from the base substrate and comprising: a first initialization signal line, wherein an orthographic projection of the first initialization signal line on the base substrate runs along the line direction; and a second initialization signal line, wherein an orthographic projection of the second initialization signal line runs along the line direction on the base substrate; a first source-drain metal layer located on a side of the second conductive layer facing away from the base substrate and comprising: a third initialization signal line, wherein an orthographic projection of the third initialization signal line on the base substrate runs along the column direction, and the third initialization signal line is connected to the first initialization signal line through a first through-hole; and / or a fourth initialization signal line, wherein an orthographic projection of the fourth initialization signal line on the base substrate runs along the column direction, and the fourth initialization signal line is connected to the second initialization signal line through a second through-hole. [15] Display field according to claim 14, wherein the display field comprises a first pixel column and a second pixel column distributed sequentially and alternately in the row direction; and the orthographic projection of the third initialization signal line is located on the base substrate at least partially in an area where the second pixel column is located, the orthographic projection of the fourth initialization signal line is located on the base substrate in an area where the first pixel column is located, and both the first through-hole and the second through-hole are located in the first pixel column. [16] Display panel according to claim 3, wherein the pixel driver circuit further comprises a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driver transistor, and a second electrode of the storage capacitor is connected to a second power supply terminal; and the display panel further comprises: a first conductive layer located on the side of the active layer facing away from the base substrate and comprising: a second conductive block, wherein an orthographic projection of the second conductive block on the base substrate covers the orthographic projection of the third active section on the base substrate, and the second conductive block is configured to form the first electrode of the storage capacitor; a second conductive layer located on a side of the first conductive layer facing away from the base substrate and comprising: a third conductive block, wherein an orthographic projection of the third conductive block on the base substrate is arranged on the orthographic projection of the second conductive block on the base substrate, and the third conductive block is configured to form the second electrode of the storage capacitor; and a first conductive block, wherein an orthographic projection of the first conductive block on the base substrate is arranged on the orthographic projection of the tenth active section on the base substrate; a first source-drain metal layer located on a side of the second conductive layer facing away from the base substrate and comprising: a first power transmission line, which is connected via a through-hole to the third conductive block and further connected via a through-hole to a first conductive block in an adjacent pixel driver circuit; and a second power transmission line, each connected to the third conductive block via a through hole, and an extent length of an orthographic projection of the second power transmission line on the base substrate along the column direction is greater than an extent length of the first power transmission line on the base substrate along the column direction. [17] Display field according to claim 16, wherein the first power transmission line comprises a first transmission section, a second transmission section and a third transmission section, both an orthographic projection of the first transmission section on the base substrate and an orthographic projection of the third transmission section on the base substrate extend along the column direction, an orthographic projection of the second transmission section on the base substrate extends along the row direction, and the first transmission section and the third transmission section are connected by the second transmission section;and the first transmission section is connected to the third conductive block and the first power line via a through-hole, and the third transmission section is located in another pixel driver circuit adjacent in the line direction and is connected to the first conductive block via a through-hole. [18] Display field according to claim 17, wherein the auxiliary unit further comprises: a second connecting section, each connected to the first auxiliary section and the second auxiliary section, wherein an orthographic projection of the second connecting section on the base substrate runs along the line direction, and two auxiliary units adjacent in the line direction are connected by the second connecting section; where an orthographic projection of the second transmission section on the base substrate partially overlaps with an orthographic projection of the second connection section on the base substrate. [19] Display field according to claim 17, wherein the first conductive layer further comprises: a gate signal line comprising a main extension section and an additional section, wherein an orthographic projection of the main extension section on the base substrate runs along the row direction and covers the orthographic projection of the third active subsection on the base substrate, an orthographic projection of the additional section on the base substrate runs along the column direction and covers the orthographic projection of the fourth active subsection on the base substrate, and a substructure of the gate signal line is configured to form a gate of the second transistor; the second conductive layer further comprises: a first initialization signal line, wherein an orthographic line of the first initialization signal line runs along the line direction on the base substrate; the first source-drain metal layer further includes: a third initialization signal line, wherein an orthographic projection of the third initialization signal line on the base substrate runs along the column direction, and the third initialization signal line is connected to the first initialization signal line via a through hole; wherein a first overlap area is provided between the orthographic projection of the third transmission section on the base substrate and the orthographic projection of the main extension section on the base substrate, a second overlap area is provided between the orthographic projection of the third initialization signal line on the base substrate and the orthographic projection of the auxiliary section on the base substrate, and the orthographic projection of the second auxiliary section on the base substrate covers the first overlap area and the second overlap area. [20] Display field according to claim 16, wherein the pixel driver circuit further comprises a fifth transistor, a gate of the fifth transistor is connected to an enable signal line, a first electrode of the fifth transistor is connected to a first power supply terminal, and a second electrode of the fifth transistor is connected to a second electrode of the driver transistor; the active layer also includes: a fifth active section configured to form a channel area of ​​the fifth transistor; a sixteenth active section connected between the fifth active section and the third active section, configured to form the second electrode of the fifth transistor and the second electrode of the driver transistor; and a seventeenth active section connected to a side of the fifth active section facing away from the sixteenth active section and configured to form the first electrode of the fifth transistor; the first conductive layer further comprises: an enable signal line, wherein an orthographic projection of the enable signal line on the base substrate runs along the row direction and covers an orthographic projection of the fifth active section on the base substrate, and a substructure of the enable signal line is configured to form the gate of the fifth transistor; the seventeenth active section is connected to the first power line via a through hole. [21] Display field according to claim 20, wherein the pixel driver circuit further comprises a fourth transistor and a sixth transistor, a gate of the second transistor is connected to a gate signal terminal, and a second electrode of the second transistor is connected to the first electrode of the driver transistor, a gate of the fourth transistor is connected to a second reset signal terminal, a first electrode of the fourth transistor is connected to the second electrode of the driver transistor, a second electrode of the fourth transistor is connected to the second electrode of the fifth transistor, a gate of the sixth transistor is connected to the enable signal terminal, a first electrode of the sixth transistor is connected to the first electrode of the driver transistor, and a second electrode of the sixth transistor is connected to an anode of a light-emitting device; the active layer also includes: a sixteenth active section connected to one side of the third active section and configured to form the second electrode of the driver transistor and the second electrode of the fifth transistor; a fourteenth active section connected via a through-hole to a second bridge section located in a first source-drain metal layer, the second bridge section further being connected via a through-hole to the sixteenth active section, and the fourteenth active section being configured to form the first electrode of the fourth transistor; a fourth active section connected to the fourteenth active section and configured to form a channel area of ​​the fourth transistor; a fifteenth active section connected to a side of the fourth active section facing away from the fourteenth active section, wherein the fifteenth active section is configured to form the second electrode of the fourth transistor; a fifth active section configured to form a channel area of ​​the fifth transistor; a sixth active section configured to form a channel area of ​​the sixth transistor; a seventh active section configured to form a channel area of ​​the seventh transistor; the first conductive layer further comprises: a first reset signal line, wherein an orthographic projection of the first reset signal line on the base substrate covers an orthographic projection of the first active section on the base substrate, and a substructure of the first reset signal line is configured to form a gate of the first transistor; a gate signal line, wherein an orthographic projection of the gate signal line on the base substrate covers the orthographic projection of the second active section on the base substrate, and a substructure of the gate signal line is configured to form the gate of the second transistor; an enable signal line, wherein an orthographic projection of the enable signal line on the base substrate covers an orthographic projection of the fifth active section on the base substrate and an orthographic projection of the sixth active section on the base substrate, a substructure of the enable signal line is configured to form the gate of the fifth transistor, and a substructure of the enable signal line is configured to form the gate of the sixth transistor; and a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate covers an orthographic projection of the fourth active section on the base substrate and an orthographic projection of the seventh active section on the base substrate, a substructure of the second reset signal line is configured to form the gate of the fourth transistor, and a substructure of the second reset signal line is configured to form a gate of the seventh transistor; wherein the orthographic projection of the first reset signal line on the base substrate, the orthographic projection of the gate signal line on the base substrate, the orthographic projection of the enable signal line on the base substrate, and the orthographic projection of the second reset signal line on the base substrate all extend along the row direction and are sequentially spaced in the column direction; and the orthographic projection of the gate signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate are located on both sides of the orthographic projection of the third active section on the base substrate. [22] Display field comprising a pixel driver circuit, wherein the pixel driver circuit comprises a second transistor and a driver transistor, a first electrode of the second transistor is connected to a gate of the driver transistor, and the display field further comprises: a base substrate that includes an organic layer; an auxiliary layer located on one side of the base substrate; an active layer located on the side of the auxiliary layer facing away from the base substrate and comprising: a second active section configured to form a channel area of ​​the second transistor; and a third active section configured to form a channel area of ​​the driver transistor; where an orthographic projection of the auxiliary layer on the base substrate covers an orthographic projection of the second active section on the base substrate and an orthographic projection of the third active section on the base substrate. [23] Display field according to claim 22, wherein the display field comprises a plurality of pixel driver circuits distributed in an array along a row direction and a column direction, the auxiliary layer comprises a plurality of auxiliary units distributed in an array along the row direction and the column direction, an auxiliary unit corresponding to a pixel driver circuit is provided, and the second active section comprises a third active subsection and a fourth active subsection; The aid unit includes: a first auxiliary section, wherein an orthographic projection of the first auxiliary section on the base substrate covers the orthographic projection of the third active section on the base substrate; and a second auxiliary section, wherein an orthographic projection of the second auxiliary section on the base substrate covers an orthographic projection of the third active subsection on the base substrate and an orthographic projection of the fourth active subsection on the base substrate. [24] Display field according to claim 23, wherein the pixel driver circuit further comprises a first transistor, and a second electrode of the first transistor is connected to the gate of the driver transistor; the active layer also includes: a first active section that is connected to one side of the second active section and is configured to form a channel area of ​​the first transistor; The aid unit also includes: a second connecting section, each connected to the first auxiliary section and the second auxiliary section, wherein an orthographic projection of the second connecting section on the base substrate runs along the line direction, and two auxiliary units adjacent in the line direction are connected by the second connecting section; and a fourth auxiliary section connected to the second auxiliary section, wherein an orthographic projection of the fourth auxiliary section on the base substrate covers an orthographic projection of the first active section on the base substrate. [25] Display device comprising the display field according to any one of claims 1 to 24.

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