Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate comprises a base substrate, a plurality of subpixels, and a first scanning line. The subpixel comprises a subpixel driver circuit with a driver transistor and a compensation transistor, wherein a gate electrode of the compensation transistor is coupled to a corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor. The compensation transistor comprises a compensation active layer, the compensation active layer comprising a first channel section, a second channel section, and a first conductor section, the first conductor section being coupled to both the first channel section and the second channel section.at least part of an orthographic projection of the first conductor section on the base substrate lies between an orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate.

Description

AREA OF TECHNOLOGY

[0001] The present disclosure relates to the field of display technology, in particular a display substrate and a display device. BACKGROUND

[0002] With the continuous development of display technology, the demands and expectations placed on smart terminal display devices in the current market are constantly increasing, as is the average daily usage time and frequency of these devices. Currently, smart terminal display devices primarily utilize display technologies such as liquid crystal display technology and OLED technology (i.e., organic light-emitting diode display technology). OLED technology offers advantageous properties such as fast response times, wide viewing angles, thinness, and light weight. Therefore, OLED technology is increasingly being used in smart terminal display devices. SUMMARY

[0003] In one aspect, the present disclosure aims to provide a display substrate and a display device.

[0004] To achieve the objective, the present disclosure offers the following technical solution.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate comprising a base substrate, a plurality of subpixels, and a first scanning line, both of which are arranged on the base substrate, wherein the first scanning line comprises at least a portion extending along a first direction, and the subpixel comprises a subpixel driver circuit comprising a driver transistor and a compensation transistor, wherein a gate electrode of the compensation transistor is coupled to a corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor;The compensation transistor comprises a compensation active layer, the compensation active layer comprising a first channel section, a second channel section and a first conductor section, wherein the first conductor section is coupled to the first channel section and the second channel section respectively; at least part of an orthographic projection of the first conductor section on the base substrate is located between an orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate.

[0006] Optionally, the compensation transistor comprises a first compensation gate electrode and a second compensation gate electrode, wherein an orthographic projection of the first compensation gate electrode on the base substrate covers the orthographic projection of the first channel section on the base substrate, and an orthographic projection of the second compensation gate electrode on the base substrate covers the orthographic projection of the second channel section on the base substrate; the first compensation gate electrode is coupled to the corresponding first scanning line, and at least a portion of the first compensation gate electrode is located between the first scanning line to which the first compensation gate electrode is coupled and the gate electrode of the driver transistors, wherein the first scanning line is multiplexed as the second compensation gate electrode.

[0007] Optionally, the display substrate further comprises a data line and a second sampling line, wherein the second sampling line includes at least a portion extending along the first direction, wherein the subpixel driver circuit further comprises a data write transistor, wherein a gate electrode of the data write transistor is coupled to a corresponding second sampling line, wherein a first electrode of the data write transistor is coupled to a corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor; in an identical subpixel, the gate electrode of the data write transistor is located on one side of the first sampling line facing the gate electrode of the driver transistor.

[0008] Optionally, the data write transistor includes a data active layer, and the gate electrode of the data write transistor comprises a gate electrode body section and a gate electrode extension section coupled together, wherein an orthographic projection of the gate electrode body section on the base substrate overlaps at least partially with an orthographic projection of the data active layer on the base substrate, the gate electrode extension section being coupled to the corresponding second scanning line; the gate electrode body section and the gate electrode of the driver transistor are arranged along the first direction, and at least a portion of the gate electrode extension section and the gate electrode of the driver transistor are arranged along a second direction, and the first direction intersects the second direction;The gate electrode body section and the gate electrode extension section are arranged in the same layer or in different layers.

[0009] Optionally, the subpixel driver circuit further comprises a first conductive interconnect and a first reset transistor, wherein a first end of the conductive interconnect is coupled to the gate electrode of the driver transistor and a second end of the first conductive interconnect is coupled to the second electrode of the first reset transistor; the second scanning line is arranged at least partially around the second end of the first conductive interconnect.

[0010] Optionally, the gate electrode of the data write transistor and the first scanning line are arranged in the same layer and made of the same material, and the second scanning line and the first scanning line are arranged in different layers, with the second scanning line and the first conductive connecting section being arranged in the same layer and made of the same material.

[0011] Optionally, the second scanning line comprises a plurality of straight edge sections and a plurality of curved edge sections, wherein the straight edge section and the curved edge section are arranged alternately along the first direction, the curved edge section is arranged around the second end of the first conductive connecting section, the straight edge section comprises a protruding end, at least a part of an orthographic projection of the protruding end onto the base substrate and the orthographic projection of the gate electrode of the driver transistor onto the base substrate are arranged along the second direction, and the protruding end is coupled to the gate electrode of the data write transistor.

[0012] Optionally, the display substrate further comprises a first initialization signal line, wherein the first initialization signal line includes at least a portion extending along the second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line; the orthographic projection of the first initialization signal line on the base substrate is located between the orthographic projection of the gate electrode of the driver transistor on the base substrate and the orthographic projection of the data line on the base substrate.

[0013] Optionally, the display substrate further comprises a power line, wherein the first initialization signal line, the power line and the data line are arranged in the same layer and are made of the same material, and wherein the first initialization signal line is located between the power line and the data line.

[0014] Optionally, the display substrate further comprises a second initialization signal line, a third initialization signal line, and a third sampling line, wherein the third sampling line includes at least one section extending along the first direction; the subpixel further comprises a light-emitting element; the subpixel driver circuit further comprises a second reset transistor and a third reset transistor, wherein a gate electrode of the second reset transistor and a gate electrode of the third reset transistor are both coupled to a corresponding identical third sampling line; a first electrode of the second reset transistor is coupled to the second initialization signal line, and a second electrode of the second reset transistor is coupled to an anode of the light-emitting element;a first electrode of the third reset transistor is coupled to the third initialization signal line, a second electrode of the third reset transistor is coupled to the first electrode of the driver transistor.

[0015] Optionally, the second scanning line and the first scanning line are arranged in different layers, and the orthographic projection of the second scanning line on the base substrate overlaps at least partially with the orthographic projection of the first scanning line on the base substrate; the display substrate comprises a second gate metal layer and a first source-drain metal layer, the second initialization signal line and the first source-drain metal layer are arranged in the same layer and made of the same material, and the third initialization signal line and the second gate metal layer are arranged in the same layer and made of the same material.

[0016] Optionally, the display substrate further comprises a power line; the first reset transistor comprises a first reset active layer, and the first reset active layer comprises a third channel section, a fourth channel section, and a second conductor section, the second conductor section being coupled to the third channel section and the fourth channel section, respectively; an orthographic projection of the second conductor section onto the base substrate overlaps at least partially with an orthographic projection of the second initialization signal line onto the base substrate; and / or the orthographic projection of the second conductor section onto the base substrate overlaps at least partially with an orthographic projection of the third initialization signal line onto the base substrate;and / or the orthographic projection of the second conductor section on the base substrate overlaps at least partially with an orthographic projection of the power line on the base substrate.

[0017] Optionally, the display substrate further comprises a power line and a first conductive link section, wherein a first end of the first conductive link section is coupled to the gate electrode of the driver transistor and a second end of the first conductive link section is coupled to the second electrode of the compensation transistor; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor and a second electrode plate of the storage capacitor is coupled to the corresponding power line;The compensation active layer further comprises a conductor extension section connected to the first conductor section, and an orthographic projection of the conductor extension section on the base substrate overlaps at least partially with an orthographic projection of the second electrode plate on the base substrate; and / or an orthographic projection of the first conductor section on the base substrate does not overlap with an orthographic projection of the first conductive connection section on the base substrate; and / or the orthographic projection of the second electrode plate on the base substrate overlaps at least partially with the orthographic projection of the first conductor section on the base substrate.

[0018] Optionally, the display substrate further comprises a light-shielding layer, and an orthographic projection of the light-shielding layer on the base substrate overlaps at least partially with the orthographic projection of the active layer of the driver transistor on the base substrate and overlaps at least partially with the orthographic projection of the compensation active layer on the base substrate.

[0019] Optionally, the subpixel further comprises a light-emitting element, and the light-emitting element comprises an anode; the subpixel driver circuit further comprises a light emission control transistor and the second conductive interconnect, wherein a first electrode of the light emission control transistor is coupled to the second electrode of the driver transistor, a first end of the second conductive interconnect is coupled to a second electrode of the light emission control transistor, and a second end of the second conductive interconnect is coupled to the anode via a first through-hole; the subpixel further comprises a pixel opening region, and an orthographic projection of the pixel opening region onto the base substrate does not overlap with an orthographic projection of the first through-hole onto the base substrate.

[0020] Optionally, the subpixels further comprise a light-emitting element, and the light-emitting element comprises an anode; the anode of at least some of the subpixels comprises an anode body section and an anode dummy section; an orthographic projection of the anode body section on the base substrate overlaps at least partially with an orthographic projection of the compensation active layer on the base substrate that is contained in the subpixel to which the anode body section belongs; an orthographic projection of the anode dummy section on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer on the base substrate that is contained in the subpixel that is adjacent to the anode dummy section along the first direction.

[0021] Optionally, the display substrate includes red subpixels, green subpixels, and blue subpixels; at least some of the subpixels include red subpixels and blue subpixels, and the adjacent subpixels include green subpixels.

[0022] In a second aspect, an embodiment of the present disclosure provides a display substrate comprising: a base substrate and a plurality of subpixels, a second scanning line and a data line, all arranged on the base substrate; wherein the second scanning line comprises at least a portion extending along a first direction; the subpixel comprises a subpixel driver circuit, the subpixel driver circuit comprising a first conductive interconnect, a driver transistor, a compensation transistor and a data write transistor; a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor and a second electrode of the compensation transistor is coupled via the first conductive interconnect to a gate electrode of the driver transistor;The compensation transistor comprises a compensation active layer, which comprises a first channel section, a second channel section, and a first conductor section. The first conductor section is coupled to both the first channel section and the second channel section. At least part of an orthographic projection of the first conductor section on the base substrate is located between an orthographic projection of the second scanning line on the base substrate and an orthographic projection of the gate electrode of the driver transistor on the base substrate. A gate electrode of the data write transistor is coupled to a corresponding second scanning line, a first electrode of the data write transistor is coupled to a corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor.at least part of the second scanning line is arranged around one end of the first conductive connection section.

[0023] Optionally, the display substrate further comprises a power line; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor and a second electrode plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second electrode plate on the base substrate overlaps at least partially with an orthographic projection of the first conductor section on the base substrate; and / or the orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the first conductive interconnect section on the base substrate.

[0024] Optionally, the display substrate further comprises a power line; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor and a second electrode plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second electrode plate on the base substrate overlaps at least partially with an orthographic projection of the first conductor section on the base substrate; and / or the orthographic projection of the first conductor section on the base substrate does not overlap with an orthographic projection of the first conductive interconnect section on the base substrate; and / or the orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the power line on the base substrate.

[0025] In a third aspect, an embodiment of the present disclosure provides a display device comprising the display substrate. BRIEF DESCRIPTION OF THE FIGURES

[0026] The drawings described herein serve to enhance understanding of the present disclosure and are an integral part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions serve to explain the present disclosure and do not constitute an impermissible limitation of the present disclosure. Fig. Figure 1 is a schematic diagram of the layout of the light-shielding layer of a display substrate according to an embodiment of the present disclosure; Fig. Figure 2 is a schematic diagram of the layout of the active layer of a display substrate according to an embodiment of the present disclosure; Fig. Figure 3 is a schematic diagram of the layout of the first gate metal layer of the display substrate according to an embodiment of the present disclosure; Fig. Figure 4 is a schematic diagram of the layout of the active layer and the first gate metal layer of the display substrate according to an embodiment of the present disclosure; Fig. Figure 5 is a schematic diagram of the layout of the second gate metal layer of the display substrate according to an embodiment of the present disclosure; Fig. Figure 6 is a schematic diagram of the layout, based on... Fig. 4 a second gate metal layer is added; Fig. Figure 7 is a schematic diagram of the first layout of the first source-drain metal layer of the display substrate according to an embodiment of the present disclosure; Fig. Figure 8 is a schematic diagram of the layout, based on... Fig. 6 a first source-drain metal layer is added; Fig. Figure 9 is a schematic diagram of the layout, based on... Fig. 4 a first source-drain metal layer is added; Fig. Figure 10 is a schematic diagram of the layout of the second source-drain metal layer of the display substrate according to an embodiment of the present disclosure; Fig. 11 is a schematic diagram of the layout, based on Fig. 8 a second source-drain metal layer is added; Fig. Figure 12 is a schematic diagram of the layout of the first source-drain metal layer and the second source-drain metal layer according to an embodiment of the present disclosure; Fig. 13 is a schematic diagram based on Fig. 11 the light shielding layer and the through-holes of the second planarization layer are added; Fig. Figure 14 is a schematic diagram of a through-hole formed on an intermediate insulating layer according to an embodiment of the present disclosure; Fig. Figure 15 is a schematic diagram of a through-hole formed on the first planarization layer according to an embodiment of the present disclosure; Fig. Figure 16 is a schematic diagram of a through-hole formed on the second planarization layer according to an embodiment of the present disclosure; Fig. Figure 17 is a schematic diagram of the layout of an anode layer according to an embodiment of the present disclosure; Fig. 18 is a schematic diagram of the layout, based on Fig. 13 an anode layer is added; Fig. 19 is a circuit diagram of a subpixel driver circuit according to an embodiment of the present disclosure; Fig. 20 is a driver timing diagram of a subpixel driver circuit according to an embodiment of the present disclosure; Fig. Figure 21 is a schematic cross-sectional view of each film layer of the display substrate according to an embodiment of the present disclosure; Fig. Figure 22 is a schematic diagram of a second layout of the first source-drain metal layer in the display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0027] In order to further explain the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0028] The present disclosure provides a display substrate. The display substrate comprises a plurality of subpixels. The subpixels include a subpixel driver circuit and a light-emitting element. The subpixel driver circuit uses an 8T1C circuit (i.e., 8 transistors and 1 storage capacitor), wherein the transistors in the subpixel driver circuit all use low-temperature polysilicon transistors.

[0029] As in Fig. As shown in Figure 19, the display substrate also includes a power line VDD, a light emission control signal line EM, a data line DA, a first sampling line GA1, a second sampling line GA2, a third sampling line GA3, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a third initialization signal line Vinit3, and a reset signal line RST. The subpixel driver circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0030] The gate electrode of the first transistor T1 is coupled to the corresponding reset signal line RST, the first electrode of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the gate electrode of the third transistor T3 (i.e., node N1).

[0031] The gate electrode of the second transistor T2 is coupled to the corresponding first scanning line GA1, and the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3, the second electrode of the second transistor T2 is coupled to the gate electrode of the third transistor T3.

[0032] The gate electrode of the fourth transistor T4 is coupled to the corresponding second sampling line GA2, the first electrode of the fourth transistor T4 is coupled to the corresponding data line DA, and the second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3 (i.e., node N2).

[0033] The gate electrode of the fifth transistor T5 is coupled to the corresponding light emission control signal line EM, the first electrode of the fifth transistor T5 is coupled to the current line VDD, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3.

[0034] The gate electrode of the sixth transistor T6 is coupled to the corresponding light emission control signal line EM, and the first electrode of the sixth transistor T6 is coupled to the second electrode (i.e., node N3) of the third transistor T3, the second electrode of the sixth transistor T6 is coupled to the anode Ano (i.e., node N4) of the light-emitting element, and a negative power supply signal VSS is fed into the cathode of the light-emitting element.

[0035] The gate electrode of the seventh transistor T7 is coupled to the corresponding third scanning line GA3, the first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, and the second electrode of the seventh transistor T7 is coupled to the anode Ano of the light-emitting element.

[0036] The gate electrode of the eighth transistor T8 is coupled to the corresponding third sampling line GA3, the first electrode of the eighth transistor T8 is coupled to the third initialization signal line Vinit3, and the second electrode of the eighth transistor T8 is coupled to the first electrode of the third transistor T3.

[0037] The first electrode plate Cst1 of the storage capacitor Cst is coupled to the gate electrode of the third transistor T3, and the second electrode plate Cst2 of the storage capacitor Cst is coupled to the current line VDD. For example, the gate electrode of the third transistor T3 is multiplexed as the first electrode plate Cst1.

[0038] As in the Fig. 19 and Fig. As shown in Figure 20, the display substrate comprises a multitude of driver cycles. Each driver cycle includes a write frame and a hold frame. The working process of the subpixel driver circuitry in each driver cycle is as follows.

[0039] In an inscription frame, at time P1 (i.e., circle 1 in Fig. 2) The light emission control signal transmitted by the light emission control signal line EM is set to a high level, the fifth transistor T5 and the sixth transistor T6 are both switched off, and nodes N1, N2, and N3 are all in a floating state. At time P2 (i.e., circuit 2 in Fig. 2) The third sampling signal transmitted by the third sampling line GA3 is set to a low level, the seventh transistor T7 and the eighth transistor T8 are both switched on, and the third initialization signal transmitted by the third initialization signal line Vinit3 updates the initial bias of a new frame at node N2, while simultaneously the second initialization signal transmitted by the second initialization signal line Vinit2 resets node N4 in time. At time P3 (i.e., circuit 3 in Fig. 2) The reset signal transmitted by the reset signal line RST is set to a low level, the first transistor T1 is switched on, and the first initialization signal transmitted by the first initialization signal line Vinit1 initializes node N1. At time P4 (i.e., circuit 4 in Fig. 2) The first sampling signal transmitted by the first sampling line GA1 is set to a low level, the first transistor T1 and the second transistor T2 are switched on simultaneously, and the first initialization signal transmitted by the first initialization signal line Vinit1 initializes node N1 and completes the initialization of all three nodes in the floating state. At time P5 (i.e., circuit 5 in Fig. 2) The second sampling signal transmitted by the second sampling line GA2 is set to a low level, the fourth transistor T4 is switched on, and a new frame with data signals is written. At time P5-P6 (i.e., circuits 5 and 6 in Fig. 2) The threshold voltage Vth of the third transistor T3 is compensated by the data signal information stored in node N2 and in the parasitic capacitance. At time P6, the first sampling signal transmitted by the first sampling line GA1 is set to a high level, the second transistor T2 is switched off, and the writing process is completed. At time P7 (i.e., circuit 7 in Fig. 2) The third sampling signal, transmitted by the third sampling line GA3, is again set to a low level, and nodes N2 and N4 are reset and updated again before light is emitted to keep the source and drain electrodes of the third transistor T3 in the same state before writing a new frame. At time P8 (i.e., circuit 8 in Fig. 2) The light emission control signal transmitted by the light emission control signal line EM is set to a low level, the fifth transistor T5 and the sixth transistor T6 are switched on, and the light-emitting element in the recording frame is charged and switches on to emit light. In the low-frequency display holding frame, at time P9 and P10 (i.e., circuits 9 and 10 in Fig. 2) the third sampling signal transmitted by the third sampling line GA3 is set to a low level, and both the seventh transistor T7 and the eighth transistor T8 are switched on, so that the bias of node N2 can be updated and node N4 can be reset.

[0040] For example, the reset signal line RST coupled to the subpixel driver circuit is supplied with a signal from a group of light emission control shift register units (EM GOA), for example: the signal transmitted by the reset signal line RST coupled to the nth row of the subpixel driver circuit is provided by the (n-7)th row EM GOA. The signals transmitted by the second sampling line GA2 and the third sampling line GA3 can be provided by independent gate electrode shift register units (Gate GOA), but are not limited to this.

[0041] In the subpixel driver circuit of the above-mentioned structure, an eighth transistor T8 and a third initialization signal line Vinit3 are added, and the voltage of node N2 is updated by timing control, which allows for a low frequency and low power consumption display and improves the problem of flickering at low frequencies.

[0042] While consumers seek low frequencies, low power consumption, and reduced flicker at low frequencies, they also desire higher resolution display products. Due to the size of the display product, the space available for arranging subpixels is severely limited. Therefore, it is necessary to consider the operating principle, the operating state, potential defects of each signal line, and so on, and to design the display thoughtfully to avoid defects.

[0043] With reference to the Fig. Figures 2 to 4 provide embodiments of the present disclosure with a display substrate comprising: a base substrate, a plurality of subpixels, and a first scanning line GA1, both of which are arranged on the base substrate, wherein the first scanning line GA1 comprises at least one section extending along the first direction, and the subpixel comprises a subpixel driver circuit comprising a driver transistor (i.e., the third transistor T3) and a compensation transistor (i.e., the second transistor T2), wherein the gate electrode T2-g of the compensation transistor is coupled to the corresponding first scanning line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driver transistor, and the second electrode of the compensation transistor is coupled to the gate electrode T3-g of the driver transistor;

[0044] The compensation transistor comprises a compensation active layer 22. The compensation active layer 22 comprises a first channel section 221, a second channel section 222, and a first conductor section 223. The first conductor section 223 is coupled to both the first channel section 221 and the second channel section 222; at least part of the orthographic projection of the first conductor section 223 on the base substrate lies between the orthographic projection of the first scanning line GA1 on the base substrate and the orthographic projection of the gate electrode T3-g of the driver transistor on the base substrate.

[0045] For example, the display substrate comprises a multitude of subpixels, and a multitude of subpixel driver circuits contained within the multitude of subpixels are distributed in an array. The multitude of subpixel driver circuits are divided into a multitude of rows of subpixel driver circuits and a multitude of columns of subpixel driver circuits. The multitude of rows of subpixel driver circuits are arranged along the second direction, and each row of subpixel driver circuits comprises a multitude of subpixel driver circuits arranged along the first direction. The multitude of columns of subpixel driver circuits are arranged along a first direction, and each column of subpixel driver circuits comprises a multitude of subpixel driver circuits arranged along a second direction. For example, the first direction and the second direction may intersect.For example, the first direction includes the transverse direction and the second direction the longitudinal direction.

[0046] For example, the subpixel comprises a subpixel driver circuit and a light-emitting element. The subpixel driver circuit is coupled to the anode of the light-emitting element and configured to supply a driver signal to the light-emitting element and control it to emit light.

[0047] For example, the display substrate comprises a plurality of first sampling lines GA1, wherein the plurality of first sampling lines GA1 is arranged along the second direction and the first sampling line GA1 includes at least a portion extending along the first direction. For example, the plurality of first sampling lines GA1 correspond to the plurality of rows of subpixel driver circuits in a one-to-one relationship, and the first sampling line GA1 is coupled to the gate electrode T2 of each compensation transistor in the corresponding row of subpixel driver circuits.

[0048] For example, the compensation transistor comprises a dual-gate transistor, and the first sampling line GA1 is coupled to two gate electrodes of the compensation transistor. For example: the first sampling line GA1 is multiplexed as at least one gate electrode of the compensation transistor.

[0049] For example, the compensation transistor comprises a compensation active layer 22, which includes a first channel section 221, a second channel section 222, and a first conductor section 223. The first conductor section 223 is coupled to both the first channel section 221 and the second channel section 222. For example, the first conductor section 223, the first channel section 221, and the second channel section 222 are formed into an integrated structure.

[0050] For example, at least part of the orthographic projection of the first channel section 221 on the base substrate is located between the orthographic projection of the first scanning line GA1 on the base substrate and the orthographic projection of the gate electrode T3-g of the driver transistor on the base substrate.

[0051] For example, the first channel section 221 and the first conductor section 223 are arranged along the first direction, and the second channel section 222 and the first conductor section 223 are arranged along the second direction.

[0052] From the specific structure of the aforementioned display substrate, it is evident that in the display substrate provided by the embodiment of the present disclosure, the compensation transistor comprises a compensation active layer 22, and at least a portion of the orthographic projection of the first conductor section 223 of the compensation active layer 22 on the base substrate lies between the orthographic projection of the first scanning line GA1 on the base substrate and the orthographic projection of the gate electrode T3-g of the driver transistor on the base substrate. In contrast to the conventional layout method, the arrangement method described above allows the compensation transistor to be formed into a double-gate inversion structure, i.e.,In the same subpixel driver circuit layout area, the first conductor section 223 and the first compensation gate electrode T2-g1 can all be arranged in the area between the first sampling line GA1 and the gate electrode T3-g of the driver transistor, which effectively compresses the vertical design space occupied by the subpixel driver circuit and is conducive to the development of high-resolution display substrates.

[0053] Since the gate electrode T2-g of the compensation transistor is coupled to the first scanning line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driver transistor, and the second electrode of the compensation transistor is coupled to the gate electrode T3-g of the driver transistor. In other words, the compensation transistor itself is coupled to the first scanning line GA1 and the driver transistor. Therefore, at least part of the compensation active layer 22 is located in a region between the first scanning line GA1 and the gate electrode T3-g of the driver transistor, thus preventing defects due to potential differences between them.

[0054] Therefore, the display substrate provided by the embodiments of the present disclosure comprehensively takes into account the working principles, operating states, possible defects, etc. of the subpixel driver circuit and the signal line, and arranges the design sensibly to improve the resolution and avoid defects.

[0055] As in the Fig. As shown in Figures 2 to 4, in some embodiments the compensation transistor comprises a first compensation gate electrode T2-g1 and a second compensation gate electrode T2-g2, wherein the orthographic projection of the first compensation gate electrode T2-g1 on the base substrate covers the orthographic projection of the first channel section 221 on the base substrate and the orthographic projection of the second compensation gate electrode T2-g2 on the base substrate covers the orthographic projection of the second channel section 222 on the base substrate.

[0056] The first compensation gate electrode T2-g1 is coupled to the corresponding first scanning line GA1, and at least a part of the first compensation gate electrode T2-g1 is located between the first scanning line GA1, with which it is coupled, and the gate electrode T3-g of the driver transistors, wherein the first scanning line GA1 is multiplexed as the second compensation gate electrode T2-g2.

[0057] For example, the first compensation gate electrode T2-g1 and the second compensation gate electrode T2-g2 are formed into an integrated structure with the first scanning line GA1, to which they are coupled.

[0058] The above arrangement allows the compensation transistor to be implemented in a dual-gate inversion structure. This means that, within the same subpixel driver circuit layout area, both the first conductor section 223 and the first compensation gate electrode T2-g1 can be located in a region between the first sampling line GA1 and the gate electrode T3-g of the driver transistor. This effectively compresses the vertical design space occupied by the subpixel driver circuit. Since the gate electrode T2-g of the compensation transistor is coupled to the first sampling line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driver transistor, and the second electrode of the compensation transistor is coupled to the gate electrode T3-g of the driver transistor. In other words, the compensation transistor itself is coupled to both the first sampling line GA1 and the driver transistor.Therefore, at least part of the compensation active layer 22 is located in an area between the first scanning line GA1 and the gate electrode T3-g of the driver transistor, thus preventing defects due to potential differences between them.

[0059] As in the Fig. As shown in Figures 3, 4 and 7 to 13, in some embodiments the display substrate further comprises a data line DA and a second sampling line GA2. The second sampling line GA2 comprises at least a portion extending along the first direction. The subpixel driver circuit further comprises a data write transistor (i.e., the fourth transistor T4). The gate electrode T4-g of the data write transistor is coupled to the corresponding second sampling line GA2. The first electrode of the data write transistor is coupled to the corresponding data line DA, and the second electrode of the data write transistor is coupled to the first electrode of the driver transistor.

[0060] As in Fig. As shown in Figure 3, the gate electrode T4-g of the data write transistor is located in the same subpixel on one side of the first sampling line GA1, which faces the gate electrode T3-g of the driver transistor.

[0061] For example, the display substrate further comprises a plurality of data lines DA and a plurality of second sample lines GA2. The plurality of data lines DA are arranged along the first direction, and the data lines DA include at least portions extending along the second direction. The plurality of second sample lines GA2 are arranged along the second direction, and the second sample lines GA2 include at least portions arranged along the first direction.

[0062] For example, the multitude of data lines DA correspond to the multitude of columns of subpixel driver circuits in a one-to-one relationship, and each data line DA is coupled to the individual subpixel driver circuits in the corresponding column of subpixel driver circuits. The second sample lines GA2 are each coupled to the individual subpixel driver circuits in a corresponding row of subpixel driver circuits.

[0063] For example, the first sampling line GA1 and the second sampling line GA2 are independent of each other and can control the transmission of sampling signals independently. The first sampling line GA1 controls the switching on or off of the compensation transistor, and the second sampling line GA2 controls the switching on or off of the data write transistor. Therefore, the compensation transistor and the data write transistor are driven independently of each other.

[0064] For example, the compensation transistor and the data write transistor are driven independently, and the refresh rate and data write are controlled via the data write transistor. The compensation transistor is driven by a group of light emission control shift register units (EM GOA). Because the priority level time of the sample signal output by the EM GOA is longer, the Vth sampling time can be extended, thereby improving the compensation rate and the low-grayscale uniformity of the display substrate.

[0065] In the display substrate provided by the above embodiments, the compensation transistor and the data write transistor can be controlled independently, resulting in a high compensation rate and low grayscale uniformity of the display substrate. By arranging them in the same subpixel, the gate electrode T4-g of the data write transistor is located on the side of the first sampling line GA1 facing the gate electrode T3-g of the driver transistor. This not only avoids the problem of layout position conflict between the gate electrode T4-g of the data write transistor and the first sampling line GA1, but also effectively compresses the vertical design space occupied by the subpixel driver circuitry, which is beneficial for the development of high-resolution display substrates.

[0066] As in the Fig. As shown in Figures 2 to 4, in some embodiments the data write transistor comprises a data active layer 24, and the gate electrode T4-g of the data write transistor comprises a gate electrode body section T4-g1 and a gate electrode extension section T4-g2, which are coupled together, wherein the orthographic projection of the gate electrode body section T4-g1 on the base substrate overlaps at least partially with the orthographic projection of the data active layer 24 on the base substrate, wherein the gate electrode extension section T4-g2 is coupled to the corresponding second scanning line GA2;

[0067] The gate electrode body section T4-g1 and the gate electrode T3-g of the driver transistor are arranged along the first direction, and at least a part of the gate electrode extension section T4-g2 and the gate electrode T3-g of the driver transistor are arranged along the second direction, with the first direction intersecting the second direction; the gate electrode body section T4-g1 and the gate electrode extension section T4-g2 are arranged in the same layer or in different layers.

[0068] For example, the gate electrode extension section T4-g2 can be used as part of the first scanning line GA1, i.e., the gate electrode extension section T4-g2 is located on the first source-drain metal layer, or the gate electrode extension section T4-g2 can also be located in other layers, for example, in the second gate metal layer.

[0069] For example, the gate electrode body section T4-g1 and the gate electrode extension section T4-g2 are formed into an integrated structure. The gate electrode body section T4-g1 comprises at least one section extending along the first direction, and the gate electrode extension section T4-g2 comprises at least one section extending along a third direction, wherein the third direction intersects the first direction and the second direction.

[0070] For example, the orthographic projection of the gate electrode extension section T4-g2 on the base substrate does not overlap with the orthographic projection of the data active layer 24 on the base substrate.

[0071] The above arrangement makes it possible to arrange the gate electrode T4-g of the data write transistor around the gate electrode T3-g of the driver transistor and can be arranged along the boundary extension direction of the gate electrode T3-g of the driver transistor, thereby maximizing the utilization of the surrounding space of the gate electrode T3-g of the driver transistor, which is beneficial for the development of high-resolution display substrates.

[0072] As in Fig. 4, Fig. 6, Fig. 8 and Fig. As shown in Figure 9, in some embodiments the subpixel driver circuit further comprises a first conductive interconnect section 31 and a first reset transistor (i.e. the first transistor T1), wherein the first end of the conductive interconnect section 31 is coupled to the gate electrode T3-g of the driver transistor and the second end of the first conductive interconnect section 31 is coupled to the second electrode of the first reset transistor; the second sampling line GA2 is arranged at least partially around the second end of the first conductive interconnect section 31.

[0073] For example, the gate electrode T4-g of the data write transistor and the first scanning line GA1 are located in the same layer and made of the same material, and the second scanning line GA2 and the first scanning line GA1 are located in different layers, with the second scanning line GA2 and the first conductive link section 31 being located in the same layer and made of the same material. The first conductive link section 31 and the first source-drain metal layer in the display substrate are located in the same layer and made of the same material.

[0074] The above arrangement, in which the second scanning line GA2 at least partially surrounds the second end of the first conductive connection section 31, allows the second scanning line GA2 to bypass the first conductive connection section 31, thereby not only avoiding a short circuit between the second scanning line GA2 and the first conductive connection section 31, but also allowing the second scanning line GA2 to maintain a sufficient safety distance from the first conductive connection section, thus preventing the transition of the scanning signal transmitted on the second scanning line GA2 from influencing the potential of the first conductive connection section 31, thereby ensuring the operational stability and reliability of the subpixel driver circuit.

[0075] As in Fig. 4, Fig. 6, Fig. 7, Fig. 8 and Fig. As shown in Figure 9, the second scanning line GA2 in some embodiments comprises a plurality of straight edge sections GA21 and a plurality of curved edge sections GA22. The straight edge section GA21 and the curved edge section GA22 are arranged alternately along the first direction. The curved edge section GA22 is arranged around the second end of the first conductive connecting section 31. The straight edge section GA21 comprises a projecting end GA21-T. At least part of the orthographic projection of the projecting end GA21-T onto the base substrate and the orthographic projection of the gate electrode T3-g of the driver transistor onto the base substrate are arranged along the second direction, and the projecting end GA21-T is coupled to the gate electrode T4-g of the data write transistor.

[0076] For example, the straight edge section GA21 and the curved edge section GA22, which are adjacent to each other, are coupled together, and the straight edge section GA21 and the curved edge section GA22 are formed into an integrated structure.

[0077] For example, the curved edge section GA22 surrounds half of the second end of the first conductive connecting section 31. The straight edge section GA21 includes at least one section extending along the first direction. The first conductive connecting section 31 includes at least one section extending along the second direction.

[0078] For example, at least part of the orthographic projection of the protruding end GA21-T on the base substrate lies between the orthographic projection of the curved edge section GA22 on the base substrate and the orthographic projection of the gate electrode T3-g of the driver transistor on the base substrate.

[0079] For example, there is an overlap area between the orthographic projection of the protruding end GA21-T on the base substrate and the orthographic projection of the gate electrode extension section T4-g2 on the base substrate, and the protruding end GA21-T and the gate electrode extension section T4-g2 are coupled to each other by through holes in the overlap area.

[0080] The above arrangement allows the curved edge section GA22 in the second scanning line GA2 to perform a similar “ A "-shaped wiring pattern is formed to prevent the transition of the sampling signal transmitted on the second sampling line GA2 from influencing the potential of the first conductive connection section 31, thereby ensuring the operational stability and reliability of the subpixel driver circuit. At the same time, the electrical connection between the second sampling line GA2 and the gate electrode T4-g of the data write transistor is also ensured.

[0081] As in the Fig. 8 and Fig. As shown in Figure 12, in some embodiments the display substrate comprises a reset signal line RST, wherein the gate electrode of the first reset transistor is coupled to the corresponding reset signal line RST and the orthographic projection of the curved edge section GA22 on the base substrate partially overlaps with the orthographic projection of the reset signal line RST on the base substrate; and / or the orthographic projection of the curved edge section GA22 on the base substrate partially overlaps with the orthographic projection of the first scanning line GA1 on the base substrate.

[0082] For example, the display substrate comprises a plurality of reset signal lines RST, wherein the plurality of reset signal lines RST is arranged along the second direction and the reset signal lines RST comprise at least one section extending along the first direction. The plurality of reset signal lines RST correspond to the plurality of rows of subpixel driver circuits in a one-to-one relationship, and the reset signal lines RST are each coupled to the individual subpixel driver circuits in a corresponding row of subpixel driver circuits.

[0083] For example, the overlap area between the orthographic projection of the curved edge section GA22 on the base substrate and the orthographic projection of the reset signal line RST on the base substrate is less than or equal to 10% of the area of ​​the curved edge section GA22. Furthermore, the overlap area between the orthographic projection of the curved edge section GA22 on the base substrate and the orthographic projection of the reset signal line RST on the base substrate can be adjusted to be less than or equal to 5% of the area of ​​the curved edge section GA22.

[0084] For example, the overlap area between the orthographic projection of the curved edge section GA22 on the base substrate and the orthographic projection of the first scanning line GA1 on the base substrate is less than or equal to 30% of the area of ​​the curved edge section GA22. Furthermore, the overlap area between the orthographic projection of the curved edge section GA22 on the base substrate and the orthographic projection of the first scanning line GA1 on the base substrate can be adjusted to be less than or equal to 20% of the area of ​​the curved edge section GA22.

[0085] The above arrangement can avoid crosstalk between the second scanning line GA2 and the reset signal line RST and largely avoid crosstalk between the second scanning line GA2 and the first scanning line GA1.

[0086] As in the Fig. 7, Fig. 8, Fig. 10 and Fig. As shown in Figure 11, in some embodiments the display substrate further comprises a current conductor VDD, and there is a first overlap area between the orthographic projection of the current conductor VDD on the base substrate and the orthographic projection of the first conductive connecting section 31 on the base substrate, and the first overlap area is greater than or equal to 80% of the area of ​​the first conductive connecting section 31.

[0087] For example, the first overlap area is greater than or equal to 90% of the area of ​​the first conductive connecting section 31.

[0088] For example, the display substrate comprises a plurality of power lines VDD, wherein the plurality of power lines VDD are arranged along the first direction and the power lines VDD include at least one section extending along the second direction. The plurality of power lines VDD correspond to the plurality of columns of subpixel driver circuits in a one-to-one relationship, and the power lines VDD are each coupled to the individual subpixel driver circuits in the corresponding column of subpixel driver circuits.

[0089] For example, the VDD power conductor and the source-drain metal layer in the display substrate are arranged in the same layer and made of the same material.

[0090] The aforementioned configuration, where the first overlap area is greater than or equal to 80% of the area of ​​the first conductive connection section 31, enables better shielding of the potential (i.e., the potential of node N1) on the first conductive connection section 31 by the power line VDD. Therefore, in the display substrate provided by the above embodiments, the potential of node N1 can be better shielded by the power line VDD through a suitable arrangement, and the risk of crosstalk in the subpixel driver circuitry during the display process can be reduced.

[0091] As in the Fig. As shown in Figures 10 to 12, in some embodiments the display substrate further comprises a first initialization signal line Vinit1, wherein the first initialization signal line Vinit1 comprises at least one section extending along the second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line Vinit1.

[0092] For example, the display substrate comprises a plurality of first initialization signal lines Vinit1, wherein the plurality of first initialization signal lines Vinit1 are arranged along the first direction and the first initialization signal line Vinit1 includes at least one section extending along the second direction. The first initialization signal line Vinit1 corresponds to a plurality of columns of subpixel driver circuits in a one-to-one relationship, and the first initialization signal line Vinit1 is coupled to each subpixel driver circuit in a corresponding column of subpixel driver circuits.

[0093] For example, the orthographic projection of the first initialization signal line Vinit1 on the base substrate is located between the orthographic projection of the gate electrode T3-g of the driver transistor on the base substrate and the orthographic projection of the data line DA on the base substrate. Due to the arrangement of the first initialization signal line Vinit1 described above, node N1 can be protected from crosstalk caused by the transition of the data signal transmitted on the data line DA.

[0094] For example, the display substrate further comprises a power line VDD, wherein the first initialization signal line Vinit1, the power line VDD, and the data line DA are arranged in the same layer and made of the same material, and wherein the first initialization signal line Vinit1 is located between the power line VDD and the data line DA. For example, the first initialization signal line Vinit1 and the second source-drain metal layer in the display substrate are arranged in the same layer and made of the same material.

[0095] For example, the overlap area between the orthographic projection of the power line VDD onto the base substrate and the lower metal layer (such as the light shielding layer LS, the first gate metal layer, the second gate metal layer, and the first source-drain metal layer) is greater than or equal to 50% of the area of ​​the power line VDD. Furthermore, the overlap area between the orthographic projection of the power line VDD onto the base substrate and the lower metal layer can be set to, but is not limited to, 70% of the area of ​​the power line VDD. The above arrangement is advantageous for improving the transmittance of the high-resolution display substrate.

[0096] As in the Fig. As shown in Figures 4 to 11, in some embodiments the display substrate further comprises a second initialization signal line Vinit2, a third initialization signal line Vinit3, and a third sampling line GA3. The third sampling line GA3 comprises at least one section extending along the first direction; the subpixel also includes a light-emitting element; the subpixel driver circuit also includes a second reset transistor (i.e., the seventh transistor T7) and a third reset transistor (i.e.,the eighth transistor T8), wherein the gate electrode of the second reset transistor and the gate electrode of the third reset transistor are both coupled to the corresponding third sampling line GA3; the first electrode of the second reset transistor is coupled to the second initialization signal line Vinit2, the second electrode of the second reset transistor is coupled to the anode Ano of the light-emitting element; the first electrode of the third reset transistor is coupled to the third initialization signal line Vinit3, the second electrode of the third reset transistor is coupled to the first electrode of the driver transistor.

[0097] For example, the display substrate further comprises a plurality of second initialization signal lines Vinit2, wherein the plurality of second initialization signal lines Vinit2 is arranged along the second direction and the second initialization signal line Vinit2 includes at least a portion extending along the first direction. The plurality of second initialization signal lines Vinit2 correspond to the plurality of rows of subpixel driver circuits in a one-to-one relationship, and the second initialization signal lines Vinit2 are each coupled to every second reset transistor in the corresponding row of subpixel driver circuits.

[0098] For example, the display substrate further comprises a plurality of third initialization signal lines Vinit3, wherein the plurality of third initialization signal lines Vinit3 are arranged along the second direction and the third initialization signal line Vinit3 includes at least one section extending along the first direction. The plurality of third initialization signal lines Vinit3 correspond to the plurality of rows of subpixel driver circuits in a one-to-one relationship, and the third initialization signal lines Vinit3 are each coupled to every third reset transistor in the corresponding row of subpixel driver circuits.

[0099] For example, the display substrate further comprises a plurality of third sampling lines GA3, wherein the plurality of third sampling lines GA3 are arranged along the second direction and the third sampling line GA3 includes at least a portion extending along the first direction. The plurality of third sampling lines GA3 are coupled to the plurality of rows of subpixel driver circuits, and the third sampling lines GA3 are coupled to the gate electrode of every second reset transistor and the gate electrode of every third reset transistor in the corresponding row of subpixel driver circuits.

[0100] By using the second initialization signal, transmitted via the second initialization signal line Vinit2, to reset the anode of the light-emitting element (i.e., node N4), the brightness of the subpixel can be ensured during low-grayscale display. The arrangement of the second initialization signal line Vinit2 and the first source-drain metal layer in the display substrate in the same layer and made of the same material improves the conductivity of the second initialization signal line Vinit2, which contributes to improved display uniformity of the display substrate.

[0101] In some embodiments, the second scanning line and the first scanning line are arranged in different layers, and the orthographic projection of the second scanning line onto the base substrate overlaps at least partially with the orthographic projection of the first scanning line onto the base substrate.

[0102] For example, the display substrate comprises a second gate metal layer and a first source-drain metal layer, wherein the second initialization signal line and the first source-drain metal layer are arranged in the same layer and are made of the same material, and the third initialization signal line and the second gate metal layer are arranged in the same layer and are made of the same material.

[0103] The second and third initialization signal lines are made of metal in different layers, allowing them, both configured to transmit constant voltage signals, to be implemented in a multilayer conductor design. The orthographic projection of the second initialization signal line onto the base substrate overlaps at least partially with the orthographic projection of the third initialization signal line, thus improving the transmittance of the display substrate.

[0104] As in the Fig. 2, Fig. 4, Fig. 6 and Fig. As shown in Figure 8, in some embodiments the display substrate further comprises a current line VDD; the first reset transistor comprises a first reset active layer 21, and the first reset active layer 21 comprises a third channel section 213, a fourth channel section 214 and a second conductor section 215. The second conductor section 215 is coupled to the third channel section 213 and the fourth channel section 214, respectively;

[0105] The orthographic projection of the second conductor section 215 on the base substrate overlaps at least partially with the orthographic projection of the second initialization signal line Vinit2 on the base substrate; and / or the orthographic projection of the second conductor section 215 on the base substrate overlaps at least partially with the orthographic projection of the third initialization signal line Vinit3 on the base substrate; and / or the orthographic projection of the second conductor section 215 on the base substrate overlaps at least partially with the orthographic projection of the power line VDD on the base substrate.

[0106] For example, the first reset transistor comprises a dual-gate transistor, and the orthographic projection of the gate electrode of the first reset transistor on the base substrate covers the orthographic projection of the third channel section 213 on the base substrate and covers the orthographic projection of the fourth channel section 214 on the base substrate. The second conductor section 215 is formed into an integrated structure with the third channel section 213 and the fourth channel section 214. For example, the second conductor section 215 forms an n-type structure with the third channel section 213 and the fourth channel section 214. The third channel section 213 and the fourth channel section 214 are arranged along the first direction.

[0107] The above arrangement makes it possible to shield the second conductor section 215 through the second initialization signal line Vinit2 and / or the third initialization signal line Vinit3, which helps to improve the operating stability of the first reset transistor.

[0108] As in the Fig. 2, Fig. 5 and Fig. As shown in Figure 6, in some embodiments the display substrate further comprises a current line VDD and a first conductive connecting section 31, wherein the first end of the first conductive connecting section 31 is coupled to the gate electrode T3-g of the driver transistor and the second end of the first conductive connecting section 31 is coupled to the second electrode of the compensation transistor; the subpixel driver circuit also comprises a storage capacitor Cst, wherein the first electrode plate Cst1 of the storage capacitor Cst is coupled to the gate electrode T3-g of the driver transistor and the second electrode plate Cst2 of the storage capacitor Cst is coupled to the corresponding current line VDD.

[0109] The compensation active layer 22 further comprises a conductor extension section 224 coupled to the first conductor section 223, and the orthographic projection of the conductor extension section 224 on the base substrate overlaps at least partially with the orthographic projection of the second electrode plate Cst2 on the base substrate; and / or

[0110] The orthographic projection of the first conductor section 223 on the base substrate does not overlap with the orthographic projection of the first conductive connecting section 31 on the base substrate; and / or

[0111] The orthographic projection of the second electrode plate Cst2 on the base substrate overlaps at least partially with the orthographic projection of the first conductor section 223 on the base substrate.

[0112] For example, the orthographic projection of the first electrode plate Cst1 on the base substrate overlaps at least partially with the orthographic projection of the second electrode plate Cst2 on the base substrate.

[0113] For example, the ladder extension section 224 and the first ladder section 223 are designed to form an integrated structure.

[0114] For example, the orthographic projection of the conductor extension section 224 on the base substrate is located between the orthographic projection of the first conductor section 223 on the base substrate and the orthographic projection of the gate electrode T3-g of the driver transistor on the base substrate.

[0115] The above arrangement adds the capacitor formed by the first conductor section 223. This arrangement helps to increase the capacitance formed by the first conductor section 223 during the light emission phase and simultaneously increases the stability of the node voltage of the first conductor section 223, thereby effectively improving flickering problems at low frequencies.

[0116] As in the Fig. 1, Fig. 2 and Fig. As shown in Figure 13, in some embodiments the display substrate further comprises a light-shielding layer LS, and the orthographic projection of the light-shielding layer LS on the base substrate overlaps at least partially with the orthographic projection of the active layer 23 of the driver transistor on the base substrate and overlaps at least partially with the orthographic projection of the compensation active layer 22 on the base substrate.

[0117] For example, an electrical signal is injected into the light-shielding layer LS. The light-shielding layer LS is located between the active layer and the base substrate.

[0118] The above arrangement allows the light shielding layer LS to block and shield the active layer 23 of the driver transistor and the compensation active layer 22, which contributes to improving the operating stability of the driver transistor and the compensation transistor.

[0119] For example, the overlap area between the orthographic projection of the light-shielding layer LS on the base substrate and the orthographic projection of the metal layer in the display substrate onto the base substrate is greater than or equal to 60% of the area of ​​the light-shielding layer LS. Furthermore, the overlap area between the orthographic projection of the light-shielding layer LS on the base substrate and the orthographic projection of the metal layer in the display substrate onto the base substrate can be adjusted to be greater than or equal to 80% of the area of ​​the light-shielding layer LS. This arrangement is advantageous for improving the optical transmittance of the display substrate.

[0120] As in Fig. As shown in Figure 4, in some embodiments the subpixel driver circuit further comprises a power control transistor (i.e., the fifth transistor T5) and a light emission control transistor (i.e., the sixth transistor T6). The display substrate further comprises a plurality of light emission control signal lines EM, wherein the plurality of light emission control signal lines EM are arranged along the second direction and the light emission control signal lines EM include at least one section extending along the first direction. The plurality of light emission control signal lines EM correspond to the plurality of rows of subpixel driver circuits in a one-to-one relationship. The light emission control signal lines EM are each coupled to each power control transistor and each light emission control transistor in the corresponding row of subpixel driver circuits.

[0121] As in the Fig. 12, Fig. 13, Fig. 16, Fig. 17 and Fig. As shown in Figure 18, in some embodiments the subpixel further comprises a light-emitting element, and the light-emitting element comprises an anode Ano; the subpixel driver circuit also comprises a light emission control transistor and the second conductive connecting section 32, the first electrode of the light emission control transistor is coupled to the second electrode of the driver transistor, the first end of the second conductive connecting section 32 is coupled to the second electrode of the light emission control transistor, and the second end of the second conductive connecting section 32 is coupled to the anode Ano via the first through-hole Via1;

[0122] The subpixel further comprises a pixel opening area 40, and the orthographic projection of the pixel opening area 40 on the base substrate does not overlap with the orthographic projection of the first through hole Via1 on the base substrate.

[0123] For example, the display substrate includes a pixel definition layer that defines the pixel opening area 40.

[0124] The arrangement described above, in which the orthographic projection of the pixel opening area 40 on the base substrate does not overlap with the orthographic projection of the first through-hole Via1 on the base substrate, is advantageous for improving the flatness of the anode Ano in the subpixel, thereby improving the display uniformity of the display substrate.

[0125] As in the Fig. 2, Fig. 4, Fig. 17 and Fig. As shown in Figure 18, in some embodiments the subpixels further comprise a light-emitting element, and the light-emitting element comprises an anode Ano; the anode Ano of at least part of the subpixels comprises an anode body section Ano1 and the anode dummy section Ano2; the orthographic projection of the anode body section Ano1 on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer 22 contained in the subpixel to which the anode body section Ano1 on the base substrate belongs; the orthographic projection of the anode dummy section Ano2 on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer 22 on the base substrate contained in the subpixel adjacent to it along the first direction.

[0126] For example, the anode body section Ano1 and the anode dummy section Ano2 are formed into an integrated structure.

[0127] For example, the orthographic projection of the anode body section Ano1 on the base substrate overlaps at least partially with the orthographic projection of the first conductor section 223 in the compensation active layer 22, which is contained in the subpixel to which the anode body section Ano1 belongs, on the base substrate. The orthographic projection of the anode body section Ano1 on the base substrate overlaps at least partially with the orthographic projection of the first channel section 221 in the compensation active layer 22, which is contained in the subpixel to which the anode body section Ano1 belongs, on the base substrate. The orthographic projection of the anode body section Ano1 on the base substrate overlaps at least partially with the orthographic projection of the second channel section 222 in the compensation active layer 22, which is contained in the subpixel to which the anode body section Ano1 belongs, on the base substrate.

[0128] For example, the orthographic projection of the anode dummy section Ano2 on the base substrate overlaps at least partially with the orthographic projection of the first conductor section 223 in the compensation active layer 22, which is contained in the subpixel adjacent to it along the first direction on the base substrate. The orthographic projection of the anode dummy section Ano2 on the base substrate overlaps at least partially with the orthographic projection of the first channel section 221 in the compensation active layer 22, which is contained in the subpixel adjacent to it along the first direction on the base substrate. The orthographic projection of the anode dummy section Ano2 on the base substrate overlaps at least partially with the orthographic projection of the second channel section 222 in the compensation active layer 22, which is contained in the subpixel adjacent to it along the first direction on the base substrate.

[0129] In the display substrate provided by the above embodiment, the corresponding compensation active layer 22 is blocked by the anode body section Ano1 and the anode dummy section Ano2, thereby effectively preventing the display substrate from displaying abnormally under strong light.

[0130] In some embodiments, the display substrate comprises red subpixels, green subpixels and blue subpixels; at least some of the subpixels comprise red subpixels and blue subpixels, and the adjacent subpixels comprise green subpixels.

[0131] For example, the orthographic projection of the anode body section Ano1 in the red subpixel on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer 22 contained in the subpixel to which it belongs on the base substrate; the orthographic projection of the anode dummy section Ano2 in the red subpixel on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer 22 contained in the green subpixel adjacent along the first direction on the base substrate.

[0132] For example, the orthographic projection of the anode body section Ano1 in the blue subpixel on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer 22 contained in the subpixel to which it belongs on the base substrate; the orthographic projection of the anode dummy section Ano2 in the blue subpixel on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer 22 contained in the green subpixel adjacent along the first direction on the base substrate.

[0133] For example, in Fig. As shown in Figure 21, the display substrate comprises a buffer layer BF, an active layer Poly, a first gate electrode insulating layer GI1 and a first gate metal layer Gate1, a second gate electrode insulating layer GI2, a second gate metal layer Gate2, an intermediate insulating layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc., which are laminated sequentially in one direction away from the base substrate 70. The display substrate may also include a passivation layer PVX, but is not limited to this.

[0134] As in Fig. Figure 2 shows the active layer 25 of the power control transistor, the active layer 26 of the light emission control transistor, the active layer 27 of the second reset transistor, and the active layer 28 of the third reset transistor. Fig. 2 shown.

[0135] As in the Fig. Shown in 7, 14 to 16, shows Fig. 7 the third conductive connecting section 33, the fourth conductive connecting section 34, the fifth conductive connecting section 35, the sixth conductive connecting section 36 and the seventh conductive connecting section 37 as well as the eighth conductive connecting section 38.

[0136] The third conductive connection section 33 is coupled to the second electrode plate Cst2 of the storage capacitor Cst via the ninth through-hole Via9, and the third conductive connection section 33 is coupled to the second electrode of the power control transistor via the twelfth through-hole Via12. The third conductive connection section 33 is coupled to the current line VDD via the fifteenth through-hole Via15.

[0137] The fourth conductive connection section 34 is coupled to the first electrode of the driver transistor via the tenth through hole Via10, and the fourth conductive connection section 34 is coupled to the second electrode of the third reset transistor via the thirteenth through hole Via13.

[0138] The fifth conductive connection section 35 is coupled to the second electrode of the light emission control transistor via the eleventh through-hole Via1 1, and the fifth conductive connection section 35 is coupled to the second conductive connection section 32 via the eighteenth through-hole Via18. The second conductive connection section 32 is coupled to the corresponding anode via the first through-hole Via1.

[0139] The sixth conductive connection section 36 is coupled to the first electrode of the data write transistor via the seventh through hole Via7, and the sixth conductive connection section 36 is coupled to the data line DA via the seventeenth through hole Via17.

[0140] The seventh conductive connection section 37 is coupled to the first electrode of the first reset transistor via the fourth through hole Via4, and the seventh conductive connection section 37 is coupled to the first initialization signal line Vinit1 via the sixteenth through hole Via16.

[0141] The eighth conductive connection section 38 is coupled to the third initialization signal line Vinit3 via the second through hole Via2, and the eighth conductive connection section 38 is coupled to the first electrode of the eighth transistor T8 via the third through hole Via3.

[0142] The first conductive connection section 31 is coupled to the second electrode of the first reset transistor via the fifth through hole Via5, and the first conductive connection section 31 is coupled to the gate electrode T3-g of the driver transistor via the eighth through hole Via8.

[0143] The gate electrode T4-g of the data write transistor is coupled to the second sampling line GA2 via the sixth through hole Via6.

[0144] The first electrode of the second reset transistor is coupled to the second initialization signal line Vinit2 via the fourteenth through hole Via14.

[0145] One embodiment of the present disclosure also provides a display substrate comprising: a base substrate and a plurality of subpixels, a second scanning line and a data line, all arranged on the base substrate; wherein the second scanning line comprises at least a portion extending along a first direction, the subpixel comprises a subpixel driver circuit, the subpixel driver circuit comprises a first conductive interconnect section, a driver transistor, a compensation transistor and a data write transistor;

[0146] A first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor via the first conductive connection section; the compensation transistor comprises a compensation active layer, the compensation active layer comprises a first channel section, a second channel section and a first conductor section, the first conductor section being coupled to both the first channel section and the second channel section; at least part of an orthographic projection of the first conductor section on the base substrate lies between an orthographic projection of the second scanning line on the base substrate and the orthographic projections of the gate electrode of the driver transistor on the base substrate;

[0147] A gate electrode of the data write transistor is coupled to the corresponding second sampling line, a first electrode of the data write transistor is coupled to the corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor; at least part of the second sampling line is arranged around one end of the first conductive connection section.

[0148] According to the specific structure of the aforementioned display substrate, in the display substrate provided by the embodiment of the present disclosure, at least a part of the orthographic projection of the first conductor section on the base substrate is located between the orthographic projection of the second scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate; compared to the conventional layout, the above arrangement causes the compensation transistor to form a double-gate inversion structure, i.e., in the same subpixel driver circuit layout area, both the first conductor section and the first compensation gate can be arranged in the area between the second sampling line and the gate electrode of the driver transistor, effectively compressing the vertical design space occupied by the subpixel driver circuit and facilitating the development of high-resolution display substrates.

[0149] In the display substrate provided by the embodiment of the present disclosure, at least a portion of the second scanning line is arranged around one end of the first conductive connection section, allowing the second scanning line to bypass the first conductive connection section. This not only prevents a short circuit between the second scanning line and the first conductive connection section, but also allows the second scanning line to maintain a sufficient safety distance from the first conductive connection section. This prevents the transition of the scanning signal transmitted on the first conductive connection section from influencing the potential of the first conductive connection section, thereby ensuring the operational stability and reliability of the subpixel driver circuit.

[0150] In some embodiments, the display substrate further comprises a power line; the subpixel driver circuit further comprises a storage capacitor, wherein the first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor and the second electrode plate of the storage capacitor is coupled to the corresponding power line; the orthographic projection of the second electrode plate on the base substrate overlaps at least partially with the orthographic projection of the first conductor section on the base substrate; and / or

[0151] An orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the first conductive connection section on the base substrate.

[0152] The above arrangement helps to increase the capacitance formed by the first conductor section during the light emission phase, and at the same time it can increase the stability of the node voltage of the first conductor section and the voltage stability of the first conductive connection section, thereby effectively improving the problem of flickering at low frequencies.

[0153] In some embodiments, the display substrate further comprises a power line; the subpixel driver circuit further comprises a storage capacitor, wherein the first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor and the second electrode plate of the storage capacitor is coupled to the corresponding power line; the orthographic projection of the second electrode plate on the base substrate overlaps at least partially with the orthographic projection of the first conductor section on the base substrate; and / or

[0154] The orthographic projection of the first conductor section on the base substrate does not overlap with the orthographic projection of the first conductive connection section on the base substrate; and / or

[0155] The orthographic projection of the first conductor section onto the base substrate overlaps at least partially with the orthographic projection of the power line onto the base substrate; and / or

[0156] The orthographic projection of the first conductive connection section on the base substrate overlaps at least partially with an orthographic projection of the power line on the base substrate.

[0157] It should be noted that the specific structure of the first conductive connecting section 31 in the above embodiment is Fig. 22 can be seen, but is not limited to this structure.

[0158] The above arrangement contributes to increasing the capacitance formed by the first conductor section during the light emission phase and can simultaneously increase the stability of the node voltage of the first conductor section and the voltage stability of the first conductive connection section, thereby effectively improving the problem of flickering at low frequencies.

[0159] One embodiment of the present disclosure also provides a display device comprising the display substrate provided in the embodiment above.

[0160] In the display substrate provided by the above embodiment, the compensation transistor comprises a compensation active layer, and at least part of the orthographic projection of the first conductor segment in the compensation active layer on the base substrate is located between the orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate. Compared to the conventional layout method, the arrangement method described above allows the compensation transistor to form a double-gate inversion structure, i.e.,Within the same subpixel driver circuit layout area, the first conductor section and the first compensation gate can both be located in the area between the first sampling line and the gate electrode of the driver transistor. This effectively compresses the vertical design space occupied by the subpixel driver circuit, which is beneficial for the development of high-resolution display substrates. Furthermore, since the gate electrode of the compensation transistor is coupled to the first sampling line, the first electrode of the compensation transistor is coupled to the second electrode of the driver transistor, and the second electrode of the compensation transistor is coupled to the gate electrode of the driver transistor. In other words, the compensation transistor itself is coupled to both the first sampling line and the driver transistor.Therefore, at least part of the compensation active layer is located in a region between the first scanning line and the gate electrode of the driver transistor, thus preventing defects due to potential differences between them. Consequently, the display substrate provided by the above embodiments comprehensively considers the operating principles, operating states, potential defects, etc., of the subpixel driver circuitry and the signal lines, and arranges the design sensibly to improve resolution and avoid defects.

[0161] If the display device provided by the embodiment of the present disclosure comprises the above-mentioned display substrate, it also has the above-mentioned advantageous effects, which are not described again here.

[0162] It should be noted that the signal line extending along the X-direction means that the signal line comprises a body section and a secondary section connected to the body section. The body section is a line, a line segment, or a rod-shaped body, and the body section extends along the X-direction, with the length of the body section extending along the X-direction being greater than the length of the secondary section extending along the other directions.

[0163] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc. The display device also includes a flexible circuit board, a printed circuit board, and a back panel, etc.

[0164] It should be noted that the layout area occupied by the subpixel driver circuitry can be any area that can accommodate the subpixel driver circuitry. For example, the area can be rectangular, but it is not limited to that.

[0165] It should be noted that in the embodiments of the present disclosure, “the same layer” can refer to film layers on the same structural layer. Or, for example, the film layers on the same layer can be a layer structure formed by using the same film-forming process to create a film layer to form a specific pattern, and then using the same mask to structure the film layer by means of a structuring process. Depending on the specific pattern, a structuring process may involve several exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also have different heights or different thicknesses.

[0166] In the various embodiments of the present method, the serial numbers of the individual steps cannot be configured in such a way as to restrict the sequence of the individual steps. For a person skilled in the art, the sequence of the individual steps can be changed without any creative effort, which is also within the scope of protection of the present disclosure.

[0167] It should be noted that each embodiment is described progressively, and identical and similar parts may refer to one another between the different embodiments. Each embodiment focuses on its differences from other embodiments. In particular, the process embodiments are described simply, as they are essentially similar to the product embodiments. Relevant details are provided in the description of the product embodiments.

[0168] Unless otherwise defined, the technical or scientific terms used in this disclosure have the usual meanings known to a person skilled in the art in the field of this disclosure. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or meaning, but serve only to distinguish different components. Words such as "comprise" or "consist of" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding any other elements or things. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. "Above," "below," "left," "right," etc., serve only to express relative positional relationships.If the absolute position of the described object changes, the relative position relationship can also change accordingly.

[0169] It is understood that when an element such as a layer, film, area or substrate is described as being “on” or “under” another element, it may be “directly on” or “under” the other element, or that intermediate elements may be present.

[0170] In the above description of embodiments, certain features, structures, materials or properties can be combined in any suitable manner in one or more embodiments or examples.

[0171] The above descriptions relate only to specific embodiments of the present disclosure; however, the scope of protection of the present disclosure is not limited thereto. All modifications or substitutions that a person skilled in the art in this field would readily conceive within the scope of the technology disclosed in this disclosure also fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure is determined by the scope of protection of the stated claims.

Claims

[1] Display substrate comprising: a base substrate, a plurality of subpixels, and a first scanning line, both of which are arranged on the base substrate, the first scanning line comprising at least one section extending along a first direction, and the subpixel comprising a subpixel driver circuit comprising a driver transistor and a compensation transistor, wherein a gate electrode of the compensation transistor is coupled to a corresponding first scanning line, a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor;The compensation transistor comprises a compensation active layer, the compensation active layer comprising a first channel section, a second channel section and a first conductor section, wherein the first conductor section is coupled to the first channel section and the second channel section respectively; at least part of an orthographic projection of the first conductor section on the base substrate is located between an orthographic projection of the first scanning line on the base substrate and the orthographic projection of the gate electrode of the driver transistor on the base substrate. [2] Display substrate according to claim 1, wherein the compensation transistor comprises a first compensation gate electrode and a second compensation gate electrode, an orthographic projection of the first compensation gate electrode on the base substrate covers the orthographic projection of the first channel section on the base substrate, an orthographic projection of the second compensation gate electrode on the base substrate covers the orthographic projection of the second channel section on the base substrate; the first compensation gate electrode is coupled to the corresponding first scanning line, and at least a part of the first compensation gate electrode is located between the first scanning line to which the first compensation gate electrode is coupled and the gate electrode of the driver transistors, wherein the first scanning line is multiplexed as the second compensation gate electrode. [3] Display substrate according to claim 1, wherein the display substrate further comprises a data line and a second sampling line, wherein the second sampling line comprises at least one section extending along the first direction, the subpixel driver circuit further comprises a data write transistor, a gate electrode of the data write transistor is coupled to a corresponding second sampling line, a first electrode of the data write transistor is coupled to a corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor; in an equal subpixel, the gate electrode of the data write transistor is located on a side of the first sampling line facing the gate electrode of the driver transistor. [4] Display substrate according to claim 3, wherein the data write transistor comprises a data active layer, and the gate electrode of the data write transistor comprises a gate electrode body section and a gate electrode extension section coupled together, wherein an orthographic projection of the gate electrode body section on the base substrate overlaps at least partially with an orthographic projection of the data active layer on the base substrate, wherein the gate electrode extension section is coupled to the corresponding second scanning line; the gate electrode body section and the gate electrode of the driver transistor are arranged along the first direction, and at least a part of the gate electrode extension section and the gate electrode of the driver transistor are arranged along a second direction, wherein the first direction intersects the second direction;the gate electrode body section and the gate electrode extension section are arranged in the same layer or in different layers. [5] Display substrate according to claim 3, wherein the subpixel driver circuit further comprises a first conductive interconnect section and a first reset transistor, and a first end of the conductive interconnect section is coupled to the gate electrode of the driver transistor, and a second end of the first conductive interconnect section is coupled to the second electrode of the first reset transistor; the second scanning line is arranged at least partially around the second end of the first conductive interconnect section. [6] Display substrate according to claim 5, wherein the gate electrode of the data write transistor and the first scanning line are arranged in the same layer and are made of the same material, and the second scanning line and the first scanning line are arranged in different layers, wherein the second scanning line and the first conductive connecting section are arranged in the same layer and are made of the same material. [7] Display substrate according to claim 5, wherein the second scanning line comprises a plurality of straight edge sections and a plurality of curved edge sections, wherein the straight edge section and the curved edge section are arranged alternately along the first direction, wherein the curved edge section is arranged around the second end of the first conductive connecting section, wherein the straight edge section comprises a projecting end, at least a part of an orthographic projection of the projecting end onto the base substrate and the orthographic projection of the gate electrode of the driver transistor onto the base substrate are arranged along the second direction, and the projecting end is coupled to the gate electrode of the data write transistor. [8] Display substrate according to claim 5, wherein the display substrate further comprises a first initialization signal line, wherein the first initialization signal line comprises at least one section extending along the second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line; the orthographic projection of the first initialization signal line on the base substrate is located between the orthographic projection of the gate electrode of the driver transistor on the base substrate and the orthographic projection of the data line on the base substrate. [9] Display substrate according to claim 8, wherein the display substrate further comprises a power line, wherein the first initialization signal line, the power line and the data line are arranged in the same layer and are made of the same material, and wherein the first initialization signal line is located between the power line and the data line. [10] Display substrate according to claim 5, wherein the display substrate further comprises a second initialization signal line, a third initialization signal line and a third sampling line, wherein the third sampling line comprises at least one section extending along the first direction; the subpixel also comprises a light-emitting element; the subpixel driver circuit further comprises a second reset transistor and a third reset transistor, wherein a gate electrode of the second reset transistor and a gate electrode of the third reset transistor are both coupled to a corresponding identical third sampling line; a first electrode of the second reset transistor is coupled to the second initialization signal line, a second electrode of the second reset transistor is coupled to an anode of the light-emitting element;a first electrode of the third reset transistor is coupled to the third initialization signal line, a second electrode of the third reset transistor is coupled to the first electrode of the driver transistor. [11] Display substrate according to claim 10, wherein the second scanning line and the first scanning line are arranged in different layers, and the orthographic projection of the second scanning line on the base substrate overlaps at least partially with the orthographic projection of the first scanning line on the base substrate; the display substrate comprises a second gate metal layer and a first source-drain metal layer, wherein the second initialization signal line and the first source-drain metal layer are arranged in the same layer and are made of the same material, and the third initialization signal line and the second gate metal layer are arranged in the same layer and are made of the same material. [12] Display substrate according to claim 10, wherein the display substrate further comprises a current line; the first reset transistor comprises a first reset active layer, and the first reset active layer comprises a third channel section, a fourth channel section and a second conductor section, wherein the second conductor section is coupled to the third channel section and the fourth channel section respectively; an orthographic projection of the second conductor section on the base substrate overlaps at least partially with an orthographic projection of the second initialization signal line on the base substrate; and / or the orthographic projection of the second conductor section on the base substrate overlaps at least partially with an orthographic projection of the third initialization signal line on the base substrate;and / or the orthographic projection of the second conductor section on the base substrate overlaps at least partially with an orthographic projection of the power line on the base substrate. [13] Display substrate according to claim 1, wherein the display substrate further comprises a current line and a first conductive connection section, wherein a first end of the first conductive connection section is coupled to the gate electrode of the driver transistor, and a second end of the first conductive connection section is coupled to the second electrode of the compensation transistor; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding current line;the compensation active layer further comprises a conductor extension section coupled to the first conductor section, and an orthographic projection of the conductor extension section on the base substrate overlaps at least partially with an orthographic projection of the second electrode plate on the base substrate; and / or; an orthographic projection of the first conductor section on the base substrate does not overlap with an orthographic projection of the first conductive connection section on the base substrate; and / or The orthographic projection of the second electrode plate on the base substrate overlaps at least partially with the orthographic projection of the first conductor section on the base substrate. [14] Display substrate according to claim 1, wherein the display substrate further comprises a light shielding layer and an orthographic projection of the light shielding layer on the base substrate overlaps at least partially with the orthographic projection of the active layer of the driver transistor on the base substrate, overlaps at least partially with the orthographic projection of the compensation active layer on the base substrate. [15] Display substrate according to claim 1, wherein the subpixel further comprises a light-emitting element, and the light-emitting element comprises an anode; the subpixel driver circuit further comprises a light emission control transistor and the second conductive interconnect section, wherein a first electrode of the light emission control transistor is coupled to the second electrode of the driver transistor, a first end of the second conductive interconnect section is coupled to a second electrode of the light emission control transistor, and a second end of the second conductive interconnect section is coupled to the anode via a first through-hole; the subpixel further comprises a pixel opening area, and an orthographic projection of the pixel opening area on the base substrate does not overlap with an orthographic projection of the first through-hole on the base substrate. [16] Display substrate according to claim 1, wherein the subpixels further comprise a light-emitting element, and the light-emitting element comprises an anode; the anode of at least one part of the subpixels comprises an anode body section and an anode dummy section; an orthographic projection of the anode body section on the base substrate overlaps at least partially with an orthographic projection of the compensation active layer on the base substrate, which is contained in the subpixel to which the anode body section belongs; an orthographic projection of the anode dummy section on the base substrate overlaps at least partially with the orthographic projection of the compensation active layer on the base substrate, which is contained in the subpixel that is adjacent to the anode dummy section along the first direction. [17] Display substrate according to claim 16, wherein the display substrate comprises red subpixels, green subpixels and blue subpixels; at least a part of the subpixels comprise red subpixels and blue subpixels, and the adjacent subpixels comprise green subpixels. [18] Display substrate comprising: a base substrate and a plurality of subpixels, a second scanning line and a data line, all arranged on the base substrate; wherein the second scanning line comprises at least one section extending along a first direction, the subpixel comprises a subpixel driver circuit, the subpixel driver circuit comprises a first conductive interconnect section, a driver transistor, a compensation transistor and a data write transistor; a first electrode of the compensation transistor is coupled to a second electrode of the driver transistor, and a second electrode of the compensation transistor is coupled to a gate electrode of the driver transistor via the first conductive connection section; the compensation transistor comprises a compensation active layer, the compensation active layer comprising a first channel section, a second channel section and a first conductor section, the first conductor section being coupled to the first channel section and the second channel section respectively; at least part of an orthographic projection of the first conductor section on the base substrate is located between an orthographic projection of the second scanning line on the base substrate and an orthographic projection of the gate electrode of the driver transistor on the base substrate; a gate electrode of the data write transistor is coupled to a corresponding second sampling line, a first electrode of the data write transistor is coupled to a corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the driver transistor; at least part of the second scanning line is arranged around one end of the first conductive connection section. [19] Display substrate according to claim 18, wherein the display substrate further comprises a current line; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding current line; an orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the first conductor section on the base substrate; and / or the orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the first conductive connection section on the base substrate. [20] Display substrate according to claim 18, wherein the display substrate further comprises a current line; the subpixel driver circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is coupled to the gate electrode of the driver transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding current line; an orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the first conductor section on the base substrate; and / or the orthographic projection of the first conductor section on the base substrate does not overlap with an orthographic projection of the first conductive connection section on the base substrate; and / or The orthographic projection of the first conductor section on the base substrate overlaps at least partially with an orthographic projection of the power line on the base substrate. [21] Display device comprising the display substrate according to any one of claims 1 to 20.

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