POWER AMPLIFICATION SYSTEM, POWER AMPLIFICATION METHOD AND DIGITAL PRE-DISTORTION CIRCUIT

Abstract

A power amplification system (7) comprises the following features: power amplifiers (2A, 2B); a switching capacitor circuit (20) configured to generate several discrete voltages based on a regulated voltage supplied by a pre-regulator circuit (10); an output switch circuit (30) configured to selectively output at least one of the several discrete voltages to the power amplifier (2A); and a DPD circuit (71) configured to pre-distort high-frequency signals (RF1, RF2). The pre-regulator circuit (10) is configured to convert an input voltage into a regulated voltage, output the regulated voltage to the switching capacitor circuit (20), and output the regulated voltage directly to the power amplifier (2B) without using the switching capacitor circuit (20).The DPD circuit (71) uses a first mathematical expression model to pre-distort the high-frequency signal (RF1) and uses a second mathematical expression model to pre-distort the high-frequency signal (RF2), or does not pre-distort the high-frequency signal (RF2).

Description

Technical field

[0001] The present invention relates to a power amplification system, a power amplification method and a digital pre-distortion circuit. Background technology

[0002] Nowadays, applying tracking technology to a power amplifier circuit improves the efficiency of power amplification. Patent document 1 discloses a tracker module for D-ET (Digital Envelope Tracking) that provides a power supply voltage that varies to several discrete levels over time (hereinafter referred to as several discrete voltages). Patent document 2 discloses a tracker module for SPT (Symbol Power Tracking) that provides several discrete voltages. Reference list patent document Patent Document 1: US Patent No. 8829993 Patent Document 2: US Patent No. 10686407 Brief description of the invention: Technical problem

[0003] When multiple discrete voltages are supplied to a power amplifier, DPD (digital pre-distortion) can be used to reduce nonlinear distortion that occurs when the power amplifier operates in a nonlinear region. By pre-distorting an input signal before it is supplied to a power amplifier, DPD can eliminate the nonlinear distortion in the power amplifier. With DPD, parameters of a mathematical expression model for DPD (hereinafter referred to as DPD parameters) are stored in memory for each power amplifier, thus increasing the amount of memory required.

[0004] The present invention provides a power amplification system, a power amplification method and a digital pre-distortion circuit that are capable of effectively improving the quality of a transmitted signal while regulating the amount of memory required for DPD parameters. Solution to the problem

[0005] A power amplification system according to one aspect of the invention comprises the following features: a first power amplifier configured to amplify a first high-frequency signal; a second power amplifier configured to amplify a second high-frequency signal; a switching capacitor circuit configured to generate several discrete voltages based on a regulated voltage supplied by a pre-regulator circuit; an output switch circuit configured to selectively output at least one of the several discrete voltages to the first power amplifier; and a digital pre-distortion circuit configured to pre-distort the first and the second high-frequency signals.The pre-regulator circuit is configured to convert an input voltage into the regulated voltage and output the regulated voltage to the switching capacitor circuit. It is also configured to output the regulated voltage directly to the second power amplifier without using the switching capacitor circuit. The digital pre-distortion circuit pre-distorts the first high-frequency signal using a first mathematical expression model for digital pre-distortion. The digital pre-distortion circuit pre-distorts the second high-frequency signal using a second mathematical expression model for digital pre-distortion, or it does not pre-distort the second high-frequency signal.

[0006] A power amplification method according to one aspect of the invention comprises the following steps: converting an input voltage into a regulated voltage; generating several discrete voltages based on the regulated voltage; selectively supplying at least one of the several discrete voltages to a first power amplifier; pre-distorting a first input signal to be supplied to the first power amplifier using a first mathematical expression model; amplifying the pre-distorted first input signal; skipping the generation of the several discrete voltages and supplying the regulated voltage to a second power amplifier; pre-distorting a second input signal to be supplied to the second power amplifier using a second mathematical expression model; and amplifying the pre-distorted second input signal.

[0007] A digital pre-distortion circuit according to one aspect of the invention pre-distorts a first input signal, which is to be supplied to a first power amplifier, using a first mathematical expression model. At least one of several discrete voltages, generated based on a regulated voltage, is selectively supplied to the first power amplifier. The digital pre-distortion circuit pre-distorts a second input signal, which is to be supplied to a second power amplifier, using a second mathematical expression model. The regulated voltage is supplied to the second power amplifier. Advantageous effects of the invention

[0008] A power amplification system according to one aspect of the present invention and other aspects of the invention can effectively improve the quality of a transmitted signal while regulating the amount of memory required for DPD parameters. Brief description of the drawings Fig. 1A is a graph illustrating an example of the transition of a power supply voltage in an APT (Average Power Tracking) mode. Fig. Figure 1B is a graph illustrating an example of the transition of a power supply voltage in an A-ET (Analog Envelope Tracking) mode. Fig. 1C is a graph illustrating an example of the transition of a power supply voltage in a D-ET mode. Fig. Figure 2 is a circuit diagram of a communication device according to an exemplary embodiment. Fig. Figure 3 is a circuit diagram of a tracker module according to the exemplary embodiment. Fig. Figure 4 is a flowchart illustrating a power amplification method according to the exemplary embodiment. Fig. Figure 5 is a layout diagram illustrating the arrangement of components in the communication device according to the exemplary embodiment. Description of exemplary implementations

[0009] Exemplary embodiments of the invention are described in detail below with reference to the drawings. All exemplary embodiments described below illustrate general or specific examples. Numerical values, configurations, materials, elements, positions, and connection states of the elements illustrated in the following exemplary embodiments are merely examples and are not intended to limit the invention.

[0010] The drawings are shown schematically only and are not necessarily precise illustrations. For the sake of clarity, the drawings are exaggerated or omitted, or the proportions of elements in the drawings are adapted. The shapes, positions, and proportions of elements in the drawings may differ from those of the actual elements. In the drawings, substantially identical elements are designated by the same reference numerals, and it is possible that an explanation of such elements will not be repeated or will be simplified.

[0011] In every drawing, the x-axis and y-axis are axes that are perpendicular to each other on a plane parallel to the main surface of a common plate. More precisely, if the common plate has a rectangular shape when viewed from above, the x-axis is parallel to a first side of the common plate, while the y-axis is parallel to a second side and perpendicular to the first side of the common plate. The z-axis is an axis perpendicular to the main surface of the common plate. The positive side of the z-axis is the upward direction, while the negative side of the z-axis is the downward direction.

[0012] In the circuit configurations of the invention, "A is connected to B" includes not only the meaning that A is directly connected to B using a connection terminal and / or a wiring conductor, but also the meaning that A is electrically connected to B via another circuit element. "A is directly connected to B" means that A is directly connected to B using a connection terminal and / or a wiring conductor without any other circuit element being located between A and B. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and that C is arranged in series with a path connecting A and B. "A path connecting A and B" means a path provided by a conductor that electrically connects A and B.

[0013] In the following description, "a terminal" means a point where a conductor ends within an element. If the impedance of a conductor between elements is low enough, a terminal may be interpreted not as a single point, but as certain points on the conductor between the elements, or as the entire conductor.

[0014] In the layout of elements in the invention, "C is closer to A than B is" means that the distance between A and C is shorter than the distance between A and B. "Distance between A and B" means the shortest distance between A and B. That is, "distance between A and B" refers to the length of the shortest line segment among several line segments that connect a specific point on the surface of A and a specific point on the surface of B.

[0015] Expressions representing the relationship between elements, such as "being parallel" and "being vertical," expressions representing the shape of an element, such as "being rectangular," and ranges of numerical values ​​are not necessarily to be interpreted in an exact sense, but rather in a broad sense. This means that such expressions and ranges also cover essentially equivalent ranges, such as a margin of error of a few percent.

[0016] As a technology for amplifying a high-frequency signal with high efficiency, a tracking mode is discussed first, in which a power supply voltage, dynamically adjusted over time based on a high-frequency signal, is delivered to a power amplifier. Tracking mode is a mode in which the power supply voltage to be applied to a power amplifier is dynamically adjusted. There are several types of tracking modes. In this example, an APT mode, an A-ET mode, and a D-ET mode are subsequently discussed with reference to... Fig. 1A, Fig. 1B and 1C explained. In Fig. From 1A to 1C, the horizontal axis represents time and the vertical axis represents voltage. The thick solid line represents the power supply voltage, while the thin solid line (waveform) represents a modulated wave.

[0017] Fig. Figure 1A is a graph illustrating an example of the power supply voltage transition in APT mode. In APT mode, the power supply voltage is varied to several discrete voltage levels in units of frames, based on an average power level. As a result, the power supply voltage signal forms a square wave.

[0018] A frame is a unit that constitutes a high-frequency signal (modulated wave). For example, 5GNR (5th Generation New Radio) and LTE (Long Term Evolution) define a frame as comprising ten subframes, each subframe containing multiple slots, and each slot represented by multiple symbols. The subframe length is 1 ms, and the frame length is 10 ms.

[0019] The mode in which the voltage level is varied in units of frames or in a larger unit based on average power is called APT mode. APT mode is distinguished from a mode in which the voltage level is varied in a unit (for example, subframe, slot, or symbol) smaller than a frame. For example, the mode in which the voltage level is varied in units of symbols is called SPT (Symbol Power Tracking) mode and is distinct from APT mode.

[0020] Fig. Figure 1B is a graph illustrating an example of the power supply voltage transition in A-ET mode. In A-ET mode, the power supply voltage is continuously varied based on an envelope signal, thus tracking the envelope of a modulated wave.

[0021] The envelope signal is a signal that indicates the envelope of a modulated wave. The envelope value is given, for example, by the square root of (I). 2 +Q 2 (I, Q) represents a constellation point. A constellation point is a point on a constellation diagram where a digitally modulated signal is represented. (I, Q) is determined, for example, by a BBIC (Baseband Integrated Circuit) based on transmission information.

[0022] Fig. Figure 1C is a graph illustrating an example of the power supply voltage transition in D-ET mode. In D-ET mode, based on an envelope signal, the power supply voltage is varied to several discrete voltage levels within a frame, thus tracking the envelope of a modulated wave. As a result, the power supply voltage signal forms a square wave. Example of implementation

[0023] An example implementation is described below. 1.1 Circuit configuration of the communication device 6

[0024] The circuit configuration of a communication device 6 according to the exemplary embodiment is first described below with reference to Fig. 2 discussed. Fig. Figure 2 is a circuit diagram of the communication device 6 according to the exemplary embodiment.

[0025] The in Fig. The circuit configuration shown in Figure 2 is only one example. The communication device 6 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following explanation of the communication device 6 should not be interpreted in a limited way.

[0026] In this embodiment, the communication device 6 corresponds to a UE (User Equipment) in a cellular network and is typically, for example, a mobile phone, a smartphone, a tablet computer, or a wearable device. The communication device 6 can be an IoT (Internet of Things) sensor device, a medical / healthcare device, a vehicle, a UAV (Unmanned Aerial Vehicle) (also known as a drone), or an AGV (Automated Guided Vehicle). The communication device 6 can serve as a BS (Base Station) in a cellular network.

[0027] As in Fig. As illustrated in Figure 2, the communication device 6 comprises a tracker module 1, power amplifiers 2A and 2B, an RFIC (Radio Frequency Integrated Circuit) 3, a BBIC 4, and antennas 5A and 5B. A power amplification system 7 comprises the tracker module 1, the power amplifiers 2A and 2B, and the RFIC 3.

[0028] Based on D-ET mode, the tracker module 1 is capable of supplying multiple discrete voltages to the power amplifier 2A as a single power supply voltage Vcc1. Based on APT mode, the tracker module 1 is capable of supplying a regulated voltage to the power amplifier 2B as a single power supply voltage Vcc2.

[0029] Power amplifier 2A is connected between RFIC 3 and antenna 5A. Power amplifier 2A is also connected to tracker module 1. Power amplifier 2A is capable of amplifying a high-frequency signal RF1 received by RFIC 3 using the power supply voltage Vcc1 provided by tracker module 1. The high-frequency signal RF1 is a signal from a first communication system built using radio access technology (RAT). Examples of first communication systems include 5GNR (5th Generation New Radio) systems and 4GLTE (4th Generation Long Term Evolution) systems, but the term "first communication system" is not limited to these examples.

[0030] Power amplifier 2B is connected between RFIC 3 and antenna 5B. Power amplifier 2B is also connected to tracker module 1. Power amplifier 2B is capable of amplifying a high-frequency signal RF2 received by RFIC 3 using the power supply voltage Vcc2 provided by tracker module 1. The high-frequency signal RF2 is a signal from a second communication system established using the RAT. This second communication system differs from the first. One example of a second communication system is a 2G (2nd Generation) communication system, but the second communication system is not limited to this example.

[0031] RFIC 3 is an example of a signal processing circuit that processes a high-frequency signal. RFIC 3 can receive a digital IQ signal from BBIC 4 and supply the high-frequency signals RF1 and RF2 to power amplifiers 2A and 2B, respectively. The internal configuration of RFIC 3 will be discussed later.

[0032] The BBIC 4 is a baseband signal processing circuit that performs signal processing using a frequency band lower than the high-frequency signals RF1 and RF2. The BBIC 4 performs digital modulation on a bit sequence, such as a video signal for displaying an image and / or an audio signal for communication via a loudspeaker, to generate a digital IQ signal. The generated IQ signal is supplied to the RFIC 3. The BBIC 4 can be omitted from the communication device 6.

[0033] Antenna 5A transmits the high-frequency signal RF1, which is amplified by power amplifier 2A, to the outside of the communication device 6. Antenna 5B transmits the high-frequency signal RF2, which is also amplified by power amplifier 2B, to the outside of the communication device 6. Either antenna 5A or 5B can transmit both high-frequency signals RF1 and RF2. In this case, the other antenna 5A or 5B can be omitted from the communication device 6. Alternatively, both antennas 5A and 5B can be omitted from the communication device 6. In this case, the communication device 6 can be connected to an external antenna. 1.2 Internal configuration of the RFIC 3

[0034] The internal configuration of the RFIC 3 is described below with reference to Fig. Figure 2 explains. The RFIC 3 comprises a DPD circuit 71, a DAC (digital-to-analog converter) 72, and a quadrature modulator 73. The RFIC 3 may include a controller (not shown) for controlling the tracker module 1. All or some of the functions of the RFIC 3, other than the controller, may be implemented outside the RFIC 3.

[0035] The DPD circuit 71 is capable of pre-distorting a digital IQ signal provided by the BBIC 4 by using a mathematical expression model for DPD. For example, the DPD circuit 71 can generate a pre-distorted digital IQ signal from the digital IQ signal. The pre-distorted digital IQ signal is then supplied to the DAC 72. The DPD circuit 71 can also skip DPD processing. In this case, the DPD circuit 71 can supply a digital IQ signal provided by the BBIC 4 (that is, a digital IQ signal that is not pre-distorted) to the DAC 72.

[0036] The DAC 72 is capable of converting the digital IQ signal provided by the DPD circuit 71 into an analog IQ signal. The converted analog IQ signal is then supplied to the quadrature modulator 73. The DAC 72 is not limited to a specific DAC and any known DAC can be used.

[0037] The quadrature modulator 73 is capable of generating a high-frequency RF signal by performing quadrature modulation and step-up conversion on the analog IQ signal provided by the DAC 72. The generated RF signal is supplied to the power amplifier 2. The quadrature modulator 73 is not limited to a specific quadrature modulator, and any known quadrature modulator can be used.

[0038] The circuit configuration of the RFIC 3 is not limited to those found in Fig. Figure 2 is shown, which illustrates only one example of the circuit configuration of RFIC 3. For example, one, more, or all of the DPD circuit 71, the DAC 72, and the quadrature modulator 73 can be provided outside of RFIC 3. For example, the DPD circuit 71 can be contained in BBIC 4.

[0039] A mathematical expression model used for DPD in DPD circuit 71 is explained below. In the embodiment, either a first mathematical expression model with memory effects or a second mathematical expression model without memory effects can be used as the mathematical expression model for DPD.

[0040] Memory effects refer to a change in distortion in a power amplifier caused by past input signals. Accordingly, the first mathematical expression model incorporates not only the change in distortion caused by an original (current) input signal, but also that caused by past input signals. Compared to the second mathematical expression model, the first can reduce a greater amount of nonlinear distortion, but increases the computational load.

[0041] In this embodiment, to effectively reduce nonlinear distortion using a smaller amount of memory, DPD is performed using different mathematical expression models for power amplifier 2A and for amplifier 2B. More precisely, an input signal intended for power amplifier 2A is pre-distorted using the first mathematical expression model, while an input signal intended for power amplifier 2B is pre-distorted using the second mathematical expression model, or the input signal is not pre-distorted.

[0042] A specific example of the second mathematical expression model without memory effects is explained below. Equation 1 x[n]=∑i=0N−1cir[n]|r[n]|i x[n]: pre-distorted signal r[n]: original input signal c i : DPD coefficients N: Polynomial order

[0043] The previously described expression (1) is an example of a polynomial used in the second mathematical expression model. The mathematical expression model using expression (1) is called the non-memory polynomial model. In expression (1), the input signal and the power of the input signal are multiplied together with respect to the original input signal r[n]. The polynomial order N and the DPD coefficient c i , the parameters of the polynomial model without memory effect, can be empirically determined in advance and are pre-stored, for example, in a (not shown) memory contained in RFIC 3.

[0044] In expression (1), one might expect that the nonlinear distortion can be reduced if the polynomial order N is increased, but on the other hand, the computational load can increase. Memory effects are not reflected in expression (1). Accordingly, there is a limit to reducing the nonlinear distortion by using a polynomial model without a memory effect.

[0045] A specific example of the first mathematical expression model with memory effects will now be explained below. Equation 2 x[n]=∑i=0N−1∑q=0Qcqir[n−q]|r[n−q]|i x[n]: pre-distorted signal r[n]: original input signal c qi : DPD coefficients Q: Memory depth N: Polynomial order

[0046] The previously described expression (2) is an example of a polynomial used in the first mathematical expression model. The mathematical expression model using expression (2) is called an MPM (memory polynomial model). In expression (2), with respect to each of the input signals r[nq] from the last Q up to the current time 0, the input signal and the power of the input signal are multiplied together. The polynomial order N, the memory depth Q, and the DPD coefficient c qi The parameters of the MPM can be empirically determined in advance and are, for example, pre-stored in a (not shown) memory contained in the RFIC 3.

[0047] In expression (2), it can be expected that the nonlinear distortion can be reduced if the polynomial order N and the memory depth Q are increased, but on the other hand, the number of parameters can be increased, the computational load can be increased, and the convergence properties can be reduced if the DPD coefficient c qi is determined. Equation 3: x[n]=∑i=0N−1∑q=0Qcqir[n−q]|r[n−q]|i⋯(3−1) +∑i=1Nd∑m=1Md∑q=0Qddqmir[n−q]|r[n−q−m]|i⋯(3−2) +∑i=1Ne∑m=1Me∑q=0Qeeqmir[n−q]|r[n−q+m]|i⋯(3−3) x[n]: pre-distorted signal r[n]: original input signal c qi , d qmi , e qmi : DPD coefficients Q: Synchronization memory depth N: Synchronization order Q d : Follow-up storage depth M d : maximum overrun N d : Follow-up order Q e : Pre-storage depth M e : maximum lead time N e Preliminary order

[0048] The previously described expression (3) is an example of a polynomial used in the first mathematical expression model. The mathematical expression model using expression (3) is called a GMP (Generalized Memory Polynomial Model). In expression (3), a synchronization term (3-1) is coupled with a lagging term (3-2) and an antecedent term (3-3). The synchronization term (3-1) is the same as the term in expression (2) for MPM. In the lagging term (3-2), the input signal and the power of the past input signal are multiplied together. In the antecedent term (3-3), the input signal and the power of the future input signal are multiplied together. The polynomial orders N, N d and N e , the memory depths Q and the DPD coefficient c qi , d qmiand e qmi The individual terms that are parameters of the GMP can be empirically determined in advance and are pre-stored, for example, in a (not shown) memory contained in RFIC 3.

[0049] In expression (3) it can be expected that the nonlinear distortion can be reduced if the memory depths Q, Q d and Q e of the individual terms and the crossing widths M d and M e The number of parameters can be increased, the computational load can be increased, and the convergence properties can be reduced if the DPD coefficients c qi , d qmi and e qmi be determined.

[0050] The reduction in nonlinear distortion increases in ascending order for the polynomial model without memory effect, MPM, and GMP. However, at the same time, the number of parameters increases, and the computational load (i.e., the power consumption) also increases in the same order. This means that GMP can reduce nonlinear distortion by a greater degree than MPM and the polynomial model without memory effect, and MPM can reduce nonlinear distortion by a greater degree than the polynomial model without memory effect. Conversely, the polynomial model without memory effect can reduce the computational load by a greater amount than MPM and GMP. MPM can reduce the computational load by a greater amount than GMP. Furthermore, the polynomial model without memory effect requires less memory to store the parameters than MPM and GMP. MPM requires less memory to store the parameters than GMP.

[0051] The first mathematical expression model is not limited to MPM and GMP. This means that a different mathematical expression model than the previously described expressions (2) and (3) can be used as the first mathematical expression model. The second mathematical expression model is not limited to the polynomial model without memory effect. This means that a different mathematical expression model than the previously described expression (1) can be used as the second mathematical expression model. 1.3 Circuit configuration of the tracker module 1

[0052] The circuit configuration of tracker module 1 is described below with reference to Fig. 2 described. The follower module 1 comprises a pre-regulator circuit 10, a switching capacitor circuit 20, an output switch circuit 30, a first and second filter circuit 41 and 42, switches S56 and S57 and a digital control circuit 60.

[0053] The pre-regulator circuit 10 can convert an input voltage provided by a (not shown) DC power source into a regulated voltage using a power inductor. The pre-regulator circuit 10 can supply a regulated voltage to the switching capacitor circuit 20 and can also supply the regulated voltage directly to the power amplifier 2B without using the switching capacitor circuit 20. The pre-regulator circuit 10 includes a power inductor and a switch. The power inductor is an inductor used to boost and / or reduce a DC (direct current) voltage. The power inductor is connected in series with a DC path. The power inductor can be connected between the DC path and ground (that is, the power inductor can be connected in parallel with the DC path).The pre-regulator circuit 10, which is configured as described above, can also be referred to as a magnetic regulator and / or a DC-DC converter.

[0054] The switching capacitor circuit 20 comprises several capacitors and several switches. The switching capacitor circuit 20 is capable of generating several discrete voltages with their respective discrete voltage levels from the voltage provided by the pre-regulator circuit 10. The switching capacitor circuit 20 can also be referred to as a switching capacitor voltage equalizer.

[0055] The output switch circuit 30 can selectively output at least one of the several discrete voltages generated by the switching capacitor circuit 20 to the power amplifier 2A.

[0056] The first and second filter circuits 41 and 42 can attenuate noise from several discrete voltages that are to be supplied to the power amplifier 2A. The first and second filter circuits 41 and 42 can also be referred to as a pulse-shaping filter or a transition-shaping filter.

[0057] Switch S56 is an ON / OFF switch for the first filter circuit 41. Switch S57 is an ON / OFF switch for the second filter circuit 42. Switch S56 is connected between output switch circuit 30 and the first filter circuit 41. Switch S57 is connected between output switch circuit 30 and the second filter circuit 42.

[0058] The digital control circuit 60 is able to control the pre-regulator circuit 10, the switching capacitor circuit 20, the output switch circuit 30 and the switches S56 and S57 based on a digital control signal from the RFIC 3.

[0059] It may be possible to omit some of the pre-regulator circuit 10, the switching capacitor circuit 20, the output switch circuit 30, the first and second filter circuits 41 and 42, the switches S56 and S57, and the digital control circuit 60 from the follower module 1. In one example, the pre-regulator circuit 10 can be omitted from the follower module 1. In another example, the first and second filter circuits 41 and 42 and the switches S56 and S57 may be omitted from the follower module 1. A desired combination of elements selected from the pre-regulator circuit 10, the switching capacitor circuit 20, the output switch circuit 30, the first and second filter circuits 41 and 42, and the switches S56 and S57 can be integrated into a single circuit. Instead of the pre-regulator circuit 10 and the switching capacitor circuit 20, the follower module 1 can include several power supply circuits, as in patent document 2.In this case, the output switch circuit 30 can be configured to select at least one of the several power supply circuits.

[0060] The circuit configurations of the individual circuits contained in the tracker module 1 are described below with reference to Fig. 3 discussed. Fig. Figure 3 is a circuit diagram of the tracker module 1 according to the exemplary embodiment.

[0061] The in Fig. The circuit configuration shown in Figure 3 is just one example. The tracker module 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following explanation of tracker module 1 should not be interpreted in a limited way. 1.3.1 Circuit configuration of the switching capacitor circuit 20

[0062] The circuit configuration of the switching capacitor circuit 20 is first described below with reference to Fig. 3 discussed. As in Fig. As illustrated in Figure 3, the switching capacitor circuit comprises capacitors C11 to C16, capacitors C10, C20, C30 and C40, and switches S11 to S14, S21 to S24, S31 to S34 and S41 to S44. Energy and electric charge are input from the pre-regulator circuit 10 into the switching capacitor circuit 20 via nodes N1 to N4 and are output from the switching capacitor circuit 20 to the output switch circuit 30 via nodes N1 to N4.

[0063] Capacitors C11 to C16 each act as a flying capacitor (also known as a transfer capacitor). This means that each of capacitors C11 to C16 is used to increase or decrease the regulated voltage supplied by the pre-regulator circuit 10. Specifically, capacitors C11 to C16 transfer electrical charge between themselves and nodes N1 to N4, so that voltages V1 to V4 (voltages referenced to ground potential), satisfying the relationship V1:V2:V3:V4 = 1:2:3:4, can be maintained at nodes N1 to N4. The voltages V1 to V4 correspond to several discrete voltages with their respective discrete voltage levels.

[0064] Capacitor C11 has two electrodes. One of the two electrodes of capacitor C11 is connected to one end of switch S11 and to one end of switch S12. The other of the two electrodes of capacitor C11 is connected to one end of switch S21 and to one end of switch S22.

[0065] Capacitor C12 has two electrodes. One of the two electrodes of capacitor C12 is connected to one end of switch S21 and to one end of switch S22. The other of the two electrodes of capacitor C12 is connected to one end of switch S31 and to one end of switch S32.

[0066] Capacitor C13 has two electrodes. One of the two electrodes of capacitor C13 is connected to one end of switch S31 and to one end of switch S32. The other of the two electrodes of capacitor C13 is connected to one end of switch S41 and to one end of switch S42.

[0067] Capacitor C14 has two electrodes. One of the two electrodes of capacitor C14 is connected to one end of switch S13 and to one end of switch S14. The other of the two electrodes of capacitor C14 is connected to one end of switch S23 and to one end of switch S24.

[0068] Capacitor C15 has two electrodes. One of the two electrodes of capacitor C15 is connected to one end of switch S23 and to one end of switch S24. The other of the two electrodes of capacitor C15 is connected to one end of switch S33 and to one end of switch S34.

[0069] Capacitor C16 has two electrodes. One of the two electrodes of capacitor C16 is connected to one end of switch S33 and to one end of switch S34. The other of the two electrodes of capacitor C16 is connected to one end of switch S43 and to one end of switch S44.

[0070] As a result of repeating a first phase and a second phase, a set of capacitors C11 and C14, a set of capacitors C12 and C15, and a set of capacitors C13 and C16 can each perform charging and discharging in a complementary manner.

[0071] In particular, during the first phase, switches S12, S13, S22, S23, S32, S33, S42, and S43 are switched ON. As a result, for example, one of the two electrodes of capacitor C12 is connected to node N3, the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C15 are connected to node N2, and the other of the two electrodes of capacitor C15 is connected to node N1.

[0072] In the second phase, switches S11, S14, S21, S24, S31, S34, S41, and S44 are switched ON. As a result, for example, one of the two electrodes of capacitor C15 is connected to node N3, the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C12 are connected to node N2, and the other of the two electrodes of capacitor C12 is connected to node N1.

[0073] As a result of repeating the first and second phases, if, for example, one of the capacitors C12 and C15 is charged by node N2, the other of the capacitors C12 and C15 can discharge to capacitor C30. This means that capacitors C12 and C15 can perform complementary charging and discharging.

[0074] As with the set of capacitors C12 and C15, as a result of repeating the first phase and the second phase, a set of capacitors C11 and C14 and a set of capacitors C13 and C16 can also perform charging and discharging in a complementary manner.

[0075] Capacitors C10, C20, C30, and C40 each act as a smoothing capacitor. This means that capacitors C10, C20, C30, and C40 are each used to hold and smooth the voltages V1 to V4 at nodes N1 to N4.

[0076] Capacitor C10 is connected between node N1 and ground. Specifically, one of the two electrodes of capacitor C10 is connected to node N1, while the other electrode is connected to ground.

[0077] Capacitor C20 is connected between nodes N2 and N1. Specifically, one of the two electrodes of capacitor C20 is connected to node N2, while the other of the two electrodes of capacitor C20 is connected to node N1.

[0078] Capacitor C30 is connected between nodes N3 and N2. Specifically, one of the two electrodes of capacitor C30 is connected to node N3, while the other of the two electrodes of capacitor C30 is connected to node N2.

[0079] Capacitor C40 is connected between nodes N4 and N3. Specifically, one of the two electrodes of capacitor C40 is connected to node N4, while the other electrode of capacitor C40 is connected to node N3.

[0080] Switch S11 is connected between one of the two electrodes of capacitor C11 and node N3. Specifically, one end of switch S11 is connected to one of the two electrodes of capacitor C11. The other end of switch S11 is connected to node N3.

[0081] Switch S12 is connected between one of the two electrodes of capacitor C11 and node N4. Specifically, one end of switch S12 is connected to one of the two electrodes of capacitor C11. The other end of switch S12 is connected to node N4.

[0082] Switch S21 is connected between one of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S21 is connected to one of the two electrodes of capacitor C12 and to the other of the two electrodes of capacitor C11. The other end of switch S21 is connected to node N2.

[0083] Switch S22 is connected between one of the two electrodes of capacitor C12 and node N3. Specifically, one end of switch S22 is connected to one of the two electrodes of capacitor C12 and to the other of the two electrodes of capacitor C11. The other end of switch S22 is connected to node N3.

[0084] Switch S31 is connected between the other of the two electrodes of capacitor C12 and node N1. Specifically, one end of switch S31 is connected to the other of the two electrodes of capacitor C12 and to one of the two electrodes of capacitor C13. The other end of switch S31 is connected to node N1.

[0085] Switch S32 is connected between the other of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S32 is connected to the other of the two electrodes of capacitor C12 and to one of the two electrodes of capacitor C13. The other end of switch S32 is connected to node N2. That is, the other end of switch S32 is connected to the other end of switch S21.

[0086] Switch S41 is connected between the other of the two electrodes of capacitor C13 and ground. Specifically, one end of switch S41 is connected to the other of the two electrodes of capacitor C13. The other end of switch S41 is connected to ground.

[0087] Switch S42 is connected between the other of the two electrodes of capacitor C13 and node N1. Specifically, one end of switch S42 is connected to the other of the two electrodes of capacitor C13. The other end of switch S42 is connected to node N1. This means that the other end of switch S42 is connected to the other end of switch S31.

[0088] Switch S13 is connected between one of the two electrodes of capacitor C14 and node N3. Specifically, one end of switch S13 is connected to one of the two electrodes of capacitor C14. The other end of switch S13 is connected to node N3. This means that the other end of switch S13 is connected to the other end of switch S11 and to the other end of switch S22.

[0089] Switch S14 is connected between one of the two electrodes of capacitor C14 and node N4. Specifically, one end of switch S14 is connected to one of the two electrodes of capacitor C14. The other end of switch S14 is connected to node N4. That is, the other end of switch S14 is connected to the other end of switch S12.

[0090] Switch S23 is connected between one of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S23 is connected to one of the two electrodes of capacitor C15 and to the other of the two electrodes of capacitor C14. The other end of switch S23 is connected to node N2. This means that the other end of switch S23 is connected to the other end of switch S21 and to the other end of switch S32.

[0091] Switch S24 is connected between one of the two electrodes of capacitor C15 and node N3. Specifically, one end of switch S24 is connected to one of the two electrodes of capacitor C15 and to the other of the two electrodes of capacitor C14. The other end of switch S24 is connected to node N3. This means that the other end of switch S24 is connected to the other end of switch S11, the other end of switch S22, and the other end of switch S13.

[0092] Switch S33 is connected between the other of the two electrodes of capacitor C15 and node N1. Specifically, one end of switch S33 is connected to the other of the two electrodes of capacitor C15 and to one of the two electrodes of capacitor C16. The other end of switch S33 is connected to node N1. This means that the other end of switch S33 is connected to the other end of switch S31 and to the other end of switch S42.

[0093] Switch S34 is connected between the other of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S34 is connected to the other of the two electrodes of capacitor C15 and to one of the two electrodes of capacitor C16. The other end of switch S34 is connected to node N2. This means that the other end of switch S34 is connected to the other end of switch S21, to the other end of switch S32, and to the other end of switch S23.

[0094] Switch S43 is connected between the other of the two electrodes of capacitor C16 and ground. Specifically, one end of switch S43 is connected to the other of the two electrodes of capacitor C16. The other end of switch S43 is connected to ground.

[0095] Switch S44 is connected between the other of the two electrodes of capacitor C16 and node N1. Specifically, one end of switch S44 is connected to the other of the two electrodes of capacitor C16. The other end of switch S44 is connected to node N1. This means that the other end of switch S44 is connected to the other end of switch S31, to the other end of switch S42, and to the other end of switch S33.

[0096] Based on a control signal S2, the ON / OFF state of a first set of switches, comprising switches S12, S13, S22, S23, S32, S33, S42, and S43, and that of a second set of switches, comprising switches S11, S14, S21, S24, S31, S34, S41, and S44, are toggled between them in a complementary manner. Specifically, in the first phase, the switches in the first set are ON, while the switches in the second set are OFF. Conversely, in the second phase, the switches in the first set are OFF, while the switches in the second set are ON.

[0097] For example, in one of the first and second phases, capacitors C11 to C13 charge capacitors C10 to C40, and in the other of the first and second phases, capacitors C14 to C16 charge capacitors C10 to C40. This means that capacitors C10 to C40 are continuously charged by either capacitors C11 to C13 or capacitors C14 to C16. Therefore, even if a high-speed current flows from nodes N1 to N4 to the output switch circuit 30, nodes N1 to N4 are quickly recharged, thus reducing potential variations at nodes N1 to N4.

[0098] The switching capacitor circuit 20 is operated in this way so that a substantially equal voltage is maintained across each of the capacitors C10, C20, C30, and C40. In particular, the voltages V1 to V4 (voltages referenced to a ground potential) can be maintained at nodes N1 to N4, each labeled V1 to V4, satisfying the relationship V1:V2:V3:V4 = 1:2:3:4. The voltage levels of V1 to V4 correspond to several discrete voltage levels that can be supplied by the switching capacitor circuit 20 to the output switching circuit 30.

[0099] The voltage ratio (V1:V2:V3:V4) is not limited to (1:2:3:4). The voltage ratio (V1:V2:V3:V4) can, for example, be (1:2:4:8).

[0100] The configuration of the switching capacitor circuit 20 is not limited to those found in Fig. Figure 3 is shown, which illustrates only one example of the circuit configuration of the switching capacitor circuit 20. Although the in Fig. While the switching capacitor circuit 20 shown in Figure 3 is configured to provide four discrete voltages, the number of discrete voltages is not limited to four. The switching capacitor circuit 20 can be configured to provide any number of multiple (two or more) discrete voltages. For example, if the switching capacitor circuit 20 provides two discrete voltages, it may comprise at least capacitors C12 and C15 and switches S21 to S24 and S31 to S34. 1.3.2 Circuit configuration of the output switch circuit 30

[0101] The circuit configuration of the output switch circuit 30 is described below with reference to Fig. 3 described. As in Fig. As illustrated in Figure 3, the output switch circuit comprises 30 input terminals 131 to 134, switches S51 to S54 and one output terminal 130.

[0102] Output terminal 130 is connected to the first and second filter circuits 41 and 42. Output terminal 130 is a connection for supplying a power supply voltage, selected from voltages V1 to V4, to the power amplifier 2A via the first filter circuit 41 and / or the second filter circuit 42.

[0103] Input terminals 131 to 134 are each connected to nodes N4 to N1 of the switching capacitor circuit 20. Input terminals 131 to 134 are each terminals for receiving the voltages V4 to V1 from the switching capacitor circuit 20.

[0104] Switch S51 is connected between input port 131 and output port 130. Specifically, switch S51 has one terminal connected to input port 131 and one terminal connected to output port 130. With this connection configuration, switch S51 is changed between ON and OFF based on a control signal S3, thus enabling selective connection or disconnection of input port 131 from output port 130.

[0105] Switch S52 is connected between input port 132 and output port 130. Specifically, switch S52 has one terminal connected to input port 132 and one terminal connected to output port 130. With this connection configuration, switch S52 is toggled between ON and OFF based on control signal S3, thus enabling selective connection or disconnection of input port 132 from output port 130.

[0106] Switch S53 is connected between input port 133 and output port 130. Specifically, switch S53 has one terminal connected to input port 133 and one terminal connected to output port 130. With this connection configuration, switch S53 is toggled between ON and OFF based on control signal S3, thus enabling selective connection or disconnection of input port 133 from output port 130.

[0107] Switch S54 is connected between input port 134 and output port 130. Specifically, switch S54 has one terminal connected to input port 134 and one terminal connected to output port 130. With this connection configuration, switch S54 is toggled between ON and OFF based on control signal S3, thus enabling selective connection or disconnection of input port 134 from output port 130.

[0108] Switches S51 to S54 are controlled so that they are mutually exclusive when switched ON. This means that only one of switches S51 to S54 is ON, while the remaining switches are OFF. This allows output switch circuit 30 to output a voltage selected from voltages V1 to V4.

[0109] The circuit configuration of the output switch circuit 30 is not limited to those found in Fig. Figure 3 illustrates only one example of the circuit configuration of the output switch circuit 30. Among other things, switches S51 to S54 can be configured in any way, provided they can selectively connect at least one of the four input terminals 131 to 134 to the output terminal 130. In one example, the output switch circuit 30 can include a different switch between a set of switches S51 to S53 and a set of switch S54 and the output terminal 130. In another example, the output switch circuit 30 can include a different switch between a set of switches S51 and S52 and a set of switches S53 and S54 and the output terminal 130.

[0110] If the switching capacitor circuit 20 provides two discrete voltages with the respective discrete voltage levels, the output switch circuit 30 may only include at least two of the switches S51 to S54. 1.3.3 Circuit configuration of the pre-regulator circuit 10

[0111] The configuration of the pre-regulator circuit 10 is described below with reference to Fig. 3 discussed. As in Fig. As illustrated in Figure 3, the pre-regulator circuit 10 includes an input terminal 110, output terminals 111 to 114, switches S61 to S63 and S71 to S73, a power inductor L71 and capacitors C61 to C64.

[0112] Input port 110 is an input port for a DC voltage. This means that input port 110 is a port for receiving an input voltage from a DC power source 50.

[0113] Output terminal 111 is the output terminal for voltage V4. This means that output terminal 111 is a terminal for supplying voltage V4 to the switching capacitor circuit 20. Output terminal 111 is connected to node N4 of the switching capacitor circuit 20.

[0114] Output terminal 112 is the output terminal for voltage V3. This means that output terminal 112 supplies voltage V3 to the switching capacitor circuit 20 and also supplies voltage V3 to the power amplifier 2B as the power supply voltage Vcc2. Output terminal 112 is connected to node N3 of the switching capacitor circuit 20 and is also connected to the power amplifier 2B.

[0115] Output terminal 113 is the output terminal for voltage V2. This means that output terminal 113 is a connection for supplying voltage V2 to the switching capacitor circuit 20. Output terminal 113 is connected to node N2 of the switching capacitor circuit 20.

[0116] Output terminal 114 is the output terminal for voltage V1. This means that output terminal 114 is a connection for supplying voltage V1 to the switching capacitor circuit 20. Output terminal 114 is connected to node N1 of the switching capacitor circuit 20.

[0117] Switch S71 is connected between input terminal 110 and one end of power inductor L71. Specifically, switch S71 has one terminal connected to input terminal 110 and one terminal connected to one end of power inductor L71. With this connection configuration, as a result of switch S71 being changed between ON and OFF based on a control signal S1, switch S71 can selectively connect input terminal 110 to one end of power inductor L71 or disconnect input terminal 110 from that end of power inductor L71.

[0118] Switch S72 is connected between one end of power inductor L71 and ground. Specifically, switch S72 has one terminal connected to one end of power inductor L71 and one terminal connected to ground. With this connection configuration, as a result of switch S72 being changed between ON and OFF based on control signal S1, switch S72 can selectively connect one end of power inductor L71 to ground or disconnect that end of power inductor L71 from ground.

[0119] Switch S73 is connected between input terminal 110 and power amplifier 2B. More precisely, switch S73 has one terminal connected to input terminal 110 and one terminal connected to power amplifier 2B. With this connection configuration, switch S73, as a result of being switched between ON and OFF based on control signal S1, can selectively connect or disconnect input terminal 110 from power amplifier 2B. That is, switch S73 can be used to select whether the input voltage fed into pre-regulator circuit 10 is supplied to power amplifier 2B.

[0120] Switch S61 is connected between the other end of power inductor L71 and output terminal 111. Specifically, switch S61 has one terminal connected to the other end of power inductor L71 and another terminal connected to output terminal 111. With this connection configuration, as a result of switch S61 being changed between ON and OFF based on control signal S1, switch S61 can selectively connect or disconnect the other end of power inductor L71 from output terminal 111.

[0121] Switch S62 is connected between the other end of power inductor L71 and output terminal 112. Specifically, switch S62 has one terminal connected to the other end of power inductor L71 and another terminal connected to output terminal 112. With this connection configuration, as a result of switch S62 being changed between ON-switched and OFF-switched based on control signal S1, switch S62 can selectively connect or disconnect the other end of power inductor L71 from output terminal 112.

[0122] Switch S63 is connected between the other end of power inductor L71 and output terminal 113. Specifically, switch S63 has one terminal connected to the other end of power inductor L71 and another terminal connected to output terminal 113. With this connection configuration, as a result of switch S63 being changed between ON-switched and OFF-switched based on control signal S1, switch S63 can selectively connect or disconnect the other end of power inductor L71 from output terminal 113.

[0123] One of the two electrodes of capacitor C61 is connected to switch S61 and to output terminal 111. The other of the two electrodes of capacitor C61 is connected to switch S62, to output terminal 112, and to one of the two electrodes of capacitor C62.

[0124] One of the two electrodes of capacitor C62 is connected to switch S62, output terminal 112, and the other of the two electrodes of capacitor C61. The other of the two electrodes of capacitor C62 is connected to a path that links switch S63, output terminal 113, and one of the two electrodes of capacitor C63.

[0125] One of the two electrodes of capacitor C63 is connected to switch S63, to output terminal 113, and to the other of the two electrodes of capacitor C62. The other of the two electrodes of capacitor C63 is connected to output terminal 114 and to one of the two electrodes of capacitor C64.

[0126] One of the two electrodes of capacitor C64 is connected to output terminal 114 and to the other of the two electrodes of capacitor C63. The other of the two electrodes of capacitor C64 is connected to ground.

[0127] Switches S61 to S63 are controlled so that they are mutually exclusive when switched ON. This means that only one of switches S61 to S63 is switched ON, while the remaining switches are switched OFF. Switching only one of switches S61 to S63 ON allows the pre-regulator circuit 10 to vary the voltage supplied to the switching capacitor circuit 20 between the voltage levels of voltages V2 to V4.

[0128] The pre-regulator circuit 10, which is configured as described above, is able to supply an electrical charge to the switching capacitor circuit 20 via at least one of the output terminals 111 to 114.

[0129] If the input voltage is to be converted into only a regulated voltage, the pre-regulator circuit 10 may comprise at least only the switches S71 and S72 and the power inductor L71. 1.3.4 Circuit configuration of the first filter circuit 41 and second filter circuit 42

[0130] The circuit configuration of the first and second filter circuits 41 and 42 according to the exemplary embodiment is described below with reference to Fig. 3 explained.

[0131] The first filter circuit 41 comprises a parallel circuit (LC parallel circuit) consisting of an inductor L51 and a capacitor C51. One end of the parallel circuit consisting of inductor L51 and capacitor C51 is connected to switch S56. The other end of the parallel circuit consisting of inductor L51 and capacitor C51 is connected to power amplifier 2A.

[0132] The second filter circuit 42 comprises a parallel connection of an inductor L52 and a capacitor C52. One end of the parallel connection of inductor L52 and capacitor C52 is connected to switch S57. The other end of the parallel connection of inductor L52 and capacitor C52 is connected to power amplifier 2A.

[0133] The first filter circuit 41, connected in this way, is switched between ON and OFF by switch S56, while the second filter circuit 42, connected in this way, is switched between ON and OFF by switch S57. The first and second filter circuits 41 and 42 can thus switch between ON and OFF a band-elimination filter used to remove noise from several discrete voltages. For example, three types of band-elimination filters, specified by the following modes (1), (2), and (3), can be implemented under the control of the open / close switches S56 and S57. (1) Switch S56 is closed and switch S57 is open, so that the first filter circuit 41 is connected between the output switch circuit 30 and the power amplifier 2A, and the second filter circuit 42 is not connected between them. Then the first filter circuit 41 acts as a band-elimination filter, while the second filter circuit 42 does not act as a band-elimination filter. (2) Switch S56 is open and switch S57 is closed, so that the second filter circuit 42 is connected between the output switch circuit 30 and the power amplifier 2A, and the first filter circuit 41 is not connected between them. Then the second filter circuit 42 acts as a band-elimination filter, while the first filter circuit 41 does not act as a band-elimination filter. (3) Switches S56 and S57 are both closed, so that the first filter circuit 41 and the second filter circuit 42 are both connected between the output switch circuit 30 and the power amplifier 2A. Then the first and the second filter circuit 41 and 42 both act as a band elimination filter.

[0134] The opening / closing of switches S56 and S57 can be controlled, for example, based on the channel bandwidth (i.e., the modulation bandwidth) of a high-frequency signal R1F. If the power amplifier 2A is capable of amplifying transmit signals from multiple frequency bands, the opening / closing of switches S56 and S57 can be controlled, for example, based on the frequency band of a transmit signal to be amplified by the power amplifier 2A. The opening / closing of switches S56 and S57 can also be controlled in another way.

[0135] The circuit configurations of the first and second filter circuits 41 and 42 are not limited to those found in Fig. Figure 3 illustrates only examples of the circuit configurations of the first and second filter circuits 41 and 42. For example, the first filter circuit 41 and / or the second filter circuit 42 can be formed by a series connection of an inductor and a capacitor (LC series circuit). In this case, the LC series circuit can be connected between a ground and a path connecting the output switch circuit 30 and the power amplifier 2A. 1.3.5 Circuit configuration of the digital control circuit 60

[0136] The circuit configuration of the digital control circuit 60 is explained below. As in Fig. As illustrated in Figure 3, the digital control circuit 60 comprises a first control 61 and a second control 62.

[0137] The first controller 61 processes a serial data signal (DATA) based on a clock signal (CLK) provided by RFIC 3, generating control signals S1 to S4. The serial data signal is a data signal transmitted bit-by-bit over a single signal line or circuit.

[0138] Control signal S1 controls the open / close states of switches S61 to S63 and S71 to S73, which are part of the pre-regulator circuit 10. Control signal S2 controls the open / close states of switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44, which are part of the switching capacitor circuit 20. Control signal S3 controls the open / close states of switches S51 to S54, which are part of the output switch circuit 30, when APT mode is applied to power amplifier 2A. Control signal S4 controls the open / close state of switch S56 for the first filter circuit 41 and of switch S57 for the second filter circuit 42.

[0139] For the clock signal, which the first controller 61 is to use to process the serial data signal, a signal line is used that differs from the one used for the serial data signal. However, this is only one example. For instance, the clock signal could be transmitted on the same signal line used for the serial data signal.

[0140] In this embodiment, the single serial data signal is used to control the pre-regulator circuit 10, the switching capacitor circuit 20, the output switch circuit 30, and the switches S56 and S57. However, multiple serial data signals can be used.

[0141] The second controller 62 processes DCL (Digital Control Logic / Line) signals (DCL1, DCL2) provided by RFIC 3, generating a control signal S5. The DCL signal is an example of a parallel data signal. A parallel data signal is a data signal that is transmitted simultaneously to multiple signal lines or circuits in parallel.

[0142] The DCL signals (DCL1, DCL2) are generated by RFIC 3 based on an envelope signal of a high-frequency signal when the D-ET mode is applied to the power amplifier 2A. Similarly, the control signal S5 is a signal for controlling the open / closed states of switches S51 to S54, which are included in the output switch circuit 30, when the D-ET mode is applied to the power amplifier 2A.

[0143] Each of the DCL signals (DCL1, DCL2) is a one-bit signal. The voltages V1 to V4 are each represented by a combination of two one-bit signals. For example, V1, V2, V3, and V4 are represented by "00", "01", "10", and "11", respectively. A Gray code can be used to represent the voltage level.

[0144] In this embodiment, two DCL signals are used to control the output switch circuit 30 in D-ET mode. However, the number of DCL signals is not limited to two. For example, any desired number (one, three, or more) of DCL signals can be used, corresponding to the number of voltage levels that the individual switches of the output switch circuit 30 can select. The digital control signal used to control the output switch circuit 30 is not limited to a single DCL signal. 1.4 Performance Enhancement Procedures

[0145] A power amplification method according to the exemplary embodiment is described below with reference to Fig. 4 described. Fig. Figure 4 is a flowchart illustrating a power amplification method according to the exemplary embodiment.

[0146] First, the pre-regulator circuit 10 converts an input voltage supplied by the DC power source into a regulated voltage (S10). Then, it determines which of the power amplifiers 2A and 2B should be used (S20). That is, it determines whether power amplifier 2A amplifies the high-frequency signal RF1 or power amplifier 2B amplifies the high-frequency signal RF2.

[0147] When power amplifier 2A is to be used (2A at S20), the switching capacitor circuit 20 generates several discrete voltages based on the regulated voltage (S30). The output switch circuit 30 selectively supplies at least one of the several discrete voltages to power amplifier 2A (S40). Then, the D-ET mode is applied to power amplifier 2A. RFIC 3 pre-distorts the input signal (RF1) to be supplied to power amplifier 2A using the first mathematical expression model with memory effects (S50). Power amplifier 2A amplifies the pre-distorted input signal (RF1) (S60).

[0148] If, in contrast, power amplifier 2B is to be used (2B at S20), the pre-regulator circuit 10 supplies the regulated voltage to power amplifier 2B (S70). That is, the generation of discrete voltages is skipped. Then the APT mode is applied to power amplifier 2B. RFIC 3 pre-distorts the input signal (RF2) to be supplied to power amplifier 2B using the second mathematical expression model without memory effects (S80). Power amplifier 2B amplifies the pre-distorted input signal (RF2) (S90).

[0149] The performance enhancement procedure is not based on the one in Fig. Figure 4 is limited and illustrates only one example of the power amplification procedure. For example, at step S80, the input signal to be supplied to power amplifier 2B may not be pre-distorted by RFIC 3. In this case, at step S90, power amplifier 2B amplifies the undistorted input signal. 1.5 Component layout of the communication device 6

[0150] The layout of the components in the communication device 6 is described below with reference to Fig. 5 discussed. Fig. Figure 5 is a layout diagram illustrating the arrangement of components in the communication device 6 according to the exemplary embodiment. More precisely, it is Fig. Figure 5 shows a top view of a common plate 1000 and antennas 5A and 5B. Fig.For ease of understanding the positional relationships between components, each component is labeled with an alphanumeric character representing a component (for example, "PA1"). However, such alphanumeric characters can be omitted from the actual components.

[0151] Antenna 5A (ANT1) and antenna 5B (ANT2) are located near the common plate 1000. The common plate 1000 houses the tracker module 1 (TM), the power amplifier 2A (PA1), the power amplifier 2B (PA2), the RFIC 3, and the BBIC 4.

[0152] Power amplifier 2A is located closer to tracker module 1 than power amplifier 2B. This means that the distance D1 between power amplifier 2A and tracker module 1 is shorter than the distance D2 between power amplifier 2B and tracker module 1.

[0153] Power amplifier 2A is located closer to RFIC 3 than power amplifier 2B. This means that the distance D3 between power amplifier 2A and RFIC 3 is shorter than the distance D4 between power amplifier 2B and RFIC 3. 1.6 Advantages and Others

[0154] As described above, the power amplification system 7 according to the exemplary embodiment comprises: the power amplifier 2A, configured to amplify a high-frequency signal RF1; the power amplifier 2B, configured to amplify a high-frequency signal RF2; the switching capacitor circuit 20, configured to generate several discrete voltages based on a regulated voltage supplied by the pre-regulator circuit 10; the output switch circuit 30, configured to selectively output at least one of the several discrete voltages to the power amplifier 2A; and the DPD circuit 71, configured to pre-distort the high-frequency signals RF1 and RF2.The pre-regulator circuit 10 is configured to convert an input voltage into the regulated voltage and output the regulated voltage to the switching capacitor circuit 20, and also to output the regulated voltage directly to the power amplifier 2B without using the switching capacitor circuit 20. The DPD circuit 71 pre-distorts the high-frequency signal RF1 using a first mathematical expression model for DPD. The DPD circuit 71 either pre-distorts the high-frequency signal RF2 using a second mathematical expression model for DPD or does not pre-distort the high-frequency signal RF2.

[0155] In the power amplification method according to the exemplary embodiment: an input voltage is converted into a regulated voltage (S10); several discrete voltages are generated based on the regulated voltage (S30); at least one of the several discrete voltages is selectively supplied to the power amplifier 2A (S40); a first input signal to be supplied to the power amplifier 2A is pre-distorted with the first mathematical expression model (S50); the pre-distorted first input signal is amplified (S60); the generation of several discrete voltages is skipped and the regulated voltage is supplied to the power amplifier 2B (S70); a second input signal to be supplied to the power amplifier 2B is pre-distorted with the second mathematical expression model (S80); and the pre-distorted second input signal is amplified (S90).

[0156] The DPD circuit 71, according to the exemplary embodiment, pre-distorts the first input signal, which is to be supplied to the power amplifier 2A, using the first mathematical expression model. At least one of several discrete voltages, which are generated based on the regulated voltage, is selectively supplied to the power amplifier 2A. The DPD circuit 71 pre-distorts the second input signal, which is to be supplied to the power amplifier 2B, using the second mathematical expression model. The regulated voltage is supplied to the power amplifier 2B.

[0157] With the configurations and procedures described above, DPD is applied to the input signal to be delivered to power amplifier 2A, to which at least one of several discrete voltages is selectively supplied, based on the first mathematical expression model. DPD is applied to the input signal to be delivered to power amplifier 2B, which receives the regulated voltage, based on the second mathematical expression model, or DPD is not applied to the input signal to be delivered to power amplifier 2B. When several discrete voltages are delivered to a power amplifier, the nonlinear region of the power amplifier may be more likely to be actively used to improve power efficiency than when a regulated voltage is delivered to the power amplifier. This increases nonlinear distortion.Therefore, to reduce nonlinear distortion, the first mathematical expression model is used for the input signal to be delivered to power amplifier 2A, thus prioritizing the improvement of the transmitted signal quality. Conversely, the second mathematical expression model is used for the input signal to be delivered to power amplifier 2B, or DPD is not used for the input signal to be delivered to power amplifier 2B, thus prioritizing the reduction of the amount of memory required for DPD parameters for power amplifier 2B. With this configuration, it is possible to effectively improve the quality of a transmitted signal while regulating the amount of memory required for DPD parameters.

[0158] Additionally, in an example in the power amplification system 7, the power amplification method or the DPD circuit 71 according to the embodiment, it may be possible that memory effects of the power amplifier 2A are integrated into the first mathematical expression model and that memory effects of the power amplifier 2B are not integrated into the second mathematical expression model.

[0159] With this configuration, pre-distorting an input signal using the first mathematical expression model can further improve the quality of a transmitted signal, while pre-distorting an input signal using the second mathematical expression model can further reduce the amount of memory that needs to be used.

[0160] Additionally, in an example in the power amplification system 7, the power amplification method or the DPD circuit 71 according to the embodiment, the D-ET mode can be applied to the power amplifier 2A, while the APT mode can be applied to the power amplifier 2B.

[0161] With this configuration, the first mathematical expression model is used for power amplifier 2A, to which the D-ET mode is applied. The second mathematical expression model is used for power amplifier 2B, to which the APT mode is applied, or DPD is not applied to power amplifier 2B. In D-ET mode, the nonlinear region of a power amplifier is utilized more than in APT mode, thereby increasing nonlinear distortion. Therefore, improving the quality of a transmitted signal is prioritized in D-ET mode, while reducing the amount of memory required for DPD parameters is prioritized in APT mode. It is thus possible to effectively improve the quality of a transmitted signal while regulating the amount of memory required for DPD parameters.

[0162] Additionally, in one example of the power amplification system 7 according to the embodiment, the power amplifier 2A can be arranged closer to the follower module 1, which includes the output switch circuit 30, than the power amplifier 2B.

[0163] This can reduce the length of the power supply path between power amplifier 2A and follower module 1. The voltage level of the power supply voltage Vcc1, which is to be delivered to power amplifier 2A, changes discretely at shorter time intervals than that of the power supply voltage Vcc2, which is to be delivered to power amplifier 2B. The power supply voltage Vcc1 is thus significantly degraded along the power supply path. Reducing the length of the power supply path between power amplifier 2A and RFIC 3 can therefore effectively suppress the degradation of the power supply voltage Vcc1. Conversely, increasing the length of the power supply path between power amplifier 2B and follower module 1 can improve the flexibility in the arrangement of power amplifier 2B.

[0164] Additionally, in one example, in the power amplification system 7 according to the embodiment, the power amplifier 2A can be located closer to the RFIC 3, which includes the DPD circuit 71, than the power amplifier 2B.

[0165] This can reduce the length of the transmission path for the RF1 high-frequency signal between power amplifier 2A and RFIC 3, thus reducing the likelihood of degradation of the input signal (RF1) to power amplifier 2A and consequently reducing the nonlinear distortion of the output signal from power amplifier 2A. Conversely, increasing the length of the transmission path for the RF2 high-frequency signal between power amplifier 2B and RFIC 3 can improve the flexibility of power amplifier 2B's placement. Other examples of implementation

[0166] The power amplification system and power amplification method according to the present invention have been discussed previously by illustrating the exemplary embodiment. However, the power amplification system and power amplification method according to the invention are not limited to the exemplary embodiment described above. Other exemplary embodiments implemented by combining certain elements of the exemplary embodiment described above, and other modified examples obtained by a person skilled in the art making various modifications to the exemplary embodiments described above, without departing from the scope of protection and the essence of the invention, are also included in the invention. Various types of equipment that integrate the power amplification system described above are also included in the invention.

[0167] For example, in the circuit configurations of various circuits according to the previously described embodiment, a different circuit element and different wiring can be inserted into a path that connects circuit elements and / or a path that connects signal paths illustrated in the drawings. In one example, a filter can be inserted between the DAC 72 and the quadrature modulator 73. In another example, a filter can be inserted between the power amplifier 2A and the antenna 5A and / or between the power amplifier 2B and the antenna 5B.

[0168] In the previously described embodiment, several discrete voltages are supplied to the output switch circuit by the switching capacitor circuit. However, this configuration is only an example. For instance, multiple voltages can be provided by the respective DC-DC converters. If the voltage levels of several discrete voltages differ by the same degree, the use of a switching capacitor circuit is preferred, which is effective in reducing the size of a tracer module.

[0169] In the previously described embodiment, four discrete voltages are supplied to the power amplifier. However, the number of discrete voltages is not limited to four. If, for example, several discrete voltages include at least one voltage corresponding to the maximum output power and one corresponding to the most frequently generated output power, the efficiency of a power increase can be improved. Industrial applicability

[0170] The present invention can be widely used for communication equipment, such as a mobile phone, as a power amplification system for amplifying a high-frequency signal. Reference symbol list 1 Follower module 2A, 2B Power Amplifier 3 RFIC 4 BBIC 5A, 5B antenna 6 Communication device 7 Power amplification system 10 Pre-regulator circuit 20 Switching capacitor circuit 30 Output switch circuit 41 first filter circuit 42 second filter circuit 60 Digital control circuit 61 first control 62 second control 71 DPD circuit 72 DAC 73 Quadrature modulator 1000 shared record QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 8829993

[0002] US 10686407

[0002]

Claims

[1] A power amplification system that has the following features: a first power amplifier configured to amplify an initial high-frequency signal; a second power amplifier configured to amplify a second high-frequency signal; a switching capacitor circuit configured to generate multiple discrete voltages based on a regulated voltage supplied by a pre-regulator circuit; an output switch circuit configured to selectively output at least one of the several discrete voltages to the first power amplifier; and a digital pre-distortion circuit configured to pre-distort the first and second high-frequency signals, wherein the pre-regulator circuit is configured to convert an input voltage into the regulated voltage and output the regulated voltage to the switching capacitor circuit, and is also configured to output the regulated voltage directly to the second power amplifier without using the switching capacitor circuit, wherein the digital pre-distortion circuit pre-distorts the first high-frequency signal by using a first mathematical expression model for digital pre-distortion, and wherein the digital pre-distortion circuit either pre-distorts the second high-frequency signal by using a second mathematical expression model for digital pre-distortion or does not pre-distort the second high-frequency signal. [2] The power amplification system according to claim 1, where memory effects of the first power amplifier are integrated into the first mathematical expression model and where memory effects of the second power amplifier are not integrated into the second mathematical expression model. [3] The power amplification system according to claim 1 or 2, where a D-ET (digital envelope tracking) mode is applied to the first power amplifier, and where an APT (Average Power Tracking) mode is applied to the second power amplifier. [4] The power amplification system according to claim 3, wherein the first power amplifier is arranged closer to a follower module comprising the output switch circuit than the second power amplifier. [5] The power amplification system according to claim 3 or 4, wherein the first power amplifier is arranged closer to an integrated circuit comprising the digital pre-distortion circuit than the second power amplifier. [6] A power amplification method that has the following features: Converting an input voltage into a regulated voltage; Generating multiple discrete voltages based on the regulated voltage; selective delivery of at least one of the several discrete voltages to a first power amplifier; Pre-distortion of a first input signal to be delivered to the first power amplifier by using a first mathematical expression model; Amplifying the pre-distorted first input signal; Skipping the generation of the multiple discrete voltages and delivering the regulated voltage to a second power amplifier; Pre-distorting a second input signal to be delivered to the second power amplifier by using a second mathematical expression model; and Amplifying the pre-distorted second input signal. [7] The power amplification method according to claim 6, wherein memory effects of the first power amplifier are integrated into the first mathematical expression model and wherein memory effects of the second power amplifier are not integrated into the second mathematical expression model. [8] The power enhancement method according to claim 6 or 7, where a D-ET mode is applied to the first power amplifier, and where an APT mode is applied to the second power amplifier. [9] A digital pre-distortion circuit, wherein the digital pre-distortion circuit pre-distorts a first input signal to be delivered to a first power amplifier by using a first mathematical expression model, wherein at least one of the several discrete voltages generated based on a regulated voltage is selectively delivered to the first power amplifier; and wherein the digital pre-distortion circuit pre-distorts a second input signal, which is to be supplied to a second power amplifier, by using a second mathematical expression model, the regulated voltage being supplied to the second power amplifier. [10] The digital pre-distortion circuit according to claim 9, wherein memory effects of the first power amplifier are integrated into the first mathematical expression model and wherein memory effects of the second power amplifier are not integrated into the second mathematical expression model. [11] The digital pre-distortion circuit according to claim 9 or 10, where a D-ET mode is applied to the first power amplifier, and where an APT mode is applied to the second power amplifier.

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