DISPLAY

Abstract

[Problem] Providing a display capable of detecting the positions of both a finger and an electromagnetic resonance stylus without interfering with attempts to shrink a frame and without increasing the size of a sensor controller circuitry. [Solution] A display according to the invention comprises a display layer 10, comprising a group of light sources 30 arranged in a display area A1, and a group of pixel control circuits 35 for switching the light sources 30 on and off, an encapsulation layer 13 encapsulating the display layer 10, a group of linear electrodes 52, 53 arranged on the encapsulation layer 13, and a group of routing paths 60 whose ends are connected to the linear electrodes 52. A logic circuit 70 is arranged in the display layer 10 within the display area A1 and is connected to other ends of the routing paths 60 to switch between a first mode in which the linear electrodes 52, 53 are used to detect induced currents and a second mode in which the linear electrodes 52, 53 are used to detect capacitances.

Description

BACKGROUND OF THE INVENTION 1. Field of the invention

[0001] The present invention relates to a display, and in particular to a display based on on-cell touch technology. 2. Description of the state of the art

[0002] In recent years, a technology has gained increasing attention (hereafter referred to as "on-cell touch technology") in which a group of linear electrodes, used to detect the position of a finger on a touch panel, is arranged on the top surface of a display. For example, according to on-cell touch technology in connection with organic electroluminescence (EL) displays, a group of linear electrodes is formed on the top surface of an encapsulation layer that encapsulates a display layer—that is, a layer on which light-emitting elements and pixel-driving circuitry are arranged. U.S. Patent No. 10739889 and U.S. Patent No. 11462597 disclose examples of on-cell touch technology.

[0003] The authors of the present invention have worked on detecting, in addition to the position of a finger using a capacitance sensing method, the position of an electromagnetic resonance stylus using an electromagnetic resonance sensing method. This requires logic circuits (or switching circuits) for applying voltages to detect capacitances and for supplying currents to detect electromagnetic resonance currents in time-division multiplexing. Previously, it was common to place the logic circuits (or switching circuits) in a frame area A2, i.e., an area outside a display area, or in a sensor controller that includes integrated circuits for applying voltages and supplying currents to a group of touch electrodes.According to the first approach, however, the switching circuits present an obstacle to attempts to reduce the frame size. The latter design generally leads to an increase in the size of the sensor controller circuitry. BRIEF SUMMARY OF THE INVENTION

[0004] Therefore, it is an object of the present invention to provide a display capable of detecting the positions of both a finger and an electromagnetic resonance stylus in relation to the display, without this being an obstacle to attempts to reduce its frame area, and moreover without increasing the size of the circuitry of a sensor controller of the display.

[0005] Circuits for applying voltages and supplying currents to a group of linear electrodes, that is, drive circuits for a group of linear electrodes, typically require complementary metal-oxide semiconductors (CMOS) in their output stages. Metal-oxide-semiconductor field-effect transistors (MOSFETs), which form the pixel drive circuits of displays, are generally either of the P-channel or N-channel type. Consequently, a process such as ion implantation would be required solely for the purpose of integrating the drive circuits for a group of linear electrodes into a display layer, thus increasing the display's cost.

[0006] Therefore, a further object of the present invention is to provide a display in which an increase in costs can be avoided, while its control circuits for a group of linear electrodes are arranged in a display layer of the display.

[0007] According to one aspect of the present invention, a display is provided comprising: a display layer comprising a group of luminescent elements arranged in a display area and a group of pixel drive circuits for turning the luminescent elements on and off; an encapsulation layer encapsulating the display layer; a group of linear electrodes arranged on the encapsulation layer; a group of routing paths having ends connected to the linear electrodes; and a switching circuit arranged in the display layer within the display area and connected to other ends of the routing paths to switch between a first mode in which the linear electrodes are used to detect induced currents and a second mode in which the linear electrodes are used to detect capacitances.

[0008] According to a further aspect of the present invention, a display is provided comprising: a display layer comprising a group of luminescent elements arranged in a display area and a group of pixel control circuits for switching the luminescent elements on and off, a group of linear electrodes lying above the display layer, and a group of control circuits arranged in the display layer for controlling the linear electrodes, each of the control circuits comprising one or more MOSFETs of a single type.

[0009] Since the switching circuit is located in the display layer within the display area, attempts to reduce the size of the frame area are not hindered, and an increase in the size of the sensor controller circuits is prevented, while at the same time the positions of both a finger and an electromagnetic resonance stylus can be detected.

[0010] Since all the drive circuits arranged in the display layer for controlling the linear circuits are formed from MOSFETs of the same channel type, according to the other aspect of the present invention, an increase in the cost of manufacturing the display can be prevented while the drive circuits for controlling the linear electrodes are arranged in the display layer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a perspective view, partly in block form, of a computer according to a first embodiment of the present invention; Fig. Figure 2 is an enlarged cross-sectional view of an organic EL-based display along line AA of Fig. 3; Fig. 3 is a top view of a sensor layer according to the first embodiment of the present invention; Fig. Figure 4 is a perspective view of the organic EL-based display according to the first embodiment; Fig. Figure 5 is a block diagram illustrating the internal configurations of logic circuits according to the first embodiment; Fig. 6A and Fig. 6B are block diagrams illustrating how a sensor controller controls the logic circuits in the computer according to the first embodiment; Fig. Figure 7 is an enlarged cross-sectional view of the organic EL-based display along line BB of Fig. 3; Fig. Figure 8 is an enlarged cross-sectional view of the organic EL-based display along the CC line. Fig. 3; Fig. Figure 9 is a block diagram illustrating the configuration and operation of a control circuit for generating transmission signals; Fig. Figure 10 is a block diagram illustrating the configuration and operation of the control circuit for generating the transmission signals; Fig. Figure 11 is a block diagram illustrating the configuration and operation of the control circuit for generating the transmission signals; Fig. Figure 12 is a block diagram illustrating the configuration and operation of the control circuit for generating the transmission signals; Fig. 13 is a circuit diagram, partly in block form, showing the specific configuration details of in Fig. 9 to 12 illustrated shift registers and selection circuits; Fig. 14 is a circuit diagram showing the internal configuration of a shift register S contained in the shift registers <0> illustrated; Fig. Figure 15 is a diagram illustrating signal waveforms that simulate the operation of a register circuit and a buffer circuit; Fig. Figure 16 is a diagram illustrating signal waveforms that simulate the operation of the register circuit, the buffer circuit, and a shift circuit; Fig. Figure 17 is a diagram illustrating signal waveforms that simulate different signals applied to respective stages of the shift registers in the same simulation as in Fig. 16 will be created; Fig. Figure 18 is a diagram illustrating signal waveforms that simulate different signals applied to respective stages of the shift registers in the same simulation as in Fig. 16 will be created; Fig. Figure 19 is a diagram illustrating signal waveforms that simulate different signals applied to respective stages of the shift registers in the same simulation as in Fig. 16 will be created; Fig. Figure 20 is a diagram illustrating signal waveforms that simulate different signals applied to a selection circuit in the same simulation as in Fig. 16 to 19 will be created, Fig. 21 is a diagram illustrating signal waveforms that simulate the transmitted signals from selection circuits in the same simulation as in Fig. 16 to 20 will be issued; Fig. 22A and Fig. 22B are block diagrams illustrating how a sensor controller controls logic circuits in a computer according to a modification of the first embodiment; Fig. 23 is a top view of a sensor layer according to a second embodiment of the present invention; Fig. Figure 24 is a perspective view of an organic EL-based display according to the second embodiment; Fig. 25A and Fig. 25B are block diagrams illustrating how a sensor controller controls logic circuits in a computer according to the second embodiment; Fig. 26 is a top view of a sensor layer according to a third embodiment of the present invention; Fig. 27 is a perspective view of an organic EL-based display according to the second embodiment; Fig. Figure 28 is a circuit diagram illustrating the internal configurations of logic circuits according to the third embodiment; Fig. Figure 29 is a block diagram illustrating the way in which a sensor controller, having entered a second mode, controls logic circuits in a computer according to the third embodiment; Fig. 30A and Fig. Figure 30B are block diagrams illustrating the way in which the sensor controller, having entered a first mode, controls the linking circuits in the computer according to the third embodiment; Fig. Figure 31 is a circuit diagram illustrating the configuration of an organic EL-based display and the internal configurations of logic circuits according to a fourth embodiment of the present invention; Fig. Figure 32 is a block diagram illustrating the way in which a sensor controller, having entered a second mode, controls the logic circuits in a computer according to the fourth embodiment; Fig. 33A and Fig. 33B are block diagrams illustrating the way in which the sensor controller, having entered a first mode, controls the linking circuits in the computer according to the fourth embodiment; Fig. 34A and Fig. 34B are block diagrams illustrating the way in which the sensor controller, having entered the first mode, controls the linking circuits in the computer according to the fourth embodiment; Fig. 35A and Fig. 35B are block diagrams illustrating the way in which a sensor controller, having entered a first mode, controls logic circuits in a computer according to a modification of the fourth embodiment; Fig. 36A and Fig. 36B are block diagrams illustrating the way in which the sensor controller, having entered the first mode, controls the linking circuits in the computer according to the modification of the fourth embodiment; Fig. 37 is a top view of a sensor layer according to a fifth embodiment of the present invention; Fig. Figure 38 is a perspective view of an organic EL-based display according to the fifth embodiment; and Fig. Figure 39 is a top view illustrating a top surface of a planarizing insulating film of the organic EL-based display according to the fifth embodiment. DETAILED DESCRIPTION OF PREFERRED EXECUTION FORMS

[0011] Preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0012] Fig. Figure 1 illustrates in perspective a computer 1 according to a first embodiment of the present invention. As in Fig. As illustrated in Figure 1, the computer 1 according to the first embodiment comprises an organic EL-based display 2, a host processor 3, and a sensor controller 4. Although the principles of the present invention are described in application to the computer 1, which has the organic EL-based display 2 according to the first embodiment, the principles of the present invention are also applicable to other types of displays, including, for example, a liquid crystal display.

[0013] The organic EL-based Display 2 has a panel surface that, according to the perspective view, is in Fig. Figure 1 is illustrated as a top side. As in Fig. As illustrated in Figure 1, the organic EL-based display 2 has a layered structure, including a circuit layer 11, an organic EL-based layer 12, an encapsulation layer 13, and a sensor layer 14, which are stacked sequentially in that order from a bottom side facing away from the panel surface. The circuit layer 11 and the organic EL-based layer 12 together form a display layer 10, which includes various components, such as light-emitting elements 30 (described later) and pixel-driving circuits 35, for performing the display function of the organic EL-based display 2. The sensor layer 14 includes various components, such as linear electrodes 52 and 53 (described later) for detecting the positions of an electromagnetic resonance stylus P and a finger E on the panel surface.

[0014] As in Fig. As illustrated in Figure 1, the organic EL-based display 2 comprises a display area A1 and a frame area A2, which is located outside and around the display area A1. The frame area A2 includes several lines or interconnect connections SL and a connector area 16, which contains several terminals. The lines SL electrically connect circuits, wires, and electrodes located in the circuit layer 11, the organic EL-based layer 12, and the sensor layer 14 to the terminals on the connector area 16. For brevity, in Fig. Figure 1 illustrates only some of the lines SL that are actually provided in the organic EL-based display 2. The terminals on terminal area 16 are electrically connected to the host processor 3 or the sensor controller 4 via lines located outside the organic EL-based display 2.

[0015] Fig. Figure 2 illustrates the organic EL-based display 2 in cross-section along line AA of Fig. 3, as will be described later. Since Fig. Figure 2 is a schematic cross-sectional view illustrating structural details for a better understanding of the organic EL-based display. Figure 2 corresponds to the figures in Fig. The structural details illustrated do not necessarily correspond to those in Fig. 3 illustrated agree. This also applies to Fig. 7 and Fig. 8, as will be described later. As in Fig. As illustrated in Figure 2, the circuit layer 11, the organic EL-based layer 12, the encapsulation layer 13, and the sensor layer 14 are stacked sequentially in that order onto the top of a substrate 20. The structure of the organic EL-based display 2 is described below with reference to Fig. 2 briefly described.

[0016] Circuit layer 11 refers to a layer comprising a matrix of pixel driver circuits 35 and is formed from a buffer layer 21, a gate insulating film 22, an intermediate insulating film 23, and a planar insulating film 24. The pixel driver circuits 35 function as active elements associated with respective pixels of the organic EL-based display 2. The pixels are arranged in a two-dimensional matrix, grouped in rows and columns. More precisely, each pixel driver circuit 35 includes a P-channel MOSFET. Each pixel driver circuit 35 comprises a semiconductor layer 36 providing a channel region, a gate electrode 37 positioned above the semiconductor layer 36 with the gate insulating film 22 between them, a drain electrode 38, and a source electrode 39.Each of the drain electrode 38 and the source electrode 39 comprises a via conductor having a lower end that is held in contact with the semiconductor layer 36 and an electrical conductor that is arranged on the top side of the interlayer insulating film 23.

[0017] Although not shown, circuit layer 11 further comprises several gate lines extending along the rows of pixels, as well as several data lines extending along the columns of pixels. The gate lines are electrically connected to the respective gate electrodes 37 of those pixel drive circuits 35 arranged along the corresponding rows. The data lines are electrically connected to the respective source electrodes 39 of those pixel drive circuits 35 arranged along the corresponding columns. The gate lines and the data lines are connected via the Fig. 1. Lines SL are electrically connected to the host processor 3.

[0018] The organic EL-based layer 12 is a layer comprising a matrix of light-emitting elements 30, i.e., a group of light-emitting elements, and is formed from an anode electrode 31, a bank layer 25, a phosphor layer 32, and a cathode electrode 33, which are stacked sequentially in that order, starting from the substrate 20. The anode electrode 31 has an electrically conductive film arranged on the top side of the planar insulating film 24 and has separate sections, each associated with the pixels. Through-holes are defined in the planar insulating film 24 at the respective positions where the drain electrodes 38 of the respective pixel driver circuits 35 are exposed. The separate sections of the anode electrode 31 are held in contact with the drain electrodes 38 of the corresponding pixel driver circuits 35 by their sections formed in the through-holes.

[0019] The bank layer 25 has an insulating film provided to separate adjacent pixels and increase the light extraction efficiency with which light is extracted from the phosphor layer 32. The phosphor layer 32 has a thin film of an organic material that emits light when an electric current is applied to it. The organic material of the phosphor layer 32 has a specific composition chosen to emit light of a preset color from each pixel. Through-holes are defined in the bank layer 25 at the positions where the separate sections of the anode electrode 31 of the respective pixel driver circuits 35 are exposed. The phosphor layer 32 is held in contact with the corresponding separate sections of the anode electrode 31 by its sections formed in the through-holes.

[0020] The cathode electrode 33 has an electrically conductive film located on the top side of the phosphor layer 32, which is shared by the pixels. Although not shown, the organic EL-based layer 12 has grounding leads connected to the surface via the Fig. In Figure 1, a ground potential is applied to the lines SL. The cathode electrode 33 is electrically connected to the grounding lines. A structure in which the anode electrode 31 and the cathode electrode 33 accommodate the phosphor layer 32 between them is arranged at a position of each pixel, thereby providing one of the phosphor elements 30.

[0021] The following briefly describes the operation of the light elements 30 and the pixel control circuits 35. The host processor 3 generates video signals and controls the gate lines and data lines based on these signals by executing programs stored in memory (not illustrated). More precisely, based on the generated video signals, the host processor 3 determines the luminance values ​​for each pixel grouped along a gate line, activates the gate line along which the pixels are grouped, and supplies data lines with drive currents representing the determined luminance values ​​for the pixels along the activated gate line. The host processor 3 repeats the above process as it switches from one gate line to another for the purpose of activation.

[0022] When the gate line is activated by the host processor 3, the pixel driver circuits 35 grouped in series along the gate line are simultaneously switched on, thereby connecting the anode electrodes 31 of the corresponding light elements 30 to the data lines connected to the pixel driver circuits 35. The host processor 3 then sends voltages to the respective data lines, depending on the luminance values ​​for the pixels associated with the pixel driver circuits 35, enabling the light elements 30 grouped in series to emit light simultaneously. In this way, the organic EL-based display 2 displays an image based on the video signals.

[0023] As in Fig. As illustrated in Figure 2, the encapsulation layer 13 protects the luminescent layer 32 from external water and oxygen and is arranged to completely cover the display area A1. The encapsulation layer 13 comprises a stack of an inorganic layer 41 (e.g., glass or metal), an organic layer 42 (e.g., polymer), and an inorganic layer 43 (e.g., glass or metal), which are stacked successively in this order, starting from the substrate 20. The display area A1 has ridges 44 along its periphery, acting as an insulating film to prevent the encapsulation layer 13 from collapsing. The ridges 44 form a periphery of the encapsulation layer 13 and extend along the periphery of the display area A1.

[0024] Sensor layer 14 represents a layer that incorporates a touch sensor for detecting the positions of the electromagnetic resonance input stylus P and the finger E (see Fig. 1) on the panel surface. The sensor layer 14 comprises a stack of an insulating film 50, an insulating film 51, a bridge conductor 55, linear electrodes 52 and 53, and a protective film 56, which are layered successively in this order, starting from the substrate 20. The linear electrodes 52 and 53 are electrically conductive films arranged on the top side of the insulating film 51 and extending along a y-direction and an x-direction, respectively. The linear electrodes 52 and 53 will be described later below with reference to Fig. 3 to 6 are described in detail.

[0025] The bridge conductor 55 is a conductor arranged on the top side of the insulating film 50. The bridge conductor 55 is provided to allow the linear electrodes 52 and 53 to cross each other without physical obstruction. More precisely, as in Fig. As illustrated in Figure 2, the linear electrode 52, which extends in the y-direction, is interrupted at a position where the linear electrode 53 extends over the linear electrode 52. At the position where the linear electrode 52 is interrupted, it has two ends that are electrically connected to the bridge conductor 55 via vias extending through the insulating film 51. Therefore, although interrupted, the linear electrode 52 remains electrically conductive along its entire length, and the linear electrodes 52 and 53 are allowed to cross each other without any physical obstruction.

[0026] Fig. Figure 3 is a top view of sensor layer 14. Fig. Figure 4 illustrates the organic EL-based display 2 from a perspective. Fig. Figure 3 shows some structural details of circuit layer 11 and the SL lines in dashed lines. Fig. Figure 4 shows the positions of the organic EL-based layer 12 and the encapsulation layer 13 in dashed lines, and some structural details of the circuit layer 11 are shown. An arrangement for detecting the positions of the electromagnetic resonance input stylus P and the finger E on the panel surface is described below with reference to Fig. 3 and Fig. 4 described.

[0027] As in Fig. 3 and Fig. As illustrated in Figure 4, the sensor layer 14 has a group of linear electrodes, including linear electrodes 52 and 53. Each of the linear electrodes 52 and 53 comprises a solid conductor as an electrically conductive film in the shape of a rectangle. Fig. 3 and Fig. Figure 4 shows only five linear electrodes 52 and ten linear electrodes 53 for illustrative purposes. In practice, however, the sensor layer 14 has more linear electrodes 52 and 53. The circuit layer 11 has logic circuits 70 to 72 and control lines 90 to 93, which are arranged within the display area A1.

[0028] Each of the linear electrodes 52 comprises a conductor formed from two linear conductors extending in the y-direction, each with ends located away from the terminal area 16 and connected to the other. In the sensor layer 14, the linear electrodes 52 thus formed are grouped at equally spaced intervals in the x-direction. Each of the linear electrodes 52 has two ends located closer to the terminal area 16 and is electrically connected to the logic circuit 70 in the circuit layer 11 via routing paths 60 extending from the sensor layer 14 to the circuit layer 11. In other words, each of the linear electrodes 52 is shaped as a loop coil extending from the logic circuit 70.

[0029] Each of the linear electrodes 53 comprises a linear conductor extending in the x-direction. In the sensor layer 14, the linear electrodes 53 thus shaped are grouped at equally spaced intervals in the y-direction. Each of the linear electrodes 53 has one end electrically connected to the logic circuit 71 in the circuit layer 11 via a routing path 61 extending from the sensor layer 14 to the circuit layer 11, and an opposite end electrically connected to the logic circuit 72 in the circuit layer 11 via a routing path 62 extending from the sensor layer 14 to the circuit layer 11.

[0030] The logic circuits 70 to 72 represent circuits for switching between a first mode, in which the sensor controller 4 uses the linear electrodes 52 and 53 to detect induced currents, and a second mode, in which the sensor controller 4 uses the linear electrodes 52 and 53 to detect capacitances. The first mode is for detecting induced currents generated in the linear electrodes 52 by alternating magnetic fields transmitted by the electromagnetically resonant input pen P in response to alternating magnetic fields sent by the linear electrodes 53. The sensor controller 4, once in the first mode, detects the position of the electromagnetically resonant input pen P based on the detected induced currents.The second mode is a mode for detecting capacitances at the respective intersections of the linear electrodes 52 and the linear electrodes 53 by detecting voltage signals generated in the linear electrodes 52 by voltage signals applied to the linear electrodes 53. The sensor controller 4, which has entered the second mode, detects the position of finger F based on the detected capacitances.

[0031] More precisely, in each of the first and second modes, the logic circuit 70 extracts an induced current or voltage signal from each of the linear electrodes 52 and outputs a received signal Rx, representing the extracted induced current or voltage signal, to the sensor controller 4. In the first mode, each of the logic circuits 71 and 72 sends an alternating current to each of the linear electrodes 53 to generate a changing magnetic field, and in the second mode, each applies a voltage signal to each of the linear electrodes 53.

[0032] Fig. Figure 5 illustrates, in block form, the internal configurations of logic circuits 70 and 71. Fig. Figure 5 does not illustrate the internal configuration of the logic circuit 72, as it is identical to the internal configuration of the logic circuit 71.

[0033] As in Fig. As illustrated in Figure 5, the logic circuit 70 has one or more receiving circuits 100 for extracting a received signal Rx from each of the linear electrodes 52 in the first mode, one or more receiving circuits 101 for extracting a received signal Rx from each of the linear electrodes 52 in the second mode, and a selection circuit 102 for selectively connecting each of the linear electrodes 52 either to the receiving circuit 100 or the receiving circuit 101 or other linear electrodes 52. The logic circuit 70 is controlled by the sensor controller 4 to switch between the receiving circuits 100 and 101 to be used and also between the connection destinations for each of the linear electrodes 52 in time-division multiplexing in order to extract a received signal Rx from each of the linear electrodes 52.

[0034] The logic circuit 71 has one or more control circuits 110 for generating alternating currents i Aand i B , which will be described later, using control signals, which will be described later, supplied by the sensor controller 4 to the control lines 90 and 91, and for supplying the generated alternating currents i A and i Bto the linear electrodes 53, one or more control circuits 111 for generating transmission signals Tx <0> to Tx <6> as voltage signals, which will be described later, using control signals, which will be described later, which are supplied by the sensor controller 4 to the control lines 90 and 91, and to apply the generated transmission signals Tx <0> to Tx <6> to the linear electrodes 53, and a selection circuit 112 for selectively connecting each of the linear electrodes 53 to one of the control circuits 110 and 111. The logic circuit 71 is controlled by the sensor controller 4 to switch between the control circuits 110 and 111 to be used and also between the connection destinations for each of the linear electrodes 53 in order to supply a current or apply a voltage to each of the linear electrodes 53.

[0035] Fig. 6A and Fig. Figure 6B illustrates in block form the way in which the sensor controller 4 controls the logic circuits 70 to 72 in the computer 1 according to the first embodiment. Fig. Figure 6A illustrates how the sensor controller 4 controls the logic circuits 70 to 72 to detect a position of the electromagnetic resonance input pen P, and Fig. Figure 6B illustrates how the sensor controller 4 controls the logic circuits 70 to 72 to detect the position of finger F. The operation of the logic circuits 70 to 72 is described below with reference to Fig. 6A and Fig. 6B described in detail.

[0036] As in Fig. As illustrated in Figure 6A, the sensor controller 4, which has entered the first mode, controls the logic circuits 71 and 72 to select one of the linear electrodes 53 at each, except for two linear electrodes 53 at each of opposite ends in the y-direction, and each time the linear electrode 53 is selected, an alternating current i A or an alternating current i BThe sensor controller 4 intermittently supplies alternating currents several times to two linear electrodes 53 adjacent to both sides of the selected linear electrode 53. The sensor controller 4 also controls the logic circuits 70 to select one of the linear electrodes 52 at a time, excluding one linear electrode 52 at each of opposite ends in the x-direction, and each time the linear electrode 52 is selected, to extract received signals Rx from the selected linear electrode 52 and the linear electrodes 52 adjacent to both sides of the selected linear electrode 52. The sensor controller 4 controls the logic circuits 70 and 72 while adjusting timings to extract the received signals Rx immediately after the supply of alternating currents i is stopped. A and i B to extract.

[0037] The alternating current i Arepresents a current that oscillates with a constant frequency and phase, whereas alternating current i B represents a phase-inverted current, which is in opposite phase to the alternating current i A is located. As a rule, each of the alternating currents contains i A and i B a sine wave signal, as in Fig. Figure 6A illustrates this, although it can also contain a square wave signal. The sensor controller 4 controls the logic circuit 71, which supplies the alternating current i to the two linear electrodes 53 adjacent to one side of the selected linear electrode 53 in the y-direction. A to supply and to the two linear electrodes 53, which are adjacent to the other side of the selected linear electrode 53 in the y-direction, the alternating current i B to supply. Synchronously with its operation to control the logic circuit 72, the sensor controller 4 controls the logic circuit 72, an alternating current iB to supply two linear electrodes 53 which are adjacent to one side of the selected linear electrode 53 in the y-direction, and an alternating current i A to supply two linear electrodes 53, which are adjacent to the other side of the selected linear electrode 53 in the y-direction. As a result, the supplied alternating currents generate A and i B a changing magnetic field above the selected linear electrode 53. When the coil of a resonant circuit arranged in the electromagnetic resonance input pen P enters the changing magnetic field, the electromagnetic resonance input pen P generates and transmits a changing magnetic field as a reflected signal.

[0038] Fig. Figure 6A illustrates a differential amplifier 70a as a concrete example of each of the in Fig. 5 illustrated receiving circuits 100. The logic circuit 70 connects the three linear electrodes 52, including the selected linear electrode 52, using the circuit shown in Fig. The selection circuit 102, illustrated in Figure 5, is connected in series and connects the opposite ends of the series-connected linear electrodes 52 to the differential amplifier 70a. The logic circuit 70 carries a signal that is output by the differential amplifier 70a immediately after the logic circuits 71 and 72 have ceased to conduct the alternating currents i A and i B to supply the received signal Rx to the sensor controller 4.

[0039] The sensor controller 4 detects as many signal intensities of received signals Rx supplied by the logic circuit 70 as corresponds to the number of combinations of linear electrodes 52 and 53 selected by the logic circuits 70 to 72, and derives the position, that is, the two-dimensional position, of the electromagnetic resonance input stylus P based on the distribution—on the panel surface—of the detected signal intensities of the organic EL-based display 2. More precisely, the sensor controller 4 can derive a position corresponding to the peak of the distribution as the position of the electromagnetic resonance input stylus P.In a case where the sensor controller 4 has a function to modulate the frequency of the alternating magnetic field transmitted by the electromagnetic resonance input pen P with data, for example an input pen pressure value representing the pressure exerted on the tip of the electromagnetic resonance input pen P, a value representing whether a switch on the electromagnetic resonance input pen P is on or off, or an input pen identification (ID) pre-assigned to the electromagnetic resonance input pen P, the sensor controller 4 performs a process of acquiring the data transmitted by the electromagnetic resonance input pen P by demodulating the receive signals Rx supplied by the logic circuit 70.Each time the sensor controller 4 derives a position and acquires data, the sensor controller 4 transmits the derived position and the acquired data to the host processor 3.

[0040] As in Fig. Figure 6B illustrates that the sensor controller 4, which has entered the second mode, controls the linking circuits 71 and 72 to select seven of the linear electrodes 53 each and transmit signals Tx <0> to Tx <6> to transmit the selected seven linear electrodes 53. Each time the sensor controller 4 controls the logic circuits 71 and 72 to select seven of the linear electrodes 53, the sensor controller 4 controls the logic circuit 70 to select one of the selected linear electrodes 52 and to extract a received signal Rx from the selected linear electrode 52.

[0041] The transmission signals Tx <0> to Tx <6> These represent alternating current signals whose phases are specified by the columns of a 7 × 7 matrix A, expressed by equation (1) below. In matrix A, “+1” corresponds to phase 0°, and “-1” corresponds to phase 180°. Typically, each of the transmitted signals Tx comprises <0> to Tx <6> a square wave signal, as in Fig. Figure 6B illustrates that it can also include a sine wave signal. The logic circuits 71 and 72 generate the transmit signals Tx sequentially. <0> to Tx <6> corresponding to the columns of matrix A and carry the generated transmission signals Tx <0> to Tx <6> to the respective selected linear electrodes 53. [Equation 1] A=(−1+1+1−1+1−1−1−1−1+1+1−1+1−1−1−1−1+1+1−1+1+1−1−1−1+1+1−1−1+1−1−1−1+1+1+1−1+1−1−1−1+1+1+1−1+1−1−1−1)

[0042] Matrix A represents an M-sequence code. Since matrix A illustrates an M-sequence code, the elements of each column can be shifted by one element to generate the next column. Therefore, the structure of the circuits for generating the transmitted signals Tx can be... <0> to Tx <6> This will be simplified. Specific structural details of such circuits will be discussed later with reference to Fig. Described in sections 9 to 21. Matrix A does not necessarily need to be configured as an M-sequence code, but can be configured as any desired code, such as a Walsh code, an Orthogonal Variable Spreading Factor (OVSF) code, or a Barker code. Matrix A can also be configured as a different square matrix instead of a 7 × 7 matrix. In the latter case, Matrix A, the sensor controller 4 controls the logic circuits 71 and 72 to select as many linear electrodes 53 as Matrix A has rows.

[0043] Fig. Figure 6B illustrates an operational amplifier 70b as a concrete example of each of the in Fig. 5 illustrated receiving circuits 101. The operational amplifier 70b has an inverted input terminal connected to ground. A capacitor for removing high-frequency noise is connected in parallel with the operational amplifier 70b. The logic circuit 70 connects the two ends of the selected linear electrode 52 to a non-inverted input terminal of the operational amplifier 70b using the circuit shown in Fig. Figure 5 illustrates selection circuit 102, whereby a series of signals output by the operational amplifier 70b are transmitted as a receive signal Rx to the sensor controller 4, while the logic circuits 71 and 72 successively transmit the send signals Tx <0> to Tx <6> supply those that correspond to the columns of matrix A.

[0044] It is assumed that the elements of the x-th column of matrix A are represented by A x1 , A x2 ... are specified, and the capacitances formed between the linear electrode 52 selected by the logic circuit 70 and the seven linear electrodes 53 selected by the logic circuits 71 and 72 are specified by C1 and C2, ... Then a received signal Rx_TP transmitted by the operational amplifier 70b to the sensor controller 4 has a value specified by the following equation (2). [Equation 2] (Ax1 Ax2 Ax3 ⋯ Ax7)(C1C2C3⋮C7)

[0045] Consequently, the received signal Rx, which is the result of sending the transmitted signals Tx, is <0> to Tx <6> , which correspond to the columns of matrix A, are obtained from the linking circuits 71 and 72 to the linear electrodes 53, represented by a vector b, which is given by the following equation (3). [Equation 3] b=AT(C1C2C3⋮C7) where A T a transpose of matrix A is represented.

[0046] The sensor controller 4 performs an arithmetic operation, expressed by the left-hand side of equation (4) below, on the vector b, thereby separately sensing the respective capacitances of the linear electrodes 53. In equation (4), the matrix (A T ) -1 an inverted matrix of matrix A T This represents the multiplication of matrix A. T with the matrix (A T ) -1By generating an identity matrix I as specified in equation (4), the sensor controller 4 can separately detect the capacitances at the intersections between the linear electrode 52 selected by the logic circuit 70 and the seven linear electrodes 52 selected by the logic circuits 71 and 72 by performing the arithmetic operation as specified by the right side of equation (4). [Equation 4] (AT)−1b=(AT)−1AT(C1C2C3⋮C7)=I(C1C2C3⋮C7)=(C1C2C3⋮C7)

[0047] The sensor controller 4 performs the arithmetic operation expressed by equation (4) each time the logic circuits 70 to 72 switch from one electrode selection to another, thereby deriving capacitances at the intersections between the linear electrodes 52 and the linear electrodes 53. The sensor controller 4 then derives the position, that is, the two-dimensional position, of finger F based on the distribution—on the panel area—of the derived capacitances of the organic EL-based display 2. More precisely, the sensor controller 4 can derive a position corresponding to the peak of the distribution as the position of finger F. Each time the sensor controller 4 derives a position, it transmits the derived position to the host processor 3.

[0048] We return to Fig. 3 and Fig. 4. The control lines 90 to 93 are lines for supplying control signals that generate the alternating currents i A and i B and the transmission signal Tx <0> to Tx <6> from the sensor controller 4 to the logic circuits 71 and 72 are required. As will be described later using a concrete example, a control signal Tx_clk, which is fed as a first control signal to the control lines 90 and 92, and a control signal xTx_clk, which is fed as a second control signal to the control lines 91 and 93, are alternating signals that have opposite phases. The control signals Tx_clk and xTx_clk can be alternating current signals such as sine wave signals, or signals generated by switching a switch on and off, such as square wave signals. The logic circuit 71 is configured to process the alternating currents i A and i Band the transmission signals Tx <0> to Tx <6> based on the control signals Tx_clk and xTx_clk supplied by the sensor controller 4 via the control lines 90 and 91. The logic circuit 72 is configured to generate the alternating currents i A and i B and the transmission signals Tx <0> to Tx <6> to generate on the basis of the control signals Tx_clk and xTx_clk supplied by the sensor controller 4 via the control lines 92 and 93.

[0049] Specific structural details of routing paths 60 and 61 and lines SL are described below with reference to cross-sectional views, including Fig. 2, described. Routing paths 62 are structurally identical to routing paths 61.

[0050] Fig. Figure 2 illustrates one of the routing paths 60 in an enlarged cross-section. As in Fig. As illustrated in Figure 2, the routing path 60 comprises a conductor 60a located on the top surface of the gate insulating film 22, a pad electrode 60b located on the top surface of the interlayer insulating film 23, a via conductor 60c connecting the conductor 60a and the pad electrode 60b, and an extension 60d of the electrically conductive film of the linear electrode 52. The pad electrode 60b and the via conductor 60c are positioned in frame area A2. The conductor 60a extends below and past the dams 44 and connects the logic circuit 70 in display area A1 and the via conductor 60c in frame area A2. The extension 60d extends over the dam 44 and is connected to the top of the pad electrode 60b via its section which is located in a via hole VH1 defined in the frame area A2.

[0051] As can be seen from the structural details of the routing path 60 described above, the routing path 60 extends from a top surface of the encapsulation layer 13 to a bottom surface of the same, over and around the dams 44, in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44. The routing path 60 thus constructed makes it possible to arrange the logic circuit 70 according to the first embodiment within the display area A1 of the organic EL-based display 2. Since the pixel driver circuits 35 occupy an area smaller than the organic EL-based layer 12, there is sufficient space in the circuit layer 11 within the display area A1 to accommodate the logic circuit 70. According to the first embodiment, the logic circuit 70 is arranged in such sufficient space within the circuit layer 11 in the display area A1.

[0052] Fig. Figure 7 illustrates the organic EL-based display 2 along line BB of Fig. 3 in an enlarged cross-section. Fig. Figure 7 illustrates the structural details of routing path 61. As in Fig. As illustrated in Figure 7, routing path 61, like routing path 60, comprises a conductor 61a located on the top surface of the gate insulating film 22, a pad electrode 61b located on the top surface of the interlayer insulating film 23, a via conductor 61c connecting the conductor 61a and the pad electrode 61b, and an extension 61d of the electrically conductive film of the linear electrode 53. The pad electrode 61b and the via conductor 61c are positioned in frame area A2. The conductor 61a extends below and past the dams 44 and connects the logic circuit 71 in display area A1 and the via conductor 61c in frame area A2.The extension 61d extends over the dam 44 and is connected to the top of the pad electrode 61b via its section which is located in a via hole VH2 defined in the frame area A2.

[0053] As can be seen from the structural details of the routing path 61 described above, the routing path 61 extends from a top surface of the encapsulation layer 13 to a bottom surface of the same, over and around the dams 44, in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44. The routing path 60 thus constructed makes it possible to arrange the logic circuit 70 according to the first embodiment within the display area A1 of the organic EL-based display 2.

[0054] Fig. Figure 7 also illustrates the control lines 90 and 91. As in Fig. As illustrated in Figure 7, the control lines 90 and 91 extend on the top side of the intermediate insulating film 23, as do the data lines.

[0055] Fig. Figure 8 schematically illustrates the organic EL-based display 2 in an enlarged cross-section along line CC of Fig. 3. Fig. Figure 8 illustrates the structure of the lines SL that connect the logic circuit 70 to the terminal area 16. As shown in Fig. As illustrated in Figure 8, the conductors SL comprise a conductor SLa located on the top surface of the gate insulating film 22, a pad electrode SLb located on the top surface of the interlayer insulating film 23, and a via conductor SLc connecting the conductor SLa and the pad electrode SLb. The conductor SLa extends below and past the dams 44 and connects the logic circuit 70 in the display area A1 and the via conductor SLc in the frame area A2. The pad electrode SLb has a top surface exposed at the bottom of a via hole VH3 defined through the protective film 56 and other layers, and is connected to a pad electrode 16a located on an inner surface of the via hole VH3.The pad electrode 16a represents an electrode that functions as a connection in the connection area 16 and is connected to the in via a line not shown. Fig. 1 illustrated sensor controller 4 connected.

[0056] The configuration of the logic circuit 71 arranged in the display area A1, for example the control circuits 111 for generating and supplying the transmit signals Tx <0> to Tx <6> , will be described in detail below. Although the configuration of the logic circuit 71 is described below using an example, the logic circuits 72 have an identical configuration. Although the configuration of the control circuits 111 for generating and supplying the transmission signals Tx <0> to Tx <6> As described below using an example, the control circuits 110 are used to generate and supply the alternating currents i A and i B an identical configuration.

[0057] Fig. Figures 9 to 12 illustrate the configuration and operation of the control circuits 111 in the logic circuit 71. As in Fig. As illustrated in Figure 9, the logic circuit 71 has seven control circuits 111 for generating and supplying the respective transmission signals Tx. <0> to Tx <6> The control circuits 111 each comprise shift registers SR. <k>(k is an integer in the range of 0 to 6) and respective selection circuits SE <k>.

[0058] Data signals code and xcode, each representing a phase setting value ("+1" or "-1"), are successively sent bit by bit from the sensor controller 4 to the shift register SR. <0> transmitted. The data signal Code (first data signal) represents a low-active binary signal that is activated as a low when the set value is "+1". The data signal xCode (second data signal) represents a low-active binary signal that activates itself as a low when the set value is "-1". The data signal Code, indicating the set value "+1", and the data signal xCode, indicating the set value "-1", are provided separately to allow the drive circuits 111 to be constructed using only MOSFETs of the same channel type.For example, if the drive circuits 111 consist only of P-channel MOSFETs, they can only output signals in response to low inputs. Therefore, they can only output "-1" when a binary signal with a high level (representing "+1") and a low level (representing "-1") is input. According to the first embodiment, the drive circuits 111, consisting only of P-channel MOSFETs, can output both "+1" and "-1" because both "+1" and "-1" can be input as a low.

[0059] Each of the shift registers SR <k>At least two clock signals, CK2 and CK3, are transmitted by the sensor controller 4. Each of the clock signals CK2 and CK3 represents a clock signal that oscillates between a ground potential VGL (more precisely -7 V) and a current potential VGH (VGH > VGL, more precisely 7 V). The clock signal CK2 represents the time at which each shift register SR <k>The data signals code and xcode reads, and the time at which each shift register SR <k>The data signals code and xcode are sent to the next shift register SR. <k>outputs. The clock signal CK3 represents the time at which each shift register sends signals to the corresponding selection circuit SE. <k>spends.

[0060] Each of the shift registers SR <k>represents a circuit that reads the values ​​supplied as the data signals code and xcode at an activation point of the clock signal CK2 and sets them within itself, and then passes the set values ​​to the next shift register SR at the next activation point of the clock signal CK2. <k>outputs, and the stored values ​​are sent to the corresponding selection circuit SE at an activation time of the clock signal CK3. <k>outputs. The shift register SR <k>The set values ​​are output as two data signals (iCode). <k>and xiCode <k>to the selection circuit SE <k>out. The data signal iCode <k>represents a low-active binary signal that goes low when the phase setting value is "+1". The data signal xiCode <k>represents a low-active binary signal that goes low when the phase setting value is "-1".

[0061] Each of the selection circuits SE <k>The control signals Tx_clk and xTx_clk described above are supplied by the sensor controller 4 via the respective control lines 90 and 91. Each of the selection circuits SE <k>represents a circuit for outputting the control signal Tx_clk in response to the activation of the data signal iCode <k>and to output the control signal xTx_clk in response to the activation of the data signal xiCode <k>The selection circuits SE <k>The control signals Tx_clk and xTx_clk are transmitted as Tx signals. <k>out of.

[0062] The operation of the control circuits 111 is described below with reference to Fig. 9 to 12 are described in concrete and detailed terms. First, as in Fig. Figure 9 illustrates how the sensor controller 4 transmits data to the shift register SR. <0> Seven bits of the data signals code and xcode, corresponding to the first column (from the left) of matrix A, are successively shifted from the bottommost element of matrix A, one bit per clock pulse of the clock signal CK2. At this stage, sensor controller 4 transmits the data to the shift register SR. <0> No clock signal CK3. Therefore, the transmitted bits of the data signals code and xcode are not sent to the selection circuit SE. <k>not output, but rather output synchronously with the clock signal CK2 to the next shift register and set within it. As a result, as in Fig. Figure 9 illustrates the point at which the last bits of the data signals, code and xcode, are entered into the shift register SR. <0> The 7 bits of the data signals code and xcode, corresponding to the first column of matrix A, are set in the respective shift registers SR. <0> up to SR <6> set.

[0063] Then the sensor controller 4 is activated, as shown in Fig. Figure 10 illustrates the clock signal CK3. Now the respective values ​​in the shift registers SR are used. <k>set bits as the data signals iCode <k>and xiCode <k>to the selection circuits SE <k>issued. The selection circuits SE <k>, which the data signals iCode <k>and xiCode <k>If the data signal iCode has been received, the control signals Tx_clk are output. <k>is activated, and output the control signals xTx_clk if the data signal xiCode <k>is activated. As a result, the seven linear electrodes 53 simultaneously transmit the Tx signals. <0> to Tx <6> supplied, whose phases correspond to the first column of matrix A.

[0064] Then, as in Fig. As illustrated in Figure 11, the sensor controller 4 transmits data to the shift register SR. <0> , together with a single clock pulse of the clock signal CK2, the next bit, that is, the topmost value of the second column - from the left - of matrix A, the data signals code and xcode. The shift registers SR <k>The set values ​​are now shifted so that the values ​​corresponding to the second column of matrix A are stored in the shift registers SR. <0> up to SR <6> be hired.

[0065] Then the sensor controller 4 is activated, as shown in Fig. Figure 12 illustrates the clock signal CK3 again. Now the respective values ​​in the shift registers SR are displayed. <k>set bits as the data signals iCode <k>and xiCode <k>to the selection circuits SE <k>output. Consequently, the selection circuits transmit SE. <k>Simultaneously, the transmission signals Tx are sent to the seven linear electrodes 53. <0> to Tx <6> , whose phases correspond to the second column of matrix A.

[0066] The same process is repeated with respect to the third to seventh row of matrix A, so that the seven linear electrodes 53 receive the transmitted signals Tx <0> to Tx <6> , which have the corresponding phases, are supplied. In this way, the logic circuit 71 transmits the transmission signals Tx. <0> to Tx <6> , corresponding to the columns of matrix A, successively to the seven linear electrodes 53.

[0067] Fig. 13 illustrates the specific configuration details of the in Fig. 9 to 12 illustrated shift registers SR <k>and selection circuits SE <k>. Fig. Figure 14 illustrates the internal configuration of the shift register S <0> (which will be described below), which is in the shift registers SR <k>is included. Although Fig. 13 just some of the shift registers SR <k>and some of the selection circuits SE <k>The other shift registers SR illustrate this. <k>and the other selection circuits SE <k>an identical configuration. Likewise, the other shift registers S <k>and shift register xS <k>(which will be described below) an identical configuration, although Fig. 14 only that in the shift registers SR <0> Included sliding registers S <0> illustrated.

[0068] As in Fig. As illustrated in 13, each of the shift registers SR contains <k>a sliding register S <k>and a shift register xS <k>. Each of the shift register S <k>and the shift register xS <k>It has an input terminal st, an output terminal g_out, which is connected to one of the selection circuits SE. <k>is connected to an output port c_out, which is connected to a shift register S<k+1> the next stage is connected to clock terminals ck1 and ck2, and an output enable terminal o_en.

[0069] At the input terminal st of the shift register S <0> The data signal code is applied by sensor controller 4. It is connected to the input terminal st of the shift register xS. <0> The data signal xCode is applied by the sensor controller 4. It is connected to the input terminal st of the shift register S.<k+1> A signal SR_o will be generated. <k>created, which is connected to the output terminal c_out of the shift register S <k>The output of the previous stage is also sent. Similarly, the input pin st of the shift register xS is also sent.<k+1> a signal xSR_o <k>created, which is connected to the output terminal c_out of the shift register xS <k>is issued at the previous stage.

[0070] Clock signals CK1 and CK2 from sensor controller 4 are applied to clock terminals ck1 and ck2, respectively. A clock signal CK3 from sensor controller 4 is applied to the output enable terminal o_en. Clock signals CK2 and CK3 are the same as the clock signals CK2 and CK3 described above. Fig. described in sections 9 to 12. Like the clock signals CK2 and CK3, the clock signal CK1 also represents a clock signal that oscillates between the ground potential VGL and the current potential VGH.

[0071] The output terminal g_out of the shift register S <k>gives a data signal iCode <k>out, and the output terminal g_out of the shift register xS <k>outputs a data signal xiCode <k>out of.

[0072] As in Fig. 14 illustrates the shift register S <0> A register circuit 80, a buffer circuit 81, and a shift circuit 82. The register circuit 80 comprises transistors T10 to T17 and a capacitor C10. The buffer circuit 81 comprises transistors T20 to T22 and capacitors C20 and C21. “A” to “D” in Fig. 14 designate nodes in the shift register S <0> .

[0073] All transistors in the logic circuits 70 to 72, comprising transistors T10 to T17 and T20 to T22, are configured as P-channel MOSFETs to ensure compatibility between the logic circuits 70 to 72 and the pixel driver circuits 35, which are also configured as P-channel MOSFETs. Therefore, the logic circuits 70 to 72 can be manufactured using the same process as the pixel driver circuits 35. However, since the logic circuits 70 to 72 cannot contain CMOS transistors in their output stages, they are configured to operate in bootstrapping mode. This allows the gate potential of the low-side P-channel MOSFET in the output stage to be lower than the low level. Details of the bootstrapping mode will be described later.

[0074] Transistor T10 is connected between input terminal st and node B and has a gate connected to clock terminal ck2. Transistor T11 is connected between clock terminal ck2 and node A and has a gate connected to node B. Transistor T12 is connected between a ground line, supplied with ground potential VGL, and node A and has a gate connected to clock terminal ck2. Transistors T13 and T14 are connected in series along a current line, supplied with current potential VGH, and are arranged in this order starting from the current line. Transistor T13 has a gate connected to node A, and transistor T14 has a gate connected to clock terminal ck1. Transistor T15 is connected between node B and node C and has a gate connected to the ground line, supplied with ground potential VGL.Transistor T16 is connected between the output terminal g_out and the output enable terminal o_en and has a gate connected to node C. Transistor T17 is connected between the output terminal g_out and the current line to which the current potential VGH is supplied and has a gate connected to node A. Capacitor C10 is connected between node C and the output terminal g_out.

[0075] Transistor T20 is connected between node B and the gate of transistor T21 and has one gate connected to the ground line, which carries the ground potential VGL. Transistor T21 is connected between node D, which provides an input to shift circuit 82, and the clock terminal ck1. Transistor T22 is connected to node D and to the current line, which carries the current potential VGH, and has one gate connected to node A. Capacitor C20 is connected to node D and the gate of transistor T21, and capacitor C21 is connected between node A and the source of transistor T22.

[0076] Fig. Figure 15 illustrates signal waveforms that simulate the operation of the register circuit 80 and the buffer circuit 81. The operation of the register circuit 80 is described below with reference to Fig. 15 as well Fig. 14 described in detail. Fig. Figure 15 has a vertical axis that represents stress values. This also applies to Fig. 16 to 21. In Fig. Figure 15 illustrates that the clock signals CK1 and CK3 are identical. The clock signals CK1 and CK3 are identical after the shift registers SR have been used. <k>have begun sending signals to the selection circuits SE <k>to spend (see Fig. 10). In other words, illustrates Fig. 15 the operation of the register circuit 80, after the shift registers SR <k>have begun sending signals to the selection circuits SE <k>to output. Before the shift registers SR <k>with the output of signals to the selection circuits SE <k>begin, that is, when the data signal codes in the shift registers SR <0> up to SR <6> is being set up (see Fig. 9), the sensor controller 4 oscillates the clock signal CK1, but the clock signal CK3 does not oscillate (see Fig. 16 and other characters, who will be described later).

[0077] When the clock signal CK2 goes low at time t1, transistor T12 is switched on, causing the potential at node A to drop to a low level. Therefore, transistor T17 is switched on, causing the potential at the output terminal g_out, i.e., the potential of the output signal iCode, to rise. <0> The clock signal CK2 goes high. Although transistor T10 is also switched on, node B is high because the data signal code is high at this time, which keeps transistor T11 off. After the clock signal CK2 returns to high, transistor T14 is switched on when the clock signal CK1 goes low at time t2. Since the potential at node A is low at this time, and therefore transistor T13 is switched on, the current potential VGH is supplied to node B. Subsequently, when the clock signal CK1 goes high at time t3, transistor T14 is switched off, thus stopping the supply of the current potential VGH to node B.

[0078] When the clock signal CK2 goes low again at time t4, the potential at node B drops because the data signal Code goes low at this time, thus turning on transistor T11. Because transistor T15 remains on, except in the bootstrapping mode described later, the potential at node B goes low, and so does the potential at node C. At this point, transistor T16 is turned on, provided the clock signal CK3 supplied to the output enable terminal o_en is high. Therefore, the current potential VGH is supplied to the output terminal g_out by both transistors T16 and T17. Capacitor C10 is charged by the potential difference between the output terminal g_out and node C.

[0079] When the clock signal CK2 goes high at time t5, transistor T10 is switched off. Since transistor T14 remains off because the clock signal CK1 remains high, the potentials at nodes B and C remain continuously low. As a result, transistor T11 remains switched on. When the clock signal CK2 goes high, the potential at node A, which is connected to clock terminal ck2 via transistor T11, goes high, thus switching off transistors T13 and T17.

[0080] When the clock signal CK3 goes low at time t6, the bootstrapping mode is initiated. More precisely, a current path is created from node C via capacitor C10 and the channel region of transistor T16 to the output enable terminal o_en, thus lowering the potential at node C from its low level. The potential drop at node C at this time has a value that is essentially equal to the difference VGH-VHL. Consequently, transistor T16 remains switched on even when the clock signal CK3 goes low at time t6, thus lowering the potential at the output terminal g_out, i.e., the potential of the output signal iCode. <0> , becomes low. While the potential at node C is lower than the low level, transistor T15 is switched off, thus isolating node B and node C from each other.

[0081] If the clock signal CK3 goes high at time t7, transistor T16 is switched off, thus ending the bootstrap mode and the potential at node C returns to low. The potential of the output signal iCode <0> The potential at node A returns to high. When the clock signal CK2 goes low at time t8, transistor T12 is switched on, causing the potential at node A to return to low. As a result, transistor T17 is switched on, supplying the output terminal g_out with the current potential VGH. At time t8, transistor T10 is also switched on, and since the data signal Code is high at this time, the potential at node B goes high. Since transistor T15 is switched on again, the potential at node C also goes high.

[0082] As described above, with the register circuit 80 and buffer circuit 81 configured in this way, it is possible for register circuit 80 to generate the output signal code due to bootstrapping mode without using a CMOS in the output stage of the circuit, and it is possible for buffer circuit 81 to generate the output signal in the same way; that is, buffer circuit 81 is able to output an input signal for shift circuit 82 at node D without using a CMOS in the output stage. However, since the clock terminal ck1 is connected to the source of transistor T21 instead of the output enable terminal o_en, the output signal from buffer circuit 81 goes low at the same time as the clock signal CK1 goes low.

[0083] Fig. Figure 14 also illustrates the internal configuration of the slide switch 82. As in Fig. As illustrated in Figure 14, the shift circuit 82 has transistors T30 to T37 and capacitors C30 and C31. The configuration of the shift circuit 82 is essentially identical to the configuration of the register circuit 80 in that transistors T10 to T17 and capacitor C20 are replaced by transistors T30 to T37 and capacitor C30. However, the shift circuit 82 differs from the register circuit 80 in several respects, which are described below.

[0084] The shift circuit 82 has one input terminal, namely the source of transistor T30, to which the output signal from the buffer circuit 81, i.e., the signal at node D, is fed. A comparison between the shift circuit 82 and the register circuit 80 clarifies that the clock signals ck1 and ck2 are reversed in the register circuit 80 and in the shift circuit 82. Furthermore, the clock terminal ck2 is connected to the source of transistor T36 instead of the output enable terminal o_en. Capacitor C31 is connected between the gate and the source of transistor T37. The junction between transistors T36 and T37 is connected to the output terminal c_out instead of the output terminal g_out.

[0085] As a result of the above configuration of the shift circuit 82, the shift circuit 82 detects the output signal from the buffer circuit 81 on a rising edge of the clock signal CK1 and outputs the output signal SR_o <0> from the output port c_out to the next stage.

[0086] The slide switch 82 also operates in bootstrapping mode in order to be able to output the signal SR_o <0> to generate without using a CMOS in its output stage.

[0087] Fig. Figure 16 illustrates signal waveforms that simulate the operation of the register circuit 80, the buffer circuit 81, and the shift circuit 82. Fig. 16 represents time 110, the time of completion of the setting of the data signal code in the shift registers SR. <0> up to SR <6> (see Fig. 9) Before time 110, the sensor controller 4 does not oscillate the clock signal CK3, thus preventing the output of the iCode signal. <0> This is prevented while the data signal code is being set.

[0088] As in Fig. As illustrated in Figure 16, register circuit 80 detects the data signal Code at time t11, when the clock signal CK2 goes low, and reflects the data signal Code in the potential at node B, that is, the potential of the output signal from register circuit 80 to buffer circuit 81. Then, at time t12, when the clock signal CK3 goes low, register circuit 80 changes the output signal iCode. <0> to a low level. Simultaneously, buffer circuit 81 also changes the potential at node D to a low level. Buffer circuit 81 changes the potential at node D to the low level because the clock signal CK1, and not the clock signal CK3, goes low.

[0089] At time t12, when the clock signal CK1 goes low, the shift circuit 82 detects the output signal from the buffer circuit 81, i.e., the potential at node D. At time t13, when the clock signal CK2 goes low, the shift circuit 82 changes the output signal SR_o. <0> to a low level. Thus, it is possible that the register circuit 80 of the shift register S <1> The next stage converts the data signal code into the output signal iCode <1> reflects a clock pulse later than the register circuit 80 of the shift register S <0> .

[0090] Fig. Figures 17 to 19 illustrate signal waveforms that simulate different signals applied to the respective stages of the shift register SR. <k>be created in the same simulation as in Fig. 16. More precisely, illustrates Fig. 17 signal waveforms, the output signals iCode <0> up to iCode <3> and output signals SR_o <0> until SR_o <2> simulate. Fig. Figure 18 illustrates signal waveforms, the output signals xiCode <0> up to xiCode <3> and output signals xSR_o <0> to xSR_o <2> simulate. Fig. Figure 19 illustrates signal waveforms that produce iCode output signals <0> up to iCode <3> on the “+1” side and output signals xiCode <0> up to xiCode <3> Simulate on the "-1" side. Due to space limitations, illustrate Fig. 17 to 19 is an example where the logic circuit 71 is a shift register SR. <k>exhibits four stages (k = 0 to 3). Similar waveforms also apply to shift registers SR. <k>in seven stages.

[0091] In Fig. Numbers 17 to 19, circled in the foreground, refer to the sequence and timing in which phase setting values ​​are transmitted from the sensor controller 4 to the logic circuit 71. In the illustrated example, eight setting values ​​are transmitted in the sequence "+1", "+1", "-1", "-1", "+1", "+1", "-1", "-1".

[0092] As from Fig. As can be seen in Figures 17 to 19, the phase setting values ​​illustrated by the data signal code are transmitted synchronously with the clock signal CK2 to subsequent stages. At time t10, which is also shown in Fig. As illustrated in 16, the first setting value is in the shift register SR. <3> The second setting value is entered in the shift register SR. <2> The third setting value is set in the shift register SR. <1> set, and the fourth setting value is stored in the shift register SR. <0> set. At time t14, when the clock signal CK3 goes low, the shift registers SR <0> up to SR <3> simultaneously displaying the respective first to fourth setting values.

[0093] The phase setting values ​​represented by the data signal code are then sent synchronously with the clock signal CK2 to the shift registers SR. <k>in the subsequent stages. Simultaneously, the shift registers SR <k>The setting values ​​at the respective stages are synchronized with the clock signal CK3 to the selection circuits SE. <k>The logic circuit 71 according to the first embodiment is thus able to simultaneously extract the setting values ​​transmitted by the data signals code and xcode from the respective shift registers SR. <k>to spend.

[0094] We return to Fig. 13 back. The SE selection circuit <0> This circuit switches between the connections between control lines 90 and 91 and the corresponding routing path 61 and includes transistors T1 to T5 and capacitors C1 and C2. Transistor T1 is connected between the output terminal g_out of the shift register S. <0> and the gate of transistor T2. The gate of transistor T1 is connected to the ground line, which is supplied with the ground potential VGL. Transistor T2 is connected between the control line 90 and the drain of transistor T5. Capacitor C1 is connected between the drain of transistor T5 and the gate of transistor T2. Transistor T3 is connected between the output terminal g_out of the shift register xS. <0> and connected to the gate of transistor T4. The gate of transistor T3 is connected to the grounding line, which is supplied with the ground potential VGL.Transistor T4 is connected between the control line 91 and the drain of transistor T5. Capacitor C2 is connected between the drain of transistor T5 and the gate of transistor T4. The source of transistor T5 is connected to the current line, which is supplied with the current potential VGH. A clock signal xCK3, which is an inverted signal of clock signal CK3, is applied to the gate of transistor T5. The drain of transistor T5 is connected to linear electrode 53 via routing path 61. The transmit signal Tx <0> , which is an output signal from the selection circuit SE <0> is extracted from the drain of transistor T5.

[0095] Fig. Figure 20 illustrates signal waveforms that simulate various signals applied to the SE selection circuit. <0> in the same simulation as in Fig. 16 to 19 are to be created. The selection circuit SE as described above. <0> The control signal Tx_clk is output when the clock signal xCK3 is high, i.e., when transistor T5 is switched off, and the output signal iCode is high. <0> of the shift register SR <0> is low, and outputs the control signal xTx_clk when the clock signal xCK3 is high and the output signal xiCode is high. <0> of the shift register SR <0> low is.

[0096] Fig. 21 illustrates signal waveforms that transmit signals Tx <0> to Tx <3> simulate the selection circuits SE <0> to SE <3> in the same simulation as in Fig. 16 to 20 will be issued. As a comparison between Fig. 19 and Fig. As can be seen in Figure 21, the logic circuit 71 according to the first embodiment outputs the transmission signals Tx. <k>from those that have an opposite phase when the output signal iCode <k>is activated and when the output signal xiCode <k>is activated. Therefore, it can be said that the logic circuit 71 controls the phases of the transmitted signals Tx. <k>The data signals Code and iCode are controlled by the logic circuit 71. Using these properties, the logic circuit 71 generates the transmit signals Tx. <0> to Tx <6> depending on the series of setting values ​​supplied by the sensor controller 4, and transmits the generated transmission signals Tx <0> to Tx <6> to the linear electrodes 53.

[0097] We return to Fig. 1. In addition to the process of displaying images based on video signals, the host processor 3 performs a process for moving a cursor displayed on the display area of ​​the organic EL-based display 2, and a process for generating line data that specifies the path followed by the electromagnetic resonance stylus P or finger F on the touch surface, using positions and data transmitted by the sensor controller 4. With respect to the line data, the host processor 3 also performs a process for rendering and displaying the generated line data, a process for generating and recording digital ink, including the generated line data, and a process for transmitting the generated digital ink to an external device in response to a user instruction.

[0098] The computer 1 according to the first embodiment offers the following advantages. Since the logic circuits 70 to 72 are arranged in the display layer 10 within the display area A1, attempts to reduce the frame area A2 are not hindered, and an increase in the size of the circuits of the sensor controller 4 is prevented, while at the same time the positions of both the finger F and the electromagnetic resonance input stylus P can be detected.

[0099] The computer 1 according to the first embodiment is further advantageous for the following reasons. Since the routing paths 60 to 62, which connect the logic circuits 70 to 72 and the linear electrodes 52 and 53, extend from the top of the encapsulation layer 13 to the bottom of the same over and around the dams 44 in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44, it is possible to place the logic circuits 70 to 72 in the display layer 10 within the display area A1.

[0100] Furthermore, the computer 1 according to the first embodiment is also advantageous for the following reasons. Since all the drive circuits 110 and 111 arranged in the display layer 10 for driving the linear electrodes 53 are formed from MOSFETs of the same channel type, an increase in the manufacturing costs of the organic EL-based display 2 is prevented, as the drive circuits 110 and 111 for driving the linear electrodes 53 are arranged in the display layer 10.

[0101] Furthermore, according to the first embodiment, computer 1 offers the following advantages. The phase setting values ​​transmitted to the drive circuits 110 and 111 in the logic circuits 71 and 72 are represented by the two low active data signals Code and xCode, and the logic circuits 71 and 72 are configured to operate in bootstrapping mode. Therefore, it is possible to design the drive circuits 110 and 111 for the linear electrodes 53 of MOSFETs of the same channel type.

[0102] According to the first embodiment, as above with reference to Fig. As described in section 6, the alternating currents i A and i B or the transmitted signals Tx from both logic circuits 71 and 72 are applied to the linear electrodes 53. The alternating currents i A and i B Alternatively, the transmitting signals Tx can also be applied to the linear electrodes 53 by only one of the logic circuits 71 and 72.

[0103] Fig. 22A and Fig. Figure 22B illustrates in block form the way in which a sensor controller 4 controls the logic circuits in a computer 1 according to a modification of the first embodiment. Fig. Figure 22A illustrates in block form the way in which the sensor controller 4, which has entered a first mode, controls the logic circuits, and Fig. Figure 22B illustrates in block form the way in which the sensor controller 4, which has entered a second mode, controls the linking circuits.

[0104] As in Fig. 22A and Fig. As illustrated in Figure 22B, a logic circuit 72 according to the present modification comprises several single-pole switches connected between the ends of the linear electrodes 53 located remote from the logic circuit 71 in the x-direction and a reference line to which a reference potential such as earth potential is supplied.

[0105] The sensor controller 4 according to the modification uses the illustrated control signals to control the switches in the logic circuit 72 such that those linear electrodes 53, to which alternating current i A and i B to be supplied, to be connected to the reference line and the other linear electrodes 53 to be disconnected from the reference line, and also to control the switches in the logic circuit 72 so that all linear electrodes 53 are disconnected from the reference line in the second mode.

[0106] According to the modification, as in the first embodiment, the positions of both the finger F and the electromagnetic resonance input pen P can be adequately detected. By arranging the switches of the logic circuit 72 in the display layer 10 within the display area A1, attempts to reduce the frame area A2 are not hindered, and an increase in the size of the sensor controller 4 circuits is prevented, while at the same time the positions of both the finger F and the electromagnetic resonance input pen P can be detected.

[0107] According to the first embodiment, the control lines 90 to 93 extend within the display area A1. Alternatively, the control lines 90 to 93 can also extend within the frame area A2. According to the alternative, the logic circuits 71 and 72 in the display area A1 and the control lines 90 to 93 can be connected to each other by lines that extend below and past the dams 44.

[0108] A computer 1 according to a second embodiment of the present invention is described below. The computer 1 according to the second embodiment differs from the computer 1 according to the first embodiment in that the linear electrodes 52 and 53 are arranged in a manner that differs by 90° relative to those of the first embodiment, the logic circuits 70 and 71 are arranged in the frame area A2, and one logic circuit 72 has a different internal configuration. Since the computer 1 according to the second embodiment is identical to the computer 1 according to the first embodiment in other respects, those different features of the computer 1 according to the second embodiment are described below.

[0109] Fig. Figure 23 is a top view of a sensor layer 14 according to the second embodiment. Fig. Figure 24 illustrates, from a perspective, a display 2 based on organic EL according to the second embodiment. Fig. Figure 23 shows some structural details of a circuit layer 11 and lines SL in dashed lines. Fig. Figure 24 shows the positions of the organic EL-based layer 12 and an encapsulation layer 13 in dashed lines, and some structural details of the circuit layer 11 are shown. Fig. 23 and Fig. Figure 24 shows only six linear electrodes 52 and nine linear electrodes 53 for illustrative purposes. In practice, however, the sensor layer 14 has more linear electrodes 52 and 53.

[0110] As a comparison between Fig. 23 and Fig. 24 and Fig. 3 and Fig. As can be seen in Figure 4, the linear electrodes 52 and 53 of the organic EL-based display 2 according to the second embodiment are arranged in a manner that differs by 90° relative to those of the organic EL-based display 2 according to the first embodiment. According to the second embodiment, the logic circuit 72 therefore extends along an edge of the display area A1 that is located away from a connection area 16.

[0111] The logic circuits 70 and 71 according to the second embodiment are arranged in the circuit layer 11 within the frame area A2. Therefore, the routing paths 60 and 61 do not extend over and around the dams 44 in and along the edge section of the encapsulation layer 13, thus not enclosing the dams 44. However, as in the first embodiment, the routing paths 60 and 61 can be arranged in the circuit layer 11 within the display area A1. The routing paths 60 and 61 arranged in the circuit layer 11 extend from a top side of the encapsulation layer 13 to a bottom side of the same over and around dams 44 (see Fig. 2) in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44.

[0112] The logic circuit 72 according to the second embodiment is, as in the first embodiment, arranged in the circuit layer 11 in the display area A1. Therefore, a routing path 62 extends from the top of the encapsulation layer 13 to the bottom of the same over and around the dams 44 (see Fig. 2) in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44. However, the logic circuit 72 according to the second embodiment does not have any control circuits 110 and 111 for generating and supplying the alternating currents i A and i B and the transmission signal Tx <0> to Tx <6> on and is formed from a simple set of switches. This feature is discussed below with reference to Fig. 25A and Fig. 25B described in detail.

[0113] Fig. 25A and Fig. Figure 25B illustrates in block form the way in which the sensor controller 4 controls the logic circuits in the computer 1 according to the second embodiment. Fig. Figure 25A illustrates in block form the way in which the sensor controller 4, which has entered the first mode, controls the logic circuits, and Fig. Figure 25B illustrates in block form how the sensor controller 4, which has entered the second mode, controls the logic circuits. Fig. 25A and Fig. The linear electrodes 52 and the logic circuits 70 are not illustrated in Figure 25B. The linear electrodes 52 and the logic circuits 70 are identical to those shown in Figure 25B. Fig. 6A and Fig. Figure 6B illustrates this, except that the linear electrodes 52 extend in the x-direction.

[0114] As in Fig. 25A and Fig. As illustrated in Figure 25B, the logic circuit 72 of the second embodiment comprises several single-pole switches, each connected between the ends furthest from the logic circuit 71 in the y-direction of adjacent pairs of the linear electrodes 53. The sensor controller 4 uses the illustrated control signal to control the switches so that all adjacent pairs of the linear electrodes 53 are connected in the first mode, and also to control the switches so that all adjacent pairs of the linear electrodes 53 are disconnected in the second mode. The ends of the linear electrodes 53 furthest from the logic circuit 71 in the y-direction are in the same state in the second mode as in Figure 25B. Fig. 22B illustrated the state. On the other hand, the ends of the linear electrodes 53 furthest from the logic circuit 71 in the y-direction are in a different state in the first mode than in the Fig. 22A illustrates the condition. However, even if the linear electrodes 53 are as shown in Fig. 25A illustrates that the sensor controller 4 is sufficiently connected to detect the position of the input pen P, which operates with electromagnetic resonance.

[0115] The computer 1 according to the second embodiment is advantageous for the following reasons. Since the logic circuit 72 is arranged in the display layer 10 within the display area A1, attempts to reduce the size of the frame area A2 are not hindered, and an increase in the size of the sensor controller 4 circuits is prevented, while at the same time the positions of both the finger F and the electromagnetic resonance input stylus P can be detected. The logic circuits 70 and 71 can also be arranged in the display layer 10 within the display area A1, thereby increasing the advantages described above.

[0116] A computer 1 according to a third embodiment of the present invention is described below. The computer 1 according to the third embodiment differs from the computer 1 according to the second embodiment in that the linear electrodes 52 and 53 are formed from a grid conductor and the computer 1 further comprises the logic circuits 73 to 75. Since the computer 1 according to the third embodiment is identical to the computer 1 according to the second embodiment in other respects, those different features of the computer 1 according to the third embodiment are described below.

[0117] Fig. Figure 26 is a top view of a sensor layer 14 according to the third embodiment. Fig. Figure 27 illustrates, from a perspective, an organic EL-based display 2 according to the third embodiment. Fig. Figure 26 shows some structural details of a circuit layer 11 and lines SL in dashed lines. Fig. Figure 27 shows the positions of the organic EL-based layer 12 and an encapsulation layer 13 in dashed lines, and some structural details of the circuit layer 11 are shown. Fig. 26 and Fig. Figure 27 shows only twelve linear electrodes 52 and eight linear electrodes 53 for illustrative purposes. In practice, however, the sensor layer 14 has more linear electrodes 52 and 53.

[0118] The linear electrodes 52 and 53 are formed from a grid conductor in the form of thin wires, which are combined into rhombic shapes and connected in chains. Although not shown, sections of one of the rhombic shapes of the linear electrodes 52 are connected to sections of another rhombic shape positioned adjacent to the first in the y-direction, and sections of one of the rhombic shapes of the linear electrodes 53 are connected to sections of another rhombic shape positioned adjacent to the first in the x-direction. The linear electrodes 52 and 53 according to the third embodiment can alternatively be made of a solid conductor, as in the first and second embodiments. Conversely, the linear electrodes 52 and 53 according to the first and second embodiments can alternatively be made of a grid conductor according to the third embodiment.

[0119] The logic circuits 73 to 75 are designed to switch between a first mode, in which a sensor controller 4 uses the linear electrodes 52 and 53 to detect induced currents, and a second mode, in which the sensor controller 4 uses the linear electrodes 52 and 53 to detect capacitances. According to the third embodiment, the logic circuits 70, 71, and 73 are arranged in the circuit layer 11 within the frame area A2, while the logic circuits 72, 74, and 75 are arranged in the circuit layer 11 within the display area A1. However, all logic circuits 70 to 75 can be arranged in the circuit layer 11 within the display area A1.

[0120] The x-direction ends of each linear electrode 52 are alternately connected to logic circuit 70 and logic circuit 74. The other x-direction ends of each linear electrode 52 are alternately connected to logic circuit 73 and logic circuit 75. More precisely, those linear electrodes 52 whose x-direction ends are connected to logic circuit 70 are connected to logic circuit 75 at their other x-direction ends, and those linear electrodes 52 whose x-direction ends are connected to logic circuit 74 are connected to logic circuit 73 at their other x-direction ends. The alternating connections of the linear electrodes 52 allow the widths of both sides of the frame area A2 to be balanced in the x-direction.

[0121] The linear electrodes 52 and the logic circuits 70 are interconnected by routing paths 60, while the linear electrodes 52 and the logic circuits 74 are interconnected by routing paths 64. The linear electrodes 52 and the logic circuits 73 are interconnected by routing paths 63, while the linear electrodes 52 and the logic circuits 75 are interconnected by routing paths 65. Since the logic circuits 74 and 75 are located in the circuit layer 11 within the display area A1, the routing paths 64 and 65 extend from a top surface of the encapsulation layer 13 to a bottom surface of the same, over and around dams 44 (see Figure 1). Fig. 2) in and along the edge sections of the encapsulation layer 13, thereby enclosing the dams 44.

[0122] The logic circuit 73 is identical in its configuration to the logic circuit 70, yet separate from it, and is capable of performing similar processes. More precisely, the logic circuit 73 comprises receiving and selection circuits similar to those of the logic circuit 70 and is controlled by the sensor controller 4 to switch between the receiving circuits to be used and also between the connection destinations for each of the linear electrodes 52 in order to extract a received signal Rx from each of the linear electrodes 52.

[0123] Fig. Figure 28 illustrates the internal configurations of the logic circuits 72, 74, and 75. As shown in Fig. As illustrated in Figure 28, the logic circuit 72 is identical in its configuration to the logic circuit 72 according to the second embodiment.

[0124] The logic circuit 74 comprises several single-pole switches, each connected between the ends furthest from logic circuit 75 in the x-direction of adjacent two of the linear electrodes 52. Similarly, logic circuit 75 comprises several single-pole switches, each connected between the ends furthest from logic circuit 74 in the x-direction of adjacent two of the linear electrodes 52. Logic circuits 74 and 75 are configured to control the switching on and off of their switches using alternating control signals supplied to them by the sensor controller 4.

[0125] Fig. 29, Fig. 30A and Fig. Figure 30B illustrates in block form the way in which the sensor controller 4 controls the logic circuits in the computer 1 according to the third embodiment. Fig. Figure 29 illustrates in block form the way in which the sensor controller 4, which has entered a second mode, controls the linking circuits, and Fig. 30A and Fig. Figure 30B illustrates in block form the way in which the sensor controller 4, which has entered a first mode, controls the logic circuits. Fig. 29, Fig. 30A and Fig. In Figure 30B, the linear electrodes 52 and 53 are depicted as simple rectangular shapes for clarity. In reality, however, the linear electrodes 52 and 53 are shaped as a grid.

[0126] As in Fig. As illustrated in 29, the sensor controller 4, which has entered the second mode, switches all in Fig. Figure 28 illustrated the switches by first controlling the logic circuits 72, 74 and 75. Therefore, all ends of the linear electrodes 53 that are not connected to the logic circuit 71 and the ends of the linear electrodes 53 that are not connected to the logic circuits 70 and 73 remain open.

[0127] Then the sensor controller 4 controls the logic circuit 71 to select seven adjacent linear electrodes 53, and controls the logic circuits 70 and 73 to connect the ends of the linear electrodes 52 to an operational amplifier 70b (see Fig. 6A and Fig. 6B). The logic circuit 71, controlled by the sensor controller 4, selects the specified seven linear electrodes 53 and transmits signal Tx. <0> to Tx <6> to the linear electrodes 53. While the logic circuit 71 transmits the signals Tx <0> to Tx <6> The sensor controller receives 4 signals, which were output by the logic circuits 70 and 73 on the basis of the respective linear electrodes 52, as received signals Rx from the linear electrodes 52 and derives capacitances at the junctions between the linear electrode 52 and the seven linear electrodes 53, which were selected by performing the arithmetic operation expressed by the equation (4) above.

[0128] The sensor controller 4 repeatedly performs the above process while changing the linear electrodes 53 to be selected by the linking circuit 71, until the selection of all linear electrodes 53 is complete. When the repetition of the process is finished, the sensor controller 4 has detected the capacitances at the intersections between the linear electrodes 52 and the linear electrodes 53. The sensor controller 4 then derives a distribution—on the panel surface—of the capacitances detected in this way and then derives the position of the finger F based on the derived distribution.

[0129] Then, as in Fig. 30A and Fig. Figure 30B illustrates that the sensor controller 4, which has entered the first mode, initially controls the logic circuits 72, 74 and 75, which in Fig. To establish the illustrated state 30A. More precisely, the sensor controller 4 controls the logic circuit 72 to connect all adjacent pairs of the linear electrodes 53 together, and controls the logic circuits 74 and 75 to connect two pairs of the linear electrodes 52 together. After the logic circuits 74 and 75 have been controlled, the pairs of linear electrodes 52 that have been connected together form a loop coil.

[0130] Then the sensor controller 4 controls the logic circuit 71 to select one of the linear electrodes 53, and controls the logic circuits 70 and 73 to connect both ends of each loop coil to a differential amplifier 70a (see Fig. 6A and Fig. 6B). The logic circuit 71, controlled by the sensor controller 4, selects the specified linear electrode 53 and applies alternating currents i to two linear electrodes 53 next to one side of the selected linear electrode 53. A to and introduces alternating currents i to two linear electrodes 53 next to the other side of the selected linear electrode 53. B to. Immediately after the alternating currents are supplied i A and i B The sensor controller detects 4 signals, which were output by the logic circuits 70 and 73 per loop coil, as received signals Rx at the respective loop coils.

[0131] Then the sensor controller 4 controls the logic circuits 74 and 75, which are in Fig. to produce the state illustrated in Figure 30B. More precisely, the sensor controller 4 controls the linking circuits 74 and 75, which change the linear electrodes 52 to be connected together. Now, loop coils are formed at positions determined by the Fig. The positions illustrated in 30A are shifted by one loop. Afterwards, the sensor controller 4 performs the same process as described above and detects received signals Rx at the respective loop coils.

[0132] The sensor controller 4 repeatedly performs the above process while changing the linear electrodes 53 to be selected by the logic circuit 71, until the selection of all linear electrodes 53—except for two linear electrodes 53 at each end in the x-direction—is complete. When the repeated process is finished, the sensor controller 4 has detected the received signals Rx at the loop coils from the respective linear electrodes 53. The sensor controller 4 then derives a distribution—on the panel surface—of the signal intensities of the received signals Rx detected in this way and subsequently derives a position of the electromagnetic resonance input stylus P based on this derived distribution.

[0133] The computer 1 according to the third embodiment offers the following advantages. Since the logic circuits 72, 74, and 75 are arranged in the display layer 10 within the display area A1, attempts to reduce the size of the frame area A2 are not hindered, and an increase in the size of the sensor controller 4 circuits is prevented, while at the same time the positions of both the finger F and the electromagnetic resonance input stylus P can be detected. The logic circuits 70, 71, and 73 can also be arranged in the display layer 10 within the display area A1 to further enhance the advantages described above.

[0134] A computer 1 according to a fourth embodiment of the present invention is described below. The computer 1 according to the fourth embodiment differs from the computer 1 according to the third embodiment in that the linear electrodes 52 and 53 are spaced apart at an angle of 90°, that the logic circuits 74 and 75 are connected to linear electrodes 53 and not to linear electrodes 52, and with respect to the internal configurations of the logic circuits 72 to 75. Since the computer 1 according to the fourth embodiment is identical to the computer 1 according to the third embodiment in other respects, those different features of the computer 1 according to the fourth embodiment are described below.

[0135] Fig. Figure 31 illustrates the configuration of an organic EL-based display 2 and the internal configurations of the logic circuits 73 to 75 according to the fourth embodiment. According to the fourth embodiment, the logic circuits 70 to 72 are located in the circuit layer 11 within the frame area A2. The logic circuits 73 to 75 are located in the circuit layer 11 within the display area A1. However, all logic circuits 70 to 75 can be located in the circuit layer 11 within the display area A1.

[0136] As in Fig. As illustrated in Figure 31, according to the fourth embodiment, the linear electrodes 53 have ends in the x-direction that are alternately connected to the logic circuit 71 and the logic circuit 74. The other ends in the x-direction of the linear electrodes 53 are alternately connected to the logic circuit 72 and the logic circuit 75. More precisely, the linear electrodes 53 whose ends in the x-direction are connected to the logic circuit 71 are connected at their other ends in the x-direction to the logic circuit 75, and the linear electrodes 53 whose ends in the x-direction are connected to the logic circuit 74 are connected at their other ends in the x-direction to the logic circuit 72. The alternative connections make it possible to compensate for the widths of the two sides of the frame area A2 in the x-direction.

[0137] The linear electrodes 53 and the logic circuit 71 are connected to each other by routing paths 61, and the linear electrodes 53 and the logic circuits 74 are connected to each other by routing paths 64. The linear electrodes 53 and the logic circuits 72 are connected to each other by routing paths 62, and the linear electrodes 53 and the logic circuits 75 are connected to each other by routing paths 65. Since the logic circuits 74 and 75 are located in the circuit layer 11 within the display area A1, the routing paths 64 and 65 extend from a top surface of an encapsulation layer 13 to a bottom surface of the same over and around dams 44 (see Fig. 2) in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44.

[0138] The linear electrodes 52 have ends located in the y-direction away from the logic circuit 73 and connected to the logic circuit 70, and other ends located in the y-direction away from the logic circuit 70 and connected to the logic circuit 73. The linear electrodes 52 and the logic circuits 70 are connected to each other by routing paths 60, and the linear electrodes 52 and the logic circuits 73 are connected to each other by routing paths 63. Since the logic circuit 73 is located in the circuit layer 11 within the display area A1, the routing path 63 extends from the top of the encapsulation layer 13 to its bottom, over and around the dams 44 (see Fig. 2) in and along the edge section of the encapsulation layer 13, thereby enclosing the dams 44.

[0139] The logic circuit 72 according to the fourth embodiment is similar in its configuration to the logic circuit 71, is separate from it, and is capable of performing similar processes to those performed by the logic circuit 71. More precisely, the logic circuit 72 comprises control circuits 110 and 111 and a selection circuit 112 (see Fig. 5), which are similar to those of the logic circuit 71, and is controlled by the sensor controller 4 to switch between the control circuits to be used and also between the connection targets for each of the linear electrodes 53 in time multiplexing in order to supply currents and apply voltages to the linear electrodes 53.

[0140] In contrast to the logic circuit 73 of the third embodiment, the logic circuit 73 according to the fourth embodiment has neither receiving circuits nor a selection circuit and is formed from a simple set of switches. More precisely, the logic circuit 73 comprises several single-pole switches, each connected between the ends in the y-direction of adjacent two of the linear electrodes 53. The logic circuit 73 is configured to control the switching on and off of its switches with alternately different control signals supplied to them.

[0141] The logic circuit 74 according to the fourth embodiment comprises several single-pole switches, each connected between the ends furthest from the logic circuit 75 in the x-direction of adjacent two of the linear electrodes 53. Similarly, the logic circuit 75 comprises several single-pole switches, each connected between the ends furthest from the logic circuit 74 in the x-direction of adjacent two of the linear electrodes 53. The logic circuits 74 and 75 are configured to simultaneously control the switching on and off of all their switches with a control signal supplied to them.

[0142] Fig. Figures 32 to 34A and 34B illustrate in block form the way in which the sensor controller 4 controls the logic circuits in the computer 1 according to the fourth embodiment. Fig. Figure 32 illustrates how the sensor controller 4, which has entered a second mode, controls the linking circuits, and Fig. 33A, Fig. 33B, Fig. 34A and Fig. Figure 34B illustrates how the sensor controller 4, which has entered a first mode, controls the logic circuits. Fig. Figures 32 to 34B show the linear electrodes 52 and 53 depicted as simple rectangular shapes for clarity. In reality, however, the linear electrodes 52 and 53 are shaped as a grid.

[0143] As in Fig. Figure 32 illustrates that the sensor controller 4, which has entered the second mode, initially controls the logic circuits 73 to 75, all in Fig. 31 illustrated switches to be switched off. Therefore, all ends of the linear electrodes 53 that are not connected to the logic circuits 71 and 72, and the ends of the linear electrodes 52 that are not connected to the logic circuit 70, remain open.

[0144] Then the sensor controller 4 controls the logic circuits 71 and 72 to select seven adjacent linear electrodes 53, and controls the logic circuit 70 to connect the ends of the linear electrodes 52 to an operational amplifier 70b (see Fig. 6A and Fig. 6B). The logic circuits 71 and 72, controlled by the sensor controller 4, select the specified seven linear electrodes 53 and transmit signals Tx. <0> to Tx <6> to the linear electrodes 53. According to the fourth embodiment, the transmitted signals Tx <0> to Tx <6> output alternately by the logic circuits 71 and 72, since the linear electrodes 52 are alternately connected to the logic circuits 71 and 72.While the logic circuits 71 and 72 transmit the Tx signals <0> to Tx <6> The sensor controller transmits 4 signals, which were output by the logic circuit 70 on the basis of the respective linear electrodes 52, as received signals Rx from the linear electrodes 52 and derives capacitances at the junctions between the linear electrode 52 and the seven linear electrodes 53, which were selected by performing the arithmetic operation expressed by the equation (4) above.

[0145] The sensor controller 4 repeatedly performs the above process while changing the linear electrodes 53 to be selected by the linking circuits 71 and 72, until the selection of all linear electrodes 53 is complete. When the repeated process is finished, the sensor controller 4 has detected the capacitances at the intersections between the linear electrodes 52 and the linear electrodes 53. The sensor controller 4 then derives a distribution—on the panel surface—of the capacitances detected in this way and then derives the position of the finger F based on this derived distribution.

[0146] As in Fig. 33A, Fig. 33B, Fig. 34A and Fig. Figure 34B illustrates that the sensor controller 4, which has entered the first mode, controls the logic circuits 73 to 75, which are described in Fig. 33A illustrates the state. More precisely, the sensor controller 4 controls the logic circuit 73 to connect two of the linear electrodes 52 together, and controls the logic circuits 74 and 75 to connect all of the linear electrodes 53 together. After the logic circuit 73 has been controlled, the pairs of linear electrodes 52 that have been connected together form a loop coil.

[0147] Then the sensor controller 4 controls the logic circuit 71 to select one of the linear electrodes 53 that is not connected to itself, and controls the logic circuit 70 to connect both ends of each loop coil to a differential amplifier 70a (see Fig. 6A and Fig. 6B). The logic circuit 71, controlled by the sensor controller 4, selects the specified linear electrode 53 and supplies an alternating current i to one side of the selected linear electrode 53. A to and supplies an alternating current i to a linear electrode 53 next to the other side of the selected linear electrode 53. B to. Immediately after the alternating currents are supplied i A and i B The sensor controller detects 4 signals, which were output by the logic circuit 70 per loop coil, as received signals Rx at the respective loop coils.

[0148] Then the sensor controller 4 controls the logic circuit 73, which is in Fig. to produce the state illustrated in 33B. More precisely, the sensor controller 4 controls the logic circuit 73 to change the linear electrodes 52 to be connected. Now loop coils are formed at positions determined by the Fig. The positions illustrated in Figure 33A are shifted by one loop. The sensor controller 4 then performs the same process as described above and detects received signals Rx at the respective loop coils.

[0149] Then the sensor controller 4 controls the logic circuit 73, which is in Fig. to produce the state illustrated in 34B. The logic circuit 73 is thus in the same state as in Fig. Figure 33A illustrates this. The sensor controller 4 then controls the logic circuit 72 to select one of the linear electrodes 53 that is not connected to itself. The logic circuit 72, controlled by the sensor controller 4, selects the specified linear electrode 53 and applies an alternating current i to one side of the selected linear electrode 53. A to and supplies an alternating current i to a linear electrode 53 next to the other side of the selected linear electrode 53. B to. Immediately after the alternating currents are supplied i A and i B The sensor controller detects 4 signals, which were output by the logic circuits 70 and 73 per loop coil, as received signals Rx at the respective loop coils.

[0150] Then the sensor controller 4 controls the logic circuit 73, which is in Fig. to produce the state illustrated in Figure 34B. More precisely, the sensor controller 4 controls the logic circuit 73 to change the linear electrodes 52 to be connected. The logic circuit 73 is thus in the same state as shown in Figure 34B. Fig. Figure 33B illustrates this. The sensor controller 4 then performs the same process as described above to detect received signals Rx at the respective loop coils.

[0151] The sensor controller 4 repeatedly performs the above process while changing the linear electrodes 53 to be selected by the logic circuit 71 or 72, until the selection of all linear electrodes 53—except for one linear electrode 53 at each of the opposite ends in the y-direction—is complete. When the repeated process is finished, the sensor controller 4 has detected the received signals Rx at the loop coils from the linear electrodes 53. The sensor controller 4 then derives a distribution—on the panel surface—of the signal intensities of the received signals Rx detected in this way and subsequently derives a position of the electromagnetic resonance input stylus P based on the derived distribution.

[0152] The computer 1 according to the fourth embodiment is advantageous for the following reasons. Since the logic circuits 73 to 75 are arranged in the display layer 10 within the display area A1, attempts to reduce the size of the frame area A2 are not hindered, and an increase in the size of the sensor controller 4 circuits is prevented, while at the same time the positions of both the finger F and the electromagnetic resonance input stylus P can be detected. The logic circuits 70 to 72 can also be arranged in the display layer 10 within the display area A1, thereby increasing the advantages described above.

[0153] Fig. 35A, Fig. 35B, Fig. 36A and Fig. Figure 36B illustrates in block form the manner in which a sensor controller 4, having entered a first mode, controls logic circuits in a computer 1 according to a modification of the fourth embodiment. The sensor controller 4 according to the modification differs from the sensor controller 4 according to the fourth embodiment in that it controls logic circuits 71 and 72, simultaneously applying alternating currents i to four linear electrodes 53. A and i B to supply. More precisely, according to the modification, the sensor controller 4 supplies the alternating current i A two linear electrodes 53 next to one side of a selected linear electrode 53 and introduces the alternating current i B two linear electrodes 53 next to the other side of the selected linear electrode 53. As a result, two linear electrodes 53 on each side in the y-direction are unable to transmit alternating magnetic fields, while each of the other linear electrodes 53 is able to transmit an alternating magnetic field with a greater intensity.

[0154] A computer 1 according to a fifth embodiment of the present invention is described below. The computer 1 according to the fifth embodiment differs from the computer 1 according to the second embodiment in that it further comprises several linear electrodes 54 and a logic circuit 76, a logic circuit 72 is arranged in the frame area A2, and the linear electrodes 52 do not form loop coils. Since the computer 1 according to the fifth embodiment is identical to the computer 1 according to the second embodiment in other respects, those different features of the computer 1 according to the fifth embodiment are described below.

[0155] Fig. Figure 37 is a top view of a sensor layer 14 according to the fifth embodiment. Fig. Figure 38 illustrates in perspective an organic EL-based display 2 according to the fifth embodiment. Fig. Figure 37 shows some structural details of a circuit layer 11 and of lines SL in dashed lines. Fig. Figure 38 shows the positions of the organic EL-based layer 12 and an encapsulation layer 13 in dashed lines, and some structural details of the circuit layer 11 are shown. Fig. 37 and Fig. Figure 38 shows only ten linear electrodes 52, eight linear electrodes 53, and six linear electrodes 54 for illustrative purposes. In practice, however, the sensor layer 14 has more linear electrodes 52 to 54.

[0156] As in Fig. 37 and Fig. As illustrated in Figure 38, the organic EL-based display 2 according to the fifth embodiment comprises several linear electrodes 54, as well as several linear electrodes 52 and several linear electrodes 53. Each of the linear electrodes 54 is formed from a linear solid conductor that extends in a coiled manner generally in the y-direction. The linear electrodes 54 are deposited on the top surface of a planar insulating film 24 by the same process as the anode electrodes 31 (see Figure 38). Fig. 2) of the lighting elements 30 manufactured.

[0157] Fig. Figure 39 is a top view of the upper surface of the planarizing insulating film 24 of the organic EL-based display 2 according to the fifth embodiment. As in Fig. As illustrated in Figure 39, the anode electrodes 31 are arranged in a matrix on the top surface of the planar insulating film 24. The linear electrodes 54 extend in a coiled pattern to avoid colliding with the anode electrodes 31 arranged in the matrix.

[0158] We return to Fig. 37 and Fig. 38 back. The ends of the linear electrodes 54, which are located near a connection area 16, are connected to the logic circuit 76 by routing paths 66, and their other ends are connected to each other. According to the fifth embodiment, the logic circuit 76—not the logic circuit 71—generates alternating currents i A and i B and directs them to the linear electrodes 54. Therefore, alternating magnetic fields are transmitted from the linear electrodes 54 to detect the position of the input pen P, which operates with electromagnetic resonance. No alternating currents are applied to the linear electrodes 53. A and i B supplied, and a linking circuit 70 transmits only sending signals Tx <0> to Tx <6> to detect the position of finger F at the linear electrodes 53. The logic circuit 72 only needs to have a set of switches similar to those of the logic circuit 72 according to the second embodiment, or it can transmit signals Tx to the linear electrodes 53. <0> to Tx <6> transmit which are identical in nature to those of the logic circuit 71, as is the case with the logic circuit 72 according to the first embodiment.

[0159] With the computer 1 according to the fifth embodiment, the sensor controller 4 – as in the first to fourth embodiments – is able to detect the positions of the electromagnetic resonance input stylus P and the finger F and to acquire data transmitted by the electromagnetic resonance input stylus P. Furthermore, with the computer 1 according to the fifth embodiment, it is possible to arrange the linear electrodes 54, which transmit alternating magnetic fields to detect the position of the electromagnetic resonance input stylus P, in the display layer 10 and not in the sensor layer 14.

[0160] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the details of the preferred embodiments, and various changes and modifications can be made to it without departing from the scope of protection of the invention. Reference symbol list 1 computer 2 organic EL-based displays 3 Host processor 4 Sensor controllers 10 Display layer 11 Circuit layer 12 layers based on organic EL 13 Encapsulation layer 14 Sensor layer 16 Connection area 16 a Pad electrode 20 substrate 21 Buffer layer 22 Gate insulating film 23 Interlayer insulating film 24 planarizing insulating film 25 bank shift 30 lighting elements 31 Anode electrode 32 phosphor layer 33 Cathode electrode 35 pixel control circuit 36 Semiconductor layer 37 Gate electrode 38 Drain electrode 39 Source electrode 41, 43 inorganic layer 42 organic layer 44 dams 50, 51 Insulating film 52 - 54 linear electrode (n) 55 bridge ladders 56 Protective film 60 - 66 Routing path 70 - 76 Linking circuit 70a Differential amplifier 70b Operational amplifier 80 register circuit 81 Buffer circuit 82 Slider 90 - 93 Control line 100, 101 Receiving circuit 102, 112 selection circuit 110, 111 Control circuit A1 Display area A2 frame area P input pen operating with electromagnetic resonance SR <k> , S <k>Sliding register SE <k>Selection circuit VH1 - VH3 through-hole QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 10739889

[0002] US 11462597

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Claims

[1] Display, including: a display layer comprising a group of light elements arranged in a display area and a group of pixel control circuits for switching the light elements on and off; an encapsulation layer that encapsulates the display layer; a group of linear electrodes arranged on the encapsulation layer; a group of routing paths that have first ends connected to the linear electrodes; and a logic circuit located in the display layer within the display area and connected to second ends of the routing paths to switch between a first mode in which the linear electrodes are used to detect induced currents and a second mode in which the linear electrodes are used to detect capacitances. [2] Display according to claim 1, further comprising: a group of first control lines to which the first control signals from a sensor controller are to be supplied, wherein the logic circuit includes a selection circuit for switching connections between the first control lines and the routing paths. [3] Display according to claim 2, further comprising: a group of second control lines to which second control signals are to be supplied, which have an opposite phase to the first control signals from the sensor controller, wherein The selection circuit connects either the first control lines or the second control lines to the routing paths. [4] Display according to claim 3, wherein the group of linear electrodes comprises several linear electrodes extending in a first direction, the routing paths extend in the first direction, and the first control lines and the second control lines extend in a second direction that intersects the first direction. [5] Display according to claim 3, wherein the first control lines and the second control lines extend in the same layer as data lines that supply control currents to the group of light elements. [6] Display according to claim 3, wherein the first control lines and the second control lines extend into the display area. [7] Display according to claim 3, wherein the first control lines and the second control lines extend outside the display area. [8] Display according to claim 1, wherein the routing paths extend from a top to a bottom of the encapsulation layer to enclose dams that form an edge section of the encapsulation layer. [9] Display according to claim 2, wherein the first control signals comprise alternating signals. [10] Display according to claim 2, wherein the first control signals comprise signals generated by switching a switch on and off. [11] Display according to claim 1, further comprising: a reference line extending to the second ends of the linear electrodes, wherein The linking circuit comprises a circuit for switching connections between the reference line and the linear electrodes. [12] Display according to claim 1, wherein the group of linear electrodes comprises several first linear electrodes to which alternating currents or voltage signals are to be supplied, and The logic circuit comprises a circuit for connecting the first ends of the first linear electrodes when alternating currents are supplied to the first linear electrodes, and for disconnecting the first ends of the first linear electrodes when voltage signals are supplied to the first linear electrodes. [13] Display according to claim 12, further comprising: a connection area for connecting the group of linear electrodes to a sensor controller, wherein The logic circuit extends along an edge of the display area that is opposite the connection area. [14] Display according to claim 1, wherein the group of linear electrodes comprises several first linear electrodes extending in a first direction, The logic circuit comprises: a first logic circuit arranged at the first ends of the first linear electrodes, a second logic circuit arranged at the second ends of the first linear electrodes, a third logic circuit arranged at the first ends of the first linear electrodes, and a fourth logic circuit arranged at the second ends of the first linear electrodes. the first ends of the first linear electrodes are alternately connected to the first logic circuit and the third logic circuit, and the second ends of the first linear electrodes are alternately connected to the second logic circuit and the fourth logic circuit. [15] Display according to claim 14, wherein the first logic circuit has several single-pole switches connected between the first ends of adjacent two of the first linear electrodes to which the first logic circuit is connected, and the second logic circuit has several single-pole switches connected between the second ends of adjacent two of the first linear electrodes to which the second logic circuit is connected. [16] Display according to claim 14, wherein the third logic circuit and the fourth logic circuit comprise circuits for extracting induced currents or voltage signals from the first linear electrodes. [17] Display according to claim 14, wherein the third logic circuit and the fourth logic circuit comprise circuits for generating and supplying alternating currents or voltage signals to the first linear electrodes. [18] Display according to claim 1, wherein The logic circuit comprises a group of control circuits for generating and supplying alternating currents or voltage signals to the linear electrodes, depending on phase setting values ​​supplied by a sensor controller, and The sensor controller supplies the phase setting values ​​to the control circuits by supplying first data signals to the control circuits, which are activated when the phase setting values ​​represent 0°, and second data signals, which are activated when the phase setting values ​​represent 180°. [19] Display according to claim 18, wherein the control circuits are configured to be operable in a bootstrapping mode to reduce gate potentials of low-side P-channel metal oxide semiconductor field-effect transistors in output stages to a level lower than a low level. [20] Display, including: a display layer comprising a group of light elements arranged in a display area and a group of pixel control circuits for switching the light elements on and off; a group of linear electrodes that lie above the display layer; and a group of drive circuits arranged in the display layer for driving the linear electrodes, wherein The control circuits are formed from one or more metal oxide semiconductor field-effect transistors, all of which are of the same channel type. [21] Display according to claim 20, wherein The control circuits include circuits for generating and supplying alternating currents or voltage signals to the linear electrodes, depending on phase setting values ​​supplied by a sensor controller, and The sensor controller supplies the phase setting values ​​to the control circuits by supplying first data signals to the control circuits, which are activated when the phase setting values ​​represent 0°, and second data signals, which are activated when the phase setting values ​​represent 180°. [22] Display according to claim 20, wherein the control circuits are configured to be operable in a bootstrapping mode to reduce gate potentials of low-side P-channel metal oxide semiconductor field-effect transistors in output stages to a level lower than a low level.

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