METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR TEST DEVICE

Abstract

A semiconductor device manufacturing process includes a reverse bias test for a device structure, including a step of applying a reverse bias voltage to the device structure, and a monitoring step of monitoring a decrease rate of a leakage current of the device structure at a time of application of the reverse bias voltage.

Description

Technical field

[0001] This application claims priority from Japanese patent application No. 2023-056214, filed with the Japan Patent Office on March 30, 2023, and the entire content of that application is incorporated herein by reference. The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor test device. State of the art

[0002] Patent literature 1 (US 2018 / 0151719 A1) discloses a reverse bias test for determining that a silicon carbide semiconductor device has failed, based on an increased value of a leakage current (see Fig. 8A). Citation list PATENT LITERATURE

[0003] Patent literature 1: US 2018 / 0151719 A1 [Overview]

[0004] The present disclosure provides a method for manufacturing a semiconductor component and a semiconductor test device for detecting a latent defect.

[0005] The present disclosure provides a method for manufacturing a semiconductor device, including a reverse bias test for a device structure, wherein the method comprises: a step of applying a reverse bias voltage to the device structure; and a monitoring step for monitoring a decrease rate of a leakage current of the device structure when the reverse bias voltage is applied.

[0006] The present disclosure provides a method for manufacturing a semiconductor device, wherein the method comprises the steps of: monitoring a decay rate of a leakage current of a device structure when a reverse bias voltage is applied to the device structure; and determining a latent defect of the device structure based on the decay rate of the leakage current.

[0007] The present disclosure provides a semiconductor test device that performs a reverse bias test on a component structure, wherein the semiconductor test device comprises: a voltage application unit that applies a test voltage to the component structure; a voltage generation unit that generates a reverse bias voltage as the test voltage and outputs the reverse bias voltage to the voltage application unit; and a control unit that monitors a rate of decrease of a leakage current of the component structure when the reverse bias voltage is applied.

[0008] The present disclosure provides a semiconductor test device that monitors a decay rate of a leakage current of a component structure when a reverse bias voltage is applied to the component structure and determines a latent defect of the component structure based on the decay rate of the leakage current.

[0009] The aforementioned or further tasks, characteristics and effects will become apparent from the present disclosure, which is described with reference to the accompanying drawings. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a schematic view representing a wafer structure according to a first embodiment. [ Fig. 2] Fig. 2 is a cross-section of the in Fig. 1 Wafer structure shown. [ Fig. 3] Fig. 3 is a cross-section that represents a main section of a Fig. 1 represents the component structure shown. [ Fig. 4] Fig. Figure 4 is a schematic diagram of a semiconductor test device according to a specific embodiment. [ Fig. 5] Fig. Figure 5 is a schematic diagram representing a reverse bias test with respect to the semiconductor test fixture. [ Fig. 6] Fig. Figure 6 is a cross-section that illustrates the reverse bias test along with the component structure. [ Fig. 7] Fig. Figure 7 is a schematic diagram representing a gate bias test in relation to the semiconductor test fixture. [ Fig. 8] Fig. Figure 8 is a cross-section showing the gate bias test along with the component structure. [ Fig. 9] Fig. Figure 9 is a diagram that illustrates the initial behavior characteristics of a leakage current. [ Fig. 10] Fig. Figure 10 is a cross-section used to describe a normal component structure. [ Fig. 11] Fig. Figure 11 is a cross-section for describing a component structure with a latent defect. [ Fig. 12] Fig. Figure 12 is a step or flow diagram that illustrates an example of a method for manufacturing a semiconductor component according to a specific embodiment. [ Fig. 13] Fig. Figure 13 is a step diagram that illustrates an example of a step for detecting a latent defect. [ Fig. 14] Fig. Figure 14 is a step diagram that presents a further example of the method for manufacturing the semiconductor component according to the specific embodiment. [ Fig. 15] Fig. Figure 15 is a cross-section representing a main section of a wafer structure according to a second embodiment. [ Fig. 16] Fig. Figure 16 is a cross-section representing a main section of a wafer structure according to a third embodiment. [ Fig. 17] Fig. Figure 17 is a cross-section representing a main section of a wafer structure according to a fourth embodiment. [ Fig. 18] Fig. 18 is a cross-section of the in Fig. 17 wafer structures shown. [ Fig. 19] Fig. Figure 19 is a cross-section representing a wafer structure according to a fifth embodiment. [Detailed description]

[0010] Specific embodiments are described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic views and not drawn to scale; therefore, relative positions, scales, proportions, angles, and the like may not always correspond. Identical reference numerals are assigned to corresponding structures in the accompanying drawings, and duplicate descriptions are omitted or simplified. For structures whose descriptions have been omitted or simplified, the description prior to the omission or simplification applies.

[0011] When the phrase "essentially" is used in this specification, it includes a numerical value (form) equal to a numerical value (form) of a comparison target, and also numerical errors (form errors) within a range of ±10%, referenced to the numerical value (form) of the comparison target. Although the terms "first," "second," etc., are used in the following description, these are indicators added to the names of the respective structures to clarify the order of description and are not intended to restrict the names of the respective structures.

[0012] In the following description, "p-type" or "n-type" is used to indicate a conductivity type of a semiconductor (impurity). However, the "p-type" can also be referred to as the "first conductivity type," and the "n-type" as the "second conductivity type." The "p-type" is a conductivity type caused by a trivalent element, and the "n-type" is a conductivity type caused by a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] Fig. Figure 1 is a schematic view representing a wafer structure 1A according to a first embodiment. Fig. 2 is a cross-section of the in Fig. 1 Wafer structure 1A shown. Fig. 3 is a cross-section representing a main section of a component structure 11 of which is in Fig. The wafer structure 1A shown in Figure 1 is an intermediate product used to manufacture a semiconductor device 10.

[0014] With reference to Fig. 1 and Fig. Wafer structure 1A comprises a wafer 2, which is formed in a flat disk shape. Wafer 2 can also be formed in a flat rectangular cuboid shape. Wafer 2 comprises a SiC single crystal, as an example of a single crystal from a wide-bandgap semiconductor. That is, wafer 2 is built from a SiC wafer. The single crystal from a wide-bandgap semiconductor is a semiconductor single crystal with a bandgap that is larger than that of the Si single crystal.

[0015] In this embodiment, wafer 2 is made of hexagonal SiC single crystal and is formed in a rectangular cuboid shape. The hexagonal SiC single crystal may have a variety of polytypes, including 2H-(hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. This embodiment describes an example in which wafer 2 has the 4H-SiC single crystal; however, wafer 2 may have other polytypes.

[0016] The wafer 2 has a first surface 3 on one side, a second surface 4 on the other side, and a peripheral end surface 5 that connects the first surface 3 and the second surface 4. The first surface 3 is a component surface and extends flat in a horizontal direction. The second surface 4 is a non-component surface and also extends flat in the horizontal direction. That is, the second surface 4 extends essentially parallel to the first surface 3. The peripheral end surface 5 extends vertically between the first surface 3 and the second surface 4.

[0017] The first surface 3 and the second surface 4 are preferably formed from a c-plane of the SiC single crystal. In this case, it is preferred that the first surface 3 is formed from a silicon face ((0001) face) of the SiC single crystal and the second surface 4 is formed from a carbon face ((000-1) face) of the SiC single crystal.

[0018] Wafer 2 (the first surface 3 and the second surface 4) has an off angle inclined by a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal. That is, the c-axis (the (0001) axis) of the SiC single crystal is inclined by the off angle relative to the vertical axis in the off direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.

[0019] The off-direction is preferably an a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle can be greater than 0° and not more than 10°. The off-angle can have a value that falls within at least one range of 0° or more and 1° or less, 1° or more and 2.5° or less, 2.5° or more and 5° or less, 5° or more and 7.5° or less, and 7.5° or more and 10° or less.

[0020] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in a range of 4° ± 0.1°. This specification does not exclude a shape where the off-angle is 0° (that is, the first surface 3 is a surface directly opposite the c-plane).

[0021] The wafer 2 has a marker or marker element 5a that indicates the crystal azimuth of the SiC single crystal on the peripheral end face 5. The marker element 5a can indicate either the a-axis direction or an m-axis direction ([1-100] direction). In this embodiment, the marker element 5a includes a recessed section. The recessed section can be referred to as an "orientation notch." The recessed section comprises a recess that is set back in a tapered shape toward a central section of the first surface 3 along the a-axis or m-axis direction.

[0022] The wafer 2 can have a diameter of 2 inches or more and 12 inches or less (50 mm or more and 300 mm or less) in a top view. The diameter of the wafer 2 is defined by the length (i.e., the diameter) of a chord passing through the center of the wafer 2 outside the marking element 5a. The diameter of the wafer 2 is preferably 6 inches or more (150 mm or more). The diameter of the wafer 2 is particularly preferably 8 inches or more (200 mm or more).

[0023] In this embodiment, the wafer 2 has a layered structure comprising a first semiconductor layer 6 and a second semiconductor layer 7. The first semiconductor layer 6 is a wafer body and forms a portion of the wafer 2, excluding the front surface portion of the first surface 3. The first semiconductor layer 6 is fabricated from the SiC single crystal, as an example of a wide-bandgap semiconductor single crystal, and exhibits the off-direction and off-angle described above. The first semiconductor layer 6 forms the second surface 4 of the wafer 2 and constitutes part or all of the peripheral end surface 5.

[0024] The second semiconductor layer 7 comprises a SiC epitaxial layer (SiC semiconductor layer), which is obtained by crystal growth of the SiC single crystal, as an example of a wide-bandgap semiconductor single crystal, starting from the first semiconductor layer 6, and exhibits the off-direction and off-angle described above. That is, in this embodiment, the wafer 2 is formed from an epitaxial wafer (so-called epi-wafer).

[0025] The wafer structure 1A comprises a multitude of component regions 8 and a multitude of planned cutting lines 9 formed in the wafer 2. For example, the multitude of component regions 8 and the multitude of planned separation or cutting lines 9 are delimited by alignment marks or the like formed in the first surface 3 (second semiconductor layer 7).

[0026] The multitude of component regions 8 are regions that each correspond to the semiconductor components 10 and are cut out as the multitude of semiconductor components 10 in the singulation step. The multitude of component regions 8 are arranged in an ordered manner (for example, in a matrix) along the a-axis and the m-axis directions. The multitude of component regions 8 are subdivided into rectangular shapes in a top view. The multitude of planned dividing lines 9 extend in a grid pattern along the a-axis and the m-axis directions and subdivide the multitude of component regions 8.

[0027] The wafer structure 1A comprises a plurality of component structures 11, which are formed in the plurality of component regions 8 on the first surface 3. Each component structure 11 can comprise at least one switching component, one rectifier component, and one passive component. The switching component can comprise at least one metal-insulator-semiconductor field-effect transistor (MISFET), one bipolar junction transistor (BJT), one insulated-gate bipolar transistor (IGBT), and one junction or junction field-effect transistor (JFET).

[0028] The rectifier component may comprise at least one pn junction diode, one pin junction diode, one Zener diode, one Schottky junction diode, and one fast recovery or fast switching diode. The passive component may comprise at least one resistor, one capacitor, one inductor, and one fuse.

[0029] Each component structure 11 can comprise a circuit network (e.g., an integrated circuit such as an LSI) in which at least two switching devices, a rectifier device, and a passive device are combined. In this embodiment, each component structure 11 comprises a MISFET structure as an example of a transistor structure Tr. Since the structures of the plurality of component regions 8 (component structures 11) are similar, the structure of one component region 8 (component structure 11) is described below.

[0030] Fig. Figure 3 is a cross-sectional view showing a main section of the component structure 11 in relation to the one in Fig. Figure 1 illustrates the wafer structure 1A. Referring to Fig. In section 3, the wafer structure 1A comprises a first n-type semiconductor region 12, which is formed in a section (surface layer section) on the side of the second surface 4 within the wafer 2. A drain potential Vd is to be applied to the first semiconductor region 12. The first semiconductor region 12 can be referred to as the "drain region".

[0031] The first semiconductor region 12 is formed within the first semiconductor layer 6 and extends in a layered form along the second surface 4. In this embodiment, the first semiconductor region 12 is formed within the entire region of the first semiconductor layer 6 and is exposed by the second surface 4 and the peripheral end surface 5. In this embodiment, the first semiconductor layer 6 is of the n-type, and the first semiconductor region 12 is formed using the first semiconductor layer 6 of the n-type.

[0032] The wafer structure 1A comprises a second n-type semiconductor region 13, which is formed in a section (surface layer section) on the side of the first surface 3 within the wafer 2. The second semiconductor region 13 can be referred to as a "drift region". The second semiconductor region 13 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 12.

[0033] The second semiconductor region 13 is formed within the second semiconductor layer 7 and extends in a layered form along the first surface 3. The second semiconductor region 13 is electrically connected to the first semiconductor region 12 in the layering direction. In this embodiment, the second semiconductor region 13 is formed within the entire region of the second semiconductor layer 7 and is exposed from the first surface 3 and the peripheral end surface 5. In this embodiment, the second semiconductor layer 7 is of the n type, and the second semiconductor region 13 is formed using the second semiconductor layer 7 of the n type.

[0034] The wafer structure 1A comprises a p-type body region 14, which is formed in a surface layer section of the first surface 3. The body region 14 is formed in a surface layer section of the second semiconductor region 13 (i.e., the second semiconductor layer 7). The body region 14 is formed at a distance from the bottom section of the second semiconductor region 13 to the first surface 3 and is opposite the first semiconductor region 12 (i.e., the first semiconductor layer 6) with a portion of the second semiconductor region 13 interposed.

[0035] Wafer structure 1A comprises an n-type source region 15 located in a surface layer portion of the p-type body region 14. The n-type source region 15 exhibits an n-type impurity concentration that is higher than that of the second n-type semiconductor region 13. The n-type source region 15 forms a channel with a MISFET structure, integrating the second n-type semiconductor region 13 into the p-type body region 14.

[0036] Wafer structure 1A comprises a multitude of electrode-trenchment-type gate structures 20, which are formed at intervals in the first surface 3. A gate potential Vg is to be applied to the gate structure 20. The gate structure 20 can be referred to as the "first structure" or as the "trenchment-gate structure". The multitude of gate structures 20 control the channel inversion and non-inversion.

[0037] The multitude of gate structures 20 are arranged at intervals in the m-axis direction and extend in a band-like manner in the a-axis direction. Of course, the multitude of gate structures 20 can also be arranged at intervals in the a-axis direction and extend in a band-like manner in the m-axis direction. The multitude of gate structures 20 penetrate the p-type body region 14 and the n-type source region 15 and are located at a distance from the bottom section of the second n-type semiconductor region 13 to the first surface 3.

[0038] Each gate structure 20 comprises a gate trench 21 (first trench), a gate insulating film 22 (first insulating film), and a gate electrode 23 (first electrode). The gate trench 21 is formed in the first surface 3. The gate insulating film 22 covers the wall surface of the gate trench 21. The gate electrode 23 is embedded in the gate trench 21 via the gate insulating film 22.

[0039] Wafer structure 1A comprises a plurality of electrode-trench type source structures 25 formed in the first surface 3. A source potential Vs is to be applied to the source structure 25. The source structure 25 can be referred to as the "second structure" or as the "trench source structure". Each of the plurality of source structures 25 extends in a band-like manner in the a-axis direction in a section between two adjacent gate structures 20. Naturally, the plurality of source structures 25 can also extend in a band-like manner in the m-axis direction, corresponding to the arrangement of the plurality of gate structures 20.

[0040] The multitude of source structures 25 penetrate the p-type body region 14 and the n-type source region 15 and are located at a distance from the bottom section of the second n-type semiconductor region 13 to the first surface 3. The multitude of source structures 25 are deeper than the multitude of gate structures 20. The multitude of source structures 25 can have a depth approximately equal to that of the gate structure 20.

[0041] Each source structure 25 comprises a source trench 26 (second trench), a source insulating film 27 (second insulating film), and a source electrode 28 (second electrode). The source trench 26 is formed in the first surface 3. The source insulating film 27 covers the wall surface of the source trench 26. The source electrode 28 is embedded in the source trench 26 with the source insulating film 27 positioned between it and the source electrode 28.

[0042] Wafer structure 1A comprises a plurality of p-type contact regions 30, each formed in sections along the plurality of source structures 25 in the second n-type semiconductor region 13. The plurality of p-type contact regions 30 exhibit a p-type impurity concentration that is higher than the p-type impurity concentration of the p-type body region 14.

[0043] The multitude of p-type contact regions 30 are arranged in a one-to-many correspondence with respect to the corresponding source structure 25. The multitude of p-type contact regions 30 are arranged at intervals along the corresponding source structure 25 in a top view. Each p-type contact region 30 extends along the side wall and the bottom wall of the corresponding source structure 25 and is electrically connected to the p-type body region 14 in the surface layer section of the first surface 3.

[0044] The wafer structure 1A comprises a plurality of p-type well regions 31, each formed in sections along the plurality of source structures 25 in the second n-type semiconductor region 13. Each p-type well region 31 has a p-type impurity concentration that is higher than the p-type impurity concentration of the p-type body region 14 and lower than the p-type impurity concentration of the p-type contact region 30.

[0045] The multitude of p-type trough regions 31 are arranged in a one-to-one correspondence with respect to the corresponding source structure 25. In plan view, the multitude of p-type trough regions 31 are arranged in a band-like pattern and extend along the corresponding source structure 25. Each p-type trough region 31 faces the corresponding source structure 25 with the corresponding multitude of p-type contact regions 30 interposed between them. Each p-type trough region 31 extends along the side wall and the bottom wall of the corresponding source structure 25 and is electrically connected to the p-type body region 14 in the surface layer section of the first surface 3.

[0046] The wafer structure 1A comprises an insulating interlayer film 35 covering the first surface 3. In the overall cross-sectional view, shown in the lower part of Fig. In Figure 2, the representation of the interlayer film 35 is omitted for the sake of simplicity (this applies accordingly to the corresponding accompanying drawings below). The interlayer film 35 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. The interlayer film 35 is formed over substantially the entire region of the first surface 3. The interlayer film 35 collectively covers the plurality of gate structures 20 in each component region 8.

[0047] The wafer structure 1A comprises a gate terminal 40, a source terminal 41, and gate wiring 42. In the overall cross-sectional view, shown in the lower part of Fig. Figure 2 shows the representation of the gate terminal 40, the source terminal 41 and the gate wiring 42, which has been omitted for the sake of simplicity (this applies accordingly to the corresponding accompanying drawings below).

[0048] The gate terminal 40 is located on the interlayer film 35. The gate terminal 40 is a terminal electrode to which an external gate potential Vg is applied. The gate terminal 40 can be referred to as the "first terminal electrode," "first pad electrode," "gate pad electrode," or the like. The gate terminal 40 is located in a region close to a central section of one side of the component region 8. The gate terminal 40 can also be located at a corner section of the component region 8. The gate terminal 40 has a rectangular shape.

[0049] Gate Terminal 40 can have a layered structure comprising a titanium-based metallic film and an aluminum-based metallic film. The titanium-based metallic film can comprise one or both a titanium film and a titanium-nitrogen (TiN) film. The aluminum-based metallic film can comprise one or both an aluminum film and an aluminum alloy film. The aluminum alloy film can comprise at least one AlSi alloy film, one AlCu alloy film, and one AlSiCu alloy film.

[0050] The source terminal 41 is arranged on the interlayer film 35 at a distance from the gate terminal 40. The source terminal 41 is a terminal electrode to which the source potential Vs is applied externally. The source terminal 41 can be referred to as the "second terminal electrode," "second pad electrode," "source pad electrode," or the like. The source terminal 41 can comprise the same type of conductive material as the conductive material of the gate terminal 40 and can have substantially the same thickness as the gate terminal 40.

[0051] The source terminal 41 is formed in a polygonal shape with a recessed section that is set back along the gate terminal 40. The source terminal 41 can also be formed in a quadrilateral shape. The source terminal 41 is electrically connected to the p-type body region 14, the n-type source region 15, and the plurality of source structures 25 via a plurality of through-holes formed in the interlayer film 35.

[0052] The maximum permissible gate voltage that can be applied between gate terminal 40 and source terminal 41 can be 1 V or more and 100 V or less. The maximum permissible gate voltage can be a value that falls within at least one of the following ranges: 1 V or more and 10 V or less, 10 V or more and 20 V or less, 20 V or more and 30 V or less, 30 V or more and 40 V or less, 40 V or more and 50 V or less, 50 V or more and 60 V or less, 60 V or more and 70 V or less, 70 V or more and 80 V or less, 80 V or more and 90 V or less, and 90 V or more and 100 V or less.

[0053] The gate wiring 42 extends from the gate terminal 40 onto the interlayer film 35. The gate wiring 42 comprises the same type of conductive material as the conductive material of the gate terminal 40 and can have substantially the same thickness as the gate terminal 40. The gate wiring 42 extends in a ribbon-like fashion along and encircles the source terminal 41. The gate wiring 42 crosses (more precisely, is perpendicular to) the end sections of the plurality of gate structures 20 and is electrically connected to the plurality of gate structures 20 via a plurality of through-holes formed in the interlayer film 35.

[0054] The wafer structure 1A comprises an insulating upper insulating film 45 that selectively covers the gate terminal 40 and the source terminal 41 on the interlayer film 35. The upper insulating film 45 covers the entire region of the gate wiring 42. The upper insulating film 45 is preferably thicker than the gate terminal 40 (source terminal 41).

[0055] The upper insulating film 45 can comprise at least one inorganic insulating film and one organic insulating film. The upper insulating film 45 can comprise a single-layer structure comprising either an inorganic insulating film or an organic insulating film. The upper insulating film 45 can comprise a layered structure comprising an inorganic insulating film and an organic insulating film, layered in that order from the side of the wafer 2. The inorganic insulating film can comprise at least one silicon nitride film, one silicon oxynitride film, and one silicon oxide film.

[0056] The organic insulating film can comprise at least one photosensitive resin film and one thermosetting resin film. The organic insulating film can comprise a single-layer structure comprising a photosensitive resin film. The organic insulating film can comprise a layered structure comprising a photosensitive resin film and a thermosetting resin film, layered in that order from side 2 of wafer 2.

[0057] The photosensitive resin film can be of a negative or positive type. The photosensitive resin film can comprise at least one polyimide film, one polyamide film, and one polybenzoxazole film. The thermosetting resin film can comprise a matrix resin (for example, an epoxy resin) and a variety of fillers.

[0058] The wafer structure 1A comprises a gate opening 46, a source opening 47, and a road opening 48 formed in the upper insulating film 45. In the overall cross-sectional view, shown in the lower part of Fig. Figure 2 shows the representation of the gate opening 46, the source opening 47 and the road opening 48, which has been omitted for the sake of simplicity (this applies accordingly to the corresponding accompanying drawings below).

[0059] Gate opening 46 exposes an inner section of gate terminal 40. Source opening 47 exposes an inner section of source terminal 41. Road opening 48 is formed in a grid pattern along the multitude of planned separation lines 9 and exposes one or both of the first surface 3 and the intermediate layer film 35.

[0060] The wafer structure 1A includes a drain terminal 49 formed on the second surface 4. The drain terminal 49 is a terminal electrode to which an external drain potential Vd is applied. The drain terminal 49 can be referred to as the "third terminal electrode," "third pad electrode," "drain pad electrode," or the like. The drain terminal 49 is electrically connected to the first semiconductor region 12 (first semiconductor layer 6). The drain terminal 49 can comprise at least one Ti film, one Ni film, one Pd film, one Au film, one Ag film, and one Al film.

[0061] The maximum rated drain voltage (i.e., breakdown voltage) that can be applied between the source terminal 41 and the drain terminal 49 (between the first surface 3 and the second surface 4) can be 500 V or more and 3000 V or less. The maximum rated drain voltage can be a value that falls within at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0062] Fig. Figure 4 is a schematic diagram of a semiconductor test device 51 according to a specific embodiment. Fig. Figure 5 is a schematic diagram illustrating a high-temperature reverse bias test with respect to the semiconductor test device 51. Fig. Figure 6 is a cross-sectional view illustrating a high-temperature reverse bias test together with the component structure 11. Fig. Figure 7 is a schematic diagram illustrating a high-temperature gate bias test with respect to the semiconductor test device 51. Fig. Figure 8 is a cross-sectional view illustrating a high-temperature gate bias test together with the component structure 11.

[0063] With reference to the Fig. Figures 4 to 8 describe the semiconductor test fixture 51 as a test fixture for performing a high-temperature reverse bias test. The high-temperature reverse bias test can be referred to as an "HTRB test." The high-temperature reverse bias test is a test in which a reverse bias voltage VRB is applied to the component structure 11 in a high-temperature environment and the characteristics of a leakage current IL are checked (see Figure 4). Fig. 5 and Fig. 6) The high-temperature reverse bias test can be a high-temperature / high-humidity reverse bias test. In the high-temperature / high-humidity reverse bias test, the reverse bias voltage VRB is applied to the component structure 11 in a high-temperature / high-humidity environment, and the leakage current characteristics IL are checked.

[0064] The high-temperature reverse bias test can be a whole-body test or a sample test. In the whole-body test, the electrical characteristics of all of the plurality of component structures 11 are checked. The leakage current characteristics IL of the plurality of component structures 11 can be checked simultaneously or sequentially. In the sample test, the electrical characteristics of one or more component structures 11 selected from the plurality of component structures 11 are checked. The high-temperature reverse bias test is preferably a whole-body test.

[0065] The test period for the high-temperature reverse bias test can be 10 hours or more and 3000 hours or less. The test period for the high-temperature reverse bias test can be set to a value that falls within at least one of the following ranges: 10 hours or more and 100 hours or less, 100 hours or more and 500 hours or less, 500 hours or more and 1000 hours or less, 1000 hours or more and 1500 hours or less, 1500 hours or more and 2000 hours or less, 2000 hours or more and 2500 hours or less, and 2500 hours or more and 3000 hours or less.

[0066] In addition to the high-temperature reverse bias test, the semiconductor test device 51 can be configured to perform a high-temperature gate bias test (see Fig. 7 and Fig. 8) The high-temperature gate bias test can be referred to as the “HTGB test”. The high-temperature gate bias test is a test in which a gate bias voltage VGS is applied to the gate structure 20 in a high-temperature environment and characteristics of a gate leakage current IGS are checked.

[0067] The high-temperature gate bias test can be a complete test or a sample test. In the complete test, the characteristics of all of the plurality of component structures 11 are checked. The characteristics of the gate leakage current IGS of the plurality of component structures 11 can be checked simultaneously or sequentially. In the sample test, the characteristics of one or more component structures 11 selected from the plurality of component structures 11 are checked. The high-temperature gate bias test is preferably a complete test.

[0068] The test period for the high-temperature gate bias test can be 10 hours or more and 3000 hours or less. The test period can be set to a value that falls within at least one of the following ranges: 10 hours or more and 100 hours or less, 100 hours or more and 500 hours or less, 500 hours or more and 1000 hours or less, 1000 hours or more and 1500 hours or less, 1500 hours or more and 2000 hours or less, 2000 hours or more and 2500 hours or less, and 2500 hours or more and 3000 hours or less.

[0069] With reference to Fig. Figure 4 of the semiconductor test apparatus 51 comprises a chamber 52, a heating unit 53, a voltage application unit 54, a voltage generation unit 55, and a control unit 56. The chamber 52 includes a box-shaped partition that separates a test space and includes a transport door 52a through which the wafer structure 1A is conveyed in and out. The transport door 52a can be an opening / closing slide.

[0070] The heating unit 53 comprises a heating element located in the chamber 52 and raises the temperature within the chamber 52 to a predetermined test temperature. The test temperature can be 50 °C or higher and 350 °C or lower. The test temperature can have a value that falls within at least one range of 50 °C or more and 75 °C or less, 75 °C or more and 100 °C or less, 100 °C or more and 125 °C or less, 125 °C or more and 150 °C or less, 150 °C or more and 175 °C or less, 175 °C or more and 200 °C or less, 200 °C or more and 225 °C or less, 225 °C or more and 250 °C or less, 250 °C or more and 275 °C or less, 275 °C or more and 300 °C or less, 300 °C or more and 325 °C or less, and 325 °C or more and 350 °C or less. The test temperature is preferably 100 °C or more and 250 °C or less.

[0071] The voltage application unit 54 is a unit that applies a predetermined test voltage to the component structure 11 (wafer structure 1A). The voltage application unit 54 comprises a table unit 57 and an application end unit 58.

[0072] The table unit 57 is arranged in the chamber 52. The table unit 57 comprises a plate-shaped (disc-shaped in this embodiment) table terminal 59 as a voltage application end. The table terminal 59 can be made of metal. The table terminal 59 has a table surface 60 that is electrically connected to the second surface 4 (drain terminal 49) of the wafer structure 1A.

[0073] The attachment end unit 58 is arranged in the chamber 52. The attachment end unit 58 has one or more (in this embodiment, a plurality of) attachment ends 61 corresponding to the number of terminals of the component structure 11. The attachment end 61 can be a probe. The type and number of attachment ends 61 are appropriately adapted to the type and number of terminal electrodes of the component structure 11. In this embodiment, the plurality of attachment ends 61 comprises a first attachment end 61A for the gate terminal 40 and a second attachment end 61B for the source terminal 41.

[0074] The connection end unit 58 can be configured to check all of the plurality of component structures 11 simultaneously. In this case, the plurality of first connection ends 61A are connected to the gate terminals 40 of all component structures 11, and the plurality of second connection ends 61B are connected to the source terminals 41 of all component structures 11. Of course, the connection end unit 58 can also be configured to check the plurality of component structures 11 individually and sequentially. In this case, a first connection end 61A is connected to the gate terminal 40 of a component structure 11, and a second connection end 61B is connected to the source terminal 41 of a component structure 11.

[0075] The voltage generation unit 55 is a unit that generates a predetermined test voltage and outputs the test voltage to the voltage application unit 54. The voltage generation unit 55 includes a power supply and is electrically connected to the table unit 57 and the application end unit 58. In this embodiment, the voltage generation unit 55 generates a predetermined drain potential Vd, a predetermined gate potential Vg, and a predetermined source potential Vs and outputs the drain potential Vd, the gate potential Vg, and the source potential Vs, respectively, to the table terminal 59, the first application end 61A, and the second application end 61B. This applies the drain potential Vd to the table terminal 59, the gate potential Vg to the first terminal 61A, and the source potential Vs to the second terminal 61B.

[0076] With reference to Fig. 5 and Fig. 6. The high-temperature reverse bias test is performed in a state where the drain terminal 49 of wafer structure 1A is electrically connected to the table terminal 59. The voltage generation unit 55 generates a reverse bias voltage VRB for the component structure 11 during the high-temperature reverse bias test. More precisely, the voltage generation unit 55 shorts the gate terminal 40 and the source terminal 41 and applies a drain bias voltage VDS, which is the reverse bias voltage VRB, to the drain terminal 49.

[0077] This means that the voltage generation unit 55 generates the gate potential Vg, the source potential Vs equal to the gate potential Vg, and the drain potential Vd, which is higher than the source potential Vs. The gate potential Vg and the source potential Vs can be 0 V. The drain bias voltage VDS is a voltage of the drain potential Vd with the source potential Vs as a reference. In the high-temperature reverse bias test, a drain cutoff current IDS is generated as the leakage current IL between the source terminal 41 and the drain terminal 49 due to the drain bias voltage VDS.

[0078] The drain bias voltage (VDS) can be the maximum permissible drain voltage or less than the maximum permissible drain voltage. The drain voltage ratio of the drain bias voltage (VDS) to the maximum permissible drain voltage can be 0.5 or more and 1 or less. The drain voltage ratio can fall within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. Preferably, the drain voltage ratio is 0.8 or more and 1 or less.

[0079] The drain bias voltage (VDS) can be 500 V or more and 3000 V or less. The drain bias voltage (VDS) can have a value that falls within at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0080] With reference to Fig. 7 and Fig. 8. The high-temperature gate bias test is performed in a state where the drain terminal 49 of wafer structure 1A is electrically connected to the table terminal 59. The voltage generation unit 55 generates a gate bias voltage VGS for the gate terminal 40 (first structure) during the high-temperature gate bias test. More precisely, the voltage generation unit 55 shorts the source terminal 41 and the drain terminal 49 and applies the gate bias voltage VGS to the gate terminal 40.

[0081] This means that the voltage generation unit 55 generates the gate potential Vg, the source potential Vs, which is lower than the gate potential Vg, and the drain potential Vd, which is equal to the source potential Vs. The source potential Vs and the drain potential Vd can be 0 V. The gate bias voltage VGS is a voltage of the gate potential Vg with the source potential Vs as a reference. In the high-temperature gate bias test, the gate leakage current IGS is generated between the gate terminal 40 and the source terminal 41 due to the gate bias voltage VGS.

[0082] The gate bias voltage VGS is set according to a breakdown voltage (thickness) of the gate insulating film 22. The gate bias voltage VGS can be the maximum permissible gate voltage or less than the maximum permissible gate voltage. The gate voltage ratio of the gate bias voltage VGS to the maximum permissible gate voltage can be 0.5 or more and 1 or less. The gate voltage ratio can have a value that falls within at least one range of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. The gate voltage ratio is preferably 0.8 or more and 1 or less.

[0083] The gate bias voltage (VGS) is lower than the drain bias voltage (VDS). The gate bias voltage (VGS) can be 1 V or more and 100 V or less. The gate bias voltage (VGS) can have a value that falls within at least one of the following ranges: 1 V or more and 10 V or less, 10 V or more and 20 V or less, 20 V or more and 30 V or less, 30 V or more and 40 V or less, 40 V or more and 50 V or less, 50 V or more and 60 V or less, 60 V or more and 70 V or less, 70 V or more and 80 V or less, 80 V or more and 90 V or less, and 90 V or more and 100 V or less.

[0084] The control unit 56 comprises a central processing unit, a main storage device, an auxiliary storage device, a communication device, a display device, an input device, and the like, and is connected to the chamber 52, the heating unit 53, the voltage application unit 54, and the voltage generation unit 55. The control unit 56 controls the chamber 52, the heating unit 53, the voltage application unit 54, and the voltage generation unit 55 based on a predetermined process recipe or predetermined process specifications stored in the auxiliary storage device or the like, and executes predetermined process operations.

[0085] The control unit 56 is configured to detect a latent defect in the component structure 11 based on the behavior of the drain cutoff current IL (DDS) of the component structure 11 when the reverse bias voltage VRB (Drain Bias Voltage VDS) is applied. That is, the control unit 56 performs a screening test to verify the presence or absence of the latent defect using the high-temperature reverse bias test. The control unit 56 may be referred to as a "measuring section," "determining unit," or the like. "Latent defect" as used in this specification refers to a potential incipient defect that persists in a test procedure (test object) with respect to a normal high-temperature reverse bias test or a high-temperature gate bias test over a long period of time.

[0086] Following a description of an example of the latent defect of component structure 11, a configuration example of the control unit 56 is described below. Fig. Figure 9 is a diagram illustrating the initial behavior characteristics of the leakage current IL with the time of the start of the application of the reverse bias voltage VRB as a reference. Fig. Figure 9 represents the vertical axis as the leakage current IL [A], and the horizontal axis represents the measurement period T [s] of the leakage current IL with the time of the start of the application of the reverse bias voltage VRB as a reference.

[0087] Fig. Figure 9 illustrates the first characteristic C1 and the second characteristic C2 with respect to the two component structures 11. The first characteristic C1 shows an initial behavior characteristic of the leakage current IL of one component structure 11, and the second characteristic C2 shows an initial behavior characteristic of the leakage current IL of the other component structure 11.

[0088] Referring to the first characteristic C1, the leakage current IL with respect to a component structure 11 was essentially constant during the measurement period T. Here, an example of component structure 11 is illustrated where the leakage current IL during the measurement period T was approximately 1 × 10 -4 A is. In a component structure 11, the rate of change of the leakage current IL during the measurement period T was 5% or less.

[0089] On the other hand, with reference to the second characteristic C2, the leakage current IL with respect to the other component structure 11 decreased significantly during the measurement period T. More precisely, the leakage current IL with respect to the other component structure 11 decreased starting from the beginning of the test (the start of the application of the reverse bias voltage VRB). In this example, the leakage current IL with respect to the other component structure 11 decreased sharply immediately after the start of the test and then continued to decrease slowly.

[0090] For the second characteristic C2, starting from an initial leakage current value Iin at the beginning of the test as a reference, the reduction rates of the leakage current IL at 5 seconds, 10 seconds, 25 seconds, 50 seconds, and 150 seconds were: 20% or more, 30% or more, 60% or more, and 70% or more, respectively. An example of component structure 11 is illustrated here, where the initial leakage current value Iin is approximately 1 × 10 4 A is. The initial value Iin of the leakage current IL assumes different values ​​according to a crystal state of the wafer 2, the electrical characteristics of the component structure 11 and the like.

[0091] Since the leakage current IL tends to decrease with respect to the second characteristic C2, it was assumed that the other component structure 11 exhibits electrical characteristics superior to those of the first component structure 11. The researchers of this specification intensively investigated the effect of reducing the leakage current IL. As a result, it was found that the leakage current IL with respect to the first characteristic C1 indicates the initial behavior of the leakage current IL with respect to the normal component structure 11, and that the leakage current IL with respect to the second characteristic C2 indicates the initial behavior of the leakage current IL with respect to the abnormal component structure 11 with the latent defect.

[0092] Fig. Figure 10 is a cross-sectional view to describe the normal component structure. Figure 11. Fig. Figure 11 is a cross-sectional view describing the component structure 11 with the latent defect. With reference to Fig. In the case of the normal component structure 11 (first characteristic C1), when the reverse bias voltage VRB is applied to the component structure 11, a first leak path P1 of the leak current IL through the wafer 2 between the source terminal 41 and the drain terminal 49 is formed.

[0093] The first leakage path P1 is considered to be caused by threading screw dislocation in the SiC single crystal. In the normal component structure 11, the leakage current IL does not exhibit any abnormal behavior because the extent of the abnormality of the first leakage path P1 (threading screw dislocation) is within the design range.

[0094] On the other hand, with reference to Fig. In the component structure 11 (second characteristic C2) with the latent defect, in addition to the first leakage path P1, one or both of a second leakage path P2, caused by the crystal defect of the semiconductor single crystal, and a third leakage path P3, caused by an unwanted residue product or the like generated in the manufacturing process, may be formed. In the component structure 11 with the latent defect, the second leakage path P2, caused by the crystal defect, tends to be observed as clearly.

[0095] The single-crystal semiconductor defect is in many cases a stacking defect that forms within the wafer 2 and extends laterally along the first surface 3 (second surface 4). The stacking defect can be present in one or both of the first semiconductor layer 6 and the second semiconductor layer 7. The stacking defect is a problem related to the fabrication of wafer 2, and it is possible that the second leakage path P2 already exists before the formation of the device structure 11.

[0096] The second leak path P2 can be formed or enlarged during the formation of the component structure 11 due to a load (stress or the like). As a result of the leakage current IL flowing through the abnormal first leak path P1, the second leak path P2 can be formed or enlarged starting from the first leak path P1. On the other hand, a residue product generated in the manufacturing process is produced during the formation of the component structure 11 or the like and adheres to the first surface 3 and / or to the structure on the first surface 3.

[0097] In the component structure 11 with the latent defect, it is assumed that the abnormality of the leakage current IL occurs due to the abnormality of the first leakage path P1, at least one of the second leakage path P2 and the third leakage path P3 or a combination of at least two of these.

[0098] If an abnormality exceeding the design range exists in the first leakage path P1 (screw offset), a portion of the leakage flow IL is dissipated as thermal energy in the abnormal section of the first leakage path P1 (screw offset). If the second leakage path P2 (stack fault) exists, a portion of the leakage flow IL flows into the second leakage path P2 (stack fault) and is dissipated as thermal energy. If the third leakage path P3 (residual product) exists, a portion of the leakage flow IL flows into the third leakage path P3 (residual product) and is dissipated as thermal energy.

[0099] As described above, the leakage current IL in component structure 11 with the latent defect decreases compared to the normal component structure 11 due to the undesired elements (P1 to P3) that reduce the leakage current IL. In component structure 11 with the latent defect, the leakage current IL decreases at an extremely low rate during the initial phase of the test (initial behavior characteristic). Furthermore, in component structure 11 with the latent defect, the rate of decrease of the leakage current IL slows over time, and favorable leakage characteristics are observed.

[0100] Therefore, the component structure 11 with the latent defect passes both the standard high-temperature reverse bias test and the high-temperature gate bias test and is marketed as a semiconductor component 10. Due to load accumulation on the latent defect as a result of long-term use, the risk of component failure increases in the semiconductor component 10 with the latent defect.

[0101] With renewed reference to Fig. In this embodiment, the control unit 56 comprises a measuring section 62 configured to detect the latent defect of the component structure 11 based on the behavior (initial behavior characteristics) of the leakage current IL. That is, the measuring section 62 is configured to detect component structures 11 exhibiting one or both of the crystal defect and residue product abnormalities based on the behavior (initial behavior characteristics) of the leakage current IL.

[0102] The measuring section 62 is configured to monitor the rate of decrease of the leakage current IL as a behavior (initial behavior characteristics) of the leakage current IL. More precisely, the measuring section 62 is configured to monitor the rate of decrease of the leakage current IL of wafer structure 1A (device structure 11) during the application period of the reverse bias voltage VRB, and the latent defect of the component structure 11 is detected based on the rate of decrease of the leakage current IL.

[0103] More precisely, the measuring section 62 has a monitoring period TM as measurement period T with the time of the start of the application of the reverse bias voltage VRB as a reference and is configured so that the decrease rate of the leakage current IL is monitored with the initial value Iin of the leakage current IL in the monitoring period TM as a reference (see Fig. 9).

[0104] The initial value Iin of the leakage current IL can be any value of the leakage current IL measured within 5 seconds of the start of the application of the reverse bias voltage VRB. The initial value Iin of the leakage current IL is preferably set to any value of the leakage current IL measured within one second of the start of the application of the reverse bias voltage VRB. The initial value Iin of the leakage current IL can be a value of the leakage current IL first recorded in the monitoring period TM.

[0105] Since the rate of decay of the leakage current IL per unit time varies depending on the aspect of the latent defect and the specification of the component structure 11, the monitoring period TM is adjusted accordingly. Naturally, the monitoring period TM can be set based on a statistical value of the decay time of the leakage current IL with respect to the multitude of component structures 11 with the latent defect.

[0106] In the case of the normal high-temperature reverse bias test step, since a load is applied to the component structure 11 for a long period of time (e.g., several hours to several thousand hours), the measurement period T of the leakage current IL is set to a long period (e.g., several hours to several thousand hours).

[0107] On the other hand, in a case where the component structure 11 exhibits the latent defect, the leakage current IL tends to decrease from the time the reverse bias voltage VRB is applied due to the latent defect (see Fig. 9) Therefore, the monitoring period TM can be set shorter than the measurement period T according to the normal high-temperature reverse bias test step.

[0108] The monitoring period TM can be within 60 minutes of the start of the application of the reverse bias voltage VRB. The monitoring period TM can be within 60 minutes, 55 minutes, 50 minutes, 45 minutes, 40 minutes, 35 minutes, 30 minutes, 25 minutes, 20 minutes, 15 minutes, 10 minutes, 5 minutes, or 1 minute. The monitoring period TM is preferably within 30 minutes.

[0109] For example, if the leakage current IL decreases within 100 seconds from the time the reverse bias voltage VRB is applied (see the second characteristic C2 in Fig. 9) The monitoring period TM can be within 10 minutes, within 5 minutes, or within 1 minute. For example, in the case of the second characteristic C2 described above, the latent defect is detected within 400 seconds.

[0110] The measuring section 62 includes a determination section 63, which determines the latent defect of the component structure 11 based on the rate of decay of the leakage current IL, in order to avoid erroneous detection of a normal leakage characteristic (first characteristic C1). The determination section 63 can be configured by software integrated into the measuring section 62. The determination section 63 is configured such that the latent defect is determined based on a rate of decay of the leakage current IL relative to a reference value set for the leakage current IL.

[0111] More precisely, determination section 63 determines the latent defect based on the rate of decay of the leakage current IL, using the initial value Iin of the leakage current IL during the monitoring period TM as a reference. Determination section 63 can determine that the component structure 11 has the latent defect if the rate of decay of the leakage current IL, using the initial value Iin of the leakage current IL as a reference, is 10% or more. Determination section 63 can determine that the latent defect is present if the rate of decay of the leakage current IL is 20% or more.

[0112] Determination section 63 can have a predetermined leakage threshold value LTh with respect to the decay rate of the leakage current IL, using the initial value Iin of the leakage current IL as a reference, and determine that the component structure 11 has the latent defect in a case where the decay rate of the leakage current IL exceeds the leakage threshold value LTh. The leakage threshold value LTh can be 10% or more and 90% or less.

[0113] The leakage threshold value LTh can have a value that falls within at least one range of 10% or more and 15% or less, 15% or more and 20% or less, 20% or more and 25% or less, 25% or more and 30% or less, 30% or more and 35% or less, 35% or more and 40% or less, 40% or more and 45% or less, 45% or more and 50% or less, 50% or more and 55% or less, 55% or more and 60% or less, 60% or more and 65% or less, 65% or more and 70% or less, 70% or more and 75% or less, 75% or more and 80% or less, 80% or more and 85% or less, and 85% or more and 90% or less. The leakage threshold LTh is preferably 10% or more. The leakage threshold LTh is particularly preferably 20% or more. The leakage threshold LTh can be 60% or less. The leakage threshold LTh can be 50% or less.

[0114] Determination section 63 can determine that the component structure 11 has the latent defect if the rate of decrease of the leakage current IL within the monitoring period TM becomes equal to or greater than the leakage threshold value LTh. For example, in a case where the leakage threshold value LTh is set to 20%, it is determined that the component structure 11 with the second characteristic C2 has the latent defect after 5 seconds (see Fig. 9). For example, in a case where the leakage threshold LTh is set to 30%, it is determined that the component structure 11 with the second characteristic C2 exhibits the latent defect after 10 seconds (see Fig. 9).

[0115] Naturally, determination section 63 can determine that the component structure 11 has the latent defect if the leakage current decay rate IL at the end of the monitoring period TM is equal to or greater than the leakage threshold LTh. For example, if the leakage threshold LTh is set to a value in the range of 20% or more and 70% or less, it is determined that the component structure 11 with the second characteristic C2 has the latent defect at the end of the monitoring period TM (see Fig. 9).

[0116] The control unit 56 can be configured to store the determination result for component structure 11 in an auxiliary storage device or the like after the latent defect has been determined, and to exclude component structure 11 with the latent defect from the production line in the subsequent manufacturing process. In this case, the determination result of the latent defect with respect to one or more (preferably all) component structures 11 can be stored in the auxiliary storage device or the like in conjunction with an identification number of the component structure 11 or a map of the wafer 2.

[0117] Fig. Figure 12 is a step diagram illustrating an example of a method for manufacturing the semiconductor device 10 according to a specific embodiment. Reference is made below, where necessary. Fig. Reference is made accordingly to sections 1 to 11. In the following description, facts that overlap with those described for the semiconductor test device 51 are omitted as necessary.

[0118] The process for manufacturing the semiconductor device 10 comprises a step (S1) for preparing the wafer structure 1A described above (see Fig. 1 to 3). The method for manufacturing the semiconductor device 10 comprises a step (S2) for detecting the latent defect of the device structure 11. The step (S2) for detecting the latent defect is performed using the semiconductor test device 51 described above (see Fig. 4) The step (S2) for detecting the latent defect can be integrated into a normal high-temperature reverse bias test step. In this case, the monitoring period TM can be set at the beginning of the measurement period T of the normal high-temperature reverse bias test (i.e., at the time of the test start).

[0119] The latent defect detection step (S2) can be performed separately from a normal high-temperature reverse bias test step. The latent defect detection step (S2) can be performed before the normal high-temperature reverse bias test. The latent defect detection step (S2) can be performed after the normal high-temperature reverse bias test. Considering potential variations in the leakage current IL characteristics caused by the normal high-temperature reverse bias test, the latent defect detection step (S2) is preferably performed before the normal high-temperature reverse bias test.

[0120] The following describes step (S2) for detecting the latent defect with reference to Fig. 13 described. Fig. Figure 13 is a step diagram illustrating an example of step (S2) for detecting the latent defect. Referring to Fig. 13 The acquisition step (S2) includes a step (S21) for introducing the wafer structure 1A into the semiconductor test device 51 described above (see Fig. 4) The wafer structure 1A is arranged on the table terminal 59 in a position where the drain terminal 49 faces the table surface 60. Thus, the drain terminal 49 is electrically connected to the table terminal 59 (see also Fig. 5).

[0121] The acquisition step (S2) includes a step (S22) to apply the reverse bias voltage VRB to the component structure 11 after the step (S21) to insert the wafer 2. In the application step (S22), the gate terminal 40 and the source terminal 41 are short-circuited at a predetermined test temperature, and the drain bias voltage VDS, which is the reverse bias voltage VRB, is applied to the drain terminal 49 (see also Fig. 5 and Fig. 6) This generates the drain cutoff current IDS as the leakage current IL between the source terminal 41 and the drain terminal 49.

[0122] The acquisition step (S2) includes a step (S23) for monitoring the behavior of the leakage current IL. The leakage current monitoring step (S23) includes a step for monitoring the rate of decrease of the leakage current IL. More precisely, the monitoring step (S23) includes a step for monitoring the rate of decrease of the leakage current IL with respect to the initial value Iin of the leakage current IL over a predetermined monitoring period TM, with the time of the start of the application of the reverse bias voltage VRB as the reference point.

[0123] Monitoring step (S23) includes a step (S23) for determining the latent defect of component structure 11. In step (S23) for determining the latent defect, the latent defect of component structure 11 is determined based on the rate of decay of the leakage current IL to avoid erroneous detection of the normal component structure 11 or of component structure 11 as normal. More precisely, in the determination step (S23), the latent defect is determined based on the rate of decay of the leakage current IL with the initial value Iin of the leakage current IL in the monitoring period TM as a reference.

[0124] The determination step (S23) may include a step in which it is determined that the component structure 11 has the latent defect, in a case where the decay rate of the leakage current IL with the initial value Iin of the leakage current IL as a reference is 10% or more. The step (S23) for determining the latent defect may include a step in which it is determined that the component structure 11 has the latent defect, in a case where the decay rate of the leakage current IL is 20% or more.

[0125] The step (S23) for determining the latent defect may include a step in which, if the leakage threshold value LTh described above (for example, 10% or more and 90% or less) is provided for the decay rate of the leakage current IL with the initial value Iin of the leakage current IL as a reference, it is determined that the component structure 11 has the latent defect in a case where the decay rate of the leakage current IL exceeds the leakage threshold value LTh.

[0126] Step (S2) for detecting the latent defect includes a step (S24) for storing the determination result in an auxiliary storage device or the like. In the storage step (S24), the determination result of the latent defect with respect to one or more (preferably all) component structures 11 is stored in the auxiliary storage device or the like in conjunction with an identification number of the component structure 11 or a card of the wafer 2. Thus, the component structure 11 with the latent defect is excluded from the production line in the subsequent steps.

[0127] With renewed reference to Fig. The method for manufacturing the semiconductor component 10 comprises a high-temperature gate bias test (S3). The high-temperature gate bias test (S3) is preferably performed after step (S2) for detecting the latent defect. Of course, the high-temperature gate bias test (S3) can also be performed before step (S2) for detecting the latent defect.

[0128] In the high-temperature gate bias test (S3), the source terminal 41 and the drain terminal 49 are short-circuited at a predetermined test temperature, and the gate bias voltage VGS is applied to the gate structure 20 (see also Fig. 7 and Fig. 8) This generates and monitors the gate leakage current IGS between the gate terminal 40 and the source terminal 41. After the high-temperature gate bias test (S3), the wafer structure 1A is ejected from the semiconductor test fixture 51.

[0129] The process for fabricating the semiconductor device 10 comprises a step (S4) for singulating the wafer structure 1A after the high-temperature reverse bias test (S2) and the high-temperature gate bias test (S3). In the singulation step (S4), the wafer structure 1A is cut along the planned parting lines 9, and a plurality of device regions 8 (device structures 11) are each cut out as a plurality of semiconductor devices 10. The semiconductor devices 10 are fabricated by steps including those described above.

[0130] As described above, the specific embodiment provides a method for manufacturing the semiconductor device 10, which includes the reverse bias test (S2) for the device structure 11. The reverse bias test (S2) comprises the step (S22) for applying the reverse bias voltage VRB and the step (S23) for monitoring the leakage current IL. In the application step (S22), the reverse bias voltage VRB is applied to the device structure 11. In the monitoring step (S23), the rate of decrease of the leakage current IL of the device structure 11 is monitored at the time the reverse bias voltage VRB is applied.

[0131] According to this manufacturing process, it is possible to detect the component structure 11 with the latent defect based on the rate of decrease of the leakage current IL. For example, the monitoring step (S23) can include the step of determining the latent defect of component structure 11 based on the rate of decrease of the leakage current IL. This excludes component structure 11 with the latent defect from the production line, and the distribution of the semiconductor component 10 with the latent defect to the market is suppressed.

[0132] The monitoring step (S23) preferably includes the step for determining the latent defect of the component structure 11 based on the decay rate of the leakage current IL with the initial value Iin of the leakage current IL as a reference. The leakage current IL of the component structure 11 with the latent defect has the characteristic of decreasing from the time the reverse bias voltage VRB is applied (see the second characteristic C2 in Fig. 9) Therefore, by using the initial value Iin of the leakage current IL as a reference, an erroneous detection of the normal component structure 11 is suppressed, and the component structure 11 with the latent defect is adequately detected.

[0133] Monitoring step (S23) preferably includes the step of determining that the component structure 11 has the latent defect in a case where the leakage current decay rate IL is 10% or more. Monitoring step (S23) preferably includes the step of determining that the component structure 11 has the latent defect in a case where the leakage current decay rate IL is 20% or more. According to the manufacturing process, a faulty detection of the normal component structure 11 is adequately suppressed.

[0134] Monitoring step (S23) can include the step for monitoring the rate of decrease of the leakage current IL from the start of the application of the reverse bias voltage VRB. That is, monitoring step (S23) can include the step for monitoring the rate of decrease of the initial behavior of the leakage current IL. Monitoring step (S23) can include the step for monitoring the rate of decrease of the leakage current IL during the monitoring period TM, with the time of the start of the application of the reverse bias voltage VRB as the reference point.

[0135] The leakage current IL of component structure 11 with the latent defect exhibits the characteristic of decreasing from the time the reverse bias voltage VRB is applied (see the second characteristic C2 in Fig. 9) Therefore, by setting the monitoring period TM with the time of the start of the application of the reverse bias voltage VRB as a reference, an erroneous detection of the normal component structure 11 is suppressed, and the component structure 11 with the latent defect is adequately detected.

[0136] Since the leakage current IL of the component structure 11 with the latent defect has the characteristic of decreasing from the time the reverse bias voltage VRB is applied (see the second characteristic C2 in Fig. 9) The latent defect is detected within a relatively short time period. For example, the monitoring period TM in monitoring step (S23) can be set shorter than the test time of the normal high-temperature reverse bias test or the test time of the normal high-temperature gate bias test. For example, the monitoring period TM can be within 60 minutes. For example, the monitoring period TM can be within 30 minutes.

[0137] The reverse bias test (S2) can be the high-temperature reverse bias test (S2), in which the reverse bias voltage VRB is applied in a high-temperature environment. The monitoring step (S23) can be performed in a relatively short time and can therefore be integrated into a standard high-temperature reverse bias test. For example, the monitoring step (S23) can be integrated at the beginning of a standard high-temperature reverse bias test.

[0138] The reverse bias voltage VRB can be 500 V or more and 3000 V or less. The reverse bias test (S2) is preferably the wafer-level test for the component structures 11 formed on wafer 2. According to this manufacturing process, since the latent defect of the component structure 11 is detected at the wafer level before the singulation step (S3), a packaging step for the semiconductor component 10 with the latent defect after the singulation step (S3) is not required. This reduces manufacturing costs.

[0139] Wafer 2 preferably comprises the SiC single crystal as an example of a wide-bandgap semiconductor single crystal. According to this fabrication process, the semiconductor device 10 is manufactured as a SiC semiconductor device. In the case of a SiC semiconductor device, the SiC semiconductor device is used in a high-load environment (under a high-voltage and / or high-temperature environment) due to the physical properties (electrical characteristics) of the SiC single crystal. For example, the SiC semiconductor device can be mounted on a drive source of a motor in a hybrid vehicle, an electric vehicle, a fuel cell vehicle, or the like.

[0140] In a case where a SiC semiconductor device with a latent defect is used in a high-load environment, the risk of device failure starting at the location of the latent defect increases. In this respect, according to the method for manufacturing the semiconductor device 10, the latent defect of the device structure 11 can be identified as a SiC semiconductor device. Therefore, the distribution of the SiC semiconductor device with the latent defect to the market is suppressed. This prevents a reduction in application reliability caused by the SiC semiconductor device with the latent defect.

[0141] The component structure 11 can include the transistor structure Tr. According to this manufacturing procedure, the latent defect of the component structure 11 with the transistor structure Tr can be detected. The transistor structure Tr can have a gate, a source, and a drain. In this case, the reverse bias voltage VRB is the drain bias voltage VDS, and the leakage current IL is the drain cutoff current IDS. The procedure for manufacturing the semiconductor component 10 can include the gate bias test (S3) for the transistor structure Tr.

[0142] From another perspective, the specific embodiment provides the semiconductor test device 51, which performs the reverse bias test (S2) on the component structure 11. The semiconductor test device 51 comprises the voltage generation unit 55, the voltage application unit 54, and the control unit 56. The voltage application unit 54 applies the test voltage to the component structure 11. The voltage generation unit 55 generates the reverse bias voltage VRB as the test voltage and outputs the reverse bias voltage VRB to the voltage application unit 54. The control unit 56 monitors the rate of decrease of the leakage current IL of the component structure 11 at the time the reverse bias voltage VRB is applied.

[0143] According to the semiconductor test device 51, it is possible to detect the component structure 11 with the latent defect based on the rate of decrease of the leakage current IL. For example, the control unit 56 can determine the latent defect of the component structure 11 based on the rate of decrease of the leakage current IL. This excludes the component structure 11 with the latent defect from the production line, and the distribution of the semiconductor component 10 with the latent defect to the market is suppressed.

[0144] The control unit 56 preferably determines the latent defect of the component structure 11 based on the decay rate of the leakage current IL, with the initial value Iin of the leakage current IL as a reference. According to this configuration, the erroneous detection of the normal component structure 11 is suppressed, and the component structure 11 with the latent defect is adequately detected.

[0145] The control unit 56 preferably determines that the component structure 11 has the latent defect if the leakage current decay rate IL is 10% or more. The control unit 56 preferably determines that the component structure 11 has the latent defect if the leakage current decay rate IL is 20% or more. According to these configurations, a false detection of the normal component structure 11 is adequately suppressed.

[0146] The control unit 56 preferably monitors the rate of decrease of the leakage current IL during the monitoring period TM, using the time of the start of the application of the reverse bias voltage VRB as a reference. According to this configuration, false detection of the normal component structure 11 is suppressed, and the component structure 11 with the latent defect is adequately detected. For example, the monitoring period TM can be within 60 minutes. For example, the monitoring period TM can be within 30 minutes.

[0147] The reverse bias test (S2) can be the high-temperature reverse bias test (S2). The reverse bias voltage VRB can be 500 V or more and 3000 V or less. The reverse bias test (S2) is preferably the wafer-level test for the component structures 11 formed on wafer 2.

[0148] According to the semiconductor test device 51, since the latent defect of the component structure 11 is detected at the wafer level before the singulation step (S3), a packaging step for the semiconductor component 10 with the latent defect after the singulation step (S3) is not required. This reduces the manufacturing costs.

[0149] Wafer 2 preferably comprises the SiC single crystal as an example of a wide-bandgap semiconductor single crystal. According to the semiconductor test device 51, the latent defect of the component structure 11 can be detected as a SiC semiconductor component. Therefore, according to the semiconductor test device 51, the distribution of a SiC semiconductor component with the latent defect to the market is suppressed, and a reduction in the reliability of applications caused by the SiC semiconductor component with the latent defect is suppressed. The semiconductor test device 51 can be a device that performs the reverse bias test (S2) on the component structure 11 according to the vehicle-integrated semiconductor component 10 (SiC semiconductor component).

[0150] The component structure 11 can include the transistor structure Tr. According to the semiconductor test device 51, the latent defect of the component structure 11 can be detected using the transistor structure Tr. The transistor structure Tr can have a gate, a source, and a drain. In this case, the reverse bias voltage VRB is the drain bias voltage VDS, and the leakage current IL is the drain cutoff current IDS. The semiconductor test device 51 can be configured to perform the gate bias test (S3) on the transistor structure Tr.

[0151] Fig. Figure 14 is a step diagram illustrating another example of the method for fabricating the semiconductor device 10 according to the specific embodiment. In the method for fabricating the semiconductor device 10 according to another example, step (S2) for detecting the latent defect is performed as a high-temperature reverse bias test, while the high-temperature gate bias test (S3) is omitted. In the high-temperature gate bias test (S3), the gate bias voltage VGS, which is lower than the drain bias voltage VDS with respect to step (S2) for detecting the latent defect, is applied to the gate structure 20.

[0152] This allows the stress exerted on the gate structure 20 due to the gate bias voltage VGS to be smaller than the stress exerted on the gate structure 20 due to the drain bias voltage VDS. Therefore, in a case where the reliability of the gate structure 20 is ensured in step (S2) for latent defect detection, the method for fabricating the semiconductor device 10 according to another example can be applied. Of course, step (S2) for latent defect detection can be integrated into a standard high-temperature reverse bias test.

[0153] The following describes another embodiment of the wafer structure 1A. Fig. Figure 15 is a cross-sectional view illustrating a main section of the component structure 11 of a wafer structure 1B according to a second embodiment. With reference to Fig. 15 According to the second embodiment, the wafer structure 1B does not have the source structure 25 in the component structure 11.

[0154] In this embodiment, the contact region 30 described above is formed in the surface layer section of the body region 14 in the area between the two adjacent gate structures 20. In this embodiment, the source terminal 41 described above is electrically connected to the body region 14, the source region 15, and the plurality of contact regions 30 via a plurality of through-holes formed in the insulating interlayer film 35.

[0155] Fig. Figure 16 is a cross-sectional view illustrating a main section of the component structure 11 of a wafer structure 1C according to a third embodiment. With reference to Fig. In the third embodiment, wafer structure 1C features a planar electrode-type gate structure 20 instead of the trench-electrode-type gate structure 20 in component structure 11. The gate structures 20 can be referred to as "planar gate structures." Since the structures of the multitude of component structures 11 are similar, one structure of a component structure 11 is described below.

[0156] The wafer structure 1C comprises a plurality of p-type body regions 14, which are formed at intervals in the surface layer section of the first surface 3. The plurality of body regions 14 are formed in the surface layer section of the second semiconductor region 13 (i.e., the second semiconductor layer 7). The plurality of body regions 14 are formed at intervals from the bottom section of the second semiconductor region 13 towards the first surface 3 and are opposite the first semiconductor region 12 (i.e., the first semiconductor layer 6) with a portion of the second semiconductor region 13 interposed.

[0157] The wafer structure 1C comprises a plurality of n-type source regions 15, each formed in the surface layer sections of the plurality of body regions 14. The plurality of source regions 15 are spaced apart in the surface layer section of the corresponding body region 14. Each of the plurality of source regions 15 forms a channel with a MISFET structure together with the second semiconductor region 13 in the surface layer section of the corresponding body region 14.

[0158] The wafer structure 1C comprises a plurality of n-type contact regions 30, each formed in the surface layer sections of the plurality of body regions 14. The plurality of contact regions 30 are formed in a region between the plurality of adjacent source regions 15 in the surface layer section of the corresponding body region 14.

[0159] Wafer structure 1C comprises a plurality of planar electrode-type gate structures 20, which are arranged at intervals on the first surface 3. The plurality of gate structures 20 are arranged across two adjacent body regions 14 and cover the plurality of source regions 15 located in one and the other body region 14.

[0160] Each gate structure 20 has a layered structure comprising the gate insulating film 22 and the gate electrode 23. The gate insulating film 22 is arranged across the two adjacent body regions 14 and covers the plurality of source regions 15 located in each of these two body regions 14. The gate electrode 23 is arranged on the gate insulating film 22 across the two adjacent body regions 14 and covers the plurality of source regions 15 located in each of these two body regions 14, with the gate insulating film 22 between them. The gate electrode 23 faces the plurality of channels with the gate insulating film 22 between them.

[0161] Analogous to the wafer structure 1A according to the first embodiment, the wafer structure 1C comprises the insulating interlayer film 35, the gate terminal 40, the source terminal 41, the gate wiring 42, the insulating upper insulating film 45, and the drain terminal 49. In this embodiment, the source terminal 41 is electrically connected to the plurality of body regions 14, the plurality of source regions 15, and the plurality of contact regions 30 via a plurality of through-holes formed in the insulating interlayer film 35.

[0162] Fig. Figure 17 is a cross-sectional view illustrating a main section of the component structure 11 of a wafer structure 1D according to a fourth embodiment. Fig. Figure 18 is a cross-sectional view of the wafer structure 1D, which is shown in Fig. Figure 17 is shown. The wafer structure 1A described above has the transistor structure Tr as an example of the component structure 11. On the other hand, the wafer structure 1D according to the fourth embodiment has the diode structure Di as an example of the component structure 11. The first semiconductor region 12 described above is configured as a "cathode region" in this embodiment. Since the structures of the multitude of component structures 11 are similar, one component structure 11 is described below.

[0163] The wafer structure 1D comprises a p-type impurity region 70 formed in the surface layer section of the first surface 3. The impurity region 70 is formed in the surface layer section of the second semiconductor region 13. The impurity region 70 is formed in a polygonal ring shape (in this embodiment, a square ring shape) that surrounds the inner section of the component region 8 in a top view. The impurity region 70 is formed at a distance from the bottom section of the second semiconductor region 13 in the direction of the first surface 3 and is opposite the first semiconductor region 12 with a portion of the second semiconductor region 13 in between.

[0164] The wafer structure 1D comprises the insulating interlayer film 35, which selectively covers the first surface 3, as in the case of wafer structure 1A according to the first embodiment. The insulating interlayer film 35 is formed over almost the entire region of the first surface 3 and has an opening 71 to selectively expose the first surface 3. In this embodiment, the opening 71 has an opening wall surface located on the contaminant region 70 and exposes the inner boundary sections of the second semiconductor region 13 and the contaminant region 70. The opening 71 is formed in a polygonal shape (in this embodiment, a square shape) that extends along the contaminant region 70 in a top view and exposes the inner circumferential section of the contaminant region 70 over its entire perimeter.

[0165] The wafer structure 1D includes an anode terminal 72 located on the first surface 3. The anode terminal 72 is a connection electrode to which the anode potential Va is applied externally. The anode terminal 72 can be referred to as the "first connection electrode," "first pad electrode," "anode pad electrode," or the like. The anode terminal 72 is formed in a polygonal shape (in this embodiment, a quadrilateral shape) along the edge of the component region 8 in a top view.

[0166] The anode terminal 72 enters the opening 71 from above the insulating interlayer film 35 and is electrically connected to the inner edge regions of the second semiconductor region 13 and the impurity region 70. The anode terminal 72 forms a Schottky junction with the second semiconductor region 13. This creates a Schottky barrier diode structure in the component region 8, as an example of the diode structure Di. The Schottky barrier diode structure has the anode terminal 72 as the anode and the second semiconductor region 13 (first semiconductor region 12) as the cathode.

[0167] The wafer structure 1D comprises the insulating upper insulating film 45, which covers the first surface 3, as in the case of wafer structure 1A according to the first embodiment. The insulating upper insulating film 45 is formed on the insulating interlayer film 35 and covers the first surface 3 over the insulating interlayer film 35. The insulating upper insulating film 45 selectively covers the anode terminal 72 on the insulating interlayer film 35. The insulating upper insulating film 45 is preferably thicker than the anode terminal 72.

[0168] The wafer structure 1D comprises an anode opening 73 and the road opening 48, which are formed in the insulating upper insulating film 45. The anode opening 73 exposes an inner section of the anode terminal 72. The road opening 48 is formed in a grid pattern along the plurality of planned separation lines 9 and exposes the first surface 3 and / or the insulating intermediate film 35.

[0169] The wafer structure 1D includes a cathode terminal 74 formed on the second surface 4. The cathode terminal 74 is a connection electrode to which the cathode potential Vc is applied externally. The cathode terminal 74 can be referred to as the "second connection electrode," "second pad electrode," "cathode pad electrode," or the like. The cathode terminal 74 is electrically connected to the first semiconductor region 12 (first semiconductor layer 6). The cathode terminal 74 can comprise at least one layer of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film.

[0170] The maximum permissible reverse voltage (i.e., breakdown voltage) that can be applied between the anode terminal 72 and the cathode terminal 74 (between the first surface 3 and the second surface 4) can be 500 V or more and 3000 V or less. The maximum permissible drain voltage can be a value that falls within at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0171] In a case where wafer structure 1D is used, the step described above (S2) for detecting the latent defect (high-temperature reverse bias test) is performed, but the high-temperature gate bias test (S3) is not performed. In a case where wafer structure 1D is used, the semiconductor test device 51 is configured such that the reverse bias voltage VRB is applied to the diode structure Di. More precisely, the application end unit 58, with respect to the voltage application unit 54, includes an application end 61 for the anode terminal 72.

[0172] On the other hand, the voltage generation unit 55 generates a predetermined anode potential Va and a predetermined cathode potential Vc and outputs the anode potential Va and the cathode potential Vc respectively to the table terminal 59 and the connection end 61. The voltage generation unit 55 generates the reverse bias voltage VRB for the diode structure Di in step (S2) for detecting the latent defect.

[0173] More precisely, the voltage generation unit 55 generates the anode potential Va and the cathode potential Vc, which is higher than the anode potential Va, and applies the cathode potential Vc to the table unit 57 and the connection unit 58. This applies a reverse voltage VR as the reverse bias voltage VRB between the anode terminal 72 and the cathode terminal 74.

[0174] The anode potential Va can be 0 V. The reverse voltage VR is a voltage of the cathode potential Vc with the anode potential Va as a reference. In step (S2) for detecting the latent defect, a reverse current IR is generated as the leakage current IL between the anode terminal 72 and the cathode terminal 74 due to the reverse voltage VR. In step (S23) for monitoring the leakage current IL, the behavior (decrease rate) of the reverse current IR is monitored as the leakage current IL (S23). This detects an initial defect in the component structure 11 with the diode structure Di.

[0175] The reverse voltage VR can be the maximum permissible reverse or blocking voltage, or it can be less than the maximum permissible blocking voltage. The voltage ratio of the reverse voltage VR to the maximum permissible blocking voltage can be 0.5 or more and 1 or less. The voltage ratio can be a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. The voltage ratio is preferably 0.8 or more and 1 or less.

[0176] The reverse voltage VR can be 500 V or more and 3000 V or less. The reverse voltage VR can have a value that falls within at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0177] Fig. Figure 19 is a cross-sectional view showing a wafer structure 1E according to a fifth embodiment. With reference to Fig. In section 19, wafer structure 1E includes a first semiconductor region 12 of the p-type instead of the first semiconductor region 12 of the n-type. That is, wafer structure 1E exhibits an IGBT structure as an example of the transistor structure Tr.

[0178] The IGBT structure comprises a gate, an emitter, and a collector. A specific configuration of the IGBT structure is obtained by replacing "source" with "emitter" and "drain" with "collector" in the description of the embodiments described above. In the IGBT structure, a gate potential Vg is applied to the gate, an emitter potential Ve to the emitter, and a collector potential Vc to the collector. In the IGBT structure, the reverse bias voltage VRB becomes a collector bias voltage VCE, and the leakage current IL becomes a collector reverse bias current ICE.

[0179] The first p-type semiconductor region 12 can be formed by introducing a p-type impurity into the surface layer section of the second surface 4 of the n-type wafer 2 (first semiconductor layer 6) using an ion implantation process. In the case of the IGBT structure, the wafer 2 does not necessarily have to have the second semiconductor layer 7 (second semiconductor region 13).

[0180] The embodiments described above can be implemented in further embodiments. For example, in each of the embodiments described above, step (S2) for detecting the latent defect is performed by a high-temperature reverse bias step. However, step (S2) for detecting the latent defect does not necessarily have to be performed in a high-temperature environment, but can be performed in a normal-temperature environment (room temperature environment) or a low-temperature environment of 0 °C or below. That is, step (S2) for detecting the latent defect can be performed by a normal-temperature reverse bias step or a low-temperature reverse bias step.

[0181] In each of the embodiments described above, wafer 2 is used with the SiC single crystal. However, wafer 2 can also comprise a wide-bandgap semiconductor single crystal other than the SiC single crystal. For example, wafer 2 can comprise gallium nitride, gallium oxide, diamond, or the like. Naturally, wafer 2 can also comprise a silicon single crystal.

[0182] Similarly, the first semiconductor layer 6 can also comprise a wide-bandgap semiconductor single crystal other than the SiC single crystal. The first semiconductor layer 6 can comprise gallium nitride, gallium oxide, diamond, or the like. Of course, the first semiconductor layer 6 can also comprise a silicon single crystal.

[0183] Similarly, the second semiconductor layer 7 can also comprise a wide-bandgap semiconductor single crystal other than the SiC single crystal. The second semiconductor layer 7 can comprise gallium nitride, gallium oxide, diamond, or the like. Likewise, the second semiconductor layer 7 can, of course, also comprise a silicon single crystal.

[0184] In each of the embodiments described above, the wafer 2 has the recessed section as an example of the marking 5a. However, instead of the recessed section, the marking 5a can also comprise a flat section that includes a straight-extending cutout section. The flat section can be referred to as the "orientation flat". The flat section can extend along the a-axis direction or the m-axis direction.

[0185] In each of the embodiments described above, the wafer 2 with a layered structure including the first semiconductor layer 6 and the second semiconductor layer 7 was shown as an example. However, the wafer 2 does not necessarily have to have the second semiconductor layer 7 and can have a single-layer structure including the first semiconductor layer 6.

[0186] In each of the embodiments described above, an example was described in which the transistor structure Tr and the diode structure Di are formed on different wafers 2. However, the wafer structures 1A to 1E can include both the component region 8 for the transistor structure Tr and the component region 8 for the diode structure Di on the same wafer 2.

[0187] Naturally, the component structure 11 can comprise both the transistor structure Tr and the diode structure Di, which are formed in the same component region 8 on the same wafer 2. In this case, the diode structure Di can be electrically connected between the source terminal 41 as the anode terminal 72 and the drain terminal 49 as the cathode terminal 74. That is, the diode structure Di can be electrically connected to the transistor structure Tr as a freewheeling diode for the transistor structure Tr.

[0188] In each of the embodiments described above, the Schottky barrier diode structure was described as an example of the diode structure Di. However, the diode structure Di can comprise at least one of the following structures: a pn junction diode, a pin junction diode, a Zener diode, and a fast-switching diode or fast-recovery diode.

[0189] In these cases, the diode structure Di can comprise one or a plurality of p-type anode regions forming a pn junction with the first semiconductor region 12 and / or the second semiconductor region 13 in the surface layer section of the first surface 3. Furthermore, the method for fabricating the semiconductor device 10 and the semiconductor test device 51 according to each embodiment can be applied to various devices to which the reverse bias voltage VRB can be applied.

[0190] In each of the embodiments described above, a structure can be assumed in which the conduction type of the semiconductor region changes from "n-type" to "p-type" and vice versa. A specific embodiment in this case can be obtained by replacing "n-type" with "p-type" in the preceding description and the accompanying drawings, and simultaneously replacing "p-type" with "n-type".

[0191] Examples of features extracted from the present description and the accompanying drawings are given below. Alphanumeric characters and the like, enclosed in parentheses below, represent corresponding components and the like in each of the embodiments described above, but are not intended to limit the scope of protection of each clause to a single embodiment. [A1] Method for manufacturing a semiconductor device (10), including a reverse bias test (S2) for a device structure (11), wherein the method comprises: a step (S22) of applying a reverse bias voltage (VRB) to the device structure (11); and a monitoring step (S23) of monitoring a decrease rate of a leakage current (IL) of the device structure (11) at a time or time of application of the reverse bias voltage (VRB). [A2] Method for manufacturing a semiconductor device (10) according to A1, wherein the monitoring step (S23) includes a step of determining a latent defect of the device structure (11) based on the rate of decrease of the leakage current (IL). [A3] Method for manufacturing a semiconductor device (10) according to A2, wherein the monitoring step (S23) includes a step of determining the latent defect based on the decay rate, using an initial value (Iin) of the leakage current (IL) as a reference. [A4] Method for manufacturing a semiconductor device (10) according to A2 or A3, wherein the monitoring step (S23) includes a step of determining that the device structure has the latent defect in a case where the acceptance rate is 10% or more. [A5] Method for manufacturing a semiconductor component (10) according to A4, wherein the removal rate is 20% or more. [A6] Method for manufacturing a semiconductor device (10) according to any one of A1 to A5, wherein the monitoring step (S23) includes a step of monitoring the rate of decrease of the leakage current (IL) in a monitoring period (TM), with a time of starting the application of the reverse bias voltage (VRB) as a reference. [A7] Method for manufacturing a semiconductor component (10) according to A6, wherein the monitoring period (TM) is within or less than 60 minutes. [A8] Method for manufacturing a semiconductor device according to A7, wherein the monitoring period (TM) is within 30 minutes. [A9] Method for manufacturing a semiconductor device (10) according to any one of A1 to A8, wherein the reverse bias test (S2) is a high-temperature reverse bias test (S2). [A10] Method for manufacturing a semiconductor device (10) according to any one of A1 to A9, wherein the reverse bias voltage (VRB) is 500 V or more and 3000 V or less. [A11] Method for manufacturing a semiconductor device (10) according to any one of A1 to A10, wherein the reverse bias test (S2) is a wafer-level test for the device structure (11) formed on a wafer (2). [A12] Method for manufacturing a semiconductor device (10) according to A11, wherein the wafer (2) contains a SiC single crystal. [A13] Method for manufacturing a semiconductor component (10) according to any one of A1 to A12, wherein the component structure (11) includes a transistor structure (Tr). [A14] Method for manufacturing a semiconductor device (10) according to A13, further comprising a gate bias test (S3) for the transistor structure (Tr). [A15] Method for manufacturing a semiconductor device (10) according to A13, wherein a gate bias test (S3) for the transistor structure (Tr) is not performed. [A16] Method for manufacturing a semiconductor device (10) according to any one of A13 to A15, wherein the transistor structure (Tr) includes a gate (20, 40), a source (15, 41) and a drain (12, 13, 49), wherein the reverse bias voltage (VRB) is a drain bias voltage (VDS) and wherein the leakage current (IL) is a drain cutoff current (IDS). [A17] Method for manufacturing a semiconductor device (10) according to any one of A13 to A15, wherein the transistor structure (Tr) includes a gate (20, 40), an emitter (15, 41) and a collector (12, 13, 49), wherein the reverse bias voltage (VRB) is a collector bias voltage (VCE) and wherein the leakage current (IL) is a collector cutoff current (ICE). [A18] Method for manufacturing a semiconductor device (10) according to any one of A1 to A17, wherein the device structure (11) includes a diode structure (Di). [A19] Method for manufacturing a semiconductor device (10) according to A18, wherein the diode structure (Di) has an anode (72) and a cathode (12, 13, 74), wherein the reverse bias voltage (VRB) is a reverse voltage or blocking voltage (VR) and wherein the leakage current (IL) is a reverse current or blocking current (IR). [A20] Method for manufacturing a semiconductor device (10), comprising a step (S2) of monitoring a decay rate of a leakage current (IL) of a device structure (11) at a time of applying a reverse bias voltage (VRB) to the device structure (11), and a step of determining a latent defect of the device structure (11) based on the decay rate of the leakage current (IL). [B1] Semiconductor test device (51) for performing a reverse bias test (S2) on a component structure (11), wherein the semiconductor test device (51) comprises: a voltage application unit or voltage source (54) that applies a test voltage to the component structure (11); a voltage generation unit (55) that generates a reverse bias voltage (VRB) as the test voltage and outputs the reverse bias voltage to the voltage application unit (54); and a control unit (56) that monitors a rate of decrease of a leakage current (IL) of the component structure (11) at a time of application of the reverse bias voltage (VRB). [B2] Semiconductor test device (51) according to B1, wherein the control unit (56) determines the latent defect of the component structure (11) on the basis of the decrease rate of the leakage current (IL). [B3] Semiconductor test device (51) according to B2, wherein the control unit (56) determines the latent defect on the basis of the depreciation rate, with an output value (Iin) of the leakage current (IL) as a reference or reference quantity. [B4] Semiconductor test device (51) according to B2 or B3, wherein the control unit (56) determines that the component structure (11) has the latent defect in a case where the rate of decrease of the leakage current (IL) is 10% or more. [B5] Semiconductor test apparatus (51) according to B4, wherein the acceptance rate is 20% or more. [B6] Semiconductor test apparatus (51) according to any one of B1 to B5, wherein the control unit (56) monitors the rate of decrease of the leakage current (IL) of the component structure (11) in a monitoring period (TM), with a time of starting the application of the reverse bias voltage (VRB) as a reference. [B7] Semiconductor test apparatus (51) according to B6, wherein the monitoring period (TM) is within or less than or equal to 60 minutes. [B8] Semiconductor test apparatus (51) according to B7, wherein the monitoring period (TM) is within 30 minutes. [B9] Semiconductor test apparatus (51) according to any one of B1 to B8, wherein the reverse bias test (S2) is a high-temperature reverse bias test (S2). [B10] Semiconductor test apparatus (51) according to any one of B1 to B9, wherein the reverse bias voltage (VRB) is 500 V or more and 3000 V or less. [B11] Semiconductor test apparatus (51) according to any one of B1 to B10, wherein the reverse bias test (S2) is a wafer-level test for the component structure (11) formed on a wafer (2). [B12] Semiconductor test apparatus (51) according to B11, wherein the wafer (2) comprises a SiC single crystal. [B13] Semiconductor test apparatus (51) according to any one of B1 to B12, wherein the component structure (11) includes a transistor structure (Tr). [B14] Semiconductor test device (51) according to B13, wherein the transistor structure (Tr) comprises a gate (20, 40), a source (15, 41) and a drain (12, 13, 49), wherein the reverse bias voltage (VRB) is a drain bias voltage (VDS) and wherein the leakage current (IL) is a drain bias cutoff current (IDS). [B15] Semiconductor test apparatus (51) according to B14, wherein the transistor structure (Tr) has a gate structure (20) of the trench electrode type and / or a gate structure (20) of the planar electrode type. [B16] Semiconductor test apparatus (51) according to B14 or B15, wherein the transistor structure (Tr) has a source structure (25) of the trench electrode type. [B17] Semiconductor test device (51) according to B13, wherein the transistor structure (Tr) comprises a gate (20, 40), an emitter (15, 41) and a collector (12, 13, 49), wherein the reverse bias voltage (VRB) is a collector bias voltage (VCE) and wherein the leakage current (IL) is a collector cutoff current (ICE). [B18] Semiconductor test apparatus (51) according to any one of B1 to B17, wherein the component structure (11) has a diode structure (Di). [B19] Semiconductor test device (51) according to B18, wherein the diode structure (Di) has an anode (72) and a cathode (12, 13, 74), wherein the reverse bias voltage (VRB) is a reverse voltage or blocking voltage (VR) and wherein the leakage current (IL) is a reverse current or blocking current (IR). [B20] Semiconductor test device (51) for monitoring a decay rate of a leakage current (IL) of a component structure (11) at a time or time of applying a reverse bias voltage (VRB) to the component structure (11) and for determining a latent defect of the component structure (11) based on the decay rate of the leakage current (IL).

[0192] The method for manufacturing the semiconductor device (10) according to any one of [A1] to [A20] can be a manufacturing method carried out in the semiconductor test apparatus (51) according to any one of [B1] to [B20]. The semiconductor test apparatus (51) according to any one of [B1] to [B20] can be a test apparatus that carries out the method for manufacturing the semiconductor device (10) according to any one of [A1] to [A20].

[0193] The "semiconductor component" as described above may be replaced by a "SiC semiconductor component," a "wide bandgap semiconductor component," a "semiconductor switching component," a "MISFET component," an "IGBT component," a "semiconductor rectifying component," or the like, as required. The "semiconductor test device" as described above may be replaced by a "semiconductor test device," a "wide bandgap semiconductor test device," a "transistor test device," a "MISFET test device," an "IGBT test device," a "diode test device," or the like, as required.

[0194] Although specific embodiments have been described in detail above, these are merely specific examples used to illustrate the technical content. The various technical ideas that can be extracted from this specification can be combined as appropriate without being restricted by the order of the descriptions, configuration examples, modification examples, etc., presented in this specification. Reference symbol list 1A Wafer structure 1B Wafer structure 1C wafer structure 1D wafer structure 1E Wafer structure 2 wafers 10 Semiconductor component 11 Component structure 12 first semiconductor region 13 second semiconductor region 15 Source Region 20-gate structure 25 Source structure 40 Gate Terminal 41 Source Terminal 49 Drain terminal 51 Semiconductor test device 54 Voltage application unit or voltage source 55 Voltage generation unit 56 Control unit 72 Anode terminal 74 Cathode terminal Tr transistor structure VRB Reverse Bias Voltage IL Leakage current Initial value of the leakage current VDS Drain Bias Voltage IDS drain-cutoff current VCE Collector Bias Voltage ICE collector cutoff current Di diode structure VR Reverse voltage or blocking voltage IR reverse current or blocking current TM Monitoring period S2 step to detect a latent defect S22 Application step S23 Monitoring Step QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-056214

[0001] US 2018 / 0151719 A1 [0002, 0003]

Claims

[1] Method for manufacturing a semiconductor device, including a reverse bias test for a device structure, wherein the method comprises: a step of applying a reverse bias stress to the component structure; and a monitoring step to monitor a decrease rate of a leakage current of the component structure at a time when the reverse bias voltage is applied. [2] Method for manufacturing a semiconductor component according to claim 1, wherein the monitoring step includes a step of determining a latent defect of the component structure based on the decrease rate of the leakage current. [3] Method for manufacturing a semiconductor device according to claim 2, wherein the monitoring step includes a step of determining the latent defect based on the decay rate, wherein an initial value of the leakage current is used as a reference. [4] Method for manufacturing a semiconductor component according to claim 2 or claim 3, wherein the monitoring step includes a step of determining that the component structure has the latent defect, in a case where the acceptance rate is 10% or more. [5] Method for manufacturing a semiconductor component according to claim 4, wherein the removal rate is 20% or more. [6] Method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the monitoring step includes a step of monitoring the rate of decrease of the leakage current in a monitoring period, with a time of starting the application of the reverse bias voltage as a reference. [7] Method for manufacturing a semiconductor component according to claim 6, wherein the monitoring period is within 60 minutes. [8] Method for manufacturing a semiconductor component according to claim 7, wherein the monitoring period is within 30 minutes. [9] Method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the reverse bias test is a high-temperature reverse bias test. [10] Method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the reverse bias voltage is 500 V or more and 3000 V or less. [11] Method for manufacturing a semiconductor component according to any one of claims 1 to 10, wherein the reverse bias test is a wafer-level test for the component structure formed on a wafer. [12] Method for manufacturing a semiconductor device according to claim 11, wherein the wafer contains a SiC single crystal. [13] Method for manufacturing a semiconductor component according to any one of claims 1 to 12, wherein the component structure includes a transistor structure. [14] Method for manufacturing a semiconductor component according to claim 13, further comprising a gate bias test for the transistor structure. [15] Method for manufacturing a semiconductor component according to claim 13, wherein a gate bias test for the transistor structure is not performed. [16] Method for manufacturing a semiconductor component according to any one of claims 13 to 15, the transistor structure includes a gate, a source and a drain, where the reverse bias voltage is a drain bias voltage and where the leakage current is a drain-cutoff current. [17] Method for manufacturing a semiconductor component according to any one of claims 13 to 15, the transistor structure includes a gate, an emitter and a collector, where the reverse bias voltage is a collector bias voltage and where the leakage current is a collector cutoff current. [18] Method for manufacturing a semiconductor component according to any one of claims 1 to 17, wherein the component structure includes a diode structure. [19] Method for manufacturing a semiconductor component according to claim 18, wherein the diode structure has an anode and a cathode, where the reverse bias voltage is a reverse voltage and where the leakage current is a reverse current. [20] Semiconductor test apparatus for performing a reverse bias test on a component structure, wherein the semiconductor test apparatus comprises: a voltage application unit that applies a test voltage to the component structure; a voltage generation unit that generates a reverse bias voltage as the test voltage and outputs the reverse bias voltage to the voltage application unit; and a control unit that monitors the rate of decrease of a leakage current of the component structure at the time of application of the reverse bias voltage.

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