STORAGE DEVICE WITH A TRANSISTOR ABOVE VERTICALLY STACKED STORAGE CELLS

Abstract

The implementations described here refer to various structures, integrated arrangements, and storage devices. In some implementations, a storage device may include a memory array containing multiple stacks of vertically stacked memory cells. The storage device may include a transistor positioned above one of the multiple stacks of vertically stacked memory cells. The transistor may include a channel positioned above the stack of vertically stacked memory cells, a first source / drain region on a first section of the channel, a second source / drain region on a second section of the channel, a gate having a top surface lower than the top surface of the first source / drain region and lower than the top surface of the second source / drain region, and a gate dielectric separating the gate from the channel.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This patent application claims priority over U.S. Preliminary Patent Application No. 63 / 502,733, filed on May 17, 2023, entitled “STORAGE DEVICE WITH A TRANSISTOR ABOVE VERTICALLY STACKED STORAGE CELLS”, and U.S. Non-Preliminary Patent Application No. 18 / 658,235, filed on May 8, 2024, entitled “STORAGE DEVICE WITH A TRANSISTOR ABOVE VERTICALLY STACKED STORAGE CELLS”, which are hereby expressly incorporated by reference herein. TECHNICAL AREA

[0002] The present disclosure relates generally to semiconductor devices and methods for forming semiconductor devices. For example, the present disclosure relates to a memory device with a transistor above vertically stacked memory cells. BACKGROUND

[0003] Storage devices are commonly used in various electronic devices to store information. A storage device includes memory cells. A memory cell is an electronic circuit capable of being programmed to a data state of two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value, often denoted by a binary "1" or a binary "0". As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, the electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read or capture the stored state from the memory cells.

[0004] There are various types of memory devices, including random access memory (RAM), solid-state memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory (e.g., NAND flash memory and NOR flash memory), and others. A memory device can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can retain data for extended periods even without an external power source. Volatile memory (e.g., DRAM) can lose stored data over time if it is not refreshed by a power source. A binary memory device might, for example, include a charged or discharged capacitor.Some properties of volatile memory can offer advantages, such as faster read or write speeds, while some properties of non-volatile memory, such as the ability to store data without regular refreshing, can be beneficial. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic cross-sectional view of an example structure, which includes a transistor above vertically stacked memory cells. Fig. Figure 2 shows schematic cross-sectional views of the example structure of Fig. 1 along the in Fig. Line AA shown in 1. Fig. Figure 3 is a flowchart of an example procedure for forming an integrated assembly or storage device that includes a transistor above vertically stacked memory cells. Fig. Figure 4 is a schematic view of a first example process for forming the structure. Fig. Figure 5 is a schematic view of a second example process for forming the structure. DETAILED DESCRIPTION

[0005] Three-dimensional (3D) memory, such as 3D DRAM, is a type of memory organized into a stack of memory cells arranged in a 3D grid. In 3D DRAM, for example, each memory cell includes a storage capacitor and a transistor that acts as a switch, allowing a memory cell to store a data state (e.g., a 1 or a 0). In 3D memory, a storage device comprises multiple memory stacks (or columns), and each stack comprises a group of memory cells stacked vertically on top of each other. A particular memory cell in a stack can be connected (e.g., via a local digit line and / or a disk line) to a memory cell above it in the stack and / or to a memory cell below it in the stack.

[0006] All memory cells in a given stack can be connected to a local digit line, which can extend vertically through the stack. The local digit line can be used to transfer data to or from the memory cells in that particular stack. The local digit lines of multiple stacks can all be connected to the same common digit line. Each common digit line of the storage device can be connected to a different group of stacks (via a corresponding group of local digit lines) and to a different input / output (I / O) component (such as a read amplifier). An I / O component connected to a particular common digit line can be used to read data from or write data to memory cells in the stacks connected to that particular common digit line.

[0007] A general digit line can be selectively connected to a local digit line via a selection component, such as a transistor (sometimes referred to herein as a "stack selection transistor"), which is located on top of a stack of vertically stacked memory cells connected to the local digit line. For example, when a transistor (or other type of selection component) is enabled via a control gate, current can flow through the transistor, and the local digit line can be electrically connected to the general digit line. When the transistor is disabled via the control gate, no current flows through the transistor, and the local digit line is electrically isolated from the general digit line.By activating or deactivating different transistors, the storage device can control which stacks of memory cells are read from and which are written to (in addition to using access lines, also called word lines, from memory cells).

[0008] Fabricating a transistor positioned above a stack of vertically stacked memory cells presents several challenges. For example, heat is applied to dopants within the transistor (e.g., in a channel region and / or a source / drain region of the transistor) to activate these dopants and impart desired electrical properties to the transistor. If the transistor is fabricated after the memory array has been fabricated, and heat (e.g., using a laser) is applied to the transistor to activate the dopants, the memory array can be compromised due to thermal stress (e.g., physical damage and / or degradation of memory cells), dopant diffusion (e.g., to or from memory cells), interface defects, and / or oxidation.One possibility is to apply a low temperature for dopant activation to reduce the degradation of the memory arrangement, but this results in a lower quality transistor that has a gate dielectric formed using a low temperature, leading to more defects in the gate dielectric and more electron loss than if the gate dielectric had been formed at a high temperature.

[0009] The implementations described herein improve three-dimensional memory by activating dopants used in the transistor and / or by forming the transistor (or at least a portion of the transistor incorporating the activated dopants) before forming the memory array. As a result, the memory array is of higher quality (e.g., with less degradation of the memory cells) than if the memory array were formed before the transistor dopants were activated and then exposed to the heat used to activate these dopants. Furthermore, if the transistor is formed and / or dopants are activated before the memory array is formed, a higher temperature can be used for dopant activation without risk of damaging the memory cells, resulting in a higher-quality transistor (e.g., with less degradation of the memory cells).a higher quality gate dielectric with lower electron loss) is preferable to using a lower temperature for dopant activation. Furthermore, a less expensive and / or less precise heat treatment process, such as thermal annealing, can be used and applied to the entire structure, instead of using a laser to apply heat to a focused area of ​​the structure (e.g., the transistor), thereby avoiding other areas of the structure (e.g., the memory array).

[0010] The implementations described herein also address challenges introduced by activating dopants used in the transistor and / or by forming the transistor (or at least a portion of the transistor including activated dopants) prior to forming the memory array. For example, a transistor located on top of a stack of vertically stacked memory cells would typically, for reasons of simple design, fabrication, or otherwise, have a gate extending above a top surface of the transistor (e.g., above source / drain regions of the transistor), resulting in a non-uniform device topography. Such a non-uniform or non-standardized device topography complicates the precise formation (e.g., deposition or growth) and removal (e.g., etching) of material to form the memory array after transistor formation.The implementations described herein enable the formation of the transistor (or part of the transistor) and the activation of transistor dopants prior to the formation of the memory arrangement, while the transistor is also fabricated with a substantially planar (e.g., flat) top surface and a substantially uniform topography to enable precise formation of the memory arrangement.

[0011] Fig. Figure 1 shows a schematic cross-sectional view of an example structure 100. The structure 100 can be part of an integrated assembly, such as a memory arrangement, part of a memory arrangement, or a memory device, which includes the memory arrangement and one or more other components (e.g., read amplifiers, a row decoder, a column decoder, a row address buffer, a column address buffer, one or more data buffers, one or more clock generators, one or more counters, and / or a memory controller).

[0012] As in Fig. As shown in Figure 1, the structure 100 includes a memory assembly 102, a stack selector transistor 104, and a local digit line 106. The memory assembly 102 includes several stacks 108 of vertically stacked memory cells 110, which are arranged in Fig. 1 are represented by a single stack 108. All of the memory cells 110 in a single stack 108 can be connected to the same local digit line 106. Furthermore, each stack 108 can have a corresponding local digit line 106 to which memory cells 110 in that stack are connected. A group of local digit lines 106 can be connected to the same general digit line (not in Fig. 1 shown) connected (e.g. selectively connected), as described in more detail elsewhere herein.

[0013] As shown, a memory cell 110 can enclose an access component 112 (e.g., an access transistor) which is connected to a memory component 114 (e.g., a capacitor). The access component 112 can control access to the memory component 114 for reading or writing data via the local digital line 106. The memory cells 110 can be separated from each other by an insulating material 116, such as a dielectric material. In some implementations, one or more memory cells 110 at the top of the stack 108 can be inactive memory cells, sometimes referred to as "dummy" memory cells (e.g., the access component 112 may not be connected to the memory component 114), to prevent parasitic electrical effects between this / these memory cell(s) and the stack selector transistor 104. The number of dummy memory cells at the top of the stack 108 can vary.In some implementations, however, memory cells 110 at the top of stack 108 are not dummy memory cells (they are, for example, functional memory cells).

[0014] In some implementations, an insulating separator layer is located between the underside of the stack selection transistor 104 and the top side of the memory arrangement 102 (or the stack 108), different from or in addition to the one described in Fig. The insulating material 116 shown in Figure 1 is used. The insulating layer can, among other examples, consist of or be substantially composed of an electrical insulator (e.g., a dielectric material), such as silicon dioxide and / or silicon nitride. In some implementations, the insulating layer has a height i along the z-axis shown, ranging from about 1 nanometer to about 30 nanometers, in order to enable desired electrical properties of the stack-select transistor 104, for example, to prevent parasitic electrical effects between the memory arrangement 102 and the stack-select transistor 104.

[0015] The stack selector transistor 104 can include a channel 118, a first source / drain region 120, a second source / drain region 122, a gate 124, and a gate dielectric 126. The stack selector transistor 104 can be separated from one or more electrical lines, such as the local digit line 106 and / or a disk line (not shown), which are connected to the memory components 114 in the stack 108, by one or more isolation regions 128, which can include insulating material (e.g., dielectric material).

[0016] As shown, the stack selection transistor 104 can be positioned above the stack 108 of vertically stacked memory cells 110. For example, the channel 118 can be located above and / or in contact with the stack 108, such as with the insulating material 116 of the stack 108. The insulating material 116 can separate the channel 118 from a memory cell 110, which in some implementations may be an inactive memory cell. Additionally or alternatively, the distance between the channel 118 and the stack 108 can be smaller than the distance between the first source / drain region 120 and the stack 108, the distance between the second source / drain region 122 and the stack 108, the distance between the gate 124 and the stack 108, and the distance between the gate dielectric 126 and the stack 108.

[0017] As shown, the first source / drain area 120 can be located on top of a first section (e.g., a first side) of channel 118. Similarly, the second source / drain area 122 can be located on top of a second section (e.g., a second side) of channel 118. As shown, the first source / drain area 120 and / or the second source / drain area 122 can abut channel 118 (e.g., be in contact with it).

[0018] The gate 124 and the gate dielectric 126 can be positioned above a third section (e.g., a middle one) of the channel 118, located between the first and second sections. As shown, the gate dielectric 126 can separate the gate 124 from the channel 118. For example, the gate dielectric 126 can be located on top of the channel 118 and abut it (e.g., be in contact with it). The gate 124 can also abut it (e.g., be in contact with it). In some implementations, the top of the first section of the channel 118 and the top of the second section of the channel 118 are at substantially the same height. In some implementations, the top of the first section of the channel 118 and the top of the second section of the channel 118 are higher than the top of the third section of the channel 118.

[0019] In some implementations, the top surface 130 of gate 124 is no higher than the top surface 132 of the first source / drain region 120. For example, the top surface 130 of gate 124 may be essentially at the same level as the top surface 132 of the first source / drain region 120, or it may be lower. Similarly, in some implementations, the top surface 130 of gate 124 is no higher than the top surface 134 of the second source / drain region 122. For example, the top surface 130 of gate 124 may be essentially at the same level as the top surface 134 of the second source / drain region 122, or it may be lower. As a result, the stack select transistor 104 can be formed with a flat top surface and / or essentially flat topography (e.g.,instead of having a gate 124 that protrudes beyond the source / drain regions, this makes it easier to accurately form and remove material for the formation of the memory arrangement 102 after the formation of the stack select transistor 104 (or a section of the stack select transistor 104). Additionally or alternatively, the top surface 130 of the gate 124 can be substantially planar (e.g., essentially flat), which also contributes to a substantially uniform topography. In some implementations, the top surface 130 of the gate 124 can be lower than the top surface 132 of the first source / drain region 120 and / or lower than the top surface 134 of the second source / drain region 122. This configuration allows larger electrical contacts (e.g.,a first electrical contact 144 and / or a second electrical contact 146 (described below) are formed without these electrical contacts being in contact with or short-circuited to the gate 124, compared with a configuration in which the top surface 130 of the gate 124 is substantially flush with or above the top surface 132 of the first source / drain region 120 and / or the top surface 134 of the second source / drain region 122.

[0020] In some implementations, a dielectric material 136 is located on top of the gate 124 in a region between the first source / drain region 120 and the second source / drain region 122. The dielectric material 136 can separate the gate 124 from other electrical components that can be formed on the illustrated structure 100. In some implementations, the surface of the dielectric material 136 can be essentially planar (e.g., essentially flat), which contributes to an essentially uniform topography.

[0021] In Fig. 1. The top surface 130 of gate 124 is lower than the top surface 132 of the first source / drain area 120 and is higher than the bottom surface of the first source / drain area 120. Furthermore, in Fig. 1. The top surface 130 of gate 124 is lower than the top surface 134 of the second source / drain region 122 and higher than the bottom surface of the second source / drain region 122. However, in some implementations, the top surface 130 of gate 124 is lower than the bottom surface 138 of the first source / drain region 120. Similarly, in some implementations, the top surface 130 of gate 124 is lower than the bottom surface 140 of the second source / drain region 122.

[0022] In some implementations, a top surface of the gate dielectric 126 is essentially at the same level as (e.g., essentially horizontally aligned with) the top surface 130 of the gate 124. Thus, all relationships described herein between the top surface 130 of the gate 124 and other components of the structure 100 can also apply to the top surface of the gate dielectric 126.

[0023] In some implementations, the gate 124 and / or the gate dielectric 126, as shown by reference numeral 142, may have rounded lower corners (rather than right-angled corners) due to the way the gate 124 and / or the gate dielectric 126 are formed (e.g., by forming a trench and then filling the trench), as described in more detail elsewhere herein. In other words, an area where the bottom surface of the gate 124 (or the gate dielectric 126) intersects a side surface of the gate 124 (or the gate dielectric 126) may form an arc or curve rather than a ninety-degree intersection. This can reduce the electric field present at the corners, which helps to preserve the gate dielectric 126, in contrast to sharp corners which have a higher electric field and would be more likely to cause a breakdown of the gate dielectric 126.

[0024] Gate 124 can be part of an access line (sometimes called a word line) used to selectively connect a group (e.g., a row) of local digit lines to corresponding general digit lines. The access line can pass through structure 100 in one direction, essentially perpendicular to the z-axis and y-axis shown (e.g., along the line shown in the diagram). Fig. (2 shown x-axis). The access line can be positioned above several stacks 108 of vertically stacked memory cells 110. A memory device can be configured to apply or remove a voltage to the access line to enable or disable gates 124 of stack select transistors 104 located above these stacks 108. Enabling a gate 124 electrically connects a local digit line 106 to a general digit line, and disabling the gate 124 electrically isolates the local digit line 106 from the general digit line. Thus, the stack select transistor 104 can be configured to selectively connect the local digit line 106, which is electrically connected to the stack 108 of vertically stacked memory cells 110, to a general digit line of the memory device.As used herein, electrical connection of the local digit line 106 with the stack 108 means an electrical connection of the local digit line 106 with the memory cells 110 in the stack 108.

[0025] In some implementations, the access line has a single, essentially flat bottom surface. In other words, the access line may have a single bottom surface (e.g., including the bottom of gate 124) that is essentially flat. Alternatively, the access line may have a bottom surface that is flatter between the first source / drain region 120 and the second source / drain region 122 (e.g., at the bottom of gate 124) and deeper in a region not located between the first source / drain region 120 and the second source / drain region 122. An essentially flat bottom surface may be easier to fabricate, while a bottom surface that alternates between flat and deep areas (thus forming a saddle shape over channel 118) may exhibit better electrical properties (e.g., by mitigating parasitic electrical effects from the memory arrangement 102).Additional details will be provided in connection with . Fig. 2 described.

[0026] As in Fig. As further shown in Figure 1, the structure 100 can include one or more electrical contacts, shown as a first electrical contact 144 and a second electrical contact 146. For example, the first electrical contact 144 can be located on top of and / or in contact with the first source / drain region 120, and the second electrical contact 146 can be located on top of and / or in contact with the second source / drain region 122. One of the electrical contacts (e.g., the first electrical contact 144) can be connected to the local digit line 106, and the other electrical contact (e.g., the second electrical contact 146) can be connected to the general digit line. In this way, the stack selector transistor 104 selectively connects the local digit line 106 and the general digit line.In some implementations, a dielectric layer 148 can be located on top of the first source / drain region 120 and / or the second source / drain region 122. The first electrical contact 144 and the second electrical contact 146 can extend through the dielectric layer 148 to contact the first source / drain region 120 and the second source / drain region 122, respectively.

[0027] The local digit line 106, the gate 124, the first electrical contact 144, and / or the second electrical contact 146 may be an electrical conductor and may include, consist of, or substantially consist of conductive material, such as a metal (e.g., titanium, tungsten, cobalt, nickel, platinum, and / or ruthenium), a metal composition (e.g., a metal silicide, a metal carbide, and / or a metal nitride, such as titanium nitride or titanium silicon nitride), and / or a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, and / or conductively doped gallium arsenide), among other examples.

[0028] The insulating material 116, the gate dielectric 126, the insulating area 128, the dielectric material 136, and / or the dielectric layer 148 may be an electrical insulator (e.g., a dielectric material capable of being polarized by an applied electric field, such as by dielectric polarization) and may comprise, consist of, or essentially consist of insulating material and / or dielectric material, such as silicon dioxide and / or silicon nitride, among other examples.

[0029] Channel 118 can be a semiconductor and may comprise, consist of, or consist substantially of semiconducting material such as silicon (e.g., polycrystalline silicon). In some implementations, channel 118 may comprise, consist of, or consist substantially of undoped semiconductor material. Alternatively, channel 118 may be lightly doped using n-type doping. However, the first source / drain region 120 and / or the second source / drain region 122 may be more heavily doped (e.g., with more electron donor atoms) than channel 118.

[0030] The first source / drain region 120 and / or the second source / drain region 122 (collectively referred to as the “source / drain regions”) can be doped semiconductors and can include, consist of, or consist substantially of doped semiconductor material, such as n-doped semiconductor material. The source / drain regions can be n-doped by incorporating a chemical element or compound that includes electron donor atoms (e.g., phosphorus and / or arsenic) into the semiconductor material (e.g., silicon). In some transformations, the source / drain regions can be heavily doped. Additionally or alternatively, one or more of the source / drain regions can include, consist of, or consist substantially of conductive material other than doped semiconductor material. For example, one or more of the source / drain regions can be a metal silicide (e.g.,titanium silicide and / or tungsten silicide) and / or other conductive material (e.g. titanium and / or tungsten), consist of, or are substantially composed of.

[0031] In some implementations, doping activation for channel 118 (if channel 118 is doped), the first source / drain region 120, and / or the second source / drain region 122 can be performed prior to the formation of the storage assembly 102. For example, channel 118, the first source / drain region 120, and / or the second source / drain region 122 can be doped using in-situ doping or ion implantation, and heat (e.g., by thermal annealing) can be applied to the structure 100 to activate the dopants in channel 118, the first source / drain region 120, and / or the second source / drain region 122. The storage assembly 102 can then be formed after the application of heat to activate the dopants. Further details will be provided in connection with Fig. 4 and Fig. 5 described.

[0032] Since heat is applied to the structure 100 for dopant activation prior to the formation of the memory assembly 102, a higher temperature can be used for dopant activation than would otherwise be possible if the memory assembly 102 were formed before dopant activation. For example, if the memory assembly 102 were formed before dopant activation, a lower temperature could be used for dopant activation to prevent or reduce degradation of the memory assembly 102. Using a higher temperature for dopant activation can lead to fewer defects in the stack selection transistor 104, resulting in less leakage from the gate 124 to the channel 118 through the gate dielectric 126.In some implementations, the channel 118, the first source / drain region 120 and / or the second source / drain region 122 can have a substantially uniform distribution of dopants (which improves the function and reliability of the storage device) because in-situ doping and dopant activation takes place prior to the formation of the storage arrangement 102.

[0033] Although the stack selector transistor 104 is described in the context of a storage device, it can be used in other contexts in some implementations. For example, the stack selector transistor 104 can be used in any electronic system that includes multiple stacks of vertically stacked electronic components (of which memory cells 110 are an example) and for which access to these stacks is to be controlled using stack selector transistors 104. In this case, a separate stack selector transistor 104 can be positioned above each stack of vertically stacked electronic components to control access to that stack.

[0034] In some implementations, channel 118 has a height along the z-axis shown, ranging from approximately 10 nanometers to approximately 300 nanometers, to enable desired electrical properties of the stack selection transistor 104. In some implementations, the distance between the first source / drain region 120 and the second source / drain region 122, along the y-axis shown, ranges from approximately 50 nanometers to approximately 200 nanometers, to enable desired electrical properties of the stack selection transistor 104. In some implementations, the first source / drain region 120 and / or the second source / drain region 122 have a height along the z-axis shown, ranging from approximately 10 nanometers to approximately 50 nanometers, to enable desired electrical properties of the stack selection transistor 104.In some implementations, the gate 124 has a height, along the z-axis shown, in a range of about 25 nanometers to about 130 nanometers to enable desired electrical properties of the stack selection transistor 104.

[0035] Each of the depicted or described x-axis, y-axis, and z-axis is essentially perpendicular to the other two axes. In other words, the x-axis is essentially perpendicular to the y-axis and the z-axis, the y-axis is essentially perpendicular to the x-axis and the z-axis, and the z-axis is essentially perpendicular to the x-axis and the y-axis.

[0036] The structure 100 can be part of an integrated assembly, such as a storage device or part of a storage device. The storage device can include a large number of structures 100 and / or memory cells (e.g., hundreds, thousands, millions, or more) that are substantially identical. The structures 100 and / or memory cells can be arranged along the x-axis shown in Figure 1. Fig. 2) and extend the y-axis shown across the storage arrangement to form a three-dimensional grid.

[0037] As stated above, Fig. 1 is provided as an example. Other examples may differ from the one relating to Fig. 1. Distinguish between those described.

[0038] Fig. Figure 2 shows schematic cross-sectional views 200 and 202 of the example structure 100 along the in Fig. Line AA shown in 1. The cross-sectional views in Fig. Figure 2 shows several channels 118 (of several corresponding stack selection transistors 104), several gates 124 (of several corresponding stack selection transistors 104) along an access line 204, the gate dielectric 126, the dielectric material 136 and several dielectric areas 206.

[0039] As in Fig. As shown in Figure 2, the access line 204 (e.g., a material of the gate 124), the gate dielectric 126, and the dielectric material 136 can extend along the x-axis shown through the structure 100 (e.g., across multiple stacks 108), while the channels 118 and the dielectric regions 206 are arranged alternately along the x-axis shown. For example, each channel 118 can be located above a corresponding stack 108, and a dielectric region 206 can separate channels 118 that are consecutive (e.g., adjacent but not in contact with each other) to provide electrical isolation. The dielectric region 206 can be an electrical insulator (e.g.,a dielectric material capable of being polarized by an applied electric field, such as by dielectric polarization) and may, among other examples, include, consist of, or essentially consist of insulating material and / or dielectric material, such as silicon dioxide and / or silicon nitride.

[0040] In the first cross-sectional view 200, the access line 204 has a single, essentially flat, underside. In other words, the access line 204 has a single underside (e.g., including the undersides of the gates 124) that is essentially flat. This can reduce manufacturing costs (e.g., compared to the structure 100 shown in the second cross-sectional view 202). In some implementations of this configuration, the gate 124 has a height in the range of approximately 25 nanometers to approximately 100 nanometers along the depicted z-axis to enable desired electrical properties of the stack selection transistor 104.

[0041] In the second cross-sectional view 202, the access line 204 has a base surface located above the channel 118 (e.g., between the first source / drain area 120 and the second source / drain area 122, which is in Fig. 1 shown) is flatter and is located in an area not above channel 118 (e.g., an area between successive channels 118, and / or an area not between the first source / drain area 120 and the second source / drain area 122, which are shown in Fig. (as shown in Figure 1), is deeper. This can enable better electrical operation of the stack selection transistors 104 (e.g., compared to the structure 100 shown in the first cross-sectional view 200). In some implementations of this configuration, the gate 124, along the z-axis shown and in the flat region above channel 118, has a height of approximately 25 nanometers to approximately 100 nanometers to enable desired electrical properties of the stack selection transistor 104. In some implementations of this configuration, the gate 124, along the z-axis shown and in the deeper region not located above channel 118, has a height of approximately 30 nanometers to approximately 130 nanometers to enable desired electrical properties of the stack selection transistor 104.

[0042] As stated above, Fig. 2 is provided as an example. Other examples may differ from the one relating to Fig. Distinguish between the two described.

[0043] Fig. Figure 3 is a flowchart of an example procedure 300 for forming an integrated assembly or a memory device that includes a transistor above vertically stacked memory cells. In some implementations, one or more process blocks of Fig. 3 different semiconductor manufacturing facilities.

[0044] As in Fig. As shown in Figure 3, the process 300 can include the formation of a silicon layer on a base layer (Block 310). As shown in Fig. As further shown in Figure 3, the process 300 can include the formation of a doped layer on the silicon layer (Block 320). As shown in Fig. As further shown in Figure 3, the procedure 300 can include the activation of dopants in the doped layer (block 330). As shown in Fig. As further shown in Figure 3, the method 300 can include forming a memory arrangement consisting of several stacks of vertically stacked memory cells (block 340). As shown in Fig. As further shown in Figure 3, the method 300 can include forming several transistors positioned above the memory arrangement, with each transistor being positioned above a respective stack of vertically stacked memory cells of the multiple stacks of vertically stacked memory cells (block 350).

[0045] Procedure 300 may include additional aspects, such as any single aspect or any combination of the aspects described below and / or in conjunction with one or more other procedures described elsewhere in this document.

[0046] In a first aspect, the transistor includes a channel located on top of the respective stack of vertically stacked memory cells, a first source / drain region on top of a first section of the channel, a second source / drain region on top of a second section of the channel, a gate with a top surface that is lower than the top surface of the first source / drain region and lower than the top surface of the second source / drain region, and a gate dielectric that separates the gate from the channel.

[0047] In a second aspect, alone or in combination with the first aspect, the memory arrangement and the multiple transistors are formed after the activation of the dopants of the doped layer.

[0048] In a third aspect, alone or in combination with one or more of the first and second aspects, the multiple transistors are formed before the memory arrangement is formed.

[0049] In a fourth aspect, alone or in combination with one or more of the first and second aspects, the multiple transistors are formed after the memory arrangement has been formed.

[0050] In a fifth aspect, alone or in combination with one or more of the first to fourth aspects, the procedure 300 includes forming the gate as part of an access line with a single underside that is essentially flat.

[0051] In a sixth aspect, alone or in combination with one or more of the first to fourth aspects, the method 300 includes forming the gate as part of an access line with a sole surface that is shallower between the first source / drain area and the second source / drain area and that is deeper in an area not located between the first source / drain area and the second source / drain area.

[0052] In a seventh aspect, alone or in combination with one or more of the first to sixth aspects, the method 300 includes forming a local digit line electrically connected to the respective stack of vertically stacked memory cells, forming a general digit line, connecting the local digit line and the first source / drain area, and connecting the general digit line and the second source / drain area.

[0053] Although Fig. Three example blocks of procedure 300 show that in some implementations, procedure 300 can have additional, fewer, different, or differently arranged blocks than those shown. Fig. 3 include the elements shown. In some implementations, the method 300 may include forming the structure 100, an integrated assembly including the structure 100, any part of the structure 100 described herein, and / or any part of an integrated assembly including the structure 100 described herein.

[0054] Fig. Figure 4 is a schematic view of a first example process 400 for forming structure 100. As in Fig. As shown in Figure 4, process 400 can include the formation (e.g., deposition or growth) of a base layer 402. In some reactions, the base layer 402 is formed on a substrate. Alternatively, the base layer 402 can be a substrate. In the example process 400 of Fig. 4 The base layer includes one or more dummy memory cells 110 and insulating material 116.

[0055] As further shown, process 400 can include the formation of a silicon layer 404 on the base layer 402. The silicon layer 404 can be undoped or can be weakly doped (e.g., with boron), as described above in connection with channel 118, and can eventually (e.g., after process 400 has been carried out) form channel 118. As further shown, process 400 can include the formation of the dielectric layer 148 on the silicon layer 404.

[0056] As further shown, process 400 can include the formation of a doped layer 406 on the silicon layer 404. In some implementations, the doped layer 406 can be formed by ion implantation in a section of the silicon layer 404, as shown in Fig. Figure 4 shows that, alternatively, the doped layer 406 can be formed using in-situ doping, such that the doped layer 406 is doped when the material of the doped layer 406 is formed (e.g., grown or deposited). In this case, process 400 can include the formation of the dielectric layer 148 on top of the doped layer 406.

[0057] The doped layer 406 can ultimately form the first source / drain region 120 and the second source / drain region 122 (e.g., after process 400 has been carried out) and can replace any of the materials of the first source / drain region 120 and the second source / drain region mentioned above in conjunction with Fig. The processes described in Section 1 include, consist of, or are essentially composed of. Process 400 may include the activation of dopants (e.g., n-dopants) of the doped layer 406. For example, heat may be applied to activate the dopants, such as by thermal annealing (e.g., rapid thermal annealing). In particular, the doping activation is performed prior to the formation of the storage arrangement 102.

[0058] As further shown, process 400 can include the formation of a mask 408 (e.g., a hard mask) on top of the dielectric layer 148. After the mask 408 is formed, process 400 can include the formation of a stack 108 of the memory arrangement 102 below the base layer 402. Although Fig. 4 shows the formation of a single stack 108 and structures on top of this single stack 108. Process 400 can include the formation of a structure comprising several stacks 108 (which extend, for example, in the v-direction along the cross-section shown and along the Fig. The multiple stacks 108 can form an entire storage arrangement 102. Thus, the storage arrangement 102 can be formed after activation of the dopants of the doped layer 406 (and / or after activation of the dopants of the channel 118), which has advantages that are described elsewhere herein.

[0059] As further shown, process 400 can involve the removal (e.g., etching) of a section of the dielectric layer 148, a section of the doped layer 406, and a section of the silicon layer 404 (e.g., material of channel 118) to form a trench 410. The trench 410 can be formed completely through the dielectric layer 148 and through the doped layer 406, forming the first source / drain region 120 and the second source / drain region 122. The trench 410 can be partially formed through the silicon layer 404 to form the channel 118 with the shape shown, wherein a top surface of a first section of the channel 118 (e.g. below the first source / drain region 120) and a top surface of a second section of the channel 118 (e.g. below the second source / drain region 122) is higher than a top surface of a third section of the channel 118 (e.g.between the first source / drain region 120 and the second source / drain region 122). In some implementations, one or more masks can be used to form the trench 410. For example, one or more masks (e.g., mask 408) can be deposited and / or structured on the dielectric layer 148 prior to the removal of material to form the trench 410. The one or more masks can then be removed.

[0060] As further shown, process 400 can include the formation of the gate dielectric 126 in the trench 410, such that the gate dielectric 126 is formed on the channel 118 between the first source / drain region 120 and the second source / drain region 122 (and in contact with the first source / drain region 120 and the second source / drain region 122). The gate dielectric 126 can be formed with a substantially flat bottom surface adjacent to several channels 118 and several dielectric regions 206 (with one dielectric region 206 being located between two channels 118), as shown above in connection with the first cross-sectional view 200 in Figure 1. Fig. 2 described. Alternatively, the gate dielectric 126 can have a bottom surface that is flatter above the channels 118 and deeper between the channels 118 (e.g., above the dielectric regions 206), as described above in connection with the second cross-sectional view 202 in Fig. 2 described. In this case, dielectric material of the dielectric regions 206 can be removed before the formation of the gate dielectric 126 (e.g. to a greater depth than the channel 118).

[0061] As further shown, process 400 can include forming the gate 124 in the trench 410 on the gate dielectric 126. In some implementations, process 400 can include planarizing the top surface of the gate 124, for example, by using chemical-mechanical polishing or another suitable planarizing technique. This can result in a gate 124 having an essentially flat, planar, or planar top surface for a more uniform topography.

[0062] As further shown, process 400 can include the formation of the dielectric material 136 in the trench 410 above the gate 124 and the gate dielectric 126. In some implementations, process 400 can include planarizing the surface of the dielectric material 136 and the dielectric layer 148, for example by using chemical-mechanical polishing or another suitable planarization technique, for a more uniform topography.

[0063] As further shown, process 400 can include forming the first electrical contact 144 through the dielectric layer 148 and in contact with the first source / drain region 120, and forming the second electrical contact 146 through the dielectric layer 148 and in contact with the second source / drain region 122. For example, a section of the dielectric layer 148 (e.g., using masking and / or structuring) can be removed through the entire dielectric layer 148 to form a first gap exposing the first source / drain region 120 and a second gap exposing the second source / drain region 122. The first electrical contact 144 can be formed in the first gap, and the second electrical contact 146 can be formed in the second gap.

[0064] In some implementations, process 400 may include forming a local digit line 106, which is electrically connected to the stack 108 of vertically stacked memory cells 110; forming a general digit line; connecting the local digit line 106 and the first source / drain area 120 (e.g., via the first electrical contact 144); and connecting the general digit line and the second source / drain area 122 (e.g., via the second electrical contact 146). In this way, the stack 108 can be selected or deselected for reading or writing data to memory cells in the stack 108.

[0065] In example process 400 of Fig. 4. The memory array 102 and the transistors 104 are formed after the activation of the dopants of the doped layer 406. Furthermore, the transistors 104 are formed after the memory array 102 is formed. In some implementations, however, the transistors 104 are formed before the memory array 102 is formed, as described below in connection with Fig. 5 described.

[0066] As stated above, Fig. 4 is provided as an example. Other examples may differ from the one relating to Fig. Distinguish between the four described.

[0067] Fig. Figure 5 is a schematic view of a second example process 500 for forming structure 100. As in Fig. As shown in Figure 5, the process 500 can include the formation (e.g., deposition or growth) of a base layer 502, the formation of a silicon layer 504 on the base layer 502, the formation of a doped layer 506 on the silicon layer 504, and the formation of the dielectric layer 148 on the doped layer 506, as described above in connection with Fig. The process described in section 400 can include the activation of dopants (e.g., n-dopants) of the doped layer 406. For example, heat can be applied to activate the dopants, such as by thermal annealing (e.g., rapid thermal annealing). In particular, the doping activation is performed prior to the formation of the storage arrangement 102.

[0068] As further shown, the process 500 can include the formation of a trench 508, the formation of the gate dielectric 126 in the trench 508, the formation of the gate 124 in the trench 508 on top of the gate dielectric 126, and the formation of the dielectric material 136 in the trench 508 on top of the gate 124 and the gate dielectric 126, as described above in connection with Fig. 4 described (with the exception that in process 500, transistor 104 is formed before the storage arrangement 102 is formed). As also described above in connection with Fig. As described in section 4, the gate dielectric 126 can be formed such that it has a cross-sectional view of 200 in the first cross-sectional view. Fig. 2 has the shape shown, or can be formed such that it has a shape shown in the second cross-sectional view 202 of Fig. 2 has the form shown.

[0069] As further shown, process 500 can include the formation of a mask 510 (e.g., a hard mask) on top of the dielectric layer 148 (and the dielectric material 136) in a similar manner to that described above in conjunction with Fig. 4 described. After the mask 510 is formed, the process 500 can include forming a stack 108 of the memory arrangement 102 (and the entire memory arrangement 102) below the base layer 502, as described above in conjunction with Fig. 5 described. Thus, the storage arrangement 102 can be formed after activation of the dopants of the doped layer 406 (and / or after activation of the dopants of channel 118), which offers advantages that are described elsewhere herein.

[0070] Although in Fig. 5 not shown, process 500 can be the removal of the mask 510, the formation of the first electrical contact 144, the formation of the second electrical contact 146, the formation of a local digit line 106, the formation of a general digit line, the connection of the local digit line 106 and the first source / drain area 120 and the connection of the general digit line and the second source / drain area 122, as above in connection with Fig. 4 described, include.

[0071] In example process 500 of Fig. 5. The memory arrangement 102 and the transistors 104 are formed after the dopants of the doped layer 506 are activated. Furthermore, the transistors 104 are formed before the memory arrangement 102 is formed.

[0072] As stated above, Fig. 5 is provided as an example. Other examples may differ from what is provided in relation to Fig. As described in section 5, they differ.

[0073] The in connection with Fig. 4 and Fig. The 5 exemplary process steps described can be applied to the 300th process. Fig. 3 and / or one or more blocks of procedure 300 of Fig. 3 correspond. The ones in connection with Fig. 4 and Fig.The processes described above are examples, and other example processes can be used to form Structure 100, an integrated assembly that includes Structure 100, and / or one or more parts of Structure 100 and / or the integrated assembly. In the process steps described above that describe material formation, such material can be formed, for example, using chemical vapor deposition, atomic layer deposition, physical vapor deposition, or another deposition technique. In the process steps described above that describe material removal, such material can be removed, for example, using a wet etching technique (e.g., wet chemical etching), a dry etching technique (e.g., plasma etching), an ion etching technique (e.g., sputtering or reactive ion etching), atomic layer etching, or another etching technique.

[0074] In some implementations, a memory device includes a memory arrangement comprising multiple stacks of vertically stacked memory cells and a transistor located above a stack of vertically stacked memory cells, the transistor comprising: a channel located above the stack of vertically stacked memory cells, a first source / drain region on top of a first section of the channel, a second source / drain region on top of a second section of the channel, a gate having a top surface lower than a top surface of the first source / drain region and lower than a top surface of the second source / drain region, and a gate dielectric separating the gate from the channel.

[0075] In some implementations, an integrated assembly includes multiple stacks of vertically stacked electronic components and a transistor positioned above one of the multiple stacks of vertically stacked electronic components, the transistor comprising: a channel positioned on top of the stack of vertically stacked electronic components; a first source / drain region on top of a first section of the channel; a second source / drain region on top of a second section of the channel; a gate that forms part of an access line passing through the integrated assembly, with a top surface of the gate being lower than a top surface of the first source / drain region and lower than a top surface of the second source / drain region; and a gate dielectric that separates the gate from the channel.

[0076] In some implementations, a process combines the formation of a silicon layer on a base layer with the formation of a doped layer on the silicon layer;Activating dopants of the doped layer, forming a memory arrangement comprising multiple stacks of vertically stacked memory cells, and forming multiple transistors above the memory arrangement, each transistor being positioned above a respective stack of vertically stacked memory cells of the multiple stacks of vertically stacked memory cells, and comprising: a channel positioned on top of the respective stack of vertically stacked memory cells, a first source / drain region on top of a first section of the channel, a second source / drain region on top of a second section of the channel, a gate having a top surface lower than a top surface of the first source / drain region and lower than a top surface of the second source / drain region, and a gate dielectric separating the gate from the channel.

[0077] The foregoing disclosure provides an illustration and description, but is not intended to be exhaustive or to limit implementations to the exact forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from the practice of the implementations described herein.

[0078] The orientations of the various elements in the figures are shown as examples, and the illustrated examples can be rotated relative to the orientations shown. The descriptions provided herein and the subsequent claims apply to all structures exhibiting the described relationships between various features, regardless of whether the structures have the orientation shown in the drawings or are rotated relative to that orientation. Similarly, spatially relative terms such as "below," "underneath," "lower," "above," "upper," "middle," "left," and "right" are used herein to describe the relationship of one element to one or more other elements, as shown in the figures.The spatially relative terms are intended to encompass different orientations of the element, structure, and / or assembly in use or operation, in addition to those shown in the figures. A structure and / or assembly may also be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, the cross-sectional views in the figures show only features within the planes of the cross-sections and do not show materials behind the planes of the cross-sections, unless otherwise indicated, to simplify the drawings.

[0079] As used herein, the terms "essentially" and "approximately" mean "within reasonable manufacturing and measurement tolerances." All ranges described herein include the numbers at the ends of those ranges unless expressly stated otherwise.

[0080] Even if certain combinations of features are listed in the claims and / or disclosed in the description, these combinations are not intended to limit the disclosure of implementations described herein. Many of these features can be combined in ways not expressly listed in the claims and / or disclosed in the specification. For example, the disclosure includes each dependent claim in a set of claims in combination with each other individual claim in that set of claims and any combination of several claims in that set of claims. As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including individual elements. For example, "at least one of: a, b, or c" means a, b, c, a + b, a + c, b + c, and a + b + c, as well as any combination with multiples of the same element (e.g.,cover a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c and c + c + c, or any other order of a, b and c).

[0081] No component, action, or instruction used herein should be construed as critical or essential unless expressly stated to be so. Furthermore, as used herein, the articles "a" and "an" are to include one or more objects and may be used interchangeably with "one or more." Similarly, as used herein, the article "the" is to include one or more objects referred to in conjunction with the article "the" and may be used interchangeably with "the one or more." When only a single object is meant, the phrase "only one," "single," or a similar phrase is used. Also, as used herein, the terms "has," "have," "possessing," or the like are to be understood as open terms that do not restrict any element they modify (e.g., an element that "has" A may also have B).Furthermore, the phrase "based on" shall mean "at least partly based on" unless explicitly stated otherwise. As used herein, the term "several" may be replaced by "a multitude of" and vice versa. Also, as used herein, the term "or" shall be inclusive when used in an enumeration and may be used interchangeably with "and / or" unless explicitly stated otherwise (e.g., when used in combination with "either" or "only one of"). QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 502,733

[0001] US 18 / 658,235

[0001]

Claims

[1] Storage device comprising: a memory array comprising multiple stacks of vertically stacked memory cells; and a transistor positioned above a stack of vertically stacked memory cells of the multiple stacks of vertically stacked memory cells, the transistor comprises the following: a channel positioned above the stack of vertically stacked memory cells; a first source / drain area on a first section of the channel; a second source / drain area on a second section of the channel; a gate having a top surface that is lower than the top surface of the first source / drain region and lower than the top surface of the second source / drain region; and a gate dielectric that separates the gate from the channel. [2] Storage device according to claim 1, wherein the transistor is configured to selectively couple a local digit line, which is electrically connected to the stack of vertically stacked memory cells, to a global digit line of the storage device. [3] Storage device according to claim 2, wherein the global digit line is selectively coupled to several local digit lines, and wherein each local digit line of the several local digit lines is electrically connected to another stack of vertically stacked memory cells of the several stacks of vertically stacked memory cells. [4] Storage device according to claim 1, wherein the top of the gate is lower than a bottom of the first source / drain region and is lower than a bottom of the second source / drain region. [5] Storage device according to claim 1, wherein the top of the gate is substantially flat. [6] Storage device according to claim 1, further comprising a dielectric material above the gate and between the first source / drain region and the second source / drain region. [7] Storage device according to claim 1, wherein the gate is part of an access line having a single, substantially flat underside. [8] Storage device according to claim 1, wherein the gate is part of an access line having a bottom surface that is flatter between the first source / drain area and the second source / drain area and deeper in an area that is not between the first source / drain area and the second source / drain area. [9] Storage device according to claim 1, wherein the doping activation for at least one of the channels, the first source / drain region or the second source / drain region is carried out prior to the formation of the storage arrangement. [10] Integrated arrangement comprising: several stacks of vertically stacked electronic devices; and a transistor positioned above a stack of vertically stacked electronic devices of several stacks of vertically stacked electronic devices, the transistor comprises the following: a channel positioned on top of the stack of vertically stacked electronic devices; a first source / drain area on a first section of the channel; a second source / drain area on a second section of the channel; a gate that forms part of an access line passing through the integrated arrangement, wherein a top surface of the gate is lower than a top surface of the first source / drain region and lower than a top surface of the second source / drain region; and a gate dielectric that separates the gate from the channel. [11] Integrated arrangement according to claim 10, wherein the top of the gate is lower than the bottom of the first source / drain area and is lower than a bottom of the second source / drain area. [12] Integrated arrangement according to claim 10, wherein the top of the gate is substantially flat. [13] Integrated arrangement according to claim 10, wherein the access line has a single, substantially flat underside. [14] Integrated arrangement according to claim 10, wherein the access conduit has an underside which is flatter above the channel and deeper in a region between the channel and the subsequent channel. [15] Procedures, including: Forming a silicon layer on a base layer; Forming a doped layer on the silicon layer; Activation of dopants in the doped layer; Forming a memory array comprising multiple stacks of vertically stacked memory cells; and Forming several transistors positioned above the memory array, wherein each transistor is positioned above a respective stack of vertically stacked memory cells of the multiple stacks of vertically stacked memory cells and comprises the following: a channel positioned above the respective stack of vertically stacked memory cells; a first source / drain area on a first section of the channel; a second source / drain area on a second section of the channel; a gate having a top surface that is lower than the top surface of the first source / drain region and lower than the top surface of the second source / drain region; and a gate dielectric that separates the gate from the channel. [16] Method according to claim 15, wherein the storage array and the multiple transistors are formed after activation of the dopants of the doped layer. [17] Method according to claim 15, wherein the multiple transistors are formed before the formation of the memory array. [18] Method according to claim 15, wherein the multiple transistors are formed after the formation of the memory array. [19] Method according to claim 15, further comprising forming the gate as part of an access line, each comprising: a single, essentially flat floor surface or a ground surface that is flatter between the first source / drain area and the second source / drain area, and deeper in an area that is not between the first source / drain area and the second source / drain area. [20] Method according to claim 15, further comprising: Forming a local digit line that is electrically connected to the respective stack of vertically stacked memory cells; Forming a global digital line; Coupling of the local digital line and the first source / drain area; and Coupling of the global Digit line and the second source / drain area.

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