Trench junction field-effect transistor with a mesa region

Abstract

A trench-junction field-effect transistor, trench JFET, (100) is proposed. The trench JFET (100) comprises a mesa region (103) bounded by a first and a second trench (1061, 1062) spaced apart in a first lateral direction (x1) of a semiconductor body (102), the first and second trenches (1061, 1062) extending from a first surface (108) into the semiconductor body (102); a mesa channel region (104) of a first conductivity type (103); and a first control region (1101) of a second conductivity type complementary to the first conductivity type, arranged in the mesa region (103) adjacent to the first trench (1061). and a second control area (1102) of the second conductivity type, which is located in the mesa area (103) adjacent to the second trench (1062).The mesa channel region (104) is arranged in the first lateral direction (x1) between the first control region (1101) and the second control region (1102), and the first control region (1101) is electrically coupled to a source contact (S) and the second control region (1102) is electrically coupled to a gate contact (G).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device, in particular a trench junction field-effect transistor, trench JFET, with a mesa region. BACKGROUND

[0002] Technological development of new generations of semiconductor devices, such as junction field-effect transistors (JFETs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. While shrinking device geometries can reduce costs, a variety of trade-offs and challenges must be addressed when increasing device functionality per unit area. For example, a trade-off between area-specific on-resistance, RDS(on), and on-resistance (RDS(on)) is often necessary. on xA, and reliability requirements, which are influenced, for example, by switching efficiency, a design optimization.

[0003] Therefore, there is a need for an improved junction field-effect transistor. SUMMARY

[0004] An example involves a trench-junction field-effect transistor, JFET. The trench JFET comprises a mesa region bounded by a first and a second trench spaced apart in a first lateral direction of a semiconductor body, with the first and second trenches extending from a first surface into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type, located in the mesa region adjacent to the first trench; and a second control region of the second conductivity type, located in the mesa region adjacent to the second trench. The mesa channel region is located in the first lateral direction between the first control region and the second control region.The first control area is electrically coupled to a source contact and the second control area is electrically coupled to a gate contact.

[0005] Another example involves a trench-junction field-effect transistor, JFET. The trench JFET comprises a mesa region bounded by a first and a second trench along a first lateral direction, the first and second trenches extending from a first surface of the semiconductor body into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type, located in the mesa region adjacent to the first trench; and a second control region of the second conductivity type, located in the mesa region adjacent to the second trench. The mesa channel region is located in the first lateral direction between the first control region and the second control region.The first and second trenches each comprise a gate or source electrode and a bottom electrode, wherein the gate or source electrode (1131, 1132) is positioned between the bottom electrode and the first surface.

[0006] Experts will recognize additional features and advantages when reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are integrated into and form part of this description. The drawings illustrate examples of trench JFETs and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and the claims. Fig. Figure 1 is a schematic and exemplary cross-sectional view of an example of a trench JFET with a mesa channel region bounded by control regions electrically coupled to different contacts. Fig. Figure 2 is a schematic and exemplary cross-sectional view of an example of a trench JFET having an upper and a lower electrode in the trenches. Fig. Figure 3 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 1 is based and includes a conductive lining that borders the control area at a lower part of the trenches. Fig. Figure 4 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 2 based and includes conductive linings that adjoin the control areas on a lower part and on side walls of the ditches. Fig. Figure 5 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 1 is based and includes a superjunction structure. Fig. Figure 6 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 1 is based and includes a measure to electrically disable a mesa canal area. Fig. Figure 7 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 1 is based and includes mesa regions with different latitudes. Fig. Figure 8 is a schematic and exemplary cross-sectional view of another example of a trench JFET that incorporates a superjunction structure. Fig. Figure 9 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 8 based. Fig. Figure 10 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 9 based. Fig. Figure 11 is a schematic and exemplary cross-sectional view of another example of a trench JFET that incorporates a superjunction structure. Fig. Figure 12 is a schematic and exemplary cross-sectional view of an example of a trench JFET, based on the trench JFET according to Fig. 11 based. Fig. Figures 13A-13F illustrate an example of a method for fabricating a trench JFET according to Fig. 12. Fig. Figure 14 is a schematic and exemplary cross-sectional view of an example of a trench JFET based on the trench JFET according to Fig. 11 based. DETAILED DESCRIPTION

[0008] The following detailed description refers to the accompanying drawings, which form part of it and illustrate specific examples of trench JFETs. It is understood that other examples may be used and structural or logical modifications made without deviating from the scope of protection of this disclosure. For example, features shown or described for one example may be used in conjunction with other examples to produce another example. It is intended that this disclosure encompasses such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of protection of the attached claims. The drawings are not to scale and are for illustrative purposes only.Corresponding elements are designated with the same reference symbols in the various drawings, unless otherwise specified.

[0009] The terms "have," "contain," "comprise," "exhibit," and the like are open-ended, indicating the presence of the specified structures, elements, or features, but not excluding the presence of additional elements or features. The articles "a," "an," and "the" are intended to encompass both the plural and the singular unless the context clearly indicates otherwise.

[0010] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a heavily doped semiconductor material. The term "electrically coupled" implies that one or more intermediate elements, designed for signal and / or power transmission, can be connected between the electrically coupled elements. These intermediate elements, for example, are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. A resistive contact is a non-rectifying electrical connection.

[0011] Ranges specified for physical dimensions include limit values. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit value such as "at most" and "at least".

[0012] The terms "on" and "over" are not to be interpreted as meaning only "directly on" and "directly over". Rather, if an element is positioned "on" or "over" another element (e.g., a layer is "on" or "over" another layer or "on" or "over" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" or "over" the substrate).

[0013] An example of a vertical junction field-effect transistor (VJFET) comprises a mesa region bounded by a first and second trench along a first lateral direction. This type of vertical JFET can also be called a trench JFET. The first and second trenches extend from a first surface of the semiconductor body into the semiconductor body. The trench JFET further comprises a mesa channel region of first conductivity type, which may be bounded along the first lateral direction by a first and second control region of second conductivity type. A first pn junction is defined by the mesa channel region and the first control region. A second pn junction is defined by the mesa channel region and the second control region. The first control region is electrically coupled to a source contact, and the second control region is electrically coupled to a gate contact.

[0014] The first lateral direction can be a transverse direction of the mesa area, which may be perpendicular to a second lateral direction. The second lateral direction can, for example, be a longitudinal direction of the mesa area. The width of the mesa area, or the width of the first and second trenches, can be measured, for example, along the first lateral direction.

[0015] The trench JFET can, for example, be part of an integrated circuit or define a discrete semiconductor device or module. The trench JFET can, for instance, be a trenched and implanted vertical-channel JFET (TI-VJFET). In a vertical-channel JFET, a load current flows between a first load contact over the first surface of the semiconductor body and a second load contact over a second surface opposite the first, along the vertical direction. In the vertical-channel JFET, the load current can flow along the vertical direction perpendicular to the first and / or the second surface.

[0016] The first surface can be, for example, a front surface or a top surface of the semiconductor body, and the second surface can be, for example, a back surface or a bottom surface of the semiconductor body. The semiconductor body can be attached to a leadframe via the second surface. Bond pads can be arranged over the first surface of the semiconductor body, and bond wires can be bonded to the bond pads.

[0017] The semiconductor body may comprise or consist of a semiconductor material from the elemental semiconductors of Group IV, a compound semiconductor material of Group IV, a compound semiconductor material of Groups III-V, or a compound semiconductor material of Groups II-VI. Examples of semiconductor materials from the elemental semiconductors of Group IV include silicon (Si) and germanium (Ge). Examples of compound semiconductor materials from Groups IV-IV include silicon carbide (SiC) and silicon germanium (SiGe). Examples of compound semiconductor materials from Groups III-V include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). Examples of compound semiconductor materials of group II-VI include cadmium telluride (CdTe), mercury cadmium telluride (CdHgTe) and cadmium magnesium telluride (CdMgTe).The semiconductor body can be, for example, a crystalline SiC semiconductor substrate with zero, one, or more SiC layers deposited on it. The silicon carbide crystal can, for example, have a hexagonal polytype, such as 4H or 6H. The silicon carbide semiconductor body can be homogeneously doped or can comprise differently doped SiC layer sections. The silicon carbide semiconductor body can include one or more layers of another material. For example, the layers of another material can be embedded in the crystalline silicon carbide substrate. The silicon carbide semiconductor substrate can have two substantially parallel main faces of the same shape and size and a lateral face region connecting the edges of the two main faces.

[0018] The trench JFET can be configured to conduct currents greater than 1 A, 10 A, or even 100 A. The transistor cell array can be a one-dimensional or two-dimensional regular arrangement of multiple transistor cells. The multiple transistor cells of the array can be electrically connected in parallel. Source regions of the multiple transistor cells of the trench JFET array can be electrically connected to each other. Similarly, drain regions of the multiple transistor cells of the trench JFET array can be electrically connected to each other. Gate regions of the multiple transistor cells of the trench JFET array can also be electrically connected to each other. A transistor cell of the array, or a portion thereof, such as the gate region, can be shaped, for example, as a strip, a polygon, a circle, or an oval.

[0019] The number of transistor cells in the transistor cell array can depend on the maximum load current. For example, the number of transistor cells in the transistor cell array can be greater than 100, greater than 1000, or even greater than 10000. Furthermore, the trench JFET can be configured to block a voltage between the load electrodes, e.g., between the drain and source of the trench JFET, of more than 60 V, 100 V, 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, or 10 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the trench JFET. The blocking voltage of the trench JFET can be adjusted by impurity concentration and / or a vertical extent of a drift zone in the semiconductor body. The doping concentration of the drift zone can vary along a lateral and / or vertical direction, e.g.The doping type increases or decreases gradually or stepwise with increasing distance from the first surface, at least in sections of its vertical extent. In the case of superjunction devices, the doping type can, for example, vary along the lateral direction, e.g., alternating.

[0020] According to other examples, the impurity concentration in the drift zone can be approximately uniform. For trench JFETs based on silicon, the average impurity concentration in the drift zone can be between 2 × 10⁻⁶. 12 cm -3 and 1 × 10 17 cm -3 lie, for example, in an area of ​​5 × 10 12 cm -3 up to 1 × 1015 cm -3 or up to 2 × 10 15 cm -3 In the case of a trench JFET based on SiC, the average defect concentration in the drift zone can be between 5 × 10 14 cm -3 and 1 × 10 17 cm -3lie, for example, in a range of 1 × 10 15 cm -3 up to 5 × 10 16 cm -3 The vertical extent of the drift zone can depend on the voltage-blocking requirements, such as a specified voltage class, of the trench JFET. When the trench JFET is operated in a voltage-blocking mode, a space charge region can extend vertically, partially or completely, through the drift zone, depending on the blocking voltage applied to the trench JFET.

[0021] The source contact and the drain contact can be part of a wiring region above the semiconductor body. The wiring region can comprise one or more than one, e.g., two, three, four, or even more wiring levels. Each wiring level can be formed by a single or a stack of conductive layers, e.g., metal layer(s). The wiring levels can be structured, for example, lithographically. A dielectric interlayer structure can be arranged between stacked wiring levels. Contact plug(s) or contact leads can be formed in openings in the dielectric interlayer structure to electrically connect parts, e.g., metal leads or contact regions, of different wiring levels. The source contact can be formed by one or more elements of the wiring region above the first surface.Similarly, the drain contact can be formed by one or more elements of the wiring area above the second surface.

[0022] The doping concentration in the mesa canal region can be adjusted, for example, by in-situ doping with dopants of the first conductivity type when a semiconductor layer is formed on a substrate, e.g., by a thin-film deposition technique. The doping concentration in the mesa canal region can additionally or alternatively be adjusted by ion implantation of dopants of the first conductivity type through a side wall of the first trench and / or a side wall of the second trench, e.g., by one or more inclined ion implantation processes.

[0023] The first and second control regions of the second conductivity type can be produced, for example, by ion implantation of dopants of the second conductivity type through a side wall and optionally through a bottom of each of the first and second trenches.

[0024] After constructing the mesa canal region and the first and second control regions, a trench structure can be created in each of the first and second trenches. The trench structure can include a contact material, which may be composed of one or more conductive materials, such as metal, metal silicide, metal compound, or highly doped semiconductor material like highly doped polycrystalline silicon. The contact material can be, for example, a single layer, such as a highly doped polycrystalline layer, or a stack of layers. The trench structure can further include, for example, a dielectric structure. The dielectric structure can comprise several assembled dielectric parts, which may differ, for example, in material. The dielectric structure can be an insulating material, such as an oxide, such as SiO₂, or a nitride, such as...The dielectric structure may be Si3N4, a high k-value dielectric, a low k-value dielectric, or any combination thereof. The dielectric structure may, for example, be a deposited oxide (TEOS). The contact material of the trench structure in the first trench may be electrically connected to the first control region of the second conductivity type via the bottom and / or side wall of the trench structure. The contact material may, for example, be electrically connected to the first control region through an opening in the dielectric structure of the trench structure, such as on the bottom of the trench structure. Similarly, the contact material of the trench structure in the second trench may be electrically connected to the second control region of the second conductivity type via the bottom and / or side wall of the trench structure.The contact material can, for example, be electrically connected to the second control area through an opening in the dielectric structure of the trench, e.g., on a bottom surface of the trench. Although the trench structures in the first and second trenches can be processed together, the contact material of the trench structure in the first trench can be electrically coupled to the source contact or the source electrode, and the contact material of the trench structure in the second trench can be electrically coupled to the gate contact.

[0025] Dopants in a semiconductor body containing SiC can include, for example, Al, B, Be, Ga, or any combination thereof for p-type doping, and N, P, or any combination thereof for n-type doping. Dopants in a semiconductor body containing Si can include, for example, Al, B, Ga, In, or any combination thereof for p-type doping, and P, As, Sb, hydrogen-related donors, or any combination thereof for n-type doping.

[0026] The trench JFET can, for example, further include an edge termination region that laterally separates an active trench JFET region from a field-free region and can completely surround the active trench JFET region laterally. In blocking or reverse-biased operation of the trench JFET, the blocking voltage between the active trench JFET region and the field-free region drops laterally across a termination structure in the edge termination region. The edge termination region can have a higher or slightly lower voltage blocking capability than the active trench JFET region. The termination structure in the edge termination region can include a JTE (Junction Termination Extension) with or without a VLD (Variation of Lateral Doping), one or more laterally separated protective rings, or any combination thereof.

[0027] By electrically coupling the first control region to the source contact instead of, for example, the gate contact, the gate-to-drain capacitance Cgd and the ratio of Cgd to the gate-to-source capacitance Cgs can be reduced. This can improve switching efficiency and switching speed by reducing the amount of gate charge that needs to be dissipated during switching. It can also improve the usability of trench JFETs.

[0028] The first trench may, for example, include a dielectric trench fill structure.

[0029] Functional or structural configuration details described above with respect to the exemplary trench JFET apply equally to another example of a trench junction field-effect transistor (JFET) that includes a mesa region bounded by first and second trenches along a first lateral direction. The first and second trenches extend from a first surface of the semiconductor body into the semiconductor body. The trench JFET further includes a mesa channel region of a first conductivity type, bounded along the first lateral direction by a first and second control region of a second conductivity type. A first pn junction is defined by the mesa channel region and the first control region. A second pn junction is defined by the mesa channel region and the second control region. The first and second trenches each include a gate or source electrode and a ground electrode.The gate or source electrode is positioned between the bottom electrode and the first surface.

[0030] The trench structure also includes, for example, a dielectric separation region, e.g., an oxide, located between the bottom electrode and the gate or source electrode.

[0031] The first and second control regions can each be subdivided into an upper and a lower part. The upper and lower parts can be vertically separated by an intermediate separation region of the first conductivity type. This prevents, for example, a short circuit between the bottom electrode and the gate or source electrode located above the bottom electrode.

[0032] The intermediate separation region can, for example, border the dielectric separation region along the first lateral direction.

[0033] The trench JFET can, for example, further comprise a first conductive lining on a sidewall section of at least one first and second trench. The first conductive lining can be located laterally between a trench fill material, e.g., a conductive material of the gate or source electrode, in which at least one of the first and second trenches is located, and a corresponding control area of ​​the first and second control area. The first conductive lining can improve or enable ohmic contact between the trench fill material in the at least one of the first and second trenches and a corresponding control area of ​​the first and second control area. Furthermore, the first conductive lining can improve transverse conductivity along a longitudinal direction of the at least one of the first and second trenches. This can, for example, contribute to reducing resistance losses from the gate electrode in the trenches to a gate pad.The first conductive lining can be formed, for example, by a metal such as Ni or Ti, which may further include additives, e.g. Al.

[0034] The trench JFET can, for example, further comprise a second conductive lining on a soil section of the first and / or the second trench. The second conductive lining can be arranged vertically between a trench fill material in at least one of the first and second trenches and a corresponding control area in the first and second trenches. The second conductive lining can improve ohmic contact between the trench fill material, e.g., a conductive material of the soil electrode, in at least one of the first and second trenches and a corresponding control area in the first and second trenches. Furthermore, the first conductive lining can improve transverse conductivity along a longitudinal direction of at least one of the first and second trenches. This can, for example, reduce resistance losses from the soil electrode in the trenches to a corresponding contact area.a source or gate contact. The second conductive lining can be formed, for example, by a metal such as Ni or Ti, which may further include additives, e.g. Al.

[0035] The trench JFET can, for example, further include a superjunction structure located between a bottom side of the first and second trenches and a second surface of the semiconductor body opposite the first surface.

[0036] The superjunction structure can, for example, comprise a first superjunction region of the first conductivity type and a second superjunction region of the second conductivity type. The first superjunction region can be electrically coupled to a drain contact on the second surface of the semiconductor body and to the source contact on the first surface of the semiconductor body. The second superjunction region can be electrically coupled to both the first and second control regions. For example, a top surface of the second superjunction region can be adjacent to a bottom surface of both the first and second control regions. Doping concentration profiles of the second superjunction region and of both the first and second control regions can, for example, overlap.

[0037] The vertical extent of the superjunction structure can, for example, range from 50% to 2000% of the vertical extent of the first and second trenches.

[0038] The trench JFET can, for example, further include a source region of the second conductivity type, located on one of the opposite side walls of the mesa region adjacent to the second trench. This can, for example, improve the ohmic contact between the mesa region and the source contact.

[0039] The trench JFET can, for example, further include a second mesa region. This second mesa region can be wider than the first. The second trench is laterally bounded by the first and second mesa regions. Mesa regions of different widths can, for example, enable the counteracting of offsets in pinch-off voltages resulting from different pinch-off behaviors caused by control regions with different potentials.

[0040] The extent of the mesa region along the first lateral direction can, for example, be in the range of 200 nm to 2 µm.

[0041] Along the first lateral direction, the mesa canal region can, for example, comprise a first, a second, and a third mesa canal subregion, all of equal extent along this direction. The concentration of first-conductivity dopants averaged along the first lateral direction in the second mesa canal subregion can be greater than the concentration of first-conductivity dopants averaged along the first lateral direction in each of the first and third mesa canal subregions. By providing a trench JFET with the above relationship regarding dopant concentration in the mesa canal region, compensation for channel charge caused by an overlap of doping profiles between the first and second control regions and the mesa canal region can be reduced. This can enable stabilization of the charge in the mesa canal.This reduces the variability of the pinch-off voltage or threshold voltage of the trench JFET. This can further improve the usability of trench JFETs.

[0042] The examples and features described above and below can be combined.

[0043] Functional and structural details described in relation to the examples above apply equally to the exemplary examples shown in the figures and described below.

[0044] Further examples of trench JFETs are explained below in conjunction with the accompanying drawings. Functional and structural details described in relation to the examples above apply equally to the exemplary embodiments shown in the figures and described below. In the examples shown, for an n-channel trench JFET, the first conductance is n-type and the second conductance is p-type. However, for a p-channel trench JFET, the first conductance can also be p-type and the second conductance n-type.

[0045] Fig. Figure 1 shows a schematic and exemplary cross-sectional view of a configuration example of a trench JFET 100.

[0046] The trench JFET 100 comprises a mesa region 103 bounded by a first and a second trench 1061, 1062 along a first lateral direction x1 of a semiconductor body 100. The first and second trenches 1061, 1062 extend from a first surface 108 of the semiconductor body 102 into the semiconductor body 102. A doped mesa channel region 104 of a first conductivity type is bounded along the first lateral direction x1 by a first and a second control region 1101, 1102 of a second conductivity type complementary to the first conductivity type. By way of example, the first conductivity type is n-type, so the mesa channel region 104 is n-doped, and the second conductivity type is p-type, so the control regions 1101, 1102 are p-doped.

[0047] In each case, a first pn transition 1121 is defined by the mesa canal region 104 and the first control region 1101, and a second pn transition 1122 is defined by the mesa canal region 104 and the second control region 1102. To form the first pn transition, the first control region 1101 can be adjacent to the mesa canal region 104. However, this is only one example. It is also possible that the first control region 1101 is spaced from the mesa canal region 104 in the first lateral direction x1, and that a region with a lower doping concentration than either the first control region 1101 or the mesa canal region 104 is located between the first control region 1101 and the mesa canal region 104. This further region can be of the first conductivity type, the second conductivity type, or it can be intrinsic.In any case, a pn transition is formed in an area between the first control area 1101 and the Mesa Canal area 104, so that the pn transition between the first control area 1101 and the Mesa Canal area 104 is arranged.

[0048] Equivalently, to form the second pn junction, the second control region 1102 can be adjacent to the mesa canal region 104. Alternatively, the second control region 1102 can be spaced from the mesa canal region 104 in the first lateral direction x1, such that a region with a lower doping concentration than either the second control region 1102 or the mesa canal region 104 is located between them. This region can be of the first conductivity type, the second conductivity type, or it can be intrinsic. In any case, a pn junction is formed in a region between the second control region 1102 and the mesa canal region 104.

[0049] The mesa channel region 104 is electrically coupled, e.g., via a drift zone 119, to a drain contact D on a second surface of the semiconductor body. The drift zone 119 is, for example, of the first conductivity type. The mesa channel region 104 is also electrically coupled to a source contact S on the first surface 108 of the semiconductor body 102, e.g., via a source region 124 on the first surface 108. The source region 124 is of the first conductivity type and can have a higher doping concentration than the drift zone 119.

[0050] For example, the extent wm of the mesa region 103 along the first lateral direction x1 can be in the range of 200 nm to 2 µm or 300 nm to 1.6 µm or 400 nm to 1.2 µm.

[0051] The first control area 1101 is electrically coupled to the source contact S, e.g., via a conductive material as part of a fill material in the first trench 1061. Alternatively, the first control area 1101 can also be electrically coupled to the source contact S via a contact on the first control area 1101 at the first surface 108. In this case, the first trench 1101 can, for example, comprise a dielectric trench fill structure.

[0052] The second control area 1102 is electrically coupled to a gate contact G in the second trench 1062 via a conductive filling material (e.g. a gate electrode).

[0053] Fig. Figure 2 shows a schematic and exemplary cross-sectional view of another configuration example of a trench JFET 100.

[0054] The first and second trenches 1061, 1062 each comprise a gate or source electrode 1131, 1132 and a bottom electrode 1141, 1142. The gate or source electrode 1131, 1132 is arranged between the bottom electrode 1141, 1142 and the first surface 108 and is electrically coupled to a gate or source contact G / S.

[0055] A capacitive behavior, e.g. C GDThe current behavior can be adjusted via a potential applied to the bottom electrodes 1141, 1142. For example, bottom electrode 1141 in the first trench 1061 can be electrically coupled to the gate contact G, and bottom electrode 1142 in the second trench 1062 can be electrically coupled to the source contact S, or vice versa. Bottom electrodes 1141, 1142 can also be electrically coupled to either the gate contact G or the source contact S. While the capacitive behavior can be adjusted via the potential of each of the bottom electrodes in trenches 1061, 1062, the current behavior can be adjusted via the potential, e.g., gate or source potential, applied to each of the gate or source electrodes 1131, 1132 in the trenches. By applying a source potential to one of the gate or source electrodes 1131, 1132, the respective trench can be deactivated, for example, with regard to the control of the channel conductivity.

[0056] A dielectric separation region 1161, 1162 is arranged between the bottom electrode 1141, 1142 and the gate or source electrode 1131, 1132 to electrically separate the gate or source electrode 1131, 1132 and the bottom electrode 1141, 1142 in each of the trenches 1061, 1062.

[0057] The first and second p-doped control regions 1101, 1102 each have an upper part 1104 and a lower part 1105. The upper part 1104 and the lower part 1105 are vertically separated from each other by an n-doped intermediate separation region 1151, 1152. A pn ​​junction insulation is formed between the n-doped intermediate separation region 1151, 1152 and the p-doped first and second p-doped control regions 1101, 1102 to prevent a short circuit between the source or gate electrode 1131, 1132 and the bottom electrode 1141, 1142. The intermediate separation region 1151, 1152 borders the dielectric separation region 1161, 1162 along the first lateral direction x1.

[0058] Fig. Figure 3 schematically and exemplarily shows a cross-sectional view of another configuration example of a trench JFET 100, which is based on the one described in Fig. The example shown is related to 1.

[0059] The trench JFET 100 according to Fig. 3 comprises a conductive lining 1181, 1182 on a bottom section of the first and second trenches 1061, 1062. The conductive lining 1181, 1182 is arranged vertically between the gate or source electrode 1131, 1132 in the first and second trenches 1061, 1062 and a corresponding one in the first and second control area 1101, 1102. The first control area 1101 is electrically connected to the source contact S via the gate or source electrode 1131 in the first trench 1061. The second control area 1102 is electrically connected to a gate contact (in) via the gate or source electrode 1132 in the second trench 1062. Fig. 3 (not shown) connected. An interlayer dielectric 126 is arranged on the gate or source electrode 1132. The mesa channel region 104 is connected via an n + -doped source region 124 on the first surface 108 electrically coupled to the source contact S on the first surface 108 of the semiconductor body 102.

[0060] Along the first lateral direction x1, the mesa canal region 104 comprises a first, a second, and a third mesa canal subregion 1041, 1042, 1043, which have equal extents along the first lateral direction x1. The concentration of n-dopers averaged along the first lateral direction x1 in the second mesa canal subregion 1042 is greater than the concentration of n-dopers averaged along the first lateral direction x1 in each of the first and third mesa canal subregions 1041, 1043.

[0061] Fig. Figure 4 schematically and exemplarily shows a cross-sectional view of another configuration example of a trench JFET 100, which is based on the one described in Fig. The example shown is related to the second example.

[0062] Similar to the configuration example according to Fig. 3 includes the trench JFET 100 according to Fig. 4 a conductive lining 1181, 1182 on a soil section of the first and second trenches 1061, 1062. The conductive lining 1181, 1182 is arranged vertically between the soil electrode 1141, 1142 and a corresponding one of the first and second control area 1101, 1102.

[0063] The trench JFET 100 comprises, as described in the configuration example according to Fig. 3 described, furthermore the Mesa Canal area 104 with the first, the second and the third Mesa Canal sub-area 1041, 1042, 1043.

[0064] The trench JFET further comprises a conductive lining 1171, 1172 on a side wall section of the first and second trenches 1061, 1062. The conductive lining 1171, 1172 is arranged laterally between a trench fill material, e.g., the gate or source electrode 1131, 1132, in the first and second trenches 1061, 1062 and a corresponding one in the first and second control area 1101, 1102.

[0065] The Fig. Figures 1-4 each illustrate only one mesa region 103 located between a first graben 1061 and a second graben 1062. This is for illustrative purposes only. It should be noted that, according to each example described herein, the graben JFET can comprise multiple first and second grabens 1061, 1062 arranged alternately in the first lateral direction x1, such that the graben JFET comprises multiple mesa regions 103 spaced apart from each other in the first lateral direction x1. Adjacent mesa regions 103 are separated from each other by either a first graben 1061 or a second graben 1062. Accordingly, the trench JFET comprises several first control areas 1101, each adjacent to a respective first trench 1061 and connected to the source contact S, and several second control areas 1102, each adjacent to a respective second trench 1062 and connected to the gate contact G.

[0066] Fig. Figure 5 shows a schematic and exemplary cross-sectional view of another example of a trench JFET 100, which is based on the one described in Fig. The example shown is related to 1.

[0067] Instead of just one drift zone 119 of the first conductivity type, the trench JFET 100 comprises according to Fig. 5 A superjunction (SJ) structure 120 is arranged between a bottom surface of the first and second trenches 1061, 1062 and a second surface 109 of the semiconductor body 102 opposite the first surface 108. More precisely, the SJ structure 120 can be arranged between the bottom surfaces of the first and second trenches 1061, 1062 and a drain region 130 of the first conductivity type. The drain region 130 is connected to the drain contact D.

[0068] The SJ structure 120 comprises first SJ areas 121 of the first conductivity type and second SJ areas 122 of the second conductivity type. Within the SJ structure 120, the first SJ areas 121 can also be referred to as drift areas, which together form at least one section of a drift zone of the trench JFET. The second SJ areas 122 can also be referred to as compensation areas. A doped area 119' of the first conductivity type can be located between the drain area 130 and the SJ structure 120. This doped area 119' can have a lower doping concentration than the drain area 130. The doped area 119' can form a further section of the drift zone and / or can form a buffer area. The doped area 119' may comprise two or more differently doped areas of the first conductivity type, arranged one above the other between the drain area 130 and the SJ area 120.

[0069] In the superjunction structure 120, the multiple first SJ regions 121 of the first conductivity type and the multiple second SJ regions 122 of the second conductivity type are arranged alternately in the first lateral direction x1. Each of the first SJ regions 121 is electrically coupled to the drain region 130, and the drain contact D is connected to the drain region 130. As shown in Fig. As shown in Figure 5, the first SJ regions 121 can be coupled to the drain region 130 via the doped region 119' of the first conductivity type. Furthermore, each of the first SJ regions 121 is electrically coupled to the source contact S on the first surface 108 of the semiconductor body 102 via the mesa channel region 104 and the source region 124.

[0070] In the Fig. In the example shown, the second SJ areas 122 comprise a first group of second SJ areas and a second group of second SJ areas. Each of the second SJ areas 122 of the first group is electrically coupled to a respective first control area 1101, and each of the second SJ areas of the second group is electrically coupled to a respective second control area 1102.

[0071] For example, the vertical extent t1 of the superjunction structure 120 can be in the range of 50% to 2000% of the vertical extent t2 of the first and second trenches 1061, 1062.

[0072] The operating principle of the trench JFET according to Fig. 5 is briefly explained below. For the sake of illustration, it is assumed that the first conductivity type, which is the conductivity type of the Mesa Canal area 124, the first SJ areas 121, the Drain area 130 and the area 119' between the Drain area 130 and the Superjunction area 120, is n-conducting, and that the second conductivity type, which is the conductivity type of the first and second Control Areas 1101, 1102 and the second SJ areas 122, is p-conducting.

[0073] In this example, the JFET is in an on-state (conducting state) when a drive voltage (gate-source voltage) is applied between the gate contact G (in Fig. (5 not shown) and the source contact S is higher than a negative threshold voltage of the trench JFET, so that a current can flow from the drain contact D through the drain region 130, region 119', the first SJ regions 121, the mesa channel region 104, and the source region 124 to the source contact S. The JFET is in the off state (blocking state) when the drive voltage is lower (more negative) than the threshold voltage. In this case, a space charge region (depletion region) expands in the mesa channel region 104, starting at the pn junction between the mesa channel region 104 and the second control region 1102, which is that of the first and second control regions 1101, 1102 connected to the gate contact G. The JFET is in the off state when the drive voltage is such that the mesa channel region 104 is completely depleted of charge carriers between the first and the second control region 1101, 1102.

[0074] Furthermore, in the off state, each first SJ area 121 is depleted of charge carriers by coupling one of the neighboring second SJ areas 122 to the source contact S via the first control area 1101 and coupling the other of the neighboring second SJ areas 122 to the gate contact G via the second control area 1102.

[0075] In comparison to a conventional trench JFET, where the control regions along both side walls of a mesa region are connected to the gate node, the threshold voltage of the transistor device is according to Fig. 5 negative. On the other hand, the transistor component exhibits according to Fig. 5 a lower gate-drain capacity, since not every control area is connected to the gate contact G, but some of the control areas (the first control areas 1101) are connected to the source node.

[0076] Fig. Figure 6 schematically and exemplarily shows a cross-sectional view of another configuration example of a trench JFET 100, which is based on the one described in Fig. The example shown is related to 1.

[0077] The n+-doped source area 124 is located only on one of the opposite side walls of the mesa area 103, which borders the second trench 1062. Thus, the n + The source region 124, doped on the side wall and on the top surface section of the mesa region 103, which borders the first trench 1061 and is adjacent to the source contact S, is omitted. This deactivates the control of a channel conductivity in the mesa region 103 on the side wall of the second trench 1062, since the source region 124 borders the intermediate dielectric 126 but not the source contact S.

[0078] Fig. Figure 7 shows a schematic and exemplary cross-sectional view of another configuration example of a trench JFET 100, which is based on the one described in Fig. The example shown is related to 1.

[0079] The trench JFET 100 comprises a second mesa region 1032 with a width wm2. The second mesa region 1032 is wider than the mesa region 103, i.e., wm2 > wm. The second mesa region 1032 borders the second control region 1102 and a third control region 1103. The second and third control regions 1102, 1103 are electrically coupled to the gate contact G. Thus, a second mesa channel region 1042 is pinched off within the second mesa region 1032 via space charge regions from opposite side walls of the second mesa region 1032. In the mesa region 103, the mesa channel region 104 is cut off by only one of opposing space charge regions, since the first control region 1101 is electrically coupled to the source contact S and the extent of the associated space charge region cannot be controlled by a voltage applied to the gate contact G.

[0080] The configuration examples according to Fig. 6 and Fig. Section 7 describes measures to counteract an offset in pinch-off voltages (threshold voltages) that can occur when different voltages are applied to the control regions that define the mesa channel regions. Different voltages, such as gate or source voltage, can be applied to the control regions, for example, to adjust the capacitive behavior of the trench JFET.

[0081] In the superjunction trench JFET according to Fig. 5 borders the first SJ region 121, in which a current flows between the mesa channel region 104 and the drain region 130 in the on-state, along the entire width of the mesa channel region 104. The width of the mesa channel region 104 is its dimension in the first lateral direction x1. To operate this JFET in the off-state, the mesa channel region 104 must be depleted of charge carriers across its entire width by applying a suitable negative drive voltage between the gate contact G, which is connected to the second control region 1102, and the source contact S, which is connected to the mesa channel region 104.

[0082] Fig. Figure 8 illustrates a modification of the trench JFET according to Fig. 5. The trench JFET according to Fig. 5 differs from the trench JFET according to Fig. 8 by the fact that the first and second SJ regions 121, 122 of the superjunction structure 120 are offset (shifted) relative to the mesa channel regions 104 such that a pn junction formed between adjacent first and second SJ regions 121, 122 is located in a vertical direction z of the semiconductor body 102 below the mesa channel region 104. The “vertical direction z” is a direction of the semiconductor body 102 that is essentially perpendicular to the first and second surfaces 108, 109. Thus, in the trench JFET according to Fig. 8 Each mesa canal region 104 is connected in the vertical direction z to a section of a first SJ region 121 and a section of an adjacent second SJ region 122. Furthermore, in the trench JFET according to Fig. 8 each first SJ area 121 is arranged under a respective second trench 1062 with a gate electrode 1132 arranged therein, and each second SJ area 122 is arranged under a respective first trench 1061 with a source electrode 1131 arranged therein.

[0083] The source electrodes 1131 are, for example, connected to a source metallization 1091, which is connected to or forms the source contact S. The gate electrodes 1132 are connected to a gate contact G, which is located in Fig. 8 is not shown.

[0084] In the Fig. In the example shown, adjacent first and second SJ regions 121, 122 are adjacent to each other. However, this is only one example. According to another example (not shown), adjacent first and second SJ regions 121, 122 are spaced apart in the first lateral direction x1, with a region of the first or second conductivity type having a lower doping concentration than either the first or second SJ region 121, such as a doping concentration of less than 5 × 15 cm⁻¹. -3 , or it may be an intrinsic area situated between the adjacent first and second SJ areas 121, 122. In any case, the Mesa Canal Area 104 borders a section of a first SJ area 121 and a section of a second SJ area 122.

[0085] Furthermore, with reference to Fig. 8, every second SJ area 122 is connected to the source contact S via one of the first control areas 1101 and a respective source electrode 1131. The first control areas 1101 can be arranged not only along the side walls of the first trenches 1061, but also along the undersides of the first trenches 1061. Every second SJ area 122 is spaced apart from the second control areas 1102.

[0086] The operating principle of the trench JFET according to Fig. 8 resembles the operating principle of the trench JFET according to Fig. 5. In the on-state, a current flows between the drain and source contacts D, S, among other things via the first SJ areas 121 and the mesa canal areas 104.

[0087] The JFET is in the off-state when the mesa channel region 104 is depleted of charge carriers. The JFET may already be in the off-state when those sections of the mesa channel region 104 adjacent to the first SJ region 121 are depleted of charge carriers. Current flow through those sections of the mesa channel region 104 adjacent to the second SJ regions 122 is prevented by a pn junction formed between the second SJ regions 122 and the mesa channel regions 104. This can have the effect of establishing a threshold voltage of the trench JFET according to Fig. 8 a smaller amount (can be less negative) than the threshold voltage of the trench JFET according to Fig. can have 5.

[0088] Furthermore, in the off state, each first SJ region 121 is depleted of charge carriers because the first SJ regions 121 are electrically coupled to the drain region 130 and the drain node D, and the second SJ regions 122 are coupled to the source node S. Unlike in the Fig. The example shown in section 5 is in the trench JFET according to Fig. 8. Each of the second tax areas 1102 is spaced apart from the SJ areas 122 and arranged adjacent to a respective first SJ area 121, so that a pn transition can exist between the second tax area 1102 and the first SJ area 121. This can help to improve the gate-drain capacity compared to that in Fig. to reduce the number of JFETs shown in the diagram.

[0089] In the trench JFET according to Fig. 8. The superjunction structure 120 with the first and second SJ regions 121, 122, arranged alternately in the first lateral direction x1, can be fabricated by a conventional multi-epi-multi-implantation (MEMI) process. This process involves fabricating two or more epitaxial layers, implanting first- and second-type dopants into each of the epitaxial layers using respective implantation masks, and a annealing process that activates the implanted first- and second-type dopants to form the first and second SJ regions 121, 122. The first and second trenches 1061, 1062 can be fabricated in an uppermost epitaxial layer formed on top of the epitaxial layers with the superjunction structure 120.The mesa canal regions 104 can be created by implanting dopants of the first conductivity type into the uppermost epitaxial layer. The first and second control regions 1101, 1102 can be created by implanting dopants of the second conductivity type into the sidewalls and floors of the first and second trenches 1061, 1062.

[0090] As from Fig. As can be seen in Figure 8, each mesa area 102 comprises a mesa channel area 104, which is arranged between a first control area 1101 and a second control area 1102. The first control areas 1101 are arranged along both side walls (and bottoms) of the first ditches 1061, and the second control areas 1102 are arranged along both side walls (and bottoms) of the second ditches 1062.

[0091] In the Fig. In the example shown in Figure 8 and the following examples, conductive linings 1181, 1182 are optional and are therefore shown in dashed lines.

[0092] Fig. Figure 9 illustrates a modification of the transistor component according to Fig. 8. In this example, each mesa canal region 104 comprises a first region 1045, located adjacent to the first steering region 1101 in the first lateral direction x1, and a second region 1046, located adjacent to the second steering region 1102 in the first lateral direction x1. In the vertical direction z, the first region 1045 borders a respective second steering region 122, and the second region 1046 borders a respective first steering region 121. The first and second regions 1045, 1046 are spaced apart from each other in the first lateral direction x1. Between the first and second regions 1045, 1046, a region 105 is arranged, which is either of the first or second conductivity type and has a lower doping concentration than either of the first and second regions 1045, 1046, such as less than 5E15 cm -3, or that is intrinsic. The first area 1045 can be adjacent to the first control area 1101 or, as shown, can be spaced away from the first control area 1101. Equivalently, the second area 1046 can be adjacent to the second control area 1102 or, as shown, can be spaced away from the second control area 1102. In the trench JFET according to Fig. 9, in both the on-state and off-state, a current flow through the first area 1045 of the Mesa Canal area 104 is prevented by the pn transition between the first area 1045 of the Mesa Canal area 104 and the second SJ area 122.

[0093] The first mesa canal regions 1045 can be produced by implanting dopant atoms into the sidewalls of the mesa regions before the electrodes 1131, 1132 are produced in the first and second trenches 1061, 1062. In this type of process, it can save costs to implant dopant atoms into each sidewall of each mesa region 103, thereby producing the first and second mesa canal regions 1045, 1046, instead of implanting dopant atoms only into the sidewalls of the mesa regions adjacent to the second trenches 1062 to produce only the second mesa canal regions 1046.

[0094] The trench JFET according to Fig. 9 is in the off state when a gate-source voltage is applied between the gate node G and the source node S, causing the second control area 1102 to become depleted of charge carriers in the second mesa canal area 1046.

[0095] Fig. Figure 10 shows a modification of the trench JFET according to Fig. 9. In comparison to the trench JFET according to Fig. 9 includes the trench JFET according to Fig. 10 Furthermore, a current widening region 106 is arranged at least between the first and second mesa channel regions 1045, 1046 in each mesa region 103. The current widening region 106 is of the first conductivity type and, in the on-state of the JFET, allows current flow from the first mesa channel region 1045 to the second mesa channel region 1046. This can help to reduce the on-resistance, which is the electrical resistance of the trench JFET between the drain contact D and the source contact S in the on-state.

[0096] In the trench JFETs according to the Fig. Figures 8-10 show that the first and second SJ areas 121, 122 are arranged alternately in the first lateral direction x1, such that each first SJ area 121 is located between two second SJ areas 122 and each second SJ area 122 is located between two first SJ areas 121. Another possibility for the alternating arrangement of the first and second SJ areas 121, 122 is shown in Fig. 11 shown.

[0097] Fig. Figure 11 shows a modification of the trench JFET according to Fig. 10. In this trench JFET, the first and second SJ regions 121, 122 are arranged alternately in the first lateral direction x1, such that pairs of adjacent first SJ regions 121 and pairs of adjacent second SJ regions 122 are arranged alternately. The first SJ regions 121 of each pair are spaced apart in the first lateral direction x1, and the second SJ regions 122 of each pair are spaced apart in the first lateral direction x1, with a semiconductor region 123 located between the SJ regions 121, 122 of each pair. The semiconductor region 123 is of the first or second conductivity type and has a lower doping concentration than either of the first and second SJ regions 121, 122, or is intrinsic.

[0098] Referring to Fig. Each of the first SJ regions 121 borders a corresponding second mesa channel region 1046 in the vertical direction z, so that in the on-state, a current can flow between the drain contact D and the source contact S, among other things, via the second mesa channel regions 1046 and the first SJ regions 121. Furthermore, each of the second SJ regions 122 borders a corresponding first mesa channel region 1045. In both the on-state and the off-state, a current flow through the first mesa channel regions 1045 is prevented due to a pn junction between the second SJ region 122 and the respective first mesa channel region 1045.

[0099] In the trench JFET according to Fig. 11. Adjacent first and second SJ regions 121, 122 can be adjacent to each other. According to another example, as shown, adjacent first and second SJ regions 121, 122 can be spaced apart from each other in the first lateral direction x1, with a semiconductor region 124 located between the adjacent first and second SJ regions. The semiconductor region 124 is of the first or second conductivity type and has a lower doping concentration than either of the first and second SJ regions 121, 122, or is intrinsic.

[0100] Fig. Figure 12 shows a modification of the trench JFET according to Fig. 11. The trench JFET according to Fig. 12 comprises only one mesa canal area 104 in each mesa area 103, which borders both the first SJ area 121 and the second SJ area 122, which are arranged in the vertical direction z below the respective mesa area 103.

[0101] Fig. 13A- Fig. Figure 13F schematically illustrates an example of a method for fabricating a trench JFET of the type in Fig. 11 types shown. Each of the Fig. 13A- Fig. Figure 13F shows a vertical cross-sectional view of the semiconductor body 102 during various process steps.

[0102] Referring to Fig. In 13A, the method is based on a semiconductor body 102 comprising the drain region 130, the first conductivity-type region 119', and an epitaxial layer 1240 formed on the region 119'. The drain region 130 is formed, for example, by a semiconductor substrate. The region 119' can be formed by one or more epitaxial layers fabricated on the substrate. The epitaxial layer 1240 fabricated on the region 119' is, for example, low-doped. According to one example, this includes a base doping concentration of the epitaxial layer 1240 lower than 1 × 10⁻⁶ cm⁻¹. -3, lower than 5E15 cm -3 or lower than 1E15 cm -3 is.

[0103] Referring to Fig. 13A The procedure includes the creation of first and second trenches 1071, 1072 in epitaxial layer 1240. The first and second trenches 1071, 1072 may extend through epitaxial layer 1240 into area 119'. The creation of the first and second trenches 1071, 1072 may involve a conventional etching process using an etching mask (in Fig. 13A not shown). In Fig. Figure 13A shows only one first trench 1071 and one second trench 1072. It should be noted that several first trenches 1071 and several second trenches 1072 are constructed, with the first and second trenches 1071, 1072 arranged alternately in the first lateral direction x1.

[0104] Referring to Fig. 13B further comprises the implantation of second-type (conductivity) dopant atoms into opposite sidewalls of the first trenches 1071 in an inclined implantation process to create second implanted regions 122' along the sidewalls. The process further comprises covering an upper surface of the epitaxial layer 1240 and of the sidewalls and bottoms of the second trenches 1072 with a first protective layer 1081 to prevent second-type dopant atoms from being implanted into the sidewalls and bottoms of the second trenches 1072.

[0105] Referring to Fig. 13C further comprises the implantation of first-type (conductivity) dopant atoms into opposite sidewalls of the second trenches 1072 in an inclined implantation process to produce first implanted regions 121' along the sidewalls. The process further comprises covering an upper surface of the epitaxial layers 1240 and of the sidewalls and floors of the first trenches 1071 with a second protective layer 1082 to prevent second-type dopant atoms from being implanted into the sidewalls and floors of the first trenches 1071.

[0106] Referring to Fig. 13D further comprises the process of at least partially filling the first and second trenches 1071, 1072 with a monocrystalline semiconductor material. According to an example, the monocrystalline semiconductor material is of the same type as the rest of the semiconductor body 102. The at least partial filling of the first and second trenches 1071, 1072 may include an epitaxial growth process.

[0107] Referring to Fig. 13E further comprises the fabrication of the first and second trenches 1061, 1062, which define the mesa regions 103 such that second implanted regions 122' extend along opposite sidewalls of the first trenches 1061 and first implanted regions 121' extend along opposite sidewalls of the second trenches 1062. The first and second trenches 1061, 1062 can be fabricated by the same etching process.

[0108] Referring to Fig. 13E further comprises the implantation of first-type dopant atoms into opposite sidewalls of the first and second trenches 1061, 1062 and the implantation of second-type dopant atoms into opposite sidewalls and bottoms of the first and second trenches 1061, 1062. The method further comprises a annealing process to activate the implanted dopant atoms. After the tempering process, the first implanted areas 121' form the first SJ areas 121, the second implanted areas 122 form the second SJ areas 122, the dopant atoms of the first type, which are implanted into the side walls of the first and second trenches 1061, 1062, form the mesa canal areas 104, and the dopant atoms of the second type, which are implanted into the side walls and the bottoms of the first and second trenches 1061, 1062, form the first and second control areas 1101, 1102.

[0109] Referring to Fig. 13F the trench JFET is completed by creating the source areas 124, the source electrodes 1131 in the first trenches 1061, the gate electrodes 1132 in the second trenches 1062 and creating the source metallization 1091, which is isolated from the gate electrodes 1132 by the insulating layer 126.

[0110] In the trench JFET according to Fig. 13F contains semiconductor region 123, which separates the first and second SJ regions 121, 122 of each pair, and has the base doping concentration of the monocrystalline semiconductor layer fabricated in the first and second trenches 1071, 1072. Furthermore, semiconductor region 124, which is located between adjacent first and second SJ regions 121, 122, has the base doping concentration of the epitaxial layer 1240 fabricated in region 119'.

[0111] As explained above, the first and second trenches 1071, 1072, into which the dopant atoms are implanted to create the first and second SJ regions 121, 122, are at least partially filled. Fig. Figure 14 shows a modification of the trench JFET according to Fig. 13F.

[0112] The trench JFET according to Fig. 14 differs from the trench JFET according to Fig. 13F by the fact that the first and second trenches 1071, 1072 are only partially filled, so that a respective cavity 125 remains under each of the first and second trenches 1061, 1062 and between the first and second SJ areas 121, 122 of each pair.

[0113] Some of the aspects explained above are briefly summarized below with reference to numbered examples.

[0114] Example A1. Trench-junction field-effect transistor, JFET, comprising: a mesa region bounded by first and second trenches spaced apart in a first lateral direction of a semiconductor body, the first and second trenches extending from a first surface into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type, located in the mesa region adjacent to the first trench; and a second control region of the second conductivity type, located in the mesa region adjacent to the second trench, the mesa channel region being situated in the first lateral direction between the first control region and the second control region, and the first control region being electrically coupled to a source contact and the second control region being electrically coupled to a gate contact.

[0115] Example A2. Trench JFET according to Example A1, wherein a first pn junction is arranged between the mesa canal region and the first control region, and wherein a second pn junction is arranged between the mesa canal region and the second control region.

[0116] Example A3. Trench JFET according to Example A1, wherein the mesa canal region is spaced from the first control region in the first lateral direction and / or wherein the mesa canal region is spaced from the second control region in the first lateral direction.

[0117] Example A4. Trench JFET according to Example A3, wherein a semiconductor region with a lower doping concentration than either of the mesa channel region and the first control region is located between the mesa channel region and the first control region and / or wherein a semiconductor region with a lower doping concentration than either of the mesa channel region and the second control region is located between the mesa channel region and the second control region.

[0118] Example A5. Trench JFET according to one of Examples A1 to A4, wherein the mesa canal region comprises a first mesa canal region and a second mesa canal region spaced apart from each other in the first lateral direction, wherein the first mesa canal region is adjacent to the first control region and wherein the second mesa canal region is adjacent to the second control region.

[0119] Example A6. Trench JFET according to one of the preceding claims, wherein the first trench comprises a dielectric trench-filling structure.

[0120] Example A7. Trench-junction field-effect transistor, trench JFET, comprising: a mesa region bounded by first and second trenches along a first lateral direction, the first and second trenches extending from a first surface of the semiconductor body into a semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type, located in the mesa region adjacent to the first trench;and a second control area of ​​the second conductivity type, which is located in the mesa region adjacent to the second trench, wherein the mesa channel region is located in the first lateral direction between the first control area and the second control area, and wherein the first and the second trench each comprise a gate or source electrode and a bottom electrode, wherein the gate or source electrode is located between the bottom electrode and the first surface.

[0121] Example A8. Trench JFET according to Example A7, which further comprises a dielectric separation region located between the bottom electrode and the gate electrode.

[0122] Example A9. Trench JFET according to Example A7 or A8, wherein the first and second control regions are each subdivided into an upper part and a lower part, the upper part and the lower part being vertically separated from each other by an intermediate separation region of the first conductivity type.

[0123] Example A10. Trench JFET according to Example A9, wherein the intermediate separation region borders the dielectric separation region along the first lateral direction.

[0124] Example A11. Trench JFET according to one of Examples A1 to A10, further comprising a first conductive lining on a side wall section of the first and / or the second trench, wherein the first conductive lining is arranged laterally between a trench fill material in the first and / or the second trench and a corresponding one of the first and the second control area.

[0125] Example A12. Trench JFET according to one of Examples A1 to A11, further comprising a second conductive lining on a soil section of the first and / or the second trench, wherein the second conductive lining is arranged vertically between a trench fill material in the first and / or the second trench and a corresponding one of the first and the second control area.

[0126] Example A13. Trench JFET according to one of the examples A1 to A12, further comprising a superjunction, SJ, structure located between a bottom side of the first and second trenches and a second surface of the semiconductor body opposite the first surface.

[0127] Example A14. Trench JFET according to Example A13, wherein the superjunction structure comprises a first SJ region of the first conductivity type arranged between two second SJ regions of the second conductivity type, wherein the first SJ region is electrically coupled to a drain contact on the second surface of the semiconductor body and to the source contact on the first surface of the semiconductor body, wherein one of the two second SJ regions is electrically coupled to the first control region and wherein the other of the two second SJ regions is electrically coupled to the second control region.

[0128] Example A15. Trench JFET according to Example A13, wherein the superjunction structure comprises a first SJ region of the first conductivity type and a second SJ region of the second conductivity type arranged side by side in the first lateral direction, wherein the first SJ region is electrically coupled between the mesa canal region and a drain region of the first conductivity type, wherein the second SJ region is electrically coupled to the first control region and spaced apart from the second control region.

[0129] Example A16. Trench JFET according to Example A15, wherein the mesa channel region is arranged in a vertical direction of the semiconductor body next to a section of the first SJ region and a section of the second SJ region.

[0130] Example A17. Trench JFET according to Example A16, wherein the mesa canal region comprises a first mesa canal region located adjacent to the first control region and a second mesa canal region located adjacent to the second control region, wherein the first and second mesa canal regions are spaced apart in the first lateral direction, wherein the first mesa canal region is located adjacent to a section of the second SJ region in the vertical direction, and wherein the second mesa canal region is located adjacent to a section of the first SJ region in the vertical direction.

[0131] Example A18. Trench JFET according to one of Examples A14 to A17, wherein the JFET comprises multiple first and second trenches arranged alternately in the first lateral direction, and multiple first and second SJ areas arranged alternately in the first lateral direction.

[0132] Example A19. Trench JFET according to Example A18, wherein each first SJ region is arranged in the vertical direction under a respective second trench, and wherein each second SJ region is arranged in the vertical direction under a respective first trench.

[0133] Example A20. Trench JFET according to Example A18, wherein two first SJ regions are arranged side by side, spaced apart from each other in the first lateral direction and are at least partially located under a respective second trench in the vertical direction, and wherein two second SJ regions are arranged side by side, spaced apart from each other in the first lateral direction and are at least partially located under a respective first trench in the vertical direction.

[0134] Example A21. Trench JFET according to Example A19 or A20, wherein a vertical extent of the superjunction structure is in the range of 50% to 2000% of a vertical extent of the first and second trenches.

[0135] Example A22. Trench JFET according to one of the examples A1 to A21, which further includes a source region of the second conductivity type located on one of the opposite side walls of the mesa region adjacent to the second trench.

[0136] Example A23. Trench JFET according to one of the examples A1 to A22, further comprising a second mesa region, wherein the second mesa region is wider than the first mesa region and wherein the second trench is laterally bounded by the first mesa region and the second mesa region.

[0137] Example A24. Trench JFET according to one of the examples A1 to A23, wherein an extent of the mesa region along the first lateral direction is in the range of 200 nm to 2 µm.

[0138] Example A25. Trench JFET according to one of Examples A1 to A24, wherein along the first lateral direction the mesa canal region comprises a first, a second and a third mesa canal subregion having equal extent along the first lateral direction, and wherein a first-constantly averaged concentration of dopants of the first conductivity type in the second mesa canal subregion is greater than a first-constantly averaged concentration of dopants of the first conductivity type in each of the first and third mesa canal subregions.

[0139] Example B1. Trench junction field-effect transistor, trench JFET, comprising: a mesa region bounded by first and second trenches along a first lateral direction, the first and second trenches extending from a first surface of the semiconductor body into a semiconductor body; a mesa channel region of a first conductivity type bounded along the first lateral direction by a first and a second control region of a second conductivity type, wherein a first pn junction is defined by the mesa channel region and the first control region, and a second pn junction is defined by the mesa channel region and the second control region, and wherein the first control region is electrically coupled to a source contact and the second control region is electrically coupled to a gate contact.

[0140] Example B2. Trench JFET according to Example B1, wherein the first trench comprises a dielectric trench-filling structure.

[0141] Example B3. Trench junction field-effect transistor, trench JFET, comprising: a mesa region bounded by first and second trenches along a first lateral direction, the first and second trenches extending from a first surface of the semiconductor body into a semiconductor body; a mesa channel region of a first conductivity type bounded along the first lateral direction by a first and a second control region of a second conductivity type, a first pn junction defined by the mesa channel region and the first control region, and a second pn junction defined by the mesa channel region and the second control region, and each of the first and second trenches comprising a gate or source electrode and a ground electrode, the gate or source electrode being located between the ground electrode and the first surface.

[0142] Example B4. Trench JFET according to Example B3, which further comprises a dielectric separation region located between the bottom electrode and the gate electrode.

[0143] Example B5. Trench JFET according to one of the examples B1 to B4, wherein the first and second control regions are each subdivided into an upper part and a lower part, the upper part and the lower part being vertically separated from each other by an intermediate separation region of the first conductivity type.

[0144] Example B6. Trench JFET according to Example B5, wherein the intermediate separation region borders the dielectric separation region along the first lateral direction.

[0145] Example B7. Trench JFET according to one of Examples B1 to B6, further comprising a first conductive lining on a side wall section of at least one of the first and second trenches, wherein the first conductive lining is arranged laterally between a trench fill material in the at least one of the first and second trenches and a corresponding one of the first and second control area.

[0146] Example B8. Trench JFET according to one of Examples B1 to B7, further comprising a second conductive lining on a soil section of at least one of the first and second trenches, wherein the second conductive lining is arranged vertically between a trench fill material in the at least one of the first and second trenches and a corresponding one of the first and second control area.

[0147] Example B9. Trench JFET according to one of the examples B1 to B8, further comprising a superjunction structure located between a bottom side of the first and second trenches and a second surface of the semiconductor body opposite the first surface.

[0148] Example B10. Trench JFET according to Example B9, wherein the superjunction structure comprises a first SJ region of the first conductivity type and a second SJ region of the second conductivity type, wherein the first SJ region is electrically coupled to a drain contact on the second surface of the semiconductor body and to the source contact on the first surface of the semiconductor body, and the second SJ region is electrically coupled to the first and second control regions.

[0149] Example B11. Trench JFET according to one of the examples B1 to B10, wherein a vertical extent of the superjunction structure is in the range of 50% to 2000% of a vertical extent of the first and second trenches.

[0150] Example B12. Trench JFET according to one of the examples B1 to B11, which further comprises a source region of the second conductivity type located on one of the opposite side walls of the mesa region adjacent to the second trench.

[0151] Example B13. Trench JFET according to one of the examples B1 to B12, further comprising a second mesa region, wherein the second mesa region is wider than the first mesa region and wherein the second trench is laterally bounded by the first mesa region and the second mesa region.

[0152] Example B14. Trench JFET according to one of the examples B1 to B13, wherein the extent of the mesa region along the first lateral direction is in the range of 200 nm to 2 µm.

[0153] Example B15. Trench JFET according to one of Examples B1 to B14, wherein along the first lateral direction the mesa canal region comprises a first, a second and a third mesa canal subregion having equal extent along the first lateral direction, and wherein a first-conductivity-type dopants averaged along the first lateral direction in the second mesa canal subregion is greater than a first-conductivity-type dopants averaged along the first lateral direction in each of the first and third mesa canal subregions.

[0154] The aspects and features mentioned and described along with one or more of the previously described examples and figures can also be combined with one or more of the other examples to replace an identical feature of the other example or to additionally introduce the feature into the other example.

[0155] Although specific embodiments have been presented and described herein, it will be obvious to those skilled in the art that a multitude of alternative and / or equivalent implementations can replace the specific embodiments shown and described without altering the scope of protection of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] Trench junction field-effect transistor, JFET, (100) which features: a mesa region (103) bounded by a first and a second trench (1061, 1062) spaced apart in a first lateral direction (x1) of a semiconductor body (102), wherein the first and the second trench (1061, 1062) extend from a first surface (108) into the semiconductor body (102); a mesa canal region (104) of a first conductivity type (103); a first control area (1101) of a second conductivity type, which is complementary to the first conductivity type, which is located in the mesa area (103) adjacent to the first trench (1061); and a second control area (1102) of the second conductivity type, which is located in the mesa area (103) adjacent to the second trench (1062), wherein the mesa canal area (104) is arranged in the first lateral direction (x1) between the first control area (1101) and the second control area (1102), and wherein the first control area (1101) is electrically coupled to a source contact (S) and the second control area (1102) is electrically coupled to a gate contact (G). [2] Trench JFET according to claim 1, wherein a first pn transition is arranged between the Mesa Canal area (104) and the first control area (1101), and wherein a second pn crossing (1122) is arranged between the Mesa Canal area (104) and the second control area (1102). [3] Trench JFET according to claim 1, wherein the Mesa Canal area (104) is spaced from the first steering area (1101) in the first lateral direction (x1), and / or wherein the Mesa Canal area (104) is spaced from the second steering area (1102) in the first lateral direction (x1). [4] Trench JFET according to claim 3, wherein a semiconductor region (105) with a lower doping concentration than either of the mesa channel region (104) and the first control region (1101) is arranged between the mesa channel region (104) and the first control region (1101), and / or wherein a semiconductor region (105) with a lower doping concentration than either of the mesa channel region (104) and the second control region (1102) is arranged between the mesa channel region (104) and the second control region (1102). [5] Trench JFET according to any one of claims 1 to 4, wherein the mesa canal region (104) has a first mesa canal region (1045) and a second mesa canal region (1046) which are spaced apart from each other in the first lateral direction (x1), wherein the first Mesa Canal area (1045) is located adjacent to the first control area (1101), and the second Mesa Canal area (1046) is located adjacent to the second control area (1102). [6] Trench JFET according to one of the preceding claims, wherein the first trench (1061) has a dielectric trench-filling structure. [7] Trench junction field-effect transistor, trench JFET (100) which features: a mesa region (103) bounded by a first and a second trench (1061, 1062) along a first lateral direction (x1), wherein the first and the second trench (1061, 1062) extend from a first surface (108) of the semiconductor body (102) into a semiconductor body (102); a mesa canal region (104) of a first conductivity type; a first control area (1101) of a second conductivity type complementary to the first conductivity type, which is located in the mesa area (103) adjacent to the first trench (1061); and a second control area (1102) of the second conductivity type, which is located in the mesa area (103) adjacent to the second trench (1062), wherein the mesa canal area (104) is arranged in the first lateral direction (x1) between the first control area (1101) and the second control area (1102), and wherein the first and second trenches (1061, 1062) each comprise a gate or source electrode (1131, 1132) and a bottom electrode (1141, 1142), wherein the gate or source electrode (1131, 1132) is arranged between the bottom electrode (1141, 1142) and the first surface (108). [8] Trench JFET according to claim 7, further comprising a dielectric separation region (1161, 1162) arranged between the bottom electrode (1141, 1142) and the gate electrode (1131, 1132). [9] Trench JFET according to claim 7 or 8, wherein the first and second control region (1101, 1102) are each divided into an upper part (1104) and a lower part (1105), wherein the upper part (1104) and the lower part (1105) are vertically spaced apart from each other by an intermediate separation region (1151, 1152) of the first conductivity type. [10] Trench JFET according to claim 9, wherein the intermediate separation region (1151, 1152) borders the dielectric separation region (1141, 1142) along the first lateral direction (x1). [11] Trench JFET according to one of the preceding claims, further comprising a first conductive lining (1171, 1172) on a side wall section of the first and / or the second trench (1061, 1062), wherein the first conductive lining (1171, 1172) is arranged laterally between a trench fill material in the first and / or the second trench (1061, 1062) and a corresponding one of the first and the second control area (1101, 1102). [12] Trench JFET according to one of the preceding claims, further comprising a second conductive lining (1181, 1182) on a bottom section of the first and / or the second trench (1061, 1062), wherein the second conductive lining (1181, 1182) is arranged vertically between a trench fill material in the first and / or the second trench (1061, 1062) and a corresponding one of the first and the second control area (1101, 1102). [13] Trench JFET according to one of the preceding claims, further comprising a superjunction, SJ, structure (120) arranged between a bottom side of the first and second trench (1061, 1062) and a second surface (109) of the semiconductor body (102) opposite the first surface (108). [14] Trench JFET according to claim 13, wherein the superjunction structure (120) comprises a first SJ area (121) of the first conductivity type, which is arranged between two second SJ areas (122) of the second conductivity type, wherein the first SJ area (121) is electrically coupled to a drain contact (D) on the second surface (109) of the semiconductor body (102) and to the source contact (S) on the first surface (108) of the semiconductor body (102), wherein one of the two second SJ areas (122) is electrically coupled to the first control area (1101), and the other of the two second SJ areas (122) is electrically coupled to the second control area (1102). [15] Trench JFET according to claim 13, wherein the superjunction structure (120) has a first SJ area (121) of the first conductivity type and a second SJ area (122) of the second conductivity type, which are arranged next to each other in the first lateral direction (x1), wherein the first SJ area (121) is electrically coupled between the mesa canal area (104) and a drain area (130) of the first conductivity type, wherein the second SJ area is electrically coupled to the first control area (1101) and is separated from the second control area (1102). [16] Trench JFET according to claim 15, wherein the mesa channel region (104) is arranged in a vertical direction (z) of the semiconductor body (102) next to a section of the first SJ region (121) and a section of the second SJ region (122). [17] Trench JFET according to claim 16, wherein the Mesa Canal area (104) comprises a first Mesa Canal area (1045) located adjacent to the first control area (1101) and a second Mesa Canal area (1046) located adjacent to the second control area (1102), wherein the first and second mesa canal regions (1045, 1046) are spaced apart from each other in the first lateral direction (x1), wherein the first mesa canal area (1045) is arranged in the vertical direction (z) next to a section of the second SJ area (122), and wherein the second Mesa Canal area (1046) is arranged in the vertical direction (z) next to a section of the first SJ area (122). [18] Trench JFET according to any one of claims 14 to 17, wherein the JFET has multiple first and second trenches (1061, 1062) arranged alternately in the first lateral direction (x1) and multiple first and second SJ areas (121, 122) arranged alternately in the first lateral direction (x1). [19] Trench JFET according to claim 18, wherein each first SJ area (121) is arranged in the vertical direction (z) under a respective second trench (1062), and wherein every second SJ area (122) is arranged in the vertical direction (z) under a respective first trench (1062). [20] Trench JFET according to claim 18, wherein two first SJ areas (121) are arranged side by side, spaced apart from each other in the first lateral direction (x1) and at least partially located under a respective second trench (1062) in the vertical direction (z), and wherein two second SJ areas (121) are arranged side by side, spaced apart from each other in the first lateral direction (x1) and at least partially located under a respective first trench (1062) in the vertical direction (z). [21] Trench JFET according to one of the two preceding claims, wherein a vertical extent (t1) of the superjunction structure (120) is in the range of 50% to 2000% of a vertical extent (t2) of the first and second trench (1061, 1062). [22] Trench JFET according to one of the preceding claims, further comprising a source region (124) of the second conductivity type arranged on one of opposite side walls of the mesa region (103) adjacent to the second trench (1062). [23] Trench JFET according to one of the preceding claims, further comprising a second mesa region, wherein the second mesa region is wider than the mesa region (103) and wherein the second trench is laterally bounded by the mesa region (103) and the second mesa region. [24] Trench JFET according to one of the preceding claims, wherein an extent (wm) of the mesa region (103) along the first lateral direction (x1) is in the range of 200 nm to 2 µm. [25] Trench JFET according to one of the preceding claims, wherein along the first lateral direction (x1) the mesa canal region (104) comprises a first, a second and a third mesa canal subregion (1041, 1042, 1043) having an equal extent (w) along the first lateral direction (x1), and wherein a concentration of dopants of the first conductivity type averaged along the first lateral direction (x1) in the second mesa canal subregion (1042) is greater than a concentration of dopants of the first conductivity type averaged along the first lateral direction (x1) in each of the first and third mesa canal subregions (1041, 1043).

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