Semiconductor device, semiconductor module and wireless communication device

Abstract

A semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer opposite the substrate; a first semiconductor layer partially buried in the surface of the channel layer opposite the substrate and in contact with the barrier layer at least a portion of a side surface; and a second semiconductor layer provided on top of the first semiconductor layer and having a higher charge carrier concentration than the first semiconductor layer.

Description

Technical field

[0001] The present disclosure relates to a semiconductor device, a semiconductor module and a wireless communication device. State of the art

[0002] Patent literature 1 discloses, for example, a transistor with a multilayer structure in which a nitride-based channel layer and a barrier layer are formed on a substrate in that order. The barrier layer is provided with a contact recess in which a contact area of ​​the channel layer is exposed. A contact layer is formed in the exposed contact area of ​​the channel layer, and an ohmic contact is thereby formed on the contact layer. Citation list of patent literature

[0003] Patent literature 1: Japanese publication (translation of PCT application no.) 2007-538402 Summary of the invention

[0004] It is now desirable to improve the output power and efficiency of a high electron mobility transistor (HEMT), which is widely used as a mobile phone terminal or power amplifier for a base station.

[0005] It is therefore desirable to provide a semiconductor device, a semiconductor module, and a wireless communication device with high output power and high efficiency.

[0006] A semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer opposite the substrate; a first semiconductor layer partially buried in the surface of the channel layer opposite the substrate and in contact with the barrier layer at least a portion of a side surface; and a second semiconductor layer provided on top of the first semiconductor layer and having a higher charge carrier concentration than the first semiconductor layer.

[0007] A semiconductor module according to an embodiment of the present disclosure comprises the semiconductor device according to the embodiment of the present disclosure described above.

[0008] A wireless communication device according to the present disclosure comprises the semiconductor device according to the embodiment described above in the present disclosure.

[0009] The semiconductor device according to one embodiment of the present disclosure, the semiconductor module according to one embodiment, and the wireless communication device according to one embodiment each have a multilayer structure in which the channel layer and the barrier layer are stacked on a surface of the substrate in that order. The multilayer structure comprises the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is partially embedded in a surface of the channel layer facing the substrate and is in contact with the barrier layer on at least part of a side face. The second semiconductor layer is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer. This reduces the contact resistance between the channel layer and an electrode formed on the second semiconductor layer. Brief description of the drawings Fig. Figure 1 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to an embodiment of the present disclosure. Fig. 2A is a schematic cross-sectional diagram illustrating an exemplary manufacturing process of the in Fig. 1 illustrated semiconductor device illustrated. Fig. 2B is a schematic cross-sectional diagram that shows one step after Fig. 2A illustrates this. Fig. 2C is a schematic cross-sectional diagram that represents one step after Fig. 2B illustrates this. Fig. 2D is a schematic cross-sectional diagram that represents one step after Fig. 2C illustrates. Fig. 2E is a schematic cross-sectional diagram that represents one step after Fig. Illustrated in 2D. Fig. Figure 3 is a schematic cross-sectional diagram illustrating a configuration of a semiconductor device according to a comparative example. Fig. Figure 4 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 1 of the present disclosure. Fig. Figure 5 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 2 of the present disclosure. Fig. Figure 6 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 3 of the present disclosure. Fig. Figure 7 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to modification example 4 of the present disclosure. Fig. Figure 8 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 5 of the present disclosure. Fig. Figure 9 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 6 of the present disclosure. Fig. Figure 10 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to modification example 7 of the present disclosure. Fig. Figure 11 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 8 of the present disclosure. Fig. Figure 12 is a schematic cross-sectional diagram illustrating an exemplary configuration of a semiconductor device according to Modification Example 9 of the present disclosure. Fig. Figure 13 is a schematic perspective diagram illustrating a configuration of a semiconductor module. Fig. Figure 14 is a block diagram illustrating a configuration of a wireless communication device. Modes for carrying out the invention

[0010] Some embodiments of the present disclosure are described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the embodiments described below. Furthermore, the present disclosure is not limited to the embodiments described below with respect to arrangements, dimensions, dimensional ratios, and the like of components illustrated in each of the drawings.

[0011] Please note that the description is given in the following order. 1. Embodiment (an example of a semiconductor device comprising a contact layer partially buried in a channel layer and having a stacked structure in which a charge carrier concentration gradually increases from the channel layer) 1-1. Configuration of a semiconductor device 1-2. Manufacturing process of a semiconductor device 1-3. Functions and Effects 2. Modification Examples 2-1. Modification example 1 (another example of the semiconductor device) 2-2. Modification example 2 (another example of the semiconductor device) 2-3. Modification example 3 (another example of the semiconductor device) 2-4. Modification Example 4 (another example of the semiconductor device) 2-5. Modification Example 5 (another example of the semiconductor device) 2-6. Modification example 6 (another example of the semiconductor device) 2-7. Modification example 7 (another example of the semiconductor device) 2-8. Modification example 8 (another example of the semiconductor device) 2-9. Modification example 9 (another example of the semiconductor device) 3. Application examples 3-1. Application example for a semiconductor module 3-2. Application example for a wireless communication device <1. Implementation>[1-1. Configuration of a semiconductor device]

[0012] Fig. Figure 1 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1) according to an embodiment of the present disclosure.

[0013] The semiconductor device 1 has a stacked structure in which a substrate 11, a channel layer 12, and a barrier layer 13 are stacked in that order. The semiconductor device 1 further comprises a contact layer 14, which is buried from a surface (surface 13S2) of the barrier layer 13 to the channel layer 12. Surface 13S2 faces a surface (surface 13S1) of the barrier layer 13 opposite the channel layer 12. The contact layer 14 comprises a first contact layer 14A and a second contact layer 14B. The first contact layer 14A is partially buried in the channel layer 12 and is in contact with the barrier layer at part of one of its side faces. The second contact layer 14B is provided on top of the first contact layer 14A and has a higher charge carrier concentration than the first contact layer 14A.The semiconductor device 1 further comprises a gate electrode G, a source electrode S, a drain electrode D, and an insulating film Z. The semiconductor device 1, for example, has a Schottky gate electrode structure. The gate electrode G and the insulating film Z are provided on the barrier layer 13, and the source electrode S and the drain electrode D are each provided on the contact layer 14.

[0014] The semiconductor device 1 according to the present embodiment is a high electron mobility transistor (HEMT) comprising a two-dimensional electron gas layer 2DEG as a channel. The two-dimensional electron gas layer 2DEG is generated due to a difference between the polarization magnitude of the channel layer 12 and the polarization magnitude of the barrier layer 13. The two-dimensional electron gas layer 2DEG is generated, for example, near an interface K1 of the channel layer 12 between the channel layer 12 and the barrier layer 13.

[0015] The substrate 11 is a support for the semiconductor device 1. The substrate 11 is, for example, a Si (silicon) substrate. Preferably, the Si substrate is, for example, a monocrystalline Si(111) substrate with a (111) surface as the main surface.

[0016] Channel layer 12 comprises a nitride semiconductor with a band gap smaller than that of barrier layer 13. Channel layer 12 is configured to accumulate charge carriers at an interface near barrier layer 13 due to the difference between the polarization magnitude of channel layer 12 and barrier layer 13.

[0017] The channel layer 12 comprises epitaxially grown gallium nitride (GaN). The channel layer 12 may comprise undoped u-GaN to which no impurities have been added. The channel layer 12 preferably has a thickness greater than or equal to 10 nm and less than or equal to 200 nm. The total thickness of the channel layer 12 and a buffer layer described below is preferably greater than or equal to 1000 nm and less than or equal to 3000 nm.

[0018] Barrier layer 13 comprises a nitride semiconductor with a band gap larger than that of channel layer 12. Barrier layer 13 is configured to accumulate charge carriers in a region of channel layer 12 near barrier layer 13 due to spontaneous or piezoelectric polarization. Accordingly, semiconductor device 1 is configured to form a two-dimensional electron gas layer 2DEG with high mobility and a high charge carrier concentration in the region near the interface K1 of channel layer 12 between channel layer 12 and barrier layer 13.

[0019] Barrier layer 13 comprises Al x2 In y2 Ga( 1-x2-y2 )N (0 ≤ x2 ≤ 1, 0 ≤ y2 ≤ 1), which is a nitride semiconductor that has grown epitaxially. For example, the barrier layer 13 can be undoped u-Al x2 In (1-x2The barrier layer 13 comprises AlInN, which, for example, has grown epitaxially. In this case, it is possible that the barrier layer 13 exhibits a small lattice mismatch with GaN, thereby providing a superior monocrystalline crystal.

[0020] The barrier layer 13 preferably has a thickness greater than or equal to 2.0 nm and less than or equal to 20 nm. In this case, the barrier layer 13 can more effectively control the band profile of the semiconductor device 1. It is therefore possible to further increase the charge carrier density of the two-dimensional electron gas layer 2DEG generated in the channel layer 12.

[0021] The semiconductor device 1 can include a further layer between the substrate 11 and the channel layer 12 and between the channel layer 12 and the barrier layer 13.

[0022] For example, a buffer layer can be provided between substrate 11 and channel layer 12. The buffer layer is configured, for example, to mitigate a mismatch between the lattice constant of substrate 11 and the lattice constant of channel layer 12. Accordingly, in a case where the buffer layer is provided, substrate 11 can comprise a material with a lattice constant that differs from the lattice constant of channel layer 12. The buffer layer might comprise, for example, GaN, AlGaN, or AlN.

[0023] A spacer layer comprising a nitride semiconductor with a band gap larger than that of channel layer 12 can, for example, be provided between channel layer 12 and barrier layer 13. The spacer layer is configured, for example, to reduce alloy scattering between channel layer 12 and barrier layer 13 and to suppress a reduction in charge carrier mobility of the two-dimensional electron gas layer 2DEG caused by alloy scattering. The spacer layer comprises, for example, AlN, AlGaN, or AlInGaN.

[0024] The charge carrier density of the two-dimensional electron gas layer 2DEG can be controlled, for example, based on a band profile of each layer from the barrier layer 13 to the channel layer 12. One factor that determines the charge carrier density of the two-dimensional electron gas layer 2DEG is the height of a conduction band minimum of the barrier layer 13.

[0025] The polarization of each layer increases when each layer, for example, contains an Al composition with a higher rate. Consequently, the slope of the conduction band minimum increases. Furthermore, the height of the conduction minimum increases with increasing thickness of each layer. Therefore, it is possible to increase the charge carrier density of the two-dimensional electron gas layer 2DEG by appropriately controlling the thickness and composition of each layer from barrier layer 13 to channel layer 12 and by controlling the height of the conduction band minimum of barrier layer 13.

[0026] The contact layer 14 forms part of a current path between the source electrode S and the drain electrode D, which are arranged with the gate electrode G in between. As shown in Fig. As illustrated in Figure 1, the contact layer 14 is provided under each of the source electrode S and the drain electrode D, which are arranged with the gate electrode G in between.

[0027] The contact layer 14 has a lower surface located within the channel layer 12 and an upper layer located above the surface 13S2 of the barrier layer 13. The contact layer 14 comprises, for example, gallium nitride (GaN) and silicon (Si) as a dopant.

[0028] The contact layer 14 has a multilayer structure in which the first contact layer 14A and the second contact layer 14B are stacked in that order from the channel layer 12. Here, the first contact layer 14A corresponds to a specific example of a “first semiconductor layer” according to an embodiment of the present disclosure. The second contact layer 14B corresponds to a specific example of a “second semiconductor layer” according to an embodiment of the present disclosure. The contact layer 14 is formed by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), or sputtering.

[0029] The first contact layer 14A comprises a nitride semiconductor with a charge carrier concentration that is lower than that of the second contact layer 14B. For example, the first contact layer 14A has a charge carrier concentration within a range greater than or equal to 10 18 cm -3 and less than or equal to 10 21 cm -3 on.

[0030] The second contact layer 14B comprises a nitride semiconductor with a higher charge carrier concentration than that of the first contact layer 14A. For example, the second contact layer 14B has a charge carrier concentration within a range greater than 10 18 cm -3 and less than or equal to 10 21 cm -3 on.

[0031] The first contact layer 14A is partially buried in the channel layer 12 and is in contact with the barrier layer 13 at one side face. The second contact layer 14B is stacked on top of the first contact layer 14A. In other words, an interface K2 is located between the first contact layer 14A and the second contact layer 14B above the channel layer 12. The first contact layer 14A preferably has a thickness greater than or equal to 3 nm and less than or equal to 200 nm to allow the portion of the side face to be in contact with the barrier layer 13, as described above. For example, the first contact layer 14A has a thickness of 20 nm. The second contact layer 14B preferably has a thickness that allows an upper surface of the second contact layer 14B to be formed above the surface 13S2 of the barrier layer 13.The combined thickness of the first contact layer 14A and the second contact layer 14B is, for example, approximately 100 nm. The contact layer 14 preferably has a thickness greater than or equal to 10 nm and less than or equal to 100 nm. For example, the contact layer 14 has a thickness of 100 nm.

[0032] Each of the gate electrode G, source electrode S, and drain electrode D comprises an electrically conductive material. The gate electrode G is positioned between the source electrode S and the drain electrode D. The gate electrode G is a Schottky gate in contact with the nitride semiconductor contained in the barrier layer 13, excluding the insulating film Z, thus forming a Schottky junction. For example, the gate electrode G can have a two-layer structure in which a nickel (Ni) layer and a gold (Au) layer are stacked on the barrier layer 13 in that order. The source electrode S and the drain electrode D can each have a structure in which a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer are stacked on the contact layer 14 in that order.

[0033] The insulating film Z comprises an insulating material. The insulating film Z is provided to cover an area of ​​the surface 13S2 of the barrier layer 13 that is not covered by the gate electrode G. Examples of the component material of the insulating film Z include aluminum oxide (Al₂O₃), silicon dioxide (SiO₂), silicon nitride (Si₃N₄), or hafnium oxide (HfO₂). The insulating film Z can be a monolayer film comprising the component material described above, or a multilayer film comprising layers comprising the component materials described above. [1-2. Manufacturing process of a semiconductor device]

[0034] Next, an exemplary manufacturing process of the semiconductor device 1 according to the present embodiment will be described with reference to Fig. 2A to Fig. 2E described. Fig. 2A to Fig. Figure 2E are schematic cross-sectional diagrams illustrating the steps of the manufacturing process of semiconductor device 1.

[0035] First, as in Fig. Figure 2A illustrates the sequential epitaxial growth of the channel layer 12 and the barrier layer 13 on the substrate 11. It should be noted that in an example described below, a Si substrate is used as the substrate 11.

[0036] For example, the Si substrate with a (111) surface as the main surface is set up in a MOCVD apparatus and subjected to thermal cleaning at approximately 1000°C for ten minutes. Furthermore, if the Si substrate is used, a buffer layer can be formed on the Si substrate. The buffer layer is formed, for example, by epitaxial growth of GaN, AlGaN, or AlN to a thickness of 100 nm to 2000 nm at approximately 900°C to 1000°C. Subsequently, the channel layer 12 is formed, for example, by epitaxial growth of GaN to a thickness of 100 nm to 2000 nm at approximately 900°C to 1100°C. Next, the barrier layer 13 is formed on the channel layer 12, for example by epitaxial growth of AlInN to a thickness of about 1 nm to 10 nm at 700°C to 900°C.

[0037] Next, as in Fig. Figure 2B illustrates how SiN, SiO2, Al2O3, or the like are deposited on the barrier layer 13 to form an insulating film Z'. Then, as shown in Fig. Figure 2C illustrates the selective removal of portions of the insulating film Z', barrier layer 13, and channel layer 12 in respective regions corresponding to the source electrode S and drain electrode D, using a resist pattern with openings. This means that only those regions of barrier layer 13 and insulating film Z' where the source electrode S and drain electrode D are to be formed are selectively removed to a depth reaching the center of channel layer 12. As a result, holes H1 are formed, and portions of channel layer 12 are exposed.

[0038] Then, as in Fig. Figure 2D illustrates a GaN layer with n-type conductivity, grown, for example, by MOCVD or sputtering, and the first contact layer 14A and the second contact layer 14B are formed sequentially. At this stage, silicon is used as a dopant, and the dopant concentration is adjusted such that the charge carrier concentration of the second contact layer 14B is higher than that of the first contact layer 14A. This results in a device with low on-resistance (Ron).

[0039] Next, the insulating film Z' on the barrier layer 13 is removed, after which a Ti layer, an Al layer, a Ni layer, and an Au layer are selectively stacked sequentially on a contact layer 14 in the respective regions corresponding to the source electrode S and the drain electrode D, using a resist pattern with openings. The resist pattern is then removed. Next, the insulating film Z is formed, and the insulating film Z is selectively removed in the respective regions corresponding to the source electrode S, the drain electrode D, and the gate electrode G, using a resist pattern with openings. That is, as in Fig. As illustrated in Figure 2E, portions of the insulating film Z, which are formed on the source electrode S and the drain electrode D, and a portion of the insulating film Z, in which the gate electrode G is to be formed, are selectively removed. The resist pattern is then removed, after which a Ni layer and an Au layer are selectively stacked sequentially on the exposed barrier layer 13 in the region corresponding to the gate electrode G, using a resist pattern with openings for the formation of the gate electrode G. The resist pattern is then removed.

[0040] The semiconductor device 1 according to the in Fig. The embodiment illustrated in point 1 is formed by the steps described above. [1-3. Functions and Effects]

[0041] Recently, research and development have become active for a HEMT incorporating a nitride semiconductor. The nitride semiconductor has a larger bandgap than Si, GaAs, or similar materials and exhibits a specific hexagonal polarization. Therefore, the HEMT incorporating the nitride semiconductor is expected to be a low-resistance, high-voltage, high-speed transistor.

[0042] In particular, the HEMT is expected to be applied to a power device, a radio frequency (RF) device, or the like. For example, a HEMT incorporating an AlGaN barrier layer has been used practically in base stations for satellite or wireless communications. A HEMT incorporating an AlInN barrier layer has a two-dimensional electron gas concentration that is higher than that of the HEMT incorporating the AlGaN barrier layer, and it is therefore expected to have a further higher output power.

[0043] Meanwhile, a HEMT comprising a nitride semiconductor increases the contact resistance (Rc) between a resistive electrode and a barrier layer in a case where the resistive electrode is formed directly on the barrier layer. One way to address this problem involves, as described in Fig. Figure 3 illustrates the formation of a semiconductor layer (contact layer 114) comprising Si or the like as a dopant, directly beneath the source electrode S and the drain electrode D, which are ohmic electrodes, in the semiconductor device 100 in which the substrate 111, the channel layer 112 and the barrier layer 113 are stacked.

[0044] This method is expected to reduce Rc when the doping concentration of the contact layer 114 is increased. However, the doping concentration has an upper limit, and therefore a reduction in Rc greater than a certain level is not expected.

[0045] In contrast, in the multilayer structure according to the present embodiment, in which the channel layer 12 and the barrier layer 13 are stacked on the substrate 11 in that order, the contact layer 14 is formed, which has the lower surface located within the channel layer 12 and the upper surface located above the surface 13S2 of the barrier layer 13. The contact layer 14 has a multilayer structure in which the first contact layer 14A and the second contact layer 14B, which have a higher charge carrier concentration than the first contact layer 14A, are formed in that order by the channel layer 12. The first contact layer 14A is embedded in the channel layer 12 and is in contact with the barrier layer 13 at part of a side surface.This reduces the contact resistance of the channel layer 12 and the contact layer 14 (especially the first contact layer 14A) and the contact resistance of the ohmic electrodes (especially the source electrode S and the drain electrode D) provided on the contact layer 14 and the contact layer 14 (especially the second contact layer 15B).

[0046] According to the semiconductor device 1 of the above described embodiment, it is possible to achieve a higher output power and higher efficiency than a HEMT comprising a general nitride semiconductor.

[0047] Next, Modification Examples 1 to 9, practical examples, and application examples of the present disclosure are described. It should be noted that components corresponding to those of the semiconductor device according to the embodiment described above are designated with the same reference numerals to omit their description. <2. Modification Examples>(2-1. Modification Example 1)

[0048] Fig. Figure 4 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1A) according to modification example 1 of the present disclosure.

[0049] In the example described in the preceding embodiment, the interface K2 between the first contact layer 14A and the second contact layer 14B is formed above the channel layer 12. However, in the semiconductor device 1A according to the present modification example, the interface K2 between the first contact layer 14A and the second contact layer 14B is formed above the surface 13S2 of the barrier layer 13.

[0050] Similar effects to those described above are also available in this configuration. (2-2. Modification example 2)

[0051] Fig. Figure 5 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1B) according to modification example 2 of the present disclosure.

[0052] In the example described in the preceding embodiment, the second contact layer 14B is stacked directly onto the first contact layer 14A. However, in the semiconductor device 1B according to the present modification example, a mask layer 15 is formed between the first contact layer 14A and the second contact layer 14B.

[0053] The mask layer 15 modifies the growth state of the second contact layer 14B. The mask layer 15 can be formed with a density of less than 100% at the interface between the first contact layer 14A and the second contact layer 14B. For example, as in Fig. Figure 5 illustrates the mask layer 15 forming an island shape on the first contact layer 14A. A component material of the mask layer 15 is an insulating material or an electrically conductive material. Examples of insulating materials include SiO2 and silicon nitride (Si3N4).

[0054] In a case where the mask layer 15 is formed between the first contact layer 14A and the second contact layer 14B, the second contact layer 14B can, for example, grow epitaxially in an island shape on the first contact layer 14A, exposed by the mask layer 15. This increases the concentration of a dopant (e.g., Si) to be doped into the second contact layer 14B. Furthermore, the surface roughness of the second contact layer 14B increases, which increases the contact area between the source electrode S and the drain electrode D formed on the second contact layer 14B and also reduces the contact resistance between the second contact layer 14B and the source electrode S, as well as the contact resistance between the second contact layer 14B and the drain electrode D.

[0055] In the semiconductor device 1B according to the present modification example, the mask layer 15 is formed between the first contact layer 14A and the second contact layer 14B. This allows the second contact layer 14B to be formed in an island configuration. This increases the charge carrier concentration of the second contact layer 14B and reduces the contact resistance between the second contact layer 14B and the source electrode S, as well as the contact resistance between the second contact layer 14B and the drain electrode D, compared to the embodiment described above. It is therefore possible to provide a semiconductor device with higher output power and higher efficiency. (2-3. Modification example 3)

[0056] Fig. Figure 6 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1C) according to modification example 3 of the present disclosure.

[0057] In the example described in the preceding embodiment, the contact layer 14 has a multilayer structure in which the first contact layer 14A and the second contact layer 14B, which have different charge carrier concentrations, are stacked. However, in the semiconductor device 1C of the present modification example, the charge carrier concentration increases continuously or gradually from the channel layer 12 to the source electrode S and the drain electrode D within the contact layer 14.

[0058] Similar effects to those of the embodiment described above are also available in this configuration. (2-4. Modification example 4)

[0059] Fig. Figure 7 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1D) according to modification example 4 of the present disclosure.

[0060] In the example described in the preceding embodiment, the contact layer 14 has a two-layer structure in which the first contact layer 14A and the second contact layer 14B, which have different charge carrier concentrations, are stacked. However, the semiconductor device 1D of the present modification example has a three-layer structure in which the first contact layer 14A, the second contact layer 14B, and a third contact layer 14C are stacked.

[0061] The third contact layer 14C comprises GaN similar to the first contact layer 14A and the second contact layer 14B. The third contact layer 14C comprises a nitride semiconductor with a higher charge carrier concentration than the second contact layer 14B. For example, the third contact layer 14C has a charge carrier concentration greater than or equal to 10 18 cm -3 and less than or equal to 10 21cm -3 on.

[0062] The contact layer 14 is not limited to the two-layer structure described above and can have a multi-layer structure comprising three or more layers. Similar effects to those of the embodiment described above are also obtainable in this configuration. (2-5. Modification example 5)

[0063] Fig. Figure 8 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1E) according to modification example 5 of the present disclosure.

[0064] In the example described in the preceding embodiment, the dopant included in contact layer 14 is silicon dioxide (Si). However, in the semiconductor device 1E according to the present modification example, contact layer 24 includes germanium (Ge) or oxygen (O) as a dopant. The first contact layer 24A and the second contact layer 24B each have a dopant concentration (charge carrier concentration) within a range greater than or equal to 10⁻⁵. 18 cm -3 and less than or equal to 10 21 cm -3 similar to the embodiment described above.

[0065] Similar effects to those of the embodiment described above are also available in this configuration. (2-6. Modification example 6)

[0066] Fig. Figure 9 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1F) according to modification example 6 of the present disclosure.

[0067] In the example described in the preceding embodiment, the contact layer 14 comprises gallium nitride (GaN). In the semiconductor device 1F according to the present modification example, the contact layer 34 comprises Al x1 In y1 Ga( 1-x1-y1 )N (0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1, 0 ≤ x1 + y1 ≤ 1), which is a nitride semiconductor.

[0068] Similar effects to those of the embodiment described above are also available in this configuration. (2-7. Modification example 7)

[0069] Fig. Figure 10 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1G) according to modification example 7 of the present disclosure.

[0070] In the example described in the preceding embodiment, the barrier layer 13 comprises AlInN. However, in the semiconductor device 1G according to the present modification example, the barrier layer 23 comprises, for example, indium gallium nitride (InGaN), indium nitride (InN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), represented by Al x2 In y2 Ga( 1-x2-y2 )N (0 ≤ x2 ≤ 1, 0 ≤ y2 ≤ 1).

[0071] Similar effects to those of the embodiment described above are also available in this configuration. (2-8. Modification example 8)

[0072] Fig. Figure 11 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1H) according to modification example 8 of the present disclosure.

[0073] In the example described in the preceding embodiment, the channel layer 12 comprises GaN. However, in the semiconductor device 1H according to the present modification example, the channel layer 22 comprises Al. x3 Iny3Ga (1-x3-y3) N (0 ≤ x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 ≤ x3 + y3 ≤ 1).

[0074] For example, channel layer 22 can comprise one or more indium gallium nitride (InGaN), indium nitride (InN), aluminum gallium nitride (AlGaN), and aluminum indium gallium nitride (AlInGaN). Furthermore, channel layer 22 can have a stacked structure comprising multiple layers with different compositions. In these cases, channel layer 22 enables the suppression of charge carrier dispersion due to impurities. It is therefore possible to improve the charge carrier mobility of channel layer 22.

[0075] Similar effects to those of the embodiment described above are also available in this configuration. (2-9. Modification example 9)

[0076] Fig. Figure 12 schematically illustrates an exemplary cross-sectional configuration of a semiconductor device (semiconductor device 1I) according to modification example 9 of the present disclosure.

[0077] In the example described in the preceding embodiment, the substrate 11 is a Si substrate. However, in the semiconductor device 1I according to the present modification example, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a ZnO substrate, a ScAlMgO substrate, or the like is used as the substrate 21.

[0078] It should be noted that a semiconductor device 1 comprising a substrate that includes SiC or GaN exhibiting superior monocrystallisation capability than Si(111) and a lower thread dislocation density than Si(111) is expected to reduce leakage currents and withstand higher voltage. Accordingly, the substrate 21 may, for example, comprise a preferred material selected according to the intended use.

[0079] Similar effects to those of the embodiment described above are also available in this configuration. <3. Application Examples>(3-1. Semiconductor Module)

[0080] Next, a semiconductor module, which is a first application example of the technology according to the present disclosure, is described with reference to Fig. 13 described. Fig. Figure 13 is a schematic perspective diagram of a configuration of a semiconductor module 1000.

[0081] As in Fig. As illustrated in Figure 13, the semiconductor module 1000 is an integrated antenna module comprising, for example, a rim antenna 1020 and a variety of front-end components mounted as modules on a single chip 1050. For example, a variety of the rim antennas 1020 are formed in arrays on the chip 1050. The front-end components include, for example, a switch 1010, a low-noise amplifier 1041, a bandpass filter 1042, and a power amplifier 1043. The semiconductor module 1000 can be used, for example, as a transceiver for wireless communication.

[0082] The semiconductor module 1000 comprises, for example, the semiconductor device according to the embodiment described above or the like (e.g., the semiconductor device 1) as a transistor, which includes the switch 1010, the low-noise amplifier 1041, or the power amplifier 1043, and the like. For example, in fifth-generation (5G) mobile communication using electrical waves in a higher frequency band, the propagation loss of the electrical waves increases. It is therefore desirable for the semiconductor module 1000 to transmit electrical waves with higher electrical power for 5G. The semiconductor module 1000, which includes the semiconductor device 1, makes it possible to improve device characteristics and thus achieves high-performance, low-power, and high-reliability wireless communication. That is, it is possible to use the semiconductor module 1000 more preferentially with regard to 5G mobile communication. (3-2. Wireless communication device)

[0083] Next, a wireless communication device, which is a second application example according to the present disclosure, is described with reference to Fig. 14 described. Fig. Figure 14 is a block diagram illustrating a configuration of the Wireless Communications Equipment 2000.

[0084] As in Fig. As illustrated in Figure 14, the Wireless Communications Equipment 2000 comprises, for example, an antenna (ANT), an antenna switching circuit (2003), a high-power amplifier (HPA), an integrated radio frequency integrated circuit (RFIC), a baseband unit (BB), an audio output unit (MIC), a data output unit (DT), and an interface unit (I / F) (e.g., wireless local area network: WLAN) or Bluetooth. The Wireless Communications Equipment 2000 is a multifunctional mobile phone system that enables audio output, data communication, and LAN connectivity.

[0085] During transmission, the Wireless Communications Unit 2000 causes the Baseband Unit BB to output a transmit signal to the antenna ANT via the integrated RFIC, the high-power amplifier HPA, and an antenna switching circuit 203. Furthermore, during reception, the Wireless Communications Unit 2000 causes the Baseband Unit BB to receive a receive signal from the antenna ANT via the antenna switching circuit 2003 and the integrated RFIC. The signal processed at the Baseband Unit BB is then output, for example, by the audio output unit MIC, the data output unit DT, or the interface unit I / F to a device outside the Wireless Communications Unit 2000.

[0086] The wireless communication device 2000 comprises the semiconductor device (e.g., the semiconductor device 1) according to the embodiment described above as a transistor, which includes the antenna switching circuit 2003, the high-power amplifier HPA, the integrated radio frequency circuit RFIC, the baseband unit BB, or the like. This makes it possible to further improve the device characteristics of the wireless communication device 2000. It is therefore possible to carry out wireless communication with low power and high reliability.

[0087] The technology according to the present disclosure has been described with reference to the embodiment, modification examples 1 to 5, practical examples, and application examples. However, the technology of the present disclosure is not limited to the embodiments and the like described above and can be modified in many ways.

[0088] Furthermore, not all of the configurations and processes described in the embodiments are as essential as the configurations and processes of the present disclosure. For example, among the components in the embodiments, those components not described in the independent claim that specifies the main concepts of the present disclosure should be understood as optional components.

[0089] The terms used in this description and the accompanying claims should be interpreted as "non-restrictive". For example, the terms "have", "comprise" or "contain" should be interpreted as "not limited to the manner described as contained".

[0090] The terminology used here is solely for the sake of clarity and includes terminology not used to restrict configuration and operation. For example, terms like "top," "bottom," and the like simply indicate directions in the drawings to which reference is made. The same applies to similar terms and terms with the same meaning.

[0091] It should be noted that the effects described here are merely examples and are not limiting, and other effects may be provided.

[0092] It should be noted that the present technology can have the following configurations. According to the configurations of the present technology, the contact resistance between the channel layer and the electrode provided on the second semiconductor layer is reduced. It is therefore possible to provide a semiconductor device with high power and high efficiency. (1) Semiconductor device comprising the following: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer facing the substrate; a first semiconductor layer that is partially buried in the surface of the channel layer opposite the substrate and is in contact with the barrier layer on at least part of a side surface; and a second semiconductor layer that is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer. (2) Semiconductor device according to (1) comprising an interface between the first semiconductor layer and the second semiconductor layer located above the channel layer. (3) Semiconductor device according to (1) or (2), wherein the barrier layer has a first surface opposite the channel layer and a second surface opposite the first surface, and an interface between the first semiconductor layer and the second semiconductor layer is located between the first surface and the second surface. (4) Semiconductor device according to one of (1) to (3), wherein the barrier layer has a first surface opposite the channel layer and a second surface opposite the first surface, and an interface between the first semiconductor layer and the second semiconductor layer is located above the second surface of the barrier layer. (5) Semiconductor device according to one of (1) to (4) wherein the second semiconductor layer is formed in an island shape on the first semiconductor layer. (6) Semiconductor device according to any of (1) to (5), further comprising a mask layer between the first semiconductor layer and the second semiconductor layer. (7) Semiconductor device according to (6) in which the mask layer is formed in an island shape between the first semiconductor layer and the second semiconductor layer. (8) Semiconductor device according to (6) or (7) wherein the mask layer comprises an insulating material or an electrically conductive material. (9) Semiconductor device according to any of (1) to (8) wherein, when the first semiconductor layer and the second semiconductor layer are considered as one layer, a charge carrier concentration changes continuously or gradually to increase from a surface of the first semiconductor layer opposite the interface with the second semiconductor layer to a surface of the second semiconductor layer opposite the interface with the first semiconductor layer. (10) Semiconductor device according to any of (1) to (9) further comprising a third semiconductor layer provided on top of the second semiconductor layer and having a higher charge carrier concentration than the second semiconductor layer. (11) Semiconductor device according to any of (1) to (10) wherein the charge carrier concentrations of the first semiconductor layer and the second semiconductor layer are greater than or equal to 10 18 cm -3 and less than or equal to 10 21cm -3 are. Semiconductor device according to one of (1) to (11), wherein the first semiconductor layer and the second semiconductor layer each comprise one or more of silicon (Si), germanium (Ge) and oxygen (O) as a dopant. (13) Semiconductor device according to any of (1) to (12), wherein the first semiconductor layer and the second semiconductor layer are each Al x1 In y1 Ga( 1-x1-y1 )N (0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1). (14) Semiconductor device according to one of (1) to (13), wherein the barrier layer Al x2 In y2 Ga( 1-x2-y2 )N (0 ≤ x2 ≤ 1, 0 ≤ y2 ≤ 1) includes. (15) Semiconductor device according to one of (1) to (14), wherein the channel layer Al x3 In y3 Ga (1-x3-y3) N (0 ≤ x3 ≤ 1, 0 ≤ y3 ≤ 1) includes. (16) Semiconductor device according to any of (1) to (15), wherein the substrate comprises one or more of silicon (Si), sapphire, silicon carbide (SiC), gallium nitride (GaN) and aluminium nitride (AlN). (17) Semiconductor device according to one of (1) to (16), wherein the barrier layer has a first surface opposite the channel layer and a second surface opposite the first surface, and An insulating film, a gate electrode, a source electrode and a drain electrode are further provided on the second surface. (18) Semiconductor device according to (17), wherein paired stacked bodies, each comprising the first semiconductor layer and the second semiconductor layer, are arranged with the barrier layer positioned between them, the gate electrode is provided on the barrier layer, and The source electrode and the drain electrode are each provided on the paired stacked bodies with the gate electrode positioned between them. (19) Semiconductor module comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer facing the substrate; a first semiconductor layer that is partially buried in the surface of the channel layer opposite the substrate and is in contact with the barrier layer on at least part of a side surface; and a second semiconductor layer that is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer. (20) Wireless communication device comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer facing the substrate; a first semiconductor layer that is partially buried in the surface of the channel layer opposite the substrate and is in contact with the barrier layer on at least part of a side surface; and a second semiconductor layer that is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer.

Claims

[1] Semiconductor device comprising: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer facing the substrate; a first semiconductor layer that is partially buried in the surface of the channel layer opposite the substrate and is in contact with the barrier layer on at least part of a side surface; and a second semiconductor layer that is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer. [2] Semiconductor device according to claim 1, comprising an interface between the first semiconductor layer and the second semiconductor layer located above the channel layer. [3] Semiconductor device according to claim 1, wherein the barrier layer has a first surface opposite the channel layer and a second surface opposite the first surface, and an interface between the first semiconductor layer and the second semiconductor layer is located between the first surface and the second surface. [4] Semiconductor device according to claim 1, wherein the barrier layer has a first surface opposite the channel layer and a second surface opposite the first surface, and an interface between the first semiconductor layer and the second semiconductor layer is located above the second surface of the barrier layer. [5] Semiconductor device according to claim 1, wherein the second semiconductor layer is formed in an island shape on the first semiconductor layer. [6] Semiconductor device according to claim 1, further comprising a mask layer between the first semiconductor layer and the second semiconductor layer. [7] Semiconductor device according to claim 6, wherein the mask layer is formed in an island shape between the first semiconductor layer and the second semiconductor layer. [8] Semiconductor device according to claim 6, wherein the mask layer comprises an insulating material or an electrically conductive material. [9] Semiconductor device according to claim 1, wherein, when the first semiconductor layer and the second semiconductor layer are considered as one layer, a charge carrier concentration changes continuously or gradually to increase from a surface of the first semiconductor layer opposite the interface with the second semiconductor layer to a surface of the second semiconductor layer opposite the interface with the first semiconductor layer. [10] Semiconductor device according to claim 1, further comprising a third semiconductor layer provided on the second semiconductor layer and having a higher charge carrier concentration than the second semiconductor layer. [11] Semiconductor device according to claim 1, wherein the charge carrier concentrations of the first semiconductor layer and the second semiconductor layer are greater than or equal to 10 18 cm -3 and less than or equal to 10 21 cm -3 are. [12] Semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer each comprise one or more of silicon (Si), germanium (Ge) and oxygen (O) as a dopant. [13] Semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are each Al x1 In y1 Ga (1-x1-y1) N (0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1) include. [14] Semiconductor device according to claim 1, wherein the barrier layer Al x2 In y2 Ga( 1-x2-y2 )N (0 ≤ x2 ≤ 1, 0 ≤ y2 ≤ 1) includes. [15] Semiconductor device according to claim 1, wherein the channel layer Al x3 In y3 Ga (1-x3-y3) N (0 ≤ x3 ≤ 1,0 ≤ y3 ≤ 1) includes. [16] Semiconductor device according to claim 1, wherein the substrate comprises one or more of silicon (Si), sapphire, silicon carbide (SiC), gallium nitride (GaN) and aluminium nitride (AlN). [17] Semiconductor device according to claim 1, wherein the barrier layer has a first surface opposite the channel layer and a second surface opposite the first surface, and An insulating film, a gate electrode, a source electrode and a drain electrode are further provided on the second surface. [18] Semiconductor device according to claim 17, wherein paired stacked bodies, each comprising the first semiconductor layer and the second semiconductor layer, with the barrier layer arranged between them, the gate electrode is provided on the barrier layer, and The source electrode and the drain electrode are each provided on the paired stacked bodies with the gate electrode positioned between them. [19] Semiconductor module comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer facing the substrate; a first semiconductor layer that is partially buried in the surface of the channel layer opposite the substrate and is in contact with the barrier layer on at least part of a side surface; and a second semiconductor layer that is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer. [20] Wireless communication device comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer comprising a first nitride semiconductor provided on a surface of the substrate; a barrier layer comprising a second nitride semiconductor provided on a surface of the channel layer facing the substrate; a first semiconductor layer that is partially buried in the surface of the channel layer opposite the substrate and is in contact with the barrier layer on at least part of a side surface; and a second semiconductor layer that is provided on top of the first semiconductor layer and has a higher charge carrier concentration than the first semiconductor layer.

Images