Semiconductor device

Abstract

A semiconductor device is provided that appropriately protects a protected circuit from overvoltage.For this purpose, the device includes: a first to third element (M1 to M3) as depletion-type MOSFETs; and a fourth element (M4) as a switching element, wherein the first element is connected with its drain terminal to a power supply (92) and with its source terminal to a drain terminal of the second element, the second element is connected with its source terminal to a first line (42), the gate terminals of the first and second elements are connected to the first line (42), the third element is connected with its drain terminal to the first line (42), with its source terminal to a second line (43) and its gate terminal to the second line (43), and the internal impedance of the fourth element is controlled by a voltage on the first line (42).

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device. BACKGROUND

[0002] As background information on this technical field, the patent literature listed below describes in its summary: “A circuit contains a first MOS transistor and a second MOS transistor connected in series with the first MOS transistor. A gate of the first MOS transistor is connected to a drain of the first MOS transistor. A gate of the second MOS transistor is connected to a drain of the second MOS transistor. The clamping circuit is designed such that a substrate bias effect occurs in at least one of the first MOS transistors and the second MOS transistor.” STATE OF THE ART Patent literature

[0003] Patent literature 1: International patent application Publication No. 2021 / 166679A1 OVERVIEW OF THE INVENTION Problems to be solved

[0004] Meanwhile, there are requirements for the technology described above regarding more suitable protection of a protected circuit against overvoltage. The present invention was developed with these circumstances in mind and is intended to provide a semiconductor device that adequately protects the protected circuit against overvoltage. Problem solving

[0005] To solve the aforementioned problem, a semiconductor device of the present invention is characterized in that the device comprises: a first to third element as depletion-type MOSFETs; and a fourth element as a switching element, wherein the first element is connected at its drain terminal to a power supply and at its source terminal to a drain terminal of the second element, the second element is connected at its source terminal directly or via a first impedance element to a first line, a gate terminal of the first element and a gate terminal of the second element are connected to the first line, the third element is connected at its drain terminal to the first line, at its source terminal is connected directly or via a second impedance element to a second line, and at its gate terminal is connected to the second line.the fourth element is connected between the power supply and a protected circuit, and its internal impedance is controlled by a voltage on the first line, and the second line is connected to the protected circuit or a predetermined potential. Advantageous effects of the invention

[0006] According to the present invention, the protected circuit is protected against overvoltage in a suitable manner. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. 1] is a circuit diagram of an overvoltage protection circuit according to a first embodiment; [ Fig. Figure 2 shows diagrams of different characteristic curves of a lower-stage bias circuit; [ Fig. Figure 3 shows diagrams of different characteristic curves of an upper-stage bias circuit; [ Fig. [4] shows diagrams of various characteristic curves of the entire overvoltage protection circuit; [ Fig. Figure 5] is a diagram illustrating the operation of the overvoltage protection circuit when the voltage is not limited; [ Fig. Figure 6] is a diagram illustrating the operation of the overvoltage protection circuit when the voltage is limited; [ Fig. [7] is a circuit diagram of an overvoltage protection circuit according to a second embodiment; [ Fig. [8] is a circuit diagram of an overvoltage protection circuit according to a third embodiment; [ Fig. [9] is a circuit diagram of an overvoltage protection circuit according to a fourth embodiment; [ Fig. 10] is a circuit diagram of an overvoltage protection circuit according to a fifth embodiment; [ Fig.

[11] is a circuit diagram of an overvoltage protection circuit according to a sixth embodiment; [ Fig.

[12] is a circuit diagram of an overvoltage protection circuit according to a seventh embodiment; [ Fig. 13] is a circuit diagram of an overvoltage protection circuit according to an eighth embodiment; [ Fig.

[14] is a block diagram of an overvoltage protection circuit according to a ninth embodiment; [ Fig.

[15] is a diagram of voltage characteristics of the overvoltage protection circuit according to the ninth embodiment; [ Fig.

[16] is a block diagram of a self-regulating synchronous rectifier element according to a tenth embodiment; and [ Fig.

[17] is a diagram of voltage characteristics of the self-controlled synchronous rectifier element according to the tenth embodiment. DETAILED DESCRIPTION OF THE EXECUTION FORMS [First embodiment]<Konfiguration der ersten Ausführungsform>

[0007] In the following, overvoltage protection circuits 11 to 19 (semiconductor devices) and a self-controlled synchronous rectifier element 20 (semiconductor device) are described successively according to a first to tenth embodiment. Fig. Figure 1 is a circuit diagram of the overvoltage protection circuit 11 according to the first embodiment. The overvoltage protection circuit 11 includes an input terminal 30 and output terminals 31 and 32. An input voltage Vin is applied to the input terminal 30 by an external power supply circuit 92 (power supply). The output terminal 31 is connected to ground potential. The output terminal 32 is connected to a protected circuit 90. The input voltage Vin is normally close to a reference voltage Vn (not shown), but may exhibit a surge voltage Vs (not shown) superimposed on the reference voltage Vn. The overvoltage protection circuit 11 suppresses the surge voltage Vs in order to apply a voltage close to the reference voltage Vn as the output voltage Vout to the protected circuit 90.

[0008] The overvoltage protection circuit 11 further comprises an element M1 (first element), an element M2 (second element), an element M3 (third element), an element M4 (fourth element), a resistor R2 (first impedance element), and a resistor R3 (second impedance element). Elements M1, M2, M3, and M4 are all N-channel depletion-type metal-oxide-semiconductor field-effect transistors (MOSFETs). Element M1 is connected to the power supply circuit 92 via input 30 at its drain terminal and is connected to a drain terminal of element M2 at its source terminal.

[0009] Element M2 is connected via resistor R2 to line 42 (first line) at its source terminal. The gate terminals of elements M1 and M2 are both connected to line 42. Element M3 is connected via its drain terminal to line 42 and via resistor R3, line 43 (second line), and output terminal 31 to ground potential at its source terminal. Additionally, one gate terminal of element M3 is connected to line 43.

[0010] Element M4 is connected to input terminal 30 via its drain terminal, to output terminal 32 via its source terminal, and to line 42 via its gate terminal. Elements M1 and M2 and resistor R2 of the components described above are referred to as the upper-stage bias circuit BP, and element M3 and resistor R3 are referred to as the lower-stage bias circuit BS. <Arbeitsweise der ersten Ausführungsform>

[0011] Fig. Figure 2 shows diagrams of various characteristic curves of the lower-stage bias circuit BS. Diagram G10 is shown in... Fig. In Figure 2, the vertical axis represents the drain current Id, and the horizontal axis represents the gate-source voltage Vgs3 of element M3. Note that the drain current Id is a common drain current for elements M1, M2, and M3. Characteristic curves Q11 and Q12 are both Id-Vgs characteristics of element M3. Characteristic curve Q13 is a voltage-current characteristic of resistor R3 and forms a straight line. Characteristic curves Q11 and Q12 intersect characteristic curve Q13 at points P14 and P15, respectively. Furthermore, characteristic curves Q11 and Q12 intersect the vertical axis of diagram G10 at points P16 and P17, respectively.

[0012] In a G20 chart in Fig. In diagram G20, the vertical axis represents the drain current Id, and the horizontal axis represents the drain-source voltage Vds3 of element M3. A characteristic curve Q21 in diagram G20 is an Id-Vds characteristic curve of element M3 as the change in drain current Id when the drain-source voltage Vds3 is changed, while the gate-source voltage Vgs3 is held constant. Points P24 and P25 on characteristic curve Q21 correspond to characteristic curves Q11 and Q12, respectively, in diagram G10.

[0013] In a diagram G30 in Fig. 2 The vertical axis represents the drain current Id and the horizontal axis represents the drain-gate voltage Vd-g3 of element M3. In other words, the drain-gate voltage Vd-g3 is the voltage between leads 42 and 43 in Fig. 1. A characteristic curve Q31 in the diagram G30 is an Id-Vd-g3 characteristic curve of element M3. The characteristic curve Q31 shows that the drain current Id rises sharply near 0 [V] and then gradually increases more gently from 0 [V] as the drain-gate voltage Vd-g3 increases.

[0014] In a diagram G40 in Fig. Figure 2 represents the vertical axis as the equivalent resistance Rd-g3, and the horizontal axis represents the drain-gate voltage Vd-g3. The equivalent resistance Rd-g3 is the equivalent resistance of the lower-stage bias circuit BS, including resistor R3 and element M3. A characteristic curve Q41 is the characteristic curve of the equivalent resistance Rd-g3 with respect to the drain-gate voltage Vd-g3 of element M3. The characteristic curve Q41 shows that the equivalent resistance Rd-g3 increases essentially linearly as the drain-gate voltage Vd-g3 is gradually increased from 0 [V], and that it slopes gently as the drain-gate voltage Vd-g3 continues to increase.

[0015] Fig. Figure 3 shows diagrams of various characteristic curves of the upper-stage bias circuit BP. Note that the characteristic curves of element M2 and resistor R2 in the upper-stage bias circuit BP are the same as those for the lower-stage bias circuit BS (see Figure 3). Fig. 2) In a diagram G50 in Fig. Figure 3 represents the vertical axis as the drain current Id and the horizontal axis as the gate-source voltage Vgs1 of element M1. Characteristic curves Q51 and Q52 are both Id-Vgs characteristics of element M1 and, in the illustrated case, have the same shapes as characteristic curves Q11 and Q12 (see Figure 3). Fig. 2) of element M3. A characteristic curve Q53 is a characteristic curve of the drain-gate voltage Vd-g2 of element M2 with respect to the gate-source voltage Vgs2 of element M2. In the case shown, the characteristic curve Q53 shows a mirror image of the characteristic curve Q31 in Fig. 2 across the vertical axis.

[0016] The characteristic curves Q51 and Q52 intersect with the characteristic curve Q53 at intersection points P54 and P55, respectively. The drain current Id at intersection points P54 and P55 has values ​​that correspond to those at intersection points P14 and P15 (see Fig. 2) for element M3, this is very close. That is, it is evident that the change in drain current Id is extremely small relative to the change in drain-source voltage Vds1 of element M1.

[0017] In a diagram G60 in Fig. The vertical axis represents the drain current Id, and the horizontal axis represents the drain-gate voltage Vd-g1 of element M1. In other words, the drain-gate voltage Vd-g1 is the voltage between input terminal 30 and line 42. Fig. 1. A characteristic curve Q61 in diagram G60 is an Id-Vd-g1 characteristic curve of element M1. The characteristic curve Q61 shows that the drain current Id rises sharply near 0 [V] and then becomes essentially constant as the drain-gate voltage Vd-g1 is gradually increased from 0 [V].

[0018] In a diagram G70 in Fig. Figure 3 represents the vertical axis as the equivalent resistance Rd-g1 and the horizontal axis as the drain-gate voltage Vd-g1. The equivalent resistance Rd-g1 is the equivalent resistance of the bias circuit BP of the upper stage, including resistor R2 and elements M1 and M2. A characteristic curve Q71 is the characteristic curve of the equivalent resistance Rd-g1 with respect to the drain-gate voltage Vd-g1 of element M1. The characteristic curve Q71 shows that the equivalent resistance Rd-g1 is approximately 0 [2] until the drain-gate voltage Vd-g1 reaches a predetermined value and then changes essentially linearly once the drain-gate voltage Vd-g1 exceeds the predetermined value.

[0019] Fig. Figure 4 shows various characteristic curves of the entire overvoltage protection circuit 11. In diagram G80 in Fig. In figure 4, the vertical axis represents the equivalent resistances Rd-g1 and Rd-g3, and the horizontal axis represents the drain-gate voltage Vd-g. Since the drain-gate voltages Vd-g1 and Vd-g3 of elements M1 and M3 described above are essentially the same, the horizontal axis of diagram G80 is labeled "drain-gate voltage Vd-g", which has values ​​common to both.

[0020] This allows the characteristic curves Q41 and Q71 to be displayed in diagrams G40 and G70 (see the Fig. 2 and Fig. 3) superimposed, as shown in diagram G80. In diagram G80, the equivalent resistances Rd-g1 and Rd-g3 are the same when the drain-gate voltage Vd-g is equal to the voltage Va in the diagram. The higher the drain-gate voltage Vd-g is compared to the voltage Va, the smaller “Rd-g3 / (Rd-g3 + Rd-g1)”.

[0021] In a G90 diagram in Fig. Figure 4 represents the vertical axis as a resistance ratio K (= Rd-g3 / (Rd-g3 + Rd-g1)) and the horizontal axis as the input voltage Vin. The relationship between the two is shown by a characteristic curve Q91. That is, when the input voltage Vin is low, the resistance ratio K is essentially 1, and the higher the input voltage Vin, the lower the resistance ratio K becomes.

[0022] The element M4 (see Fig. 1) is conductive when its gate-source voltage Vgs4 is higher than its threshold voltage Vth. Accordingly, element M4 is switched off when the output voltage Vout is higher than the drain-gate voltage Vdg3 of element M3 minus the threshold voltage Vth. This provides overvoltage protection for the protected circuit 90.

[0023] Fig. Figure 5 is a diagram illustrating the operation of the overvoltage protection circuit 11 when the voltage is not limited. Fig. 5. The input voltage Vin is close to the reference voltage Vn. Furthermore, the threshold voltages Vth of elements M1 to M4 are assumed to be equal. The voltage drops across resistors R2 and R3 and element M2 are all close to the threshold voltage Vth, and the voltage drop across element M1 is approximately 0 V. This causes the drain-gate voltage Vd-g3 of element M3 to be sufficiently high to turn on element M4, so that the voltage drop across it is essentially 0 V. This results in the output voltage Vout being essentially equal to the input voltage Vin and the reference voltage Vn.

[0024] Fig. Figure 6 is a diagram illustrating the operation of the overvoltage protection circuit 11 when the voltage is limited. Fig. 6. The input voltage Vin is the reference voltage Vn, to which the voltage surge voltage Vs is superimposed, with Vs being relatively higher than Vn. As in the case of Fig. 5. The voltage drops across resistors R2 and R3 and element M2 are all close to the threshold voltage Vth. When the input voltage Vin increases, thus increasing the drain current Id of elements M1, M2, and M3, the resistance ratio K decreases (see Fig. 4) of the equivalent resistance Rd-g3 of element M3, so that the voltage across element M3 is a voltage Vk that is slightly higher than the reference voltage Vn.

[0025] Accordingly, the voltage drop across element M1 is close to the value obtained by "Vin - Vk". When the equivalent resistance Rd-g3 decreases, the gate-source voltage Vgs4 of element M4 is lower than the threshold voltage Vth required to switch off element M4. That is, the internal impedance of element M4 increases. This causes the output voltage Vout to be close to the voltage Vk, so that the drain-source voltage Vds4 of element M4 is close to the value obtained by "Vin - Vk". This provides overvoltage protection for the protected circuit 90. [Second embodiment]

[0026] Fig. Figure 7 is a circuit diagram of an overvoltage protection circuit 12 according to a second embodiment. Note that the components corresponding to those in other embodiments, when described in those embodiments, are designated with the same reference numerals and their descriptions may be omitted. Fig. 7 The overvoltage protection circuit 12 contains an output terminal 33 instead of the output terminals 31 and 32 in the overvoltage protection circuit 11 (see Fig. 1) That is, the protected circuit 90, the line 43 and the source terminal of element M4 are all connected to the output terminal 33.

[0027] The operation of the second embodiment is similar to that of the first embodiment. However, a small electric current always flows through the bias circuit BS of the lower stage and the bias circuit BP of the upper stage of the overvoltage protection circuit 12. Thus, the overvoltage protection circuit 12 of this embodiment can be used for the protected circuit 90 to simplify the circuit whenever a small electric current flows through the protected circuit 90. In contrast, the overvoltage protection circuit 11 of the first embodiment is preferably used when a situation may arise in which even a small electric current cannot flow through the protected circuit 90. [Third embodiment]

[0028] Fig. Figure 8 is a circuit diagram of an overvoltage protection circuit 13 according to a third embodiment. One configuration of the overvoltage protection circuit 13 corresponds to that of the overvoltage protection circuit 12 (see Figure 8). Fig. 7) of the second embodiment, wherein the resistance values ​​of resistors R2 and R3 are “0 Ω”.

[0029] The operation of the third embodiment is similar to that of the first or second embodiments. However, the intersection points P14 and P15 in diagram G10 (see Fig. 2) shifted to the positions of the intersection points P16 and P17. In the case where this does not affect the operation, the configuration of the overvoltage protection circuit 13 of this embodiment is further simplified compared to the overvoltage protection circuits 11 and 12 of the first and second embodiments. [Fourth embodiment]

[0030] Fig. Figure 9 is a circuit diagram of an overvoltage protection circuit 14 according to a fourth embodiment. The overvoltage protection circuit 14 of this embodiment includes an input terminal 51 (first input terminal), an input terminal 52 (second input terminal), an output terminal 53 (first output terminal), an output terminal 54 (second output terminal), a Zener diode 57 (first overvoltage protection element), a Zener diode 58 (second overvoltage protection element), and the overvoltage protection circuit 12 of the second embodiment (see Figure 9). Fig. 7) Input terminal 51 is connected to input terminal 30 of the surge protection circuit 12, output terminal 53 is connected to output terminal 33 of the surge protection circuit 12, and input terminal 52 is connected to output terminal 54. In other words, input terminal 51 is connected via input terminal 30 to a drain terminal of element M1 (see Fig. 7) connected. In addition, output terminal 53 is connected to a source terminal of element M4 via output terminal 33.

[0031] Furthermore, the Zener diode 57 is connected between the input terminals 51 and 52, and the Zener diode 58 is connected between the output terminals 53 and 54. In this embodiment, the Zener diodes 57 and 58 are designed to absorb the voltage surge voltage that is partially unabsorbed by the overvoltage protection circuit 12. Note that an active terminal can also be used instead of the Zener diodes 57 and 58. [Fifth embodiment]

[0032] Fig. Figure 10 is a circuit diagram of an overvoltage protection circuit 15 according to a fifth embodiment. The overvoltage protection circuit 15 of this embodiment includes a pair of input terminals 51 and 52, a pair of output terminals 53 and 54, Zener diodes 57 and 58, and the overvoltage protection circuit 11 of the first embodiment (see Figure 10). Fig. 1) Input terminal 51 is connected to input terminal 30 of the surge protection circuit 11, output terminal 53 is connected to output terminal 31 of the surge protection circuit 11, and input terminal 52 and output terminal 54 are connected to output terminal 32 of the surge protection circuit 11. In other words, input terminal 51 is connected via input terminal 30 to the drain terminal of element M1 (see Fig. 1) connected. In addition, output terminal 53 is connected to line 43 via output terminal 31. Furthermore, input terminal 52 and output terminal 54 are connected to the source terminal of element M4 via output terminal 32.

[0033] Additionally, the Zener diode 57 is connected between the input terminals 51 and 52, and the Zener diode 58 is connected between the output terminals 53 and 54. In this embodiment as well, the Zener diodes 57 and 58 are provided, as in the fourth embodiment, to absorb the voltage surge voltage that is partially not absorbed by the overvoltage protection circuit 12. Note that this embodiment can also use an active terminal instead of the Zener diodes 57 and 58. [Sixth embodiment]

[0034] Fig. Figure 11 is a circuit diagram of a surge protection circuit 16 according to a sixth embodiment. A configuration of the surge protection circuit 16 according to the sixth embodiment is the same as that of the surge protection circuit 11, except for the points described below (see Figure 11). Fig. 1) according to the first embodiment. That is, the elements M1, M2, and M3 of the sixth embodiment are depletion-type P-channel MOSFETs. In this way, the elements M1, M2, and M3 can be P-channel MOSFETs as long as they are depletion-type. However, the connections between the elements M1, M2, and M3 and the resistors R2 and R3 have been changed to those suitable for P-channel MOSFETs. The operation of this embodiment is the same as that of the first embodiment. [Seventh embodiment]

[0035] Fig. Figure 12 is a circuit diagram of an overvoltage protection circuit 17 according to a seventh embodiment. A configuration of the overvoltage protection circuit 17 according to the seventh embodiment is, with the exception of the points described below, the same as that of the overvoltage protection circuit 11 (see Figure 12). Fig. 1) according to the first embodiment. That is, the seventh embodiment uses a Zener diode ZD2 (first impedance element) and a Zener diode ZD3 (second impedance element) instead of the resistors R2 and R3 of the first embodiment. This embodiment has the effect of reducing the current consumption with the Zener diodes ZD2 and ZD3, and the effect of changing the resistance ratio K (see Fig. 4) to tighten the limits in order to be able to set the limit voltage for voltage limitation more precisely. [Eighth embodiment]

[0036] Fig. Figure 13 is a circuit diagram of an overvoltage protection circuit 18 according to an eighth embodiment. A configuration of the overvoltage protection circuit 18 according to the eighth embodiment is, with the exception of the points described below, the same as that of the overvoltage protection circuit 11 (see Figure 13). Fig. 1) according to the first embodiment. That is, the eighth embodiment uses coils L2 (first impedance element) and L3 (second impedance element) instead of the resistors R2 and R3 of the first embodiment. The drain currents Id of elements M1, M2, and M3 are constant in this embodiment, so that the voltage drop across coils L2 and L3 is 0 [V] when no voltage surge is superimposed on the input voltage Vin. However, when a voltage surge is superimposed on the input voltage Vin, the voltages across coils L2 and L3 drop by approximately the threshold voltage Vth. That is, the gate-source voltages Vgs of elements M2 and M3 are approximately the threshold voltage Vth. This suppresses the current flowing through elements M1, M2, and M3, which has the effect of reducing power consumption. [Ninth embodiment]

[0037] Fig. Figure 14 is a block diagram of an overvoltage protection circuit 19 according to a ninth embodiment. The overvoltage protection circuit 19 is a cascade connection of the overvoltage protection circuit 11 of the first embodiment (see Figure 14). Fig. 1) and the overvoltage protection circuit 12 of the second embodiment (see Fig. 7) That is, the input terminal 30 of the surge protection circuit 12 is connected to the power supply circuit 92, and its output terminal 33 is connected to the input terminal 30 of the surge protection circuit 11. Furthermore, the output terminal 31 of the surge protection circuit 11 is connected to ground potential, and its output terminal 32 is connected to the protected circuit 90.

[0038] Fig. Figure 15 is a diagram of the voltage characteristics of the overvoltage protection circuit 19. Fig. In Figure 15, the horizontal axis represents the input voltage Vin, and the vertical axis represents the voltages across the circuits. The voltage V90, or output voltage Vout, and the voltages V11 and V12 are the voltages applied to the protected circuit 90 and the overvoltage protection circuits 11 and 12, respectively. As the input voltage Vin gradually increases from 0 V, the output voltage Vout is initially essentially equal to the input voltage Vin and then increases. Once it reaches a value close to the reference voltage Vn, the output voltage Vout remains close to the reference voltage Vn. As the input voltage Vin continues to increase, the voltage V11 begins to rise. Once it reaches a value close to the reference voltage Vn, the voltage V11 remains close to the reference voltage Vn. If the input voltage Vin continues to rise, the voltage V12 subsequently increases with the input voltage Vin.In this way, this embodiment can absorb overvoltages through both overvoltage protection circuits 11 and 12, which further improves the tolerance to overvoltages. [Tenth embodiment]

[0039] Fig. Figure 16 is a block diagram of a self-regulating synchronous rectifier element 20 according to a tenth embodiment. The self-regulating synchronous rectifier element 20 comprises an anode terminal 71 (first terminal), a cathode terminal 72 (second terminal), the overvoltage protection circuit 12, a control circuit 74, a capacitor 76, and a MOSFET element M5. Here, the control circuit 74 includes a buck converter 74a.

[0040] The overvoltage protection circuit 12 is similar to that of the second embodiment. Of the anode terminal 71 and the cathode terminal 72, one is connected, for example, to an AC power supply (not shown), and the other is connected, for example, to a DC load (not shown). The self-regulating synchronous rectifier element 20 rectifies current similarly to a diode. That is, the element conducts a forward current from the anode terminal 71 to the cathode terminal 72, but blocks a reverse current from the cathode terminal 72 to the anode terminal 71. While a diode generally exhibits a forward voltage drop, the self-regulating synchronous rectifier element 20 differs in that it can reduce a forward voltage drop to essentially 0 V.

[0041] The control circuit 74 switches off element M5 when a reverse voltage is applied to the self-regulating synchronous rectifier element 20, and switches element M5 on otherwise. When a reverse voltage is applied to the self-regulating synchronous rectifier element 20, the control circuit 74 charges capacitor 76 via the buck converter 74a. The control circuit 74 then uses the charge stored in capacitor 76 as a power source to control the switching on or off of element M5. In this embodiment, the overvoltage protection circuit 12 is inserted between the cathode terminal 72 and the control circuit 74. This allows the control circuit 74 to be protected against overvoltage even if the reverse voltage exceeds the maximum voltage that can be applied to the control circuit 74.

[0042] Fig. Figure 17 is a diagram of voltage characteristics of the self-regulating synchronous rectifier element 20. Fig. Figure 17 represents the horizontal axis as the reverse input voltage Vin, and the vertical axis represents the voltages across the circuits. Voltages V12 and V74 are voltage drops across overvoltage protection circuit 12 and control circuit 74, respectively. Furthermore, voltage V74n is the voltage drop across control circuit 74 that would occur if overvoltage protection circuit 12 were not present. Additionally, nominal voltage Vmax is the nominal voltage of both control circuit 74 and overvoltage protection circuit 12.

[0043] The voltage V74n shows that the voltage drop across the control circuit 74 is equal to or greater than the voltage Vmax when the input voltage Vin is equal to or greater than the voltage Vin1. In contrast, the voltages V12 and V74 of this embodiment show that the voltage drop across the overvoltage protection circuit 12 and the control circuit 74 is less than the nominal voltage Vmax until the input voltage Vin reaches the voltage Vin2, which is higher than the voltage Vin1.

[0044] Additionally, the voltage V12 remains at a relatively low value until the input voltage Vin exceeds the voltage Vin1, which results in the voltage V74 having a relatively high value. This allows the buck converter 74a to efficiently charge the capacitor 76. In this way, this embodiment can improve the voltage withstand capability of the self-regulating synchronous rectifier element 20 without affecting the operation of the buck converter 74a. [Modifications]

[0045] The present invention is not limited to the embodiments described above, and they can be modified in various ways. The embodiments described above serve only to illustrate the present invention and are not necessarily limited to those containing all the components described. Furthermore, components of one embodiment can be partially replaced by one or more components of another embodiment, and components of one embodiment can be joined by one or more components of another embodiment. Additionally, components of the embodiments can be partially removed or supplemented or replaced by other components.Furthermore, the control and information lines shown in the drawings are those deemed necessary for the description and do not necessarily represent all control and / or information lines required for the product. In reality, it can be assumed that almost all components are interconnected. Possible modifications to the embodiments described above are, for example, as follows. (1) The resistors R2 and R3 can be obtained from the first embodiment described above (see Fig. 1) are removed, with the source terminal of element M2 being directly connected to line 42 and the source terminal of element M3 being directly connected to line 43. Furthermore, in the sixth to eighth embodiments (see the Fig. 11 to 13) connected and similar to the output terminal 33 of the second embodiment (see Fig. 7) can be used. (2) In the embodiments described above, a predetermined potential other than the ground potential may be used. (3) In the embodiments described above, a depletion-type MOSFET is used as element M4. However, element M4 can be any element as long as its internal impedance depends on the voltage across line 42 (see Figure 4). Fig. 1) is controlled to be conductive or non-conductive. In particular, element M4 can be an enhancement-type MOSFET or a bipolar transistor. (4) The element M5 of the tenth embodiment can be any element as long as it switches the connection between the anode terminal 71 and the cathode terminal 72 on or off, and can therefore be a MOSFET or a bipolar transistor. [Advantageous effects of the embodiments]

[0046] As described above, the overvoltage protection circuits 11 to 19 and the self-regulating synchronous rectifier element 20 of the embodiments described above each comprise: first to third elements (M1 to M3) as depletion-type MOSFETs; and a fourth element (M4) as a switching element, wherein the first element (M1) is connected at its drain terminal to a power supply (92) and at its source terminal to a drain terminal of the second element (M2), the second element (M2) is connected directly or via a first impedance element (R2, L2 or ZD2) to its source terminal, a gate terminal of the first element (M1) and a gate terminal of the second element are connected to the first line (42), the third element (M3) is connected at its drain terminal to the first line (42), and at its source terminal directly or via a second impedance element (R3,L3 or ZD3) is connected to a second line (43) and its gate terminal is connected to the second line (43), the fourth element (M4) is connected between the power supply (92) and the protected circuit 90 and its internal impedance is controlled by the voltage on the first line (42), and the second line (43) is connected to the protected circuit 90 or a predetermined potential (0 V).

[0047] This allows the protected circuit to be adequately protected against overvoltage. Furthermore, the drain currents Id of elements M1, M2, and M3 can be small in the embodiments described above to reduce power consumption and achieve high-speed operation. Additionally, the dielectric strengths of elements M1 to M4 can be equal to or lower than those required by the overvoltage protection circuits 11 to 19 themselves, enabling the use of elements with relatively low dielectric strengths and thus reducing costs. Moreover, the overvoltage protection circuits 11 to 19 each exhibit low suppression of the input voltage Vin at or below the reference voltage Vn, thereby reducing power loss and heat generation within the overvoltage protection circuits 11 to 19.Furthermore, elements M1 to M4 exhibit properties prior to dielectric breakdown, so reliable operation can be expected. Additionally, the number and types of elements M1 to M4 can be reduced in the embodiments described above, thereby minimizing the impact of variations in elements M1 to M4.

[0048] As with the overvoltage protection circuits 11 and 12 of the first and second embodiments, it is further preferred that the first and second impedance elements are resistors, that the source terminal of the second element (M2) is connected to the first line (42) via the first impedance element (R2), and that the source terminal of the third element (M3) is connected to the second line (43) via the second impedance element (R3). This allows the current flowing through the first to third elements (M1 to M3) to be further reduced.

[0049] Furthermore, as with the overvoltage protection circuit 13 of the third embodiment, it is preferable that the source terminal of the second element (M2) is directly connected to the first conductor (42) and the source terminal of the third element (M3) is directly connected to the second conductor (43). This allows the number of parts to be further reduced.

[0050] Furthermore, as with the surge protection circuits 12 and 13 of the second and third embodiments, it is preferable that the second line (43) is connected to the protected circuit 90. This further simplifies the configuration of the semiconductor device (12, 13).

[0051] Furthermore, as with the overvoltage protection circuit 11 of the first embodiment, it is preferable that the second conductor (43) is connected to a predetermined potential. This makes it possible to protect the protected circuit 90 appropriately, even if current cannot constantly flow through the protected circuit 90.

[0052] Furthermore, as with the overvoltage protection circuits 14 and 15 of the fourth and fifth embodiments, it is preferable to include a first overvoltage protection element (57) connected between the first and second input terminals (51, 52) and a second overvoltage protection element (58) connected between the first and second output terminals (53, 54). This further increases the resistance to overvoltage.

[0053] Furthermore, as with the self-regulating synchronous rectifier element 20 of the tenth embodiment, it is preferable to further include a first terminal (71) connected to a drain terminal of a first element (M1), a second terminal (72), a fifth element (M5) as a switching element connected between the first and second terminals (71, 72), the capacitor 76, and the control circuit 74 as a protected circuit 90 operating using the charge stored in the capacitor 76, wherein the control circuit 74 has a function of switching off the fifth element (M5) to charge the capacitor 76 when the potential of the first terminal (71) exceeds that of the second terminal (72), and a function of switching on the fifth element (M5) when the potential of the first terminal (71) falls to or below that of the second terminal (72).This allows the control circuit 74 to efficiently charge the capacitor 76, thereby improving the voltage withstand capability of the self-controlled synchronous rectifier element 20 without affecting the operation of the control circuit 74. REFERENCE MARK LIST

[0054] 11 to 19: Overvoltage protection circuit (semiconductor device), 20: Self-regulating synchronous rectifier element (semiconductor device), 42: Line (first line), 43: Line (second line), 51: Input terminal (first input terminal), 52: Input terminal (second input terminal), 53: Output terminal (first output terminal), 54: Output terminal (second output terminal), 57: Zener diode (first overvoltage protection element), 58: Zener diode (second overvoltage protection element), 71: Anode terminal (first terminal), 72: Cathode terminal (second terminal), 74: Control circuit, 76: Capacitor, 90: Protected circuit, 92: Power supply circuit (power supply), L2: Inductor (first impedance element), L3: Inductor (second impedance element), M1: Element (first element), M2: Element (second element), M3: Element (third element) Element), M4: Element (fourth element), M5: Element (fifth element), R2: Resistor (first impedance element),R3: Resistor (second impedance element), ZD2: Zener diode (first impedance element) and ZD3: Zener diode (second impedance element).

Claims

[1] Semiconductor device comprising: a first to third element as depletion-type MOSFETs; and a fourth element as a switching element, where the first element is connected to a power supply via its drain terminal and to a drain terminal of the second element via its source terminal, the second element is connected to a first line directly or via a first impedance element with its source connection, a gate terminal of the first element and a gate terminal of the second element are connected to the first line, the third element is connected to the first line via its drain terminal, is connected to a second line via its source terminal directly or via a second impedance element, and is connected to the second line via its gate terminal. the fourth element is connected between the power supply and a protected circuit, and its internal impedance is controlled by a voltage on the first line, and the second line is connected to the protected circuit or a predetermined potential. [2] Semiconductor device according to claim 1, wherein the first and second impedance elements are resistors, the second element is connected to the first line via the first impedance element with its source terminal and the third element is connected to the second line via its source terminal through the second impedance element. [3] Semiconductor device according to claim 1, wherein the second element is directly connected to the first line via its source terminal, and the third element is directly connected to the second line via its source connection. [4] Semiconductor device according to claim 1, wherein the second line is connected to the protected circuit. [5] Semiconductor device according to claim 1, wherein the second conductor (43) is connected to a predetermined potential. [6] Semiconductor device according to claim 4, wherein the device further comprises: a first input port and a second input port connected to the power supply; a first output terminal and a second output terminal, which are connected to the protected circuit; a first surge protection element connected between the first and second input terminals; and a second surge protection element connected between the first and second output terminals, wherein the first input port is connected to a drain port of the first element, the first output terminal is connected to the second line and the fourth element, and the second input port is connected to the second output port. [7] Semiconductor device according to claim 5, further comprising: a first input port and a second input port connected to the power supply; a first output terminal and a second output terminal, which are connected to the protected circuit; a first surge protection element connected between the first and second input terminals; and a second surge protection element connected between the first and second output terminals, wherein the first input port is connected to a drain port of the first element, the first output terminal is connected to the second line, and the second input terminal is connected to the second output terminal and the fourth element. [8] Semiconductor device according to claim 4, wherein the device further comprises: a first connection that is connected to a drain connection of the first element; a second connection; a fifth element as a switching element, which is connected between the first and second terminals; a capacitor; and a control circuit as a protected circuit that operates using a charge stored in the capacitor, where the control circuit a function to switch off the fifth element in order to charge the capacitor when the potential of the first terminal exceeds that of the second terminal, and a function to switch on the fifth element when the potential of the first terminal falls to or below that of the second terminal, exhibits.

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