ASYMMETRIC POWER DIVISION

Abstract

Techniques are disclosed relating to the management of power allocation for component circuits coupled to one or more power sources. A system may include a first integrated circuit die that is indirectly coupled to a second integrated circuit die via a set of intermediate integrated circuit dies. The system may include a first power source configured to supply power to component circuits of both the first and second integrated circuit dies. The first integrated circuit may allocate a first set of power credits to a first set of component circuits of the first integrated circuit die for receiving power from the first power source.The first integrated circuit can send a second set of power credits to the second integrated circuit die through the set of intervening integrated circuit dies without the set of intervening integrated circuit dies using the second set of power credits to obtain power from the first power source.

Description

STATE OF THE ART Technical field

[0001] This disclosure relates generally to integrated circuits and in particular to various mechanisms for managing power allocation for component circuits coupled to power sources. Description of the state of the art

[0002] Modern computer systems often include a system-on-a-chip (SoC), which integrates many component circuits (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) onto a single integrated circuit die. These component circuits can be connected to a power source, such as a battery, which supplies them with power to enable their functionality. SoCs often have multiple independent voltage domains that can simultaneously have different supply voltages and represent different loads (e.g., current drawn under a given load). As SoCs continue to increase in complexity and performance, so too does the complexity of delivering stable and reliable power to the component circuits within these SoCs.There is also a growing trend towards using multiple dies or chiplets integrated into a single package, rather than using one large monolithic SOC die. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram illustrating exemplary elements of a system comprising a SOC and multiple power sources that supply power to component circuits of this SOC, according to some embodiments. Fig. Figure 2 is a block diagram illustrating exemplary elements of component circuits coupled with a power divider circuit, according to some embodiments. Fig. Figure 3 is a block diagram illustrating exemplary elements of a power divider circuit that supplies power to a component circuit, according to some embodiments. Fig. Figure 4 is a block diagram illustrating different device configurations that have different power source configurations, according to some embodiments. Fig. Figure 5 is a block diagram illustrating exemplary elements of a multi-die configuration in which dies share power credits for multiple power sources, according to some embodiments. Fig. Figure 6 is a block diagram illustrating exemplary elements of a die-to-die (D2D) interface used to send power credits between dies, according to some embodiments. Fig. Figure 7 is a block diagram illustrating exemplary elements of a multi-die configuration in which several dies share power credits through a set of intervening dies which do not consume these power credits, according to some embodiments. Fig. Figure 8 is a block diagram illustrating exemplary elements of a multi-die configuration in which dies that are asymmetric to each other share power credits for a common power source, according to some embodiments. Fig. 9 and Fig. Figure 10 are flowcharts illustrating exemplary procedures relating to the allocation of power to component circuits based on an assignment, according to some embodiments. Fig. 11 and Fig. Figure 12 are flowcharts illustrating exemplary procedures relating to the division of performance credits by a set of intermediate dies, according to some embodiments. Fig. Figure 13 is a block diagram illustrating elements of a device implementing components described in the present disclosure, according to some embodiments. Fig. Figure 14 is a block diagram illustrating an exemplary system used in various types of applications, according to some embodiments. Fig. Figure 15 is a block diagram illustrating an exemplary process for manufacturing an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0003] A system-on-a-chip (SoC) can include various component circuits connected to a power source that supplies them with power. In some embodiments, these component circuits are also connected to a power divider circuit that distributes power from this power source among these component circuits. Specifically, the power available from the power source can be represented by power credits that constitute a power budget. The power divider circuit can distribute the power credits among the various component circuits according to a power-sharing policy, and the component circuits receive power from the power source based on their received power credits. However, power configurations become more complex with multiple power sources that have different power limits and rails to which they supply power.For example, a system might include two power sources: one that supplies power to a first set of component circuits managed by a power sharing circuit, and another that supplies power to a second set of component circuits, also managed by this power sharing circuit. Furthermore, different products (e.g., laptops, tablets, mobile phones, etc.) might have different power configurations (e.g., different numbers of power sources), and the distribution of power rails within these products might also vary. In many cases, these different power configurations, in which a power sharing circuit is located, change during development or are unknown to the development team responsible for managing power within SOCs.This disclosure addresses, among other things, the problem of how to allocate power in device configurations with multiple power sources, where the device configurations may also have different power configurations (e.g., different types and numbers of power sources).

[0004] There is also a growing trend toward using multiple dies instead of one large monolithic SoC die. In many cases, dies in a multi-die configuration are symmetrically similar and directly coupled. As used here, the term "symmetrically similar dies" refers to dies designed to include the same component circuitry, even though the dies may differ physically due to manufacturing defects. The component circuit layouts of symmetrically similar dies may also differ. For example, symmetrically similar dies packaged together may have mirror-image component circuit layouts. Dies that are asymmetrically similar to each other do not include the same component circuitry.For example, a die that includes GPU processors but no CPU processors is asymmetric to a die that includes CPU processors but no GPU processors.

[0005] These can share a common power source that supplies power to component circuits within these dies, and thus they can share power. If a die has a residual power allocation, then that die can send power credits, according to the remaining allocation, to the symmetrically similar die that is directly coupled to it. But multi-die configurations are shifting to an asymmetric "chiplet" strategy, where the dies / chiplets are arranged asymmetrically. As used herein, the description of dies arranged asymmetrically refers to at least two symmetrically similar dies separated by one or more intervening dies that are asymmetric with respect to the symmetrically similar dies. For example, the layout "CPU-Die<->GPU-Die<->GPU-Die<->CPU-

[0006] The "asymmetric" dies are separated by intervening GPU dies, which are asymmetric with respect to those CPU dies. Dies separated by one or more intervening dies can share a common power source that is not coupled to those intervening dies—for example, the CPU dies in the previous example can share a power source that is not used by the GPU dies. It may be desirable for the dies coupled to the same power source to share power credits, even if there are intervening dies that are not coupled to that power source. This disclosure further addresses, among other things, the problem of how to share power credits between dies when there are intervening dies that do not use those power credits.

[0007] In various embodiments described below, a system comprises multiple power sources, component circuits, and a power divider circuit configured to allocate power from the power sources to the component circuits. These power sources supply power to respective sets of these component circuits, and there may be overlaps between these sets. In various embodiments, the power divider circuit is coupled to one or more programmable registers configured to store an allocation specifying which power sources supply power to a given component circuit managed by the power divider circuit.The mapping stored in the programmable registers can differ between systems with different power configurations, and thus the power divider circuit can determine the specific configuration of power sources to component circuits of its system through this mapping. Accordingly, the power divider circuit can allocate power to a given component circuit based on the power budget(s) of the power source(s) assigned to that component circuit, as specified by the mapping. In some cases, a component circuit can receive power from multiple power sources. Consequently, in various embodiments, the power divider circuit allocates power to that component based on the most limiting power source supplying power to the component.As used herein, the term "most limiting power source" refers to the power source(s) whose power deliverable to a component is the lowest among several power sources. For example, if a first power source can deliver 10 watts to a component and a second power source can deliver 20 watts, then the first power source is the most limiting power source among these power sources for that component. There can be multiple power sources that are designated as the most limiting power source for a component if they deliver the same amount of power, which corresponds to the lowest power output. Continuing the previous example, if a third power source can deliver 10 watts to the component, then the first and third power sources are considered the most limiting power sources.

[0008] For the power source(s) that allocate more power than the most limiting power source(s), in some embodiments the excess amount is added to the available power budget of its next power allocation cycle.

[0009] In various embodiments, the system comprises multiple dies that are coupled together and can be arranged asymmetrically. Thus, a first and a second die can be indirectly coupled to each other by one or more intervening dies. At least one of the system's power sources can be configured to supply power to component circuits of the first and second dies. The first and second dies can receive power from the power source based on power credits that are actively shared between them. As used herein, the term "actively shared" with respect to power credits refers to the sharing of power credits between components (e.g., dies) that results in a change to an initial amount of power credits allocated to those components.For example, a power source might supply power represented by one hundred power credits, and two dies linked to that power source might each initially be allocated fifty power credits. If one of the dies sends, say, ten power credits to the other die, changing the allocation of the other die to sixty power credits, then the power credits are considered actively shared. Actively shared power credits are the opposite of "passively shared" power credits, which refers to components that receive an allocation from a power source's pool of power credits without sending any of their power credits to another component.If, therefore, these entities do not physically send power credits to each other, but rather share the same power source, then they are considered to be passively sharing the pool of power credits from that power source, and thus the power credits are passively shared. In the case of actively shared power credits, a first entity can send a set of power credits for a power source to a second entity via one or more intermediary entities without these intermediary entities using the power credits to receive power from the power source.

[0010] These techniques can be advantageous over previous approaches because they allow a power divider to support different systems with varying power configurations. For example, by mapping component circuits to power sources and storing this mapping in programmable registers, the same power divider circuit arrangement can be used in different systems with different power configurations. Based on this mapping, the power divider circuit is able to allocate power from the various power sources of a given system to the different components of that system. Furthermore, by implementing a mechanism that allows power credits to be passed through any intermediate power dividers, symmetrically similar power dividers can share power credits even if they are not directly coupled.

[0011] Now, referring to Fig. Figure 1 shows a block diagram of a System 100. System 100 includes a set of components that can be implemented using hardware or a combination of hardware and software. In various embodiments, System 100 is any hardware-based system, such as a desktop computer, a laptop computer, a tablet computer, a mobile phone, or the like. Examples of different types of systems that can correspond to System 100 are given in relation to Fig. 14 is discussed in more detail. In the illustrated embodiment, System 100 comprises a SOC 110 and power sources 130A-B that supply power to the circuits of the SOC 110 via power rails 135. As shown, SOC 110 includes components 120A-C and a power divider 140 coupled to these components 120. As also shown, components 120A-B are coupled to power source 130A, component 120C is coupled to power source 130B, and power divider 140 includes power budgets 142, a power sharing policy 144, and a power source allocation 150. System 100 can be implemented differently than shown. For example, SOC 110 can include multiple dies coupled together, as described in section 142. Fig. Sections 5 to 8 are discussed in more detail. It is noted that the number of components of the system is 100 (and also the number of subcomponents for these in Fig. As shown in Figure 1, the power divider (140) can vary within the embodiments. Accordingly, there may be more or less of each component or subcomponent than shown in Figure 1. Fig. 1 number shown.

[0012] In various embodiments, SOC 110 integrates many components (e.g., components 120, power dividers 140, etc.) onto a single semiconductor substrate as an integrated circuit chip and is therefore referred to as a system-on-a-chip. However, in some embodiments, the components are implemented on two or more discrete chips in System 100. For example, regarding... Fig. As discussed in Sections 4 to 8, System 100 can include multiple dies / chiplets coupled together as an integrated circuit arrangement. For the sake of simplicity, various embodiments are described in this disclosure as being implemented using one or more SOCs. However, it is understood that each disclosed SOC can also be implemented using a chiplet-based architecture. Therefore, wherever the term "SOC" appears in this disclosure, these references are intended to suggest alternative embodiments in which the same functionality is implemented via a less monolithic architecture, such as multiple dies / chiplets, which in some embodiments may be enclosed in a single integrated component package.

[0013] Architectures containing multiple dies are to be understood as encompassing both homogeneous implementations (in which each die has identical or nearly identical functionality) and heterogeneous implementations (in which the functionality of each die differs considerably). This disclosure also encompasses embodiments in which the functionality of multiple SoCs is implemented using different levels of discreteness. For example, the functionality of a first system could be implemented on a single IC, while the functionality of a second system (which could be the same or different from the first system) could be implemented using a number of co-packaged dies / chiplets.

[0014] Components 120, in various embodiments, include any hardware components that may be enclosed in a system. Examples of components 120 include central processing units (CPUs), graphics processing units (GPUs), memory controllers, peripheral component circuits (or, more simply, peripherals), etc. Peripherals may include display controllers, image signal processors, audio processors, video or audio encoder / decoder circuits, bridges to external connections of various types, input / output devices, etc. A given component 120 may include a power control circuit that implements a set of power management mechanisms within that component 120 as a whole.This means that a component 120 can be a unit that is power-managed as a unit by a power control circuit, which can employ power management mechanisms to reduce power consumption and potentially decrease performance. In various embodiments, the power control circuit is coupled with a rate control circuit that manages power consumption by, for example, providing inputs that request reduced power consumption based on specified allocated power. A rate control circuit is used in relation to... Fig. 2 discussed in more detail.

[0015] Although not shown, SOC 110 in various embodiments comprises multiple independent power domains that can simultaneously have different supply voltages and represent different loads (e.g., current drawn at a given load). A given component 120 can reside in a single power domain, and more than one component 120 can reside in a given power domain. For example, component 120A can reside in a first power domain, and components 120B-C can reside in a second power domain. Power divider 140 is also located in a power domain, which can be shared with or separate from one or more component circuits 120. A power domain can be independent if it is controlled separately from the other power domains. For example, an independent power domain can have dedicated voltage inputs to the system, which, for example, control the power supply to a power supply.B. can be controlled by a separate voltage controller. Consequently, power management within the power domain may be sufficient to protect the stability of the voltage controller supplying power to that domain. However, system-wide power management can be used to manage power across power domains and can thus protect higher-level voltage controllers in the system.

[0016] Power sources 130, in various embodiments, are circuits configured to supply power to the SOC 110 and other components that may be included in the System 100, such as memory (e.g., dynamic random-access memory). For example, a power source 130 may be configured to generate one or more supply voltages to power the SOC 110 via power rails 135, and one or more supply voltages to power other components arranged in the System 100. Examples of power sources 130 include, but are not limited to, a coupled inductor voltage regulator (CLVR), an electronic voltage regulator (EVR), and a battery. Different combinations of power source types can be coupled to the SOC 110.For example, power source 130A may be a CLVR, while power source 130B is an EVR in one System 100 configuration, while in another System 100 configuration both power sources 130A and 130B may be CLVRs.

[0017] In some embodiments, a multi-level power transmission network is provided. In a multi-level power transmission network, a first level of voltage regulator(s) can supply an initial amount of load current to the second level of voltage regulators. The second level of voltage regulators can supply power to the various independent power networks in System 100. Different loads (e.g., CPUs, GPUs, peripherals, etc.) can reside within these independent power domains, as discussed above. Local power estimation and power control within the power domains can be used to prevent overloading a given second-level voltage regulator. However, providing a first-level regulator capable of supplying the second-level regulators when they are simultaneously at their peak loads would not be cost-effective, as such loads are likely to be infrequent.Therefore, a further power management mechanism can be implemented (e.g. by power divider 140) to protect the voltage regulator(s) of the first stage.

[0018] Power divider 140 (or power divider circuit 140) is, in various embodiments, switching logic configured to allocate deliverable power to components 120 from the power budget(s) 142 corresponding to the power source(s) 130 that supply power to these components. A power budget 142, in various embodiments, is based on the capability of the corresponding voltage regulator that supplies power to the system 100 (e.g., a first-level voltage regulator, such as a CLVR, that supplies second-level voltage regulators, which in turn supply power domains). The available power (e.g., the maximum current reliably supplied by a first-level voltage regulator multiplied by the voltage nominally supplied by that regulator) can be represented in terms of power credits, where a given credit represents a specified amount of power.Accordingly, in various embodiments, a power budget 142 comprises a pool of power credits that collectively represent the total available power of a corresponding power source 130. A given power source 130 can provide a power specification 132 to power dividers 140, which can specify the available power of this source or a certain number of power credits. As in relation to . Fig. As discussed in more detail in Section 3, a power divider 140 can generate power budgets 142 based on power sources 130 of the system 100 and power information 132 received. In various embodiments, the power divider 140 allocates power to components 120 by issuing information about the allocated power (e.g., power allocations 145 specifying a number of power credits) to these components (e.g., to their respective rate control circuits). Components 120 manage their respective power consumption based on their information about the allocated power (i.e., the power allocation 145 they receive). Power credits are calculated with reference to Fig. 2 discussed in more detail.

[0019] In various embodiments, the power divider 140 is programmable with a power-sharing policy 144 and distributes power budget(s) 142 based on this policy. In particular, components 120 can be divided into groups in any desired manner. For example, components 120 could be grouped by type (e.g., CPUs, GPUs, peripherals, etc.), and the power-sharing policy 144 can specify a power allocation by type (e.g., different percentages of a given power budget 142 for different types). For example, the power-sharing policy 144 can specify that a CPU group (e.g., components 120A-B) receives 40% of the available power from the power source 130A, and a GPU group (e.g., component 120C) receives the remaining 60% of the available power.Different sets of peripheral devices can be types of components such as audio peripherals, video peripherals, network peripherals, storage peripherals, etc. In another embodiment, however, components 120 can be grouped according to power domain. While the same power sharing policy 144 can be used for both power sources 130A-B, in some embodiments each power source 130 is assigned a specific power sharing policy 144. The type of grouping for each power sharing policy 144 can be based on the types of components 120 coupled to the corresponding power source 130—for example, if a particular power source 130 is coupled with CPU components and peripheral components, then its corresponding power sharing policy 144 can be based on a ratio assigned to CPUs and peripherals.

[0020] In various embodiments, the power divider 140 can also be programmed with a power source assignment 150, which specifies which components 120 are coupled to which power sources 130 of the system 100. As shown, for example, components 120A-B are coupled to power source 130A, and component 120C is coupled to power source 130B. Thus, for the embodiment shown, the power source assignment 150 assigns components 120A-B to power source 130A and component 120C to power source 130B. As explained previously, different systems 100 can have different power configurations (examples of which are given with reference to Fig. 4 discussed), and thus power source allocation 150 can differ between different systems 100. Accordingly, power divider 140 can determine, based on a given power source allocation 150, which power sources 130 of its system 100 are configured to supply power to those components 120 managed by power divider 140. Furthermore, in some embodiments, power source allocation 150 assigns power sources 130 of system 100 to other components of system 100 that are not managed by power divider 140 (e.g., memory, such as dynamic random-access memory).

[0021] When allocating power to components 120, the power divider 140, in various embodiments, accesses power source assignments 150 from internal programmable registers. Power budgets 142, power allocation policies 144, and power source assignments 150 can be stored during specific operating phases of the system 100 (e.g., the system 100's firmware can store power allocation policies 144 and power source assignments 150 during system startup; control software can store power budgets 142 during system use, etc.). Based on power source assignments 150, the power divider 140 can supply power to a given component 120 based on one or more power budgets 142 from one or more power sources 130 assigned to that given component 120.In the illustrated embodiment, for example, power divider 140 can allocate power to component 120A based on a power budget 142 from power source 130A (since component 120A is coupled to power source 130A) and power sharing policy 144. In some cases, power divider 140 can determine, based on power source allocation 150, that different power sources 130 supply power to a component 120, and thus power divider 140 can allocate power to this component 120 based on the respective power budgets 142 of these power sources. As with respect to . Fig. As discussed in more detail in section 3, the power divider can allocate 140 power to this component 120 based on the most limiting power source 130.

[0022] Now, referring to Fig. Figure 2 shows a block diagram of an embodiment of a set of components 120 coupled to a power divider 140. In the illustrated embodiment, each component 120 includes a set of subcomponents 210 (SCs 210) and a rate control circuit 220. As also shown, the power divider 140 is coupled to a die-to-die interface (D2D interface) 240, and two of the four illustrated components 120 are GPU components, and the remaining two are CPU components. Different combinations of components 120 can be coupled to the power divider 140, such as a combination of CPU components and peripheral components.

[0023] As explained, power divider 140 allocates power to components 120 and communicates corresponding information about the allocated power to these components 120. In particular, in various embodiments, power divider 140 provides one or more power credits 230 to a rate controller 220 of a component 120, where a credit 230 represents a defined quantity of power. In cases where multiple power sources 130 supply power to a particular component 120, power divider 140 can provide power credits 230 to the rate controller 220 of that component for each of these power sources 130. As mentioned in relation to Fig. As discussed in more detail in Section 3, a power divider 140 can provide a number of power credits 230 based on the most limiting power source 130 of the power sources 130 coupled to a component 120. By measuring credits 230 in terms of power (e.g., watts), the power divider 140 can provide information on the allocated quantities in a common format that can be transmitted across different power domains that may be operating at different voltages at any given time. Based on the power credits 230 provided to it, a rate controller 220 can manage the power consumption of its component 120.

[0024] To manage power consumption, in some embodiments a rate controller 220 is connected to a power control circuit enclosed within its component 120. Generally, a power control circuit can implement a set of power management mechanisms, each designed to reduce power consumption in its component 120 when that mechanism is enabled, compared to when it is disabled. For example, if a component 120 includes multiple pipelines, the power management mechanism can reduce the number of actively used pipelines, so that operations performed by that component 120 are carried out in a reduced number of pipelines, and power is conserved by the inactivity of one or more of the pipelines.Another performance management mechanism can involve reducing the output rate of operations in a pipeline, thus introducing "bubbles" into the pipeline where inactivity occurs. Yet another performance management mechanism can involve periodically terminating a pipeline or temporarily reducing the clock frequency of the clocks fed into the pipeline. Furthermore, clock manipulation techniques such as clock dithering, clock dividers, and clock throttling can be used.

[0025] In various cases, a component 120 can have subcomponent circuits 210 (referred to as "subcomponents" 210 for short). These subcomponents 210 can be relatively independent, so the power control circuit of this component 120 can disable one or more of the subcomponents 210 without preventing the operation of the remaining components. For example, a CPU processor cluster can have a large number of CPU processors, and one or more of these CPU processors can be disabled (e.g., blocked, clock-controlled, or even power-controlled) without preventing the remaining CPU processors from executing program instructions. Similarly, in a GPU, there can be several symmetric units, such as shaders, rasterizers, etc., which are subcomponents 210 that can be disabled.Accordingly, in a component 120 with subcomponent circuits 210, the power control circuit can implement power management mechanisms to disable or reduce the power of a subset of the subcomponents 210, while other subcomponents 210 can operate unhindered.

[0026] A given power control circuit can apply one or more of its various power management mechanisms based on an input from its corresponding rate controller 220. The rate controller 220 can determine which input to provide to the power control circuit based on the number of power credits 230 received for a power allocation cycle. For example, if a rate controller 220 receives fewer power credits 230 than the number required for its component 120 to operate at full capacity, then the rate controller 220 could, for example, provide a special input to the corresponding power control circuit that causes this power control circuit to reduce the number of pipelines actively in use.In various embodiments, the inputs provided by a rate controller 220 to a power control circuit specify different levels of aggressiveness that the power control circuit should apply to reduce power consumption. For more aggressive cases, the power control circuit can apply multiple power management mechanisms to reduce power. As the power balance 230 increases (e.g., returns to an amount associated with normal operation), the power control circuit can reduce the number of applied power management mechanisms or it can stop applying the power management mechanisms altogether.

[0027] As shown, rate controllers 220 are configured to generate power requests 225 and send them to power distributors 140. A power request 225 can specify a requested power quantity or a minimum value representing a minimum power quantity to ensure the proper operation of the associated component 120. In various embodiments, a rate controller 220 generates a power request 225 based on a power estimate received from a power estimator (included in the associated component 120), as well as on previously allocated and consumed power—the power estimate can be expressed in terms of power credits 230. The power estimate can be based on the current and / or expected processing demand on subcomponents 210 of the associated component 120.Thus, the power requested by a component 120 can vary between different power allocation cycles, and the power allocated to component 120 can also vary based on the requirements of the other components 120 connected to the power divider 140. In various embodiments, the power divider 140 ensures that the components 120 receive a power allocation that is at least equal to the minimum of their respective minimum values ​​to guarantee their correct operation. The remaining power budget (left over after fulfilling the minimum base values) of a power source 130 can then be allocated based on the power allocation policy 144 and the respective power requirements 225.

[0028] As mentioned, System 100 can be implemented on a single semiconductor substrate (one chip) or on multiple interconnected chips. The chips can be interconnected via D2D interface 240, and thus D2D interface 240 can enable a given power divider 140 to communicate with power dividers 140 on other chips. In particular, multiple chips can share a power source 130 (e.g., CLVR). Thus, a power divider 140 can share power credits 230 (corresponding to the deliverable power of this power source 130) that are not used by its local components 120 with other power dividers 140 on the other dies / chips and / or can receive power credits 230 from the other power dividers 140 for use by its components 120. An explanation of the sharing of power credits 230 among multiple dies will be given in relation to Fig. 5 to 8 provided.

[0029] Now, referring to Fig. Figure 3 shows a block diagram of an embodiment of a power divider 140. In the illustrated embodiments, the power divider 140 is coupled to a component 120 and comprises a power budget generator 310, a divider controller 320, a minimum selector 330, a residual distributor 340, and a transfer circuit 350. As further shown, the divider controller 320 includes a power allocation guideline 144 and a power source assignment 150. As also shown, component 120 is coupled to power sources 130A and 130B.

[0030] As explained, power divider 140 can allocate power to components 120 based on one or more power budgets 142 corresponding to one or more power sources 130. Power budget generator 310, in various embodiments, includes switching logic configured to generate power budgets 142 for power sources 130 of the system 100 or only for the power sources 130 assigned to the generator's power divider 140. To generate power budgets 142, power budget generator 310 receives power information 132, which provides information indicating the amount of available power from the various power sources 130.For example, a power management circuit can be a component 120 that indicates the amount of available power based on various power states managed by this power management circuit, as well as inputs from the power sources 130 and / or other parts of the external power management unit. The inputs can provide information regarding the loads of voltage regulators in case undervoltage events due to an overload of these voltage regulators are detected, etc.

[0031] Based on the received power indication(s) 132 and programmable configuration data, in various embodiments, the power budget generator 310 generates for each relevant power source 130 an indication of an available power quantity of that power source 130, represented as a number of power credits 230, where each power credit represents a specific power quantity (a number of watts). A power budget 142 can be based on various programmable values ​​(e.g., an initial budget) that can be modified based on the received power indication(s) 132. For example, a power indication 132 could indicate that power reduction is being requested from external (to the integrated circuit) hardware, such as the power management unit, even though the system hardware has not yet detected a problem.Power Budget Generator 310 can thus reduce the power budget 142 for the associated power source 130 in these cases. Furthermore, a power budget 142 can be adjusted based on unused power from a previous power cycle and / or from other shared power credits 230. For example, as discussed further below, the most limiting power source 130 with respect to a given component 120 can determine the power allocation provided to that component 120. If multiple power sources 130 supply power to this given component 120, then the excess power can be added in the next power allocation cycle from the corresponding power budgets 142 that supply more than the most limiting power source 130.

[0032] In one embodiment, a first-level voltage regulator (a power source 130) can be operated with fewer than a maximum number of active phases (e.g., a single-phase mode), and the power budget generator 310 can reduce the voltage regulator's power budget 142 based on the load current that the reduced number of phases can support (e.g., a reduced budget can be provided to match the reduced number of phases, and the power budget generator 310 can switch to the reduced budget based on an input specifying the reduced-phase mode). In other embodiments, the initial power budget of a power source 130 can be programmed to different values ​​by control software during use (e.g., within a predefined range that has been tested and is known to be safe).Controlling the software can modify the performance budget 142 to reduce or eliminate the occurrence of performance specifications 132, causing budget reductions which can improve overall efficiency.

[0033] The power budget generator 310 can further consider any dynamic random-access memory (DRAM) rails coupled to a power source 130, for which the power budget generator 310 generates a power budget 142. While in some embodiments no direct power control mechanisms for the DRAM are present, including the DRAM in the power allocation can enable the protection of power sources 130 (e.g., the battery) that also supply power to the DRAM. Accordingly, the power budget generator 310 can access power source allocation 150 to determine whether a particular power source 130 supplies power to the DRAM.

[0034] In various embodiments, the power budget generator 310 generates a power budget 142 for each power source 130 assigned to its power divider 140. Different power sources 130 can provide different amounts of available power and can thus include power budgets 142 of different amounts of power credits 230. For example, the power budget 142 for power source 130A may be one hundred power credits 230 in a particular power allocation cycle, while the power budget 142 for power source 130B may be fifty power credits 230 in the same power allocation cycle. In the next power allocation cycle, these power budgets 142 may change. In some embodiments, a power credit of a first power source (e.g., power source 130A) represents a different amount of power (e.g.,1 watt versus 2 watts) represents a power credit of a second power source (e.g., power source 130B). Power budget generator 310 provides the power budget(s) 142 to the divider controller 320, as shown – each power budget 142 can also include a specification of the corresponding power source 130.

[0035] Distribution controller 320, in various embodiments, is switching logic configured to distribute a received power budget 142 among components 120 connected to the power source 130 corresponding to that power budget 142. In various embodiments, distribution controller 320 distributes a power budget 142 based on power distribution policy 144 and power source allocation 150. In particular, power distribution policy 144 can specify percentages of power to be allocated to different groups of components (e.g., the CPU processors, GPU processors, specific peripherals, and the rest of the system 100 – components can be grouped according to criteria other than type).While considerable flexibility may be available when specifying the power distribution policy 144, at least the base amount of power for each component 120 should be available to ensure proper operation. Consequently, in various embodiments, distribution control 320 can override power distribution policy 144 so that the base amount of power is provided. That is, if a given group of components 120 is allocated too little power according to power distribution policy 144 to meet the base amount of power for members of that group, power control 320 can ensure that that component 120 receives the base amount (or the requested amount if less than the base amount).In various embodiments, the same power distribution policy 144 is applied to all power sources 130. This can be done to maintain relative importance across all power sources 130—that is, if CPUs are more important than GPUs for one power source 130, then this is likely to be true for another power source 130 as well. While in various embodiments the power controller 320 is configured to apply the same power distribution policy 144 to all power budgets 142, in some embodiments the distribution controller 320 applies a power source-specific power distribution policy 144 to the power budget 142 of that power source 130—that is, each power source 130 could have its own power distribution policy 144.

[0036] As part of the allocation of a power budget 142, the allocation controller 320, in various embodiments, accesses the power source allocation 150 (e.g., from a set of programmable registers) to determine which components 120 are allocated to this power budget 142. In particular, the allocation controller 320 can determine which components 120 are connected to a given power source 130 and then allocate the power budget 142 for that given power source 130 among those components 120. Thus, the allocation controller 320 can apply the power allocation policy 144 to the power budget 142 of a particular power source 130 to allocate the deliverable power of the particular power source 130 among components 120 that receive power from the particular power source 130, as specified by the power source allocation 150.After dividing the power budget(s) 142 based on power distribution policy 144 and power source allocation 150, the allocation controller 320 can provide the resulting power allocations to the minimum selector 330. However, in some embodiments, the allocation controller 320 provides the minimum selector 330 only with the power allocations for components 120 that are coupled with multiple power sources 130, and provides the remaining power allocation(s) (e.g., in the form of power credits 230) to the relevant component(s) 120. That is, if a particular component 120 is not coupled with multiple power sources 130 and therefore may not be assigned multiple power allocations, then it may not be necessary to select a minimum power allocation. Therefore, the power allocation to the particular component can be provided to it without sending the power allocation through the minimum selector 330.

[0037] Minimum selector 330, in various embodiments, is switching logic configured to select a minimum power allocation from a set of power allocations and provide it to a component 120 that is assigned to those power allocations. For example, as shown, component 120 is coupled to two power sources, 130A and 130B. Power sources 130A and 130B can be of different types (e.g., EVR and CLVR) and can be configured to supply different amounts of power to component 120 relative to the other power source 130. Consequently, minimum selector 330 can receive two power allocations for component 120: one power allocation corresponding to power source 130A and another power allocation corresponding to power source 130B.When allocating power credits 230 to component 120, minimum selector 330 selects the minimum power amount between the two power allocations and allocates this minimum power amount to component 120. For example, if 20 watts of power from power source 130A and 50 watts of power from power source 130B are available to component 120 based on power distribution policy 144, then minimum selector 330 can provide power credits 230 corresponding to 20 watts to component 120. In various embodiments, power divider 140 implements a delay-adjustment mechanism so that components 120 that are physically closer to power divider 140 receive their power allocation at approximately the same time as components 120 that are physically farther away from power divider 140.For example, each power allocation can be delayed by the difference between the actual transport delay to a component 120 and the transport delay to the most distant component 120 (for example, in the granularity of a clock cycle).

[0038] In various embodiments, power credits 230, representing the excess power (e.g., 30 watts) from power sources 130 configured to supply more than the selected minimum power, are provided to residual distributors 340 for reallocation. Residual distributor 340, in various embodiments, is switching logic configured to reallocate remaining / excess power credits 230 by providing power credits 230 to other power dividers 140 on other dies and / or adding power credits 230 to the power budget 142 of the corresponding power source 130 in the next power allocation cycle. One or more power credits 230 can be provided to transfer circuitry 350, which is configured to transfer these power credits to the other power dividers 140 on other dies via D2D interface 240.Additionally, if another power credit 230 is shared with the current power credit 230, these shared power credits 230 can be received via D2D interface circuit 240 and can be sent to power budget generator 310 to be added to a corresponding power budget 142. As per [reference to...]. Fig. As discussed in more detail in section 6, performance credits 230 for different performance budgets 142 can be sent and received via D2D interface 240.

[0039] With reference to Fig. Figure 4 shows a block diagram of different device configurations 410, each with a different power source configuration. In the illustrated embodiment, there are three device configurations: 410A, 410B, and 410C. As shown, device configuration 410A includes three components 120 coupled to a power divider 140 and a power source 130A. As further shown, device configuration 410B includes a power source 130B coupled to two components 120 and a power source 130C coupled to a third component 120, all three components 120 being coupled to a power divider 140.As also shown, device configuration 410C includes a power source 130D coupled to two components 120, and a power source 130E coupled to two components 120, one of which overlaps with the power source 130D – all three components 120 are coupled to a power divider 140. Other device configurations 410 may have more or fewer power sources 130 and / or more or fewer components 120.

[0040] In various cases, the same design for a power divider 140 is used in different device configurations 410, which may correspond to different products (e.g., laptops, tablets, phones, etc.) with different power source configurations. As discussed, in order to support the different configurations, a power divider 140 stores a mapping 150 between components 120 and power sources 130 of its device configuration 410. The mapping 150 can represent different device configurations 410 with different power configurations, and thus, through this mapping 150, a power divider 140 can determine the specific configuration of its system from power sources 130 to component 120.For example, assignment 150A of device configuration 410A differs from assignment 150B of device configuration 410B because device configuration 410B has multiple power sources 130.

[0041] While device configuration 410B and device configuration 410C have the same number of power sources 130, assignment 150B differs from assignment 150C of configuration 410C because the power sources 130 of device configuration 410C are coupled to the three illustrated components 120 differently than the power sources 130 of device configuration 410B. Accordingly, based on assignment 150 of a given device configuration 410, a power divider 140 can allocate power credits 230 to the components 120 of that given device configuration 410.

[0042] With reference to Fig. Figure 5 shows a block diagram of an embodiment of a multi-die configuration with dies 500 that can share power credits 230 for multiple power sources 130. In the illustrated embodiment, there are dies 500A and 500B coupled to each other via a D2D interface 240, and power sources 130A and 130B coupled to dies 500A and 500B. As further shown, die 500A includes a set of components 120 coupled to a power divider 140A, and die 500B includes a set of components 120 coupled to a power divider 140B. As also shown, power dividers 140A and 140B each include power credits 230A corresponding to power source 130A and power credits 230B corresponding to power source 130B, respectively.

[0043] Integrated Circuit Dies 500 (or simply "dies") are component packages in various configurations that integrate one or more components (e.g., Component 120, Power Divider 140A, etc.) onto respective semiconductor substrates—each Die 500 can be a SoC. In some cases, Dies 500A and 500B may contain the same set of hardware components printed on each chip and are referred to as symmetrical dies relative to each other. In other cases, Dies 500A and 500B may contain different sets of hardware components printed on each chip and are referred to as asymmetrical dies relative to each other. For example, Die 500A may be a CPU die, containing CPU-oriented components, while Die 500B may be a GPU die, containing GPU-oriented components, and thus these Dies 500 are asymmetrical.In various embodiments, Dies 500A and 500B are configured as a single system in which the presence of multiple dies is transparent to software running on the single system - System 100 can be a multi-die system in which the hardware hides the fact that there are multiple dies from software (e.g., by ensuring that latencies are low, keeping power states synchronized, etc.).

[0044] In various embodiments, several Dies 500 can be powered by a single power source 130 (e.g., a first-level voltage regulator up to second-level voltage regulators). Since Dies 500A and 500B share a common power source 130 (e.g., power source 130A), in various embodiments their respective power dividers 140 can share power credits 230 while still protecting the capacity of the same power source 130. Accordingly, power divider 140A can send power credits 230 corresponding to unused power to power divider 140B, which can then be used by power divider 140B to allocate additional power from the shared power source 130 to components 120 of Die 500B. These power credits 230 can be included in a subsequent power allocation.Furthermore, multiple power sources can supply 130 power to the same dies (as shown), and thus power dividers can share power credits of 230 for multiple power sources. For example, as shown, power dividers 140A and 140B share power credits of 230A for power source 130A and 230B for power sources 130B.

[0045] Various combinations for distributing power credits are possible. For example, power divider 140A can share power credits 230 for power sources 130A and 130B in one power allocation cycle, while receiving no power credits 230 from power divider 140B within that same cycle. In another power allocation cycle, power divider 140A can share only power credits 230A, while power divider 140B can share only power credits 230B. In yet another power allocation cycle, both power dividers 140A and 140B can share power credits 230 for both power sources 130A and 130B. In various embodiments, a power divider 140 is forced to share at least one portion of the power credits 230 for a given power source 130 (if sharing is applicable).Accordingly, the power divider 140 can 1) ensure that the base values ​​of its components 120 are met, 2) share a defined number of power credits 230 with power dividers 140 of other dies 500, and 3) then allocate additional power to its components 120 from the remaining power budget 142 based on a power sharing policy 144. The number of power credits 230 that a power divider 140 is required to share can be defined in a power distribution policy 144 or in a separate forced sharing policy, which can be stored in programmable registers accessible to a power divider 140. Furthermore, power dividers 140 located in different dies 500 can use the same power sharing policy 144 or different power sharing policies 144.

[0046] With reference to Fig. Figure 6 shows a block diagram of an embodiment of power credits 230 shared between dies 500 via a D2D interface 240. In the illustrated embodiment, die 500A includes a power divider 140 that allocates power credits 230A, 230B, and 230C, each corresponding to different power sources 130. As shown, power divider 140 includes a transfer circuit 350 connected to D2D interface 240 to transfer power credits 230A, 230B, and 230C to die 500B. As further shown, D2D interface 240 includes a multiplexer 600 configured to transfer these power credits 230.

[0047] To reduce the number of physical lines in D2D interface 240 between dies 500, in various embodiments the dies 500 are configured to each send one type of power credit using the multiplexer 600. In various embodiments, the multiplexer 600 is switching logic configured to send power credit 230 from a first given power source 130 before power credit 230 from a second given power source 130 on the same set of lines. As illustrated, for example, power divider 140 causes power credit 230A to be sent first, followed by power credit 230B, and finally power credit 230C. In some embodiments, D2D interface 240 does not include a multiplexer 600, and instead, transmission circuitry 350 controls the flow of power credit 230 on the same set of lines of D2D interface 240.In some embodiments, the D2D interface 240 supports multiple power credit types being transmitted in parallel over separate lines. Consequently, power credits 230A-C can be transmitted in parallel over the D2D interface 240, instead of sequentially. This can improve the transmission speed of multiple power credit types at the cost of die space and the complexity associated with adding and managing the additional bus lines.

[0048] In some cases, a Die 500 is coupled with several Dies 500s arranged around it – for example, a Die 500 might be located between several Dies 500s, as in Fig. Figure 7 shows that a section of the D2D interface 500 can be located on different sides of a Dies 500 to allow it to send power credits 500 to the surrounding Dies 500s. For example, in the case of a Dies 500 located between two Dies 500s, it can send power credits 230 in one direction on D2D interface 240 to one of the other two Dies 500s and can send power credits 230 in the other direction on D2D interface 240 to the other Dies 500. In some cases, in a multi-die layout, a particular Die 500 can only be paired with one other Die 500, which can be paired with multiple Dies 500s. The special Die 500 may only be able to send performance credits 230 in one direction (i.e., to the other Die 500 that is coupled to it).

[0049] Now, referring to Fig. Figure 7 shows a block diagram of an embodiment of an asymmetric layout of Dies 500. In the illustrated embodiment, there are Dies 500A-D and power sources 130A-B. As further shown, Die 500A is coupled to Die 500B and power source 130A, Die 500B is coupled to Die 500C and power source 130B, Die 500C is coupled to Die 500D and power source 130B, and Die 500D is coupled to power source 130A. As shown, Dies 500A and 500D are CPU dies, while Dies 500B and 500C are GPU dies.

[0050] In certain device configurations, multiple dies 500 can share a power source 130 but be separated by one or more intervening dies 500 that are not coupled to this power source. This can occur in asymmetric layouts, such as the one illustrated, because symmetrically similar dies 500 can share a power source 130 for which it is undesirable to be coupled with intervening dies 500 that are asymmetric with respect to these symmetrically similar dies 500. For example, two dies 500 that include a first processor type (e.g., CPUs) but not a second processor type (e.g., GPUs) can share a power source 130 that is not shared with a set of intervening dies 500 that include the second processor type but not the first.In various embodiments, dies 500s sharing a power source 130 are configured to share power credits 230, even in cases where intervening dies 500s are present that cannot use these power credits 230 because they are not coupled to the power source 130 and therefore cannot receive power from it. To share power credits 230 in such cases, in various embodiments, a die 500 transfers these power credits 230 through the intervening dies 500s (via D2D interface 240) to the target die 500 that shares the particular power source 130. As shown, for example, power dividers 140A and 140D share power credits 230A (corresponding to power source 130A) by sending them through dies 500B and 500C. The 500B and 500C do not use these 230A power credits because they are not connected to the 130A power source.Instead, in various embodiments, these dies include switching logic configured to forward these power credits 230 to the nearest adjacent die 500.

[0051] Accordingly, when allocating power to a power source 130 configured to supply power to dies 500 separated by intermediate dies 500, the power dividers 140 of these dies 500 can generate power budgets 142 for that power source 130. These power budgets 142 can be generated based on a power sharing policy 144 and a power source mapping 150, which allows a given power divider 140 to determine which other power dividers 140 and their dies 500 are connected to a particular power source 130. For example, power divider 140A can determine from a power source mapping 150 that die 500D is connected to power source 130A, and thus power divider 140A can share power credits 230A with power divider 140D.Based on the power budgets 142, the power dividers 140 can allocate at least a subset of power credits 230 from their respective power budgets 142 to components 120 in their respective dies 500 (e.g., to meet minimum values ​​of these components 120). The power dividers 140 can then provide a subset of power credits to their companion die(s) 500 (e.g., power divider 140A can send power credit 230A to power divider 140D in die 500D and vice versa) through the intermediate dies 500 (e.g., dies 500B and 500C) without the intermediate dies 500 using the power credits 230 to obtain power from the power source 130.

[0052] In various embodiments, power dividers 140 share power credits 230 that remain after fulfilling the requirements of their components 120. Thus, in one power allocation, a power divider 140 may share power credits 230 with another power divider 140, and then in the next power allocation, it may not share any power credits 230 (e.g., due to changes in the requirements of its own components 120). In some embodiments, a power-sharing policy 144 specifies a number of power credits 230 that must be shared in a power allocation, although more could be shared. Thus, a power divider 140 may share a minimum number of power credits 230 (e.g., 20% of a power budget 142) with another power divider 140 for each power allocation.

[0053] In various cases (e.g., in asymmetrical layouts), certain Dies 500 are coupled to a Power Source 130 without any intervening Dies 500. For example, Dies 500B and 500C are coupled to Power Source 130B, and there is no intervening Die 500 between them. Therefore, these Dies 500 can share power credits (e.g., power credit 230B corresponding to Power Source 130B) without sending them through intervening Dies 500. While Dies 500A-D in Fig. While the Dies 500A-D are arranged in a straight line, other asymmetrical layouts than those shown can be used. For example, Dies 500A-D could be arranged in a circle, with, say, Die 500A and Die 500D placed on the west and east sides of the circle, respectively, and Die 500B and Die 500C placed on the north and south sides, respectively. In such a layout, both symmetrical sets of Dies (e.g., Dies 500A / D and Dies 500B / C) can share power credits through intervening Dies 500 that do not use them—that is, Die 500A and Die 500D can send power credits to each other through Die 500B or 500C, and Die 500B and Die 500C can send power credits to each other through Die 500A or 500D.

[0054] Now, referring to Fig. Figure 8 shows a block diagram of an embodiment of an asymmetric layout of Dies 500. In the illustrated embodiment, there are Dies 500A-D and power sources 130A-B. As shown, Die 500A is coupled to Die 500B and power sources 130A and 130B, Die 500B is coupled to Die 500C and power source 130B, Die 500C is coupled to Die 500D and power source 130B, and Die 500D is coupled to power sources 130A and 130B. As also shown, Dies 500A and 500D are CPU dies, while Dies 500B and 500C are GPU dies.

[0055] In various embodiments, symmetrically similar Dies 500 can share a power source 130 with Dies 500 that are asymmetric with respect to these symmetrically similar Dies 500. As shown, for example, all Dies 500A-D share power source 130B. Power source 130B can be a battery of a system 100 with Dies 500A-D. It may be desirable to couple all Dies 500 of this system 100 to a battery so that these Dies 500 can continue to receive power when this system 100 is, for example, not connected to a power outlet. In various embodiments, Dies 500A-D are configured to share power credits 230B for power source 130B, although Dies 500A and 500D are asymmetric with respect to Dies 500B and 500C.

[0056] Different approaches can be used when power credits 230 are shared with many dies 500. In some embodiments, a power divider 140 divides the power credits 230 to be shared into equal amounts, so that each of the other dies 500s receives an equal (or approximately equal) amount of power credits 230. For example, die 500 can provide ten power credits 230B to dies 500B, 500C, and 500D. In some embodiments, a power divider 140 divides power credits 230 based on the type of die 500 with which it is sharing—for example, GPU dies 500s can receive more power credits 230 than CPU dies 500. In some embodiments, a power divider 140 divides power credits 230 based on whether a particular die 500 is symmetrically similar to it.For example, power divider 140A can provide 20 power credits 230B to Die 500D from 30 power credits 230B, since it is symmetrically similar, and 5 power credits 230B each to Die 500B and 500C, since these are asymmetric with respect to Die 500A. In some embodiments, a power divider 140 provides all power credits 230 (of those being divided) to the adjacent Die 500, which can use them all or send at least a portion to the next adjacent Die 500. For example, power divider 140A can provide 30 power credits 230B to Die 500B, and Die 500B can use 10 of these power credits 230B and send the remaining amount to Die 500C. Any combination of the above approaches can be used.Other approaches can be used and are being considered, such as a Die 500 making a request for a specific amount of Performance Credits 230 to the other Dies 500, and these Dies 500 allocating their Performance Credits 230 (of those to be shared) based on that request.

[0057] While asymmetrical layouts of the Dies 500A-D in Fig. 7 and Fig. As illustrated in Figure 8, Dies 500A-D can be arranged in various ways. For example, Die 500A and 500D can be directly coupled, and either of these two Dies 500 can be directly coupled to Die 500B or 500C, which can be directly coupled to each other—i.e., CPU-Die<-> CPU-Die<-> GPU-Die<-> GPU-Die. In such a layout, Dies 500A and 500D can directly share power credits 230, and Dies 500B and 500C can also share power credits 230 without routing them through intervening asymmetric Dies 500. Additionally, in some power configurations, there can be a first set of Dies 500 sharing a power source 130 and separated by a second set of intervening Dies 500 that are symmetrically similar to the first set of Dies 500.The first set of Dies 500 can divide performance credits 500 by the second set of intermediate Dies 500 without the intermediate Dies 500 using these performance credits 230 to obtain performance from this performance source 130.

[0058] Now, referring to Fig. Figure 9 shows a flowchart of Method 900. Method 900 is an embodiment of a method performed by a power divider circuit (e.g., Power Divider 140) to allocate power to a plurality of component circuits (e.g., Components 120) coupled to a plurality of power sources (e.g., Power Sources 130A-B). Method 900 may include more steps than shown. For example, Method 900 could include a step in which the power divider circuit actively shares power credits with another power divider circuit (which may be on a different die) to obtain power from the power sources.

[0059] Method 900 begins in step 910 with the power divider circuit accessing information (e.g., power source assignment 150) from one or more programmable registers accessible to the power divider circuit. This information specifies which of the system's multiple power sources are configured to supply power to the multiple component circuits managed by the power divider circuit. In step 920, based on this information, the power divider circuit determines that several of the multiple power sources are configured to supply power to a particular component circuit. In some embodiments, at least two of these power sources are of different types (e.g., EVR and CLVR) and are each configured to supply a different amount of power to the particular component circuit.At least one of the multiple power sources can be a battery.

[0060] In step 930, the power divider circuit then allocates power to the special component circuit based on the respective power budgets (e.g., power budgets 142) of the multiple power sources. Allocating power to the special component circuit may involve the power divider circuit determining a plurality of power quantities that can be supplied to the special component circuit by the multiple power sources based on their respective power budgets. The power divider circuit may then select a minimum of the plurality of power quantities and allocate this minimum power quantity to the special component circuit. In some embodiments, the power divider circuit shares power credits corresponding to unused power with another power divider circuit that manages a different component circuit.The other power divider circuit can then allocate additional power from the multiple power sources of the different component circuits based on the power credits.

[0061] Now, referring to Fig. Figure 10 shows a flowchart of a method 1000. Method 1000 is an embodiment of a method performed by a power divider circuit (e.g., power divider 140) to allocate power to a plurality of component circuits (e.g., components 120) coupled to a plurality of power sources (e.g., power sources 130A-B). Method 1000 may include more or fewer steps than shown. For example, method 1000 could include a step in which the power divider circuit actively shares power credits with another power divider circuit (which may be on a different die) to obtain power from the power sources.

[0062] Method 1000 begins in step 1010 with the power divider circuit accessing from one or more programmable registers an assignment (e.g., power source assignment 150) that maps between individual components of the plurality of component circuits and individual power sources of the plurality. Two of the plurality of power sources can be configured to supply different amounts of power, and a particular component of the plurality can also be configured to receive power from the two or more power sources. In some cases, a first power source of the plurality can be an electronic voltage regulator, and a second power source of the plurality can be an inductor-based voltage regulator. At least one component of the plurality can be a graphics processing unit (GPU).

[0063] In step 1020, the power divider circuit allocates power to a given plurality of component circuits based on one or more power budgets (e.g., power budgets 142) of one or more power sources assigned to the given component circuit, as specified by the assignment. In various embodiments, the power divider circuit is configured to allocate power to at least two different component circuits coupled to different power sources. Two power sources can supply power to a particular component circuit. The power divider circuit can determine a first amount of power to supply the particular component circuit from one of the first of the two power sources, and a second amount of power to supply the particular component circuit from a second of the two power sources.The power divider circuit can then select a minimum of the first power quantity and the second power quantity and allocate the minimum power quantity to the specific component circuit. The power divider circuit can reallocate an unused power portion from at least one of the power sources (e.g., the second power source if it did not provide the minimum power) to a corresponding power budget (e.g., the budget of the second power source) in the next power allocation cycle. In various embodiments, the power divider circuit is configured to apply the same power allocation policy (e.g., a power allocation policy 144) to the respective power budgets of the power sources. Allocated power can be represented in the form of a plurality of credits.A given credit can represent a specified amount of power, and a given component circuit can include a rate control circuit configured to manage power consumption in the given component circuit based on received allocated credits.

[0064] In some embodiments, the system includes a plurality of integrated circuit dies coupled together. A first integrated circuit die may include the plurality of component circuits and the power divider circuit, and a second integrated circuit die may include a plurality of component circuits and another power divider circuit. The first and second integrated circuit dies may be symmetrical or asymmetrical with respect to each other. In some embodiments, at least two of the plurality of power sources are configured to supply power to the same integrated circuit dies of the plurality of integrated circuit dies.

[0065] Now, referring to Fig. Figure 11 shows a flowchart of a method 1100. Method 1100 is an embodiment of a method that starts from a first integrated circuit die (e.g., the 500A die). Fig. 7) as part of the allocation of power from a set of power sources (e.g., power sources 130). Procedure 1100 begins in step 1110 with the first integrated circuit die accessing information that identifies a power budget (e.g., a power budget 142) of a first power source configured to power the first integrated circuit die and a second integrated circuit die (e.g., the 500D from Fig. 7) to provide power. In various embodiments, power is available from the first power source based on a plurality of power credits included in the power budget.

[0066] In step 1120, the first integrated circuit die assigns a first set of the plurality of power credits to a set of component circuits (e.g., Component 120) of the first integrated circuit die. In step 1130, the first integrated circuit die sends a second set of the plurality of power credits to the second integrated circuit die through a set of intermediate integrated circuit dies (e.g., Die 500B-C of the first). Fig. 7) without the set of intermediate integrated circuit dies using the second set of power credits to obtain power from the first power source. In various embodiments, the first and second integrated circuit dies are asymmetric with respect to the set of intermediate integrated circuit dies—for example, the first and second integrated circuit dies include CPU circuits, and the set of intermediate integrated circuit dies includes GPU circuits. The first power source may not supply power to the set of intermediate integrated circuit dies. Furthermore, the first integrated circuit die may receive a third set of power credits for the first power source from the second integrated circuit die and allocate the third set of power credits to the set of component circuits of the first integrated circuit die.

[0067] In some cases, the first integrated circuit die sends a fourth set of power credits to a special intermediate die. The special intermediate die can receive power based on the fourth set of power credits from a second power source configured to supply power to both the first integrated circuit die and the special intermediate die. The second set of credits can be sent before the fourth set of credits on the same set of lines of a die-to-die interface connecting the first integrated circuit die to the special intermediate die.

[0068] Now, referring to Fig. Figure 12 shows a flowchart of a method 1200. Method 1200 is an embodiment of a method that starts with a first integrated circuit die (e.g., the 500A die from Fig. 7) is performed as part of the allocation of power from a set of power sources (e.g., power sources 130). Procedure 1200 begins in step 1210 with the first integrated circuit die allocating a first set of power credits to a first set of component circuits (e.g., components 120) of the first integrated circuit die, which is configured to receive power from a first power source based on the first set of power credits.

[0069] In step 1220, the first integrated circuit die sends a second set of power credits to a second integrated circuit die through the set of intermediate integrated circuit dies, which is configured to receive power from the first power source based on the second set of power credits. The group of intermediate integrated circuit dies may not be configured to use the second set of power credits to receive power from the first power source. In various embodiments, individual components of the set of intermediate integrated circuit dies are configured to share power credits with each other to receive power from a second power source without sending those power credits through other integrated circuit dies (e.g., dies 500B-C of Fig. 7. Share power credits directly). In various embodiments, the first and second integrated circuit dies are asymmetric with respect to the set of intermediate integrated circuit dies. For example, the first and second integrated circuit dies may include central processing units (CPUs) but not graphics processing units (GPUs), while the set of intermediate integrated circuit dies may include GPU processors but not CPU processors.

[0070] A second power source can be configured to supply power to component circuits of the first and second integrated circuit dies. The first integrated circuit die can allocate a third set of power credits to a second set of component circuits of the first integrated circuit die, which can be used to receive power from the second power source, and send a fourth set of power credits to the second integrated circuit die through the set of intervening integrated circuit dies, which can also be used to receive power from the second power source. In various embodiments, the first and second power sources are different types of power sources (e.g., EVR and CLVR). The first integrated circuit die can be coupled to a multiplexer circuit (e.g., Multiplexer 600) configured to operate on the same set of lines of a die-to-die interface (e.g., a 600-series interface).B. D2D interface 240) to send the credit balance of a first given power source before the credit balance of a second given power source.

[0071] A power source can be configured to supply power to component circuits of the first and second integrated circuit dies and the set of intermediate integrated circuit dies. Therefore, the first and second integrated circuit dies and the set of intermediate integrated circuit dies can be configured to share power reserves to receive power from the second power source. In some cases, the power source is a battery.

[0072] Realizations of the subject matter of the application are, but are not limited to, the following examples 1 to 40. 1. System, comprehensive: a plurality of integrated circuit dies, wherein a first plurality of integrated circuit dies is indirectly coupled to a second plurality of integrated circuit dies by a set of intermediate integrated circuit dies; and a first power source configured to supply power to component circuits of the first and second integrated circuit dies, wherein the first and second integrated circuit dies are configured to receive power from the first power source based on first power credits actively shared between the first and second integrated circuit dies, and wherein the first integrated circuit die is configured to send a first set of power credits to the second integrated circuit die through the set of intermediate integrated circuit dies, without the set of intermediate integrated circuit dies using the first set of power credits to receive power from the first power source. 2. System of Example 1, wherein the set of interposed integrated circuit dies is configured to receive power from a second power source based on second power credits actively shared between the set of interposed integrated circuit dies. 3. System of Example 2, wherein the set of intervening integrated circuit dies is configured to share the second power credits with each other without sending the second power credits through other integrated circuit dies. 4. System of Example 1, further comprising: a second power source configured to supply power to component circuits of the first and second integrated circuit dies, wherein the first and second integrated circuit dies are configured to receive power from the second power source based on second power credits actively shared between the first and second integrated circuit dies, and wherein the first integrated circuit die is configured to send a second set of power credits to the second integrated circuit die through the set of intervening integrated circuit dies. 5. System of Example 4, where the first and second power sources are different types of power sources. 6. System of Example 4, wherein the first integrated circuit die is coupled to a multiplexer circuit configured to send power credits of a first given power source ahead of power credits of a second given power source on an equal set of lines of a die-to-die interface. 7. System of Example 1, further comprising: a second power source configured to supply power to component circuits of the first and second integrated circuit dies and the set of intermediate integrated circuit dies, wherein the first and second integrated circuit dies and the set of intermediate integrated circuit dies are configured to receive power from the second power source based on power credits actively shared between the first and second integrated circuit dies and the set of intermediate integrated circuit dies. 8. System of Example 7, where the second power source is a battery. 9. System of Example 1, wherein the first power source is not coupled to the set of intermediate integrated circuit dies in order to supply power to the set of intermediate circuit dies. 10. System of Example 1, wherein the first and second integrated circuit dies include a first processor type but not a second processor type, and the set of intermediate integrated circuit dies includes the second processor type but not the first processor type. 11. Procedure, comprehensive: Accessing, through a first integrated circuit die, information that identifies a power budget of a first power source configured to supply power to the first integrated circuit die and a second integrated circuit die, with power available from the first power source based on a plurality of power credits included in the power budget; Allocate, by the first integrated circuit die, a first set of the multitude of power credits to a set of component circuits of the first integrated circuit die; and Sending, through the first integrated circuit die, a second set of the plurality of power credits to the second integrated circuit die through a set of intermediate integrated circuit dies, without the set of intermediate integrated circuit dies using the second set of power credits to obtain power from the first power source. 12. Procedure of Example 11, further comprising: Sending, through the first integrated circuit die, a third set of power credits to a special set of intermediate integrated circuit dies, wherein the special intermediate integrated circuit die is configured to receive power based on the third set of power credits from a second power source configured to supply power to the first integrated circuit die and the special intermediate integrated circuit die. 13. Method of Example 12, wherein the second set of credits is sent before the third set of credits on an equal set of lines of a die-to-die interface connecting the first integrated circuit die to the special intermediate integrated circuit die. 14. Procedure of Example 11, further comprising: Received, by the first integrated circuit die and by the second integrated circuit die, a third set of power credits for the first power source; and Allocating, by the first integrated circuit die, of power to the set of component circuits of the first integrated circuit die based on the third set of power credits. 15. Method of Example 11, wherein the first power source does not supply power to the set of intermediate integrated circuit dies. 16. Method of Example 11, wherein the first and second integrated circuit dies are asymmetric with respect to the set of intervening integrated circuit dies. 17. Method of Example 16, wherein the first and second integrated circuit dies include central processing units (CPUs) but do not include graphics processing units (GPUs), while the set of intermediate integrated circuit dies includes GPU processors but not CPU processors. 18. Non-transitory computer-readable medium containing design information that specifies a circuit design in a format recognizable by a manufacturing system configured to use the design information to manufacture a hardware-integrated circuit comprising: a plurality of integrated circuit dies, wherein a first plurality of integrated circuit dies is indirectly coupled to a second plurality of integrated circuit dies by a set of intermediate integrated circuit dies; and a first power source configured to supply power to component circuits of the first and second integrated circuit dies, where the first die is configured with an integrated circuit for: Allocate to a first set of component circuits of the first integrated circuit die, a first set of power credits, wherein the first set of component circuits is configured to receive power from the first power source based on the first set of power credits; and Sending to the second integrated circuit die through the set of interposed integrated circuit dies, a second set of power credits, wherein the second integrated circuit die is configured to receive power from the first power source based on the second set of power credits. 19. Medium of Example 18, wherein the set of intervening integrated circuit dies is not configured to use the second set of power credits to obtain power from the first power source. 20. Medium of Example 18, wherein individual components from the set of intervening integrated circuit dies are configured to receive power from a second power source based on actively shared power credits, without sending those power credits through other integrated circuit dies. 21. System, comprehensive: a large number of component circuits; a plurality of power sources, wherein at least two of the plurality of power sources are configured to supply power to respective sets of the plurality of component circuits; and A power divider circuit coupled to a plurality of component circuits, wherein the power divider circuit includes one or more programmable registers configured to store an assignment between one of the plurality of component circuits and one of the plurality of power sources, wherein the power divider circuit is configured to: Allocating power to a given plurality of component circuits based on one or more power budgets of one or more power sources assigned to the given component circuit, as specified by the allocation. 22. System of Example 21, wherein multiple power sources of the multitude of power sources are each configured to supply a respective different amount of power. 23. System of Example 22, where the power divider circuit is configured to: Determine, based on the respective power budgets of the multiple power sources and a set of power sharing policies, a multitude of power quantities that can be supplied by the multiple power sources to a particular or a multitude of component circuits; Selecting a minimum of the multitude of power quantities; and allocating the minimum power quantity to the specific component circuit. 24. System of Example 23, wherein the power divider circuit is configured to reallocate an unused power portion from at least one of the multiple power sources to a corresponding power budget in a subsequent power allocation cycle. 25. System of Example 23, wherein the power divider circuit is configured to apply an equal power sharing policy to the respective power budgets of the multiple power sources. 26. System of Example 21, wherein the power divider circuit is configured to allocate power to at least two different component circuits coupled to different power sources. 27. System of Example 21, further comprising: a multitude of interconnected integrated circuit dies, including the multitude of integrated circuit dies: a first integrated circuit die that includes the multitude of component circuits and the power divider circuit; and a second integrated circuit die, which includes a further variety of component circuits and another power divider circuit; wherein at least two of the plurality of power sources are configured to supply power to an equal integrated circuit die of the plurality of integrated circuit dies. 28. System of Example 27, wherein the first integrated circuit die and the second integrated circuit die are asymmetric to each other. 29. System of Example 21, wherein the allocated power is represented in the form of a plurality of power credits, wherein a given power credit represents a specified amount of power, and wherein the given component circuit includes a rate control circuit configured to manage the power consumption in the given component circuit based on received allocated power credits. 30. System of Example 21, wherein a first of the plurality of power sources is an electronic voltage regulator, and a second of the plurality of power sources is an inductor-based voltage regulator. 31. System of Example 21, wherein at least one of the plurality of component circuits is a graphics processing unit (GPU). 32. Procedure, comprehensive: Accessing, through a power divider circuit of a system, information from one or more programmable registers accessible to the power divider circuit, wherein the information specifies which of a plurality of power sources of the system are configured to supply power to individual components of a plurality of component circuits managed by the power divider circuit; Determine, by means of the power divider circuit based on the information that several of the multitude of power sources are configured to supply power to a particular one of the multitude of component circuits; and Allocation, via the power divider circuit, of power to the specific component circuit based on the respective power budgets of the multiple power sources. 33. Method of Example 32, wherein at least two of the multiple power sources are of different types and are each configured to supply a different amount of power to the particular component circuit. 34. Method of Example 32, including the allocation of power to the particular component circuit: Determining a variety of power quantities that can be supplied by the multiple power sources of the particular component circuit, based on the respective power budgets; Selecting a minimum of the multitude of power quantities; and allocating the minimum power quantity to the specific component circuit. 35. Procedure of Example 32, further comprising: Providing, through the power divider circuit and to a different power divider circuit managing a different component circuit, of power credits corresponding to unused power, wherein the different power divider circuit is configured to supply additional power from the multiple power sources of the other component circuit based on the power credits. 36. Method of Example 32, including the allocation of power to the particular component circuit: Applying a power sharing policy to a power budget of a particular of several power sources to divide the deliverable power of the particular power source among component circuits that receive power from the particular power source, wherein the power allocated to the particular component circuit is based on the divided deliverable power. 37. Method of Example 32, wherein at least one of the multiple power sources is a battery. 38. Non-transitory computer-readable medium containing design information that specifies a circuit design in a format recognizable by a manufacturing system configured to use the design information to manufacture a hardware-integrated circuit comprising: a large number of integrated circuit dies that are coupled together; and a multitude of power sources, wherein at least two of the multitude of power sources are configured to supply power to a particular one of the multitude of integrated circuit dies, wherein the particular integrated circuit die comprises a plurality of component circuits coupled to a power divider circuit which includes one or more programmable registers configured to store an assignment between one of the plurality of component circuits and one of the at least two power sources, wherein the power divider circuit is configured to: Accessing the mapping from one or more programmable registers; and Allocating power to a given plurality of component circuits based on one or more power budgets of one or more power sources assigned to the given component circuit, as specified by the allocation. 39. Medium of Example 38, wherein two of the plurality of power sources are configured to supply a different amount of power, and wherein a particular one of the plurality of component circuits is configured to receive power from the two power sources. 40. Medium of Example 38, wherein two of the plurality of power sources are configured to supply power to a particular one of the plurality of component circuits, and wherein the power divider circuit is configured to: Determining a first amount of power to be supplied to the particular component circuit from one of the two power sources; and Determining a second power quantity to supply the special component circuit from a second of the two power sources; Selecting a minimum from the first power quantity and the second power quantity; and Allocating the minimum power quantity to the specific component circuit. Example device

[0073] Now, referring to Fig. Figure 13 shows a block diagram illustrating an exemplary embodiment of a device 1300. In various embodiments, device 1300 corresponds to system 100. Elements of device 1300 can be enclosed in a system-on-a-chip. In some embodiments, device 1300 is enclosed in a mobile device, which may be battery-powered. Thus, the power consumption of device 1300 can be an important design consideration. In the illustrated embodiment, device 1300 includes fabric 1310, compute complex 1320, input / output bridge (I / O bridge) 1350, cache / memory controller 1345, graphics unit 1375, and display unit 1365. Compute complex 1320, cache / memory controller 1345, input / output (I / O) bridge 1350, graphics unit 1375, and display unit 1365 can be components 120.In some embodiments, device 1300 may include other components (not shown) in addition to or instead of the illustrated components, such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0074] The Fabric 1310 can include various intermediate connections, buses, MUXs, controllers, etc., and can be configured to support communication between different elements of the Device 1300. In some embodiments, sections of the Fabric 1310 can be configured to implement different communication protocols. In other embodiments, the Fabric 1310 can implement a single communication protocol, and elements connected to the Fabric 1310 can internally translate from this single communication protocol to other communication protocols.

[0075] In the illustrated embodiment, Computing Complex 1320 includes Bus Interface Unit (BIU) 1325, Cache 1330, and Cores 1335 and 1340. In various embodiments, Computing Complex 1320 can include different numbers of processors, processor cores, and caches. For example, Computing Complex 1320 can include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, Cache 1330 is a set associative L2 cache. In some embodiments, Cores 1335 and 1340 can include internal instruction and data caches. In some embodiments, a Coherence Unit (not shown) can be configured in Fabric 1310, Cache 1330, or elsewhere in Device 1300 to maintain coherence between different caches of Device 1300. The BIU 1325 can be configured to manage communication between the computing complex 1320 and other elements of the device 1300.Processor cores, such as the 1335 and 1340 cores, can be configured to execute instructions of a specific Instruction Set Architecture (ISA), which may include operating system instructions and user application instructions. These instructions may be stored in a computer-readable medium, such as memory, coupled to the 1345 memory controller discussed below.

[0076] As used herein, the term "coupled to" can indicate one or more connections between elements, and a coupling can include intervening elements. For example, in Fig. 13 the graphics unit 1375 is described as being “coupled to” a memory by the Fabric 1310 and the cache / memory controller 1345. In contrast, in the illustrated embodiment of Fig. 13 Graphics unit 1375 with Fabric 1310 “directly coupled” because there are no intervening elements.

[0077] The Cache / Memory Controller 1345 can be configured to manage the transfer of data between the Fabric 1310 and one or more caches and storage locations. For example, the Cache / Memory Controller 1345 can be coupled to an L3 cache, which in turn can be coupled to system memory. In other embodiments, the Cache / Memory Controller 1345 can be directly coupled to storage. In some embodiments, the Cache / Memory Controller 1345 can include one or more internal caches. Memory coupled to the controller 1345 can be any type of volatile memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR, DDR2, DDR3, etc.) (including mobile versions of SDRAMs, such as mDDR3, etc., and / or low power versions of SDRAMs, such as LPDDR4, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc.One or more memory devices can be coupled on a printed circuit board to form memory modules, such as single-row memory modules (SIMMs), dual-row memory modules (DIMMs), etc. Alternatively, the devices can be mounted with an integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration. Memory coupled to the controller 1345 can be any type of non-volatile memory, such as NAND flash memory, NOR flash memory, nano-RAM (NRAM), magnetoresistive RAM (MRAM), phase-change RAM (PRAM), racetrack memory, memristor memory, etc. As mentioned above, this memory can store program instructions that can be executed by the compute complex 1320 to cause the compute device to perform the functionality described herein.

[0078] The Graphics Unit 1375 can include one or more processors, such as one or more graphics processing units (GPUs). The Graphics Unit 1375 can receive graphics-oriented instructions, such as OPENGL®, Metal®, or DIRECT3D® instructions. The Graphics Unit 1375 can execute specialized GPU instructions or perform other operations based on received graphics-oriented instructions. The Graphics Unit 1375 can be generally configured to process large blocks of data in parallel and can create images in a frame buffer for output to a display, which may be included in the device or be a separate device. The Graphics Unit 1375 can include transformation, lighting, triangle, and / or rendering engines in one or more graphics processing pipelines. The Graphics Unit 1375 can output pixel information for display images.The 1375 graphics unit can, in various embodiments, include programmable shader switching logic, which can include highly parallel execution cores configured to run graphics programs that may include pixel tasks, vertex tasks, and computational tasks (which may or may not be graphics-related).

[0079] The Display Unit 1365 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the Display Unit 1365 can be configured as a display pipeline. Additionally, the Display Unit 1365 can be configured to concatenate multiple frames into a single output frame. Furthermore, the Display Unit 1365 can include one or more interfaces (e.g., MIPI® or Embedded DisplayPort (eDP)) for connecting to a user display (e.g., a touchscreen or external display).

[0080] The I / O bridge 1350 can include various elements configured to implement, for example, Universal Serial Bus (USB) communication, security, audio, and low-power always-on functionality. The I / O bridge 1350 can also include interfaces such as pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripheral devices and equipment can be connected to the device 1300 via the I / O bridge 1350.

[0081] In some embodiments, the device 1300 includes (not explicitly shown) network interface switching logic, which may be connected to the fabric 1310 or the I / O bridge 1350. The network interface switching logic can be configured to communicate over various networks, which may be wired, wireless, or both. For example, the network interface switching logic can be configured to communicate over a wired local area network, a wireless local area network (e.g., via Wi-Fi). TM) or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface switching logic is configured to communicate over one or more cellular networks using one or more wireless access technologies. In some embodiments, the network interface switching logic is configured to communicate using device-to-device communication (e.g., Bluetooth® or Wi-Fi™ Direct), etc. In various embodiments, the Device 1300's network interface switching logic can provide connectivity to various types of other devices and networks. Application examples

[0082] Now, referring to Fig. 14. Different types of systems can include any of the circuits, devices, or systems discussed above. System or Device 1400, which may incorporate one or more of the techniques described herein (e.g., System or Device 1400 may correspond to System 100), can be used in a wide range of applications. For example, System or Device 1400 can be used as part of the hardware of systems such as a desktop computer 1410, a laptop computer 1420, a tablet computer 1430, a mobile phone 1440, or a television 1450 (or a set-top box connected to a television).

[0083] Similarly, disclosed elements can be used in a wearable device 1460, such as a smartwatch or a health monitoring device. Smartwatches, in many embodiments, can perform a variety of different functions, for example, accessing emails, mobile services, calendars, health monitoring, etc. A wearable device can also be designed to perform exclusively health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions like contact tracing, providing communication with an emergency medical service, etc.Other types of devices are also conceivable, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets that offer computer-generated reality experiences, such as those based on augmented and / or virtual reality, etc.

[0084] The system or device 1400 can also be used in various other contexts. For example, the system or device 1400 can be used in the context of a server computer system, such as a dedicated server, or on shared hardware implementing a cloud-based service 1470. Furthermore, the system or device 1400 can also be implemented in a wide range of specialized everyday devices, including common household devices 1480, such as refrigerators, thermostats, security cameras, etc. The networking of such devices is often referred to as the "Internet of Things" (IoT). The elements can also be implemented in various means of transport. The system or device 1400 could, for example, be used in the control systems, guidance systems, entertainment systems, etc., of various types of vehicles 1490.

[0085] The in Fig. The 14 illustrated applications are merely examples and are not intended to limit the possible future applications of disclosed systems or devices. Other application examples include, without limitation: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc. Example of a computer-readable medium

[0086] In the present disclosure, various exemplary circuits have been described in detail above. It is intended that the present disclosure not only covers embodiments that include such switching logic, but also a computer-readable storage medium that includes design information specifying such switching logic. Accordingly, the present disclosure is intended to support claims that cover not only a device that includes the disclosed switching logic, but also a storage medium that specifies the switching logic in a format that programs a computing system to generate a simulation model of the hardware circuit, programs a manufacturing system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed switching logic, and so on.Claims for such a storage medium should, for example, cover an entity that produces a circuit design but does not itself perform complete operations, such as: design simulation, design synthesis, circuit manufacturing, etc.

[0087] Fig. Figure 15 is a block diagram illustrating an exemplary non-transitory, computer-readable storage medium that stores circuit design information, according to some embodiments. In the illustrated embodiment, the computing system 1540 is configured to process the design information. This may include executing instructions included in the design information, interpreting instructions included in the design information, compiling, transforming, or otherwise updating the design information, etc. Therefore, in some embodiments, the design information controls the computing system 1540 (e.g., by programming the computing system 1540) to perform various operations discussed below.

[0088] In the illustrated example, the Computing System 1540 processes the design information to generate both a computer simulation model of a hardware circuit 1560 and more detailed design information 1550. In other embodiments, the Computing System 1540 may produce only one of these outputs, produce other outputs based on the design information, or produce both. With respect to the computational simulation, the Computing System 1540 can execute instructions of a hardware description language, which may include register-transfer-level (RTL) code, behavioral code, structure code, or a combination thereof. The simulation model can perform the functionality specified by the design information, enable verification of the functional correctness of the hardware design, generate power consumption estimates, generate timing estimates, and so on.

[0089] In the illustrated example, the computing system 1540 also processes the design information to generate the more detailed design information 1550 (e.g., gate-level design information, a netlist, etc.). This can include synthesis operations, such as constructing a multi-level network, optimizing the network using technology-independent or technology-dependent techniques, or both, and outputting a gate network (with possible constraints based on gates available in a technology library, dimensioning, delay, current, etc.). Based on the more detailed design information 1550 (possibly among other inputs), the semiconductor fabrication system 1520 is configured to fabricate an integrated circuit 1530 (which may correspond to the functionality of the simulation model 1560).It should be noted that the 1540 computer system can generate various simulation models based on design information at different levels of description, including information 1550, 1515, and so on. The data representing design information 1550 and model 1560 can be stored on medium 1510 or on one or more other media.

[0090] In some embodiments, the more detailed design information 1550 controls (e.g., programs) the semiconductor manufacturing system 1520 to manufacture the integrated circuit 1530. When the design information is processed by the manufacturing system, it can thus program the manufacturing system to produce a circuit that incorporates various switching logics disclosed herein.

[0091] The non-transitory computer-readable storage medium 1510 can comprise any of several suitable types of storage devices or storage devices. The non-transitory computer-readable storage medium 1510 can be an installation medium, such as a CD-ROM, floppy disks, or a tape device; computer system memory or random-access memory, such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as a hard disk drive or optical storage; registers or other similar types of storage elements, etc. The non-transitory computer-readable storage medium 1510 can also include other types of non-transitory memory or combinations thereof.Accordingly, the non-transitory computer-readable storage medium 1510 can include two or more storage media; such media can be located in different places - for example, in different computer systems connected via a network.

[0092] The design information 1515 can be specified using any of several suitable computer languages, including hardware description languages ​​such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The format of various design information can be recognized by one or more applications executed by the computing system 1540, the semiconductor manufacturing system 1520, or both. In some embodiments, the design information may also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 1530. In some embodiments, the design information is specified wholly or partly in the form of a netlist that specifies the cell library elements and their connectivity.The design information discussed herein may, on its own, contain sufficient information for the fabrication of a corresponding integrated circuit, but it need not. For example, the design information may specify the circuit elements to be manufactured, but not their physical layout. In this case, the design information can be combined with layout information to actually fabricate the specified circuit logic.

[0093] The 1530 integrated circuit, in various embodiments, can include one or more user-defined macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, the design information can include information relating to the included macrocells. Such information can include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device- or transistor-level netlists. Mask design data can be formatted according to the Graphics Data System (GDSII) or any other suitable format.

[0094] The Semiconductor Manufacturing System 1520 can include any of several suitable elements configured to manufacture integrated circuits. These can include, for example, elements for depositing semiconductor materials (e.g., onto a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), and so on. The Semiconductor Manufacturing System 1520 can also be configured to perform various tests on manufactured circuits to ensure proper function.

[0095] In various embodiments, the integrated circuit 1530 and model 1560 are configured to operate according to a circuit design specified by design information 1515, which may include performing any of the functionality described herein. For example, integrated circuit 1530 may perform any of the various functions described in Fig. Include the elements shown in points 1 to 8. Furthermore, integrated circuit 1530 can be configured to perform various functions described herein in conjunction with other components. Additionally, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0096] As used herein, an expression of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured for the element to be satisfied. Rather, this expression indicates that the design information describes a circuit that, after manufacturing, will be configured to perform the specified actions or to include the specified components. Similarly, the statement "instructions of a hardware description programming language that are 'executable' to program a computing system to generate a computer simulation model" does not imply that the instructions must be executed for the element to be satisfied, but rather indicates properties of the instructions.Additional features relating to the model (or the circuit represented by the model) can similarly relate to properties of the instructions in this context. Therefore, an entity that sells a computer-readable medium containing instructions that meet the specified properties may be supplying an infringing product, even if another entity actually executes the instructions on the medium.

[0097] It is important to note that a given design, at least in the context of digital logic, can be implemented using a variety of different gate arrangements, circuit technologies, and so on. For example, different designs may select or combine gates based on design compromises (e.g., to focus on power consumption, performance, circuit area, etc.). Furthermore, different manufacturers may have proprietary libraries, gate designs, physical gate implementations, and so forth. Different entities may also use different tools to process design information at various levels (e.g., from behavioral specifications to the physical layout of gates).

[0098] Once a digital logic design is specified, professionals in this field do not need to conduct extensive experimentation or investigation to determine these implementations. Rather, they are familiar with procedures that reliably and predictably produce one or more circuit implementations that provide the functionality described in the design information. The different circuit implementations may affect the performance, area, power consumption, etc., of a given design (possibly with trade-offs between different design goals), but the logical functionality does not vary between the different circuit implementations of the same circuit design.

[0099] In some embodiments, the instructions included in the design information provide RTL information (or other higher-level design information) and are executable by the computing system to synthesize a gate-level netlist that represents the hardware circuit based on the RTL information as input. Similarly, the instructions can provide behavioral information and be executable by the computing system to synthesize a netlist or other more detailed design information. This more detailed design information can program the manufacturing system 1520 to manufacture the integrated circuit 1530.

[0100] The present disclosure includes references to an “embodiment” or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “embodiment,” “an embodiment,” “a particular embodiment,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are considered, including those specifically disclosed, as well as modifications or alternatives that fall within the nature or scope of protection of the disclosure.

[0101] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all potential advantages. Whether an advantage is achieved for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are several reasons why an implementation that falls within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation might include different switching logic outside the scope of the disclosure, which, in conjunction with one of the disclosed embodiments, eliminates or reduces one or more of the disclosed advantages. Furthermore, a suboptimal design implementation of a particular implementation (e.g.,Implementation techniques or tools) negate or diminish disclosed benefits. Even assuming a qualified implementation, the attainment of benefits may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, thereby potentially preventing the benefit of its solution from being achieved. Due to the existence of possible factors outside this disclosure, it is expressly intended that all potential benefits described herein are not to be construed as limitations on claims that must be satisfied to prove infringement.Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvement available to designers who benefit from this disclosure. Describing such benefits in a permissive manner (e.g., stating that a particular benefit “may occur”) is not intended to cast doubt on the attainability of such benefits, but instead to acknowledge the technical reality that achieving such benefits often depends on additional factors.

[0102] Unless otherwise stated, embodiments are not limiting. This means that the disclosed embodiments are not intended to limit the scope of protection of claims formulated on the basis of this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not limiting, unless the disclosure contains statements to the contrary. The application is thus intended to allow the application to cover embodiments disclosed in claims as well as the alternatives, modifications, and equivalents that are apparent to a person skilled in the art who benefits from this disclosure.

[0103] For example, features in this application may be combined in any suitable way. Accordingly, during the further pursuit of this application (or an application claiming priority thereof), new claims may be formulated to any such combination of features. In particular, with reference to the accompanying claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims dependent on other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

[0104] While the accompanying dependent claims may be formulated such that each depends on a single other claim, additional dependencies are also considered. All combinations of features in the dependents that are consistent with this disclosure are considered and may be claimed in this or any other application. In summary, combinations are not limited to those specifically enumerated in the accompanying claims.

[0105] Where appropriate, consideration will also be given to ensuring that claims formulated in one format or statutory type (e.g., establishment) support corresponding claims in another format or statutory type (e.g., procedure).

[0106] Since this disclosure is a legal document, various terms and expressions may be subject to regulatory and legal interpretation. It is hereby announced that the following paragraphs, as well as definitions provided throughout this disclosure, shall be used in determining how claims formulated on the basis of this disclosure are to be interpreted.

[0107] References to a singular form of an element (i.e., a noun or noun phrase preceded by "a" or "the") should, unless the context clearly indicates otherwise, mean "one or more." Thus, a reference to "an element" in a claim, without accompanying context, does not exclude additional instances of the element. A "multitude" of elements refers to a set of two or more of the elements.

[0108] The word “can / can” is used here in a permissive sense (i.e. having the potential to be able to) and not in an obligatory sense (i.e. must / must).

[0109] The terms “comprehensive” and “inclusive” and forms thereof are open and mean “including without being limited to”.

[0110] When the term “or” is used in this disclosure in relation to a list of options, it is generally understood to be used in an inclusive sense, unless the context indicates otherwise. Thus, a statement of “x or y” is equivalent to “x or y or both” and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, an expression such as “either x or y, but not both” makes it clear that “or” is used in an exclusive sense.

[0111] A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities involving a single element up to the total number of elements in the sentence. For the sentence [w, x, y, z], for example, these expressions cover each individual element of the sentence (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The expression "at least one of ... x, y, and z" thus refers to at least one element of the sentence [w, x, y, z], thereby covering all possible combinations in this list of elements. This expression must not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0112] Various “labels” may appear before nouns or noun phrases in this disclosure. Unless the context indicates otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, when applied to a feature, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0113] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on specified factors, or on the specified factors as well as other, unspecified factors. Consider the expression "determine A based on B." This expression indicates that B is a factor used to determine A, or that influences the determination of A. This expression does not exclude the possibility that the determination of A may also be based on another factor, such as C. This expression is also intended to cover an embodiment in which A is determined solely based on B. As used herein, the expression "based on" is synonymous with the expression "based at least partially on."

[0114] The expressions "in response to" and "in reaction to" describe one or more factors that cause an effect. This expression does not exclude the possibility that additional factors may influence or otherwise cause the effect, either together with the stated factors or independently of them. That is, an effect may occur solely in response to these factors, or it may occur in response to the stated factors as well as other, unspecified factors. Consider the expression "to perform A in response to B." This expression indicates that B is a factor that causes A to be performed or that causes a particular outcome for A. This expression does not exclude the possibility that A may also be performed in response to another factor, such as C. Nor does it exclude the possibility that A may be performed in response to both B and C.This expression is also intended to cover an embodiment in which A is carried out solely in response to B. As used herein, the expression "responding to" is synonymous with the expression "at least partially responding to". Similarly, the expression "in response to" is synonymous with the phrase "at least partially in response to".

[0115] Within this disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed to be "configured" to perform one or more tasks or operations. This phrase—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be described as "configured to" perform a task even if the structure is not currently operating.Thus, an entity described or specified as "configured to" perform a task refers to something physical, such as a device, a circuit, a system with a processing unit and memory that stores program instructions executable to implement the task, etc. This expression is not used herein to refer to something intangible.

[0116] In some cases, various units / circuits / components herein may be described as performing a set of tasks or operations. It is understood that these entities are "configured to" perform these tasks / operations, even if this is not specifically stated.

[0117] The term "configured to" should not be interpreted as "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA may be "configurable to" perform that function. After appropriate programming, the FPGA can then be described as "configured to" perform the specific function.

[0118] For the purposes of U.S. patent applications based on this disclosure, a claim that a structure is "configured to" perform one or more functions shall expressly not rely on the application of 35 U.S.C. § 112(f) for that claim element. If, during the grant proceedings of a U.S. patent application based on this disclosure, the applicant wishes to rely on the application of section 112(f), they shall state claim elements using the construct "means to" [perform a function].

[0119] Various “circuits” can be described in this disclosure. These circuits, or “switching logic,” constitute hardware that includes various types of circuit elements, such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random-access memory), programmable logic arrays, and so on. Switching logic can be user-defined or derived from standard libraries. In various implementations, switching logic may, as appropriate, include digital components, analog components, or a combination of both. Certain types of circuits may be referred to more generally as “units” (e.g., a decoding unit, an arithmetic logic unit (ALU), a functional unit, a memory management unit (MMU), etc.).Such units also refer to circuits or switching logic.

[0120] The disclosed circuits / units / components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decoding unit" can be described as performing the function of "processing an opcode of an instruction and redirecting that instruction to one or more of a plurality of functional units," meaning that the decoding unit is "configured to" perform this function. This functional description is sufficient for a person skilled in the art in computing to further define a set of possible structures for the circuit.

[0121] In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements can be defined by the functions or operations for which they are configured. The arrangement of these circuits / units / components in relation to one another and the way in which they interact constitute a microarchitectural definition of the hardware, which is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition is recognized by the person skilled in the art as a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitectural definition.This means that the person skilled in the art, to whom the microarchitecture definition provided according to this disclosure is presented, can implement the structure without undue experimentation and by applying average skills by encoding the description of the circuits / units / components in a hardware description language (HDL), such as Verilog or VHDL. The HDL description is often expressed in a way that may appear functional. However, to the person skilled in the art, this HDL description is the way in which the structure of a circuit, unit, or component is transformed to the next level of implementation detail. Such an HDL description may take the form of behavioral code (which is not usually synthesizable), register-transfer language (RTL) code (which, unlike behavioral code, is usually synthesizable), or structural code (e.g.,a netlist specifying logic gates and their connectivity). The HDL description can then be synthesized against a library of cells designed for a given integrated circuit fabrication technology and modified for timing, power, and other reasons to produce a final design database. This database is then sent to a foundry to generate masks and ultimately fabricate the integrated circuit. Some hardware circuits, or sections thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with synthesized switching logic. The integrated circuits can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and connect the transistors and circuit elements.Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete elements can be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and implemented within the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits typically results in a scenario where the circuit or logic designer never specifies a particular set of structures for low-level implementation beyond a description of what the circuit is configured for, as this process is performed at a different stage of the circuit implementation process.

[0122] The fact that many different low-level combinations of circuit elements can be used to implement the same circuit specification leads to a large number of equivalent structures for that circuit. As indicated, these low-level circuit implementations can vary according to changes in the manufacturing technology, the foundry chosen to produce the integrated circuit, the library of cells provided for a particular project, and so on. In many cases, the choices made by different design tools or methodologies for producing these different implementations can be arbitrary.

[0123] Furthermore, for a single implementation of a particular functional specification of a circuit, it is common to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete low-level specification of the structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes a structure of circuits using the functional shorthand notation commonly employed in industry.

Claims

[1] System, encompassing: a plurality of integrated circuit dies, wherein a first plurality of integrated circuit dies is indirectly coupled to a second plurality of integrated circuit dies by a set of intermediate integrated circuit dies; and a first power source configured to supply power to component circuits of the first and second integrated circuit dies, wherein the first and second integrated circuit dies are configured to receive power from the first power source based on first power credits actively shared between the first and second integrated circuit dies, wherein the first integrated circuit die is configured to allocate a first set of power credits to a set of component circuits of the first integrated circuit die to receive power from the first power source based on the first set of power credits, and wherein the first integrated circuit die is configured to send a second set of power credits to the second integrated circuit die through the set of intermediate integrated circuit dies, without the set of intermediate integrated circuit dies using the second set of power credits to receive power from the first power source. [2] System according to claim 1, wherein the set of intermediate integrated circuit dies is configured to receive power from a second power source based on second power credits that are actively shared between the set of intermediate integrated circuit dies. [3] System according to claim 2, wherein the set of intermediate integrated circuit dies is configured to share the second power credits with each other without sending the second power credits through other integrated circuit dies. [4] System according to claim 1, further comprising: a second power source configured to supply power to component circuits of the first and second integrated circuit dies, wherein the first and second integrated circuit dies are configured to receive power from the second power source based on second power credits actively shared between the first and second integrated circuit dies, and wherein the first integrated circuit die is configured to send a third set of power credits to the second integrated circuit die through the set of intervening integrated circuit dies. [5] System according to claim 4, wherein the first and second power sources are different types of power sources. [6] System according to claim 4, wherein the first integrated circuit die is coupled to a multiplexer circuit configured to send power credits of a first given power source ahead of power credits of a second given power source on an equal set of lines of a die-to-die interface. [7] System according to claim 1, further comprising: a second power source configured to supply power to component circuits of the first and second integrated circuit dies and the set of intermediate integrated circuit dies, wherein the first and second integrated circuit dies and the set of intermediate integrated circuit dies are configured to receive power from the second power source based on power credits actively shared between the first and second integrated circuit dies and the set of intermediate integrated circuit dies. [8] System according to claim 7, wherein the second power source is a battery. [9] System according to claim 1, wherein the first power source is not coupled to the set of intermediate integrated circuit dies in order to supply power to the set of intermediate circuit dies. [10] System according to claim 1, wherein the first and second integrated circuit dies include a first processor type but not a second processor type, and the set of intermediate integrated circuit dies includes the second processor type but not the first processor type. [11] Procedure, encompassing: Accessing information through a first integrated circuit die, which identify a power budget of a first power source configured to supply power to the first integrated circuit die and to supply a second integrated circuit die, with power being drawn from the first power source based on a variety of power credits, which are included in the performance budget, is available; Allocate, by the first integrated circuit die, a first set of the multitude of power credits to a set of component circuits of the first integrated circuit die; and Sending, through the first integrated circuit die, a second set of the plurality of power credits to the second integrated circuit die through a set of intermediate integrated circuit dies, without the set of intermediate integrated circuit dies using the second set of power credits to obtain power from the first power source. [12] The method of claim 11, further comprising: Sending, through the first integrated circuit die, a third set of power credits to a special set of intermediate integrated circuit dies, wherein the special intermediate integrated circuit die is configured to receive power based on the third set of power credits from a second power source configured to supply power to the first integrated circuit die and the special intermediate integrated circuit die. [13] Method according to claim 12, wherein the second set of credits is sent before the third set of credits on an equal set of lines of a die-to-die interface connecting the first integrated circuit die to the special intermediate integrated circuit die. [14] The method of claim 11, further comprising: Received, by the first integrated circuit die and by the second integrated circuit die, a third set of power credits for the first power source; and Allocating, by the first integrated circuit die, of power to the set of component circuits of the first integrated circuit die based on the third set of power credits. [15] Method according to claim 11, wherein the first power source does not supply any power to the set of intermediate integrated circuit dies. [16] Method according to claim 11, wherein the first and second integrated circuit dies are asymmetric with respect to the set of intervening integrated circuit dies. [17] Method according to claim 16, wherein the first and second integrated circuit dies include central processing units (CPUs) but do not include graphics processing units (GPUs), while the set of intermediate integrated circuit dies includes GPU processors but not CPU processors. [18] Institution, comprehensive: a plurality of integrated circuit dies, wherein a first plurality of integrated circuit dies is indirectly coupled to a second plurality of integrated circuit dies by a set of intermediate integrated circuit dies; and a first power source configured to supply power to component circuits of the first and second integrated circuit dies, where the first die is configured with an integrated circuit for: Allocate, to a first set of component circuits of the first integrated circuit die, a first set of power credits, wherein the first set of component circuits is configured to receive power from the first power source based on the first set of power credits; and Sending to the second integrated circuit die through the set of interposed integrated circuit dies, a second set of power credits, wherein the second integrated circuit die is configured to receive power from the first power source based on the second set of power credits. [19] Device according to claim 18, wherein the set of intermediate integrated circuit dies is not configured to use the second set of power credits to obtain power from the first power source. [20] Device according to claim 18, wherein individual components from the set of intermediate integrated circuit dies are configured to receive power from a second power source based on actively shared power credits without sending these power credits through other integrated circuit dies.

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