Display system for setting the aspect ratio of a displayed image

Abstract

Display system (100) for setting an aspect ratio of a displayed image, characterized by: a display field (15) with several pixels (16) designed to display an image; a gate control circuit (16) coupled to the multiple pixels (16); a data control circuit (14) coupled to the multiple pixels (16); a logic board (12) coupled to the gate control circuit (16) and the data control circuit (14) and designed to control the gate control circuit (16) and the data control circuit (14); a backlight control circuit (11) designed to control multiple backlight components (BLCs); and a chip processor (10) coupled to the logic board (12) and the backlight control circuit (11) and designed to control the logic board (12) and the backlight control circuit (11); wherein, after the chip processor (10) receives a signal corresponding to a first displayed image area (R1), the chip processor (10) generates a second displayed image area (R2) of a display field (15) corresponding to the first displayed image area (R1), wherein the gate drive circuit (13) and the data drive circuit (14) drive several pixels (16) within the second displayed image area (R2) of the display panel (15) to display the image and deactivate several pixels outside the second displayed image area (R2).

Description

Field of invention

[0001] The present invention describes a display system for setting the aspect ratio of a displayed image, in particular a display system for setting the aspect ratio of the displayed image using coordinate information. Background of the invention

[0002] With the rapid advancement of technology, various powerful processing units are being integrated into displays to deliver audio / video entertainment and satisfying visual experiences. Since every user has specific visual preferences, the display must offer the ability to adjust the aspect ratio of a displayed image. For example, the screen size supported by the display might be 27 inches with a 16:9 aspect ratio. When the aspect ratio is adjusted, the display must use an internal processor to buffer video data or images in a frame buffer and then perform a scaling process. As a result, a slight image delay typically occurs.

[0003] In other words, on a conventional display where the aspect ratio of the displayed image can be adjusted, a delay or asynchronicity of the video stream information can occur when a user watches a video stream (e.g., a movie) and adjusts the aspect ratio of the displayed image. For example, adjusting the aspect ratio of the displayed image can lead to a delay of several seconds in the video stream information. The delay time of the video stream depends on the resolution of the displayed image. However, this video stream delay impairs the user's viewing experience and leads to eye strain. Summary of the invention

[0004] The present invention aims to provide a display system for adjusting the aspect ratio of a displayed image without causing a time delay by optimizing the image color tones according to the backlight area and the image coordinates.

[0005] This is achieved by a display system according to the following claims. The dependent claims relate to corresponding further developments and improvements.

[0006] As will become clearer from the following detailed description, a method for setting the aspect ratio of the displayed image includes defining a first displayed image area, creating a second displayed image area of ​​a display panel corresponding to the first displayed image area, addressing several pixels within the second displayed image area of ​​the display panel to display an image, and disabling several pixels outside the second displayed image area of ​​the display panel.

[0007] As will become clearer from the following detailed description, a claimed display system comprises a display panel, a gate drive circuit, a data drive circuit, a logic board, a backlight drive circuit, and a chip processor. The display panel comprises several pixels configured to display an image. The gate drive circuit is coupled to the several pixels. The data drive circuit is coupled to the several pixels. The logic board is coupled to the gate drive circuit and the data drive circuit and is configured to control the gate drive circuit and the data drive circuit. The backlight drive circuit is configured to control several backlight components.The chip processor is coupled to the logic board and the backlight driver circuitry and is designed to control these components. After receiving a signal corresponding to a first displayed image area, the chip processor generates a second displayed image area on the display panel, mirroring the first. The gate and data drive circuits control several pixels within the second displayed image area to show the image and disable several pixels outside of it.

[0008] A method for adjusting the aspect ratio of the displayed image and the display system according to the present invention can generate multiple coordinates around an image area corresponding to the aspect ratio and can easily adjust the image area to optimize the image color tones by aligning the image area with a backlight area in the backlight arrangement surrounded by grid lines. This avoids a time delay in the video stream or images, resulting in an improved visual experience. Brief description of the drawings

[0009] The invention will now be explained in more detail with reference to the accompanying drawings and examples. Fig. 1 is a block diagram of a display system according to an embodiment of the present invention; Fig. Figure 2 is a representation of the initial setting of a first displayed image area of ​​the display system in Fig. 1; Fig. Figure 3 is a representation of the generation of a second displayed image area of ​​the display system in Fig. 1; Fig. 4 is a structure of a backlight arrangement of the display system in Fig. 1; Fig. 5 is a representation of a first mode for adapting the first displayed image area to the second displayed image area of ​​the display system in Fig. 1; Fig. 6 is a representation of a second mode for adapting the first displayed image area to the second displayed image area of ​​the display system in Fig. 1; Fig. Figure 7 is a representation of the control of edge-illuminated LED backlight components by a backlight control circuit according to the second displayed image area of ​​the display system in Fig. 1; Fig. Figure 8 is a representation of the setting of the first displayed image area using an on-screen display (OSD) interface of the display system in Fig. 1; and Fig. Figure 9 is a flowchart of a procedure for adjusting the aspect ratio of a displayed image using the display system in Fig. 1. Detailed description

[0010] Fig. Figure 1 is a block diagram of a display system 100 according to an embodiment of the present invention. The display system 100 comprises a display panel 15, a gate drive circuit 13, a data drive circuit 14, a logic board 12, a backlight drive circuit 11, a backlight assembly BLA, and a chip processor 10. The display panel 15 comprises several pixels 16 for displaying an image. The several pixels 16 can be arranged in an array structure. The gate drive circuit 13 is coupled to the several pixels 16. The gate drive circuit 13 can be used to control control terminals of the several pixels 16. The data drive circuit 14 can be used to control drive operations of the several pixels 16 to display the image with different shades of gray and color. The logic board 12 (i.e., the 12)a T-CON board) is coupled to the gate drive circuit 13 and the data drive circuit 14 to control the gate drive circuit 13 and the data drive circuit 14. For example, the logic board 12 can be a core circuit for controlling time pulse sequences of clock signals from the display panel 15. Thus, the logic board 12 can control the sampling time of multiple pixels 16 via the gate drive circuit 13 and the data drive circuit 14. The logic board 12 can also be used to convert an input video signal (i.e., for example, a low-voltage differential signal, LVDS) into a signal used by a digital driver circuit with a standard format (i.e., for example, a reduced swing differential signal, RSDS). The backlight drive circuit 11 is coupled to the backlight assembly BLA to control multiple backlight components (i.e.,several backlight components BLC in . Fig. 4) to control the backlight assembly (BLA). The chip processor 10 is coupled to the logic board 12 and the backlight control circuit 11 to control the logic board 12 and the backlight control circuit 11. The chip processor 10 can be any programmable chip or any type of processor. For example, the chip processor 10 can be a scalar within the display system 100 or a microprocessor capable of programming instructions. The chip processor 10 can store and configure multiple time parameters. Furthermore, data communication between the chip processor 10 and the logic board 12 can take place via an I2C (Inter-Integrated Circuit) bus.

[0011] In the display system 100, the display panel 15 can perform an on-screen display (OSD) function. The OSD function provides an interface for a user to adjust image configurations. After the user has set an initial displayed image area via the display panel 15, the display panel 15 can generate a signal corresponding to this initial displayed image area and send it to the chip processor 10. After the chip processor 10 receives the signal corresponding to the initial displayed image area, it can generate a signal corresponding to a second displayed image area on the display panel 15, corresponding to the initial displayed image area. Here, the signal corresponding to the second displayed image area is relevant to the signal corresponding to the first displayed image area. For example, the first and second displayed image areas are essentially the same.In the display system 100, the chip processor 10 can be used to adapt the first displayed image area to the second displayed image area according to the assignments of grid lines of the backlight components in the backlight assembly BLA, which is controlled by the backlight control circuit 11.

[0012] An adjustment procedure is described below. The chip processor 10 can control the display panel 15 via the logic board 12, the gate drive circuit 13, and the data drive circuit 14 to display the image by activating several pixels 16 within the second displayed image area. Furthermore, the processor 10 can adjust at least one clock signal used to display the image according to the second displayed image area. For example, the processor 10 can proportionally adjust the timing windows or pulse widths of a horizontal clock signal and / or a vertical clock signal. In addition, the processor 10 can deactivate several pixels 16 outside the second displayed image area of ​​the display panel 15. A procedure for adjusting the aspect ratio of the displayed image is described below.

[0013] Fig. Figure 2 shows the setting of the first displayed image area R1 of the display system 100. The first displayed image area R1 can be a user-defined area or a predefined area by the display system 100. For example, the first displayed image area R1 can be 17 inches with an aspect ratio of 16:9. Furthermore, the center point of the first displayed image area R1 can be the center point of the display panel 15. However, the center point of the first displayed image area R1 can be set as desired. For example, a user can set a vertical offset of the first displayed image area R1, while a center horizontal line of the first displayed image area R1 is aligned with a horizontal line of the center position.Furthermore, the user can set a horizontal offset of the first displayed image area R1, while a vertical center line of the first displayed image area R1 is aligned with a vertical line of the center position. The user can also set both the horizontal and vertical offsets of the first displayed image area R1. In addition, the user can adjust the center points of the first displayed image area R1 and the second displayed image area R2 (i.e., as shown later) using the OSD function of display field 15. When the first displayed image area R1 is set, the chip processor 10 can generate first coordinates P1 and second coordinates P2 according to the first displayed image area R1. Fig. The first coordinates P1 and the second coordinates P2 are diagonally opposite corners of the first displayed image area R1. The first coordinates P1 are designated as (x1, y1). The second coordinates P2 are designated as (x2, y2). However, the first displayed image area R1 is not limited to a rectangular shape. In other words, the user can define a specific shape for the area to display the image on the display field 15. In this embodiment, the first displayed image area R1 has a rectangular shape. However, the displayed image area of ​​the present invention is not limited to a rectangular shape.

[0014] Fig. Figure 3 is a representation of the generation of a second displayed image area R2 of the display system 100. As mentioned earlier, the display system 100 includes the backlight drive circuit 11 for driving the multiple backlight components of the backlight assembly BLA. To overlap the first displayed image area R1 with a backlight area surrounded by the grid lines of the backlight components, the display system 100 can adjust the first displayed image area R1 to generate the second displayed image area R2. In other words, the second displayed image area R2 can be considered the final area of ​​the display panel 15 for displaying the image. However, the first displayed image area R1 can be considered a user-defined initial image area. The first displayed image area R1 and the second displayed image area R2 can be essentially the same.A generation method for the second displayed image area R2 depends on some digital coordinates. For example, the chip processor 10 can generate first coordinates P1' and second coordinates P2' for displaying the image. The first coordinates P1' and the second coordinates P2' can be diagonally opposite corners of the second displayed image area R2. The first coordinates P1' can be denoted as (x1', y1'). The second coordinates P2' can be denoted as (x2', y2'). The chip processor 10 can control the logic board 12 to drive the gate drive circuit 13 and the data drive circuit 14 according to the first coordinates P1' and the second coordinates P2'. In this way, several pixels 16 can be sequentially driven from the first coordinates P1' to the second coordinates P2' of the second displayed image area R2. One step of the process can be illustrated below.Since the second displayed image area R2 can have a rectangular shape, once two diagonally opposite corners are defined by the first coordinates P1' and the second coordinates P2', two further diagonally opposite corners can also be defined. For example, the first coordinates P1' can be designated as (x1', y1'). The second coordinates P2' can be designated as (x2', y2'). Therefore, the third coordinates P3' can be derived as (x2', y1'). The fourth coordinates P4' can be derived as (x1', y2'). The gate control circuit 14 and the data control circuit 13 can control several pixels 16 of the second displayed image area R2, which is surrounded by the first coordinates P1', the second coordinates P2', the third coordinates P3', and the fourth coordinates P4', to display the image. In the embodiment of . Fig. 3. The multiple pixels 16 of the second displayed image area R2 can be controlled by activating a pixel subarray from a horizontal coordinate x1' to a horizontal coordinate x2' on a horizontal axis and from a vertical coordinate y1' to a vertical coordinate y2' on a vertical axis.

[0015] As explained above, the chip processor 10 can easily adjust the first displayed image area R1 to generate the second displayed image area R2. The second displayed image area R2 can be considered the final area for displaying the image. In particular, the uniformity of the image tones can be varied by adjusting the first displayed image area R1. However, the first displayed image area R1 and the second displayed image area R2 can be identical. If the first displayed image area R1 and the second displayed image area R2 are identical, the uniformity of the image tones cannot be optimized because the distribution of the backlight components is ignored. Embodiments are described later. Without limiting generality, a method for optimizing the uniformity of the image tones by setting an initial image area (i.e.,of the first displayed image area R1).

[0016] Fig. Figure 4 shows the structure of the backlight array BLA of the display system 100. The backlight array BLA can be controlled by the backlight drive circuit 11. The backlight array BLA can comprise multiple backlight components BLC. The multiple backlight components BLC can be any light-emitting devices, such as LEDs. Each backlight component corresponds to an illumination area. Since the multiple backlight components BLC can be arranged in an array structure, two adjacent backlight components BLC in the backlight array BLA have a corresponding grid line L. The grid line L can be considered the boundary line between two illumination areas with respect to two adjacent backlight components BLC.In other words, if the number of backlight components BLC in the backlight array BLA is large, the distribution of horizontal or vertical grid lines will be dense. In the Display System 100, a boundary line of the first displayed image area R1 can be shifted to a position that overlaps with a grid line of the backlight array BLA that is closest to the boundary line. In this way, any aliasing offsets between the second displayed image area R2 and a backlight area (i.e., a backlight subarray) surrounded by grid lines can be minimized. Because the aliasing offsets are minimized, the backlight components BLC can accurately emit a backlight signal within the second displayed image area R2 to display the image, resulting in optimized uniformity of image tones.The embodiment is explained below.

[0017] Fig. Figure 5 is a representation of a first mode for adapting the first displayed image area R1 to the second displayed image area R2 of the display system 100. Fig. In step 5, the first displayed image area R1 is initially defined by the user. After the chip processor 10 has detected several grid lines corresponding to several backlight components BLC, the chip processor 10 determines that the boundary lines of the first displayed image area R1 and the grid lines of the backlight components BLC do not match. For example, the chip processor 10 can generate a minimum distance between a boundary line B1 of the first displayed image area R1 and a grid line L1 closest to boundary line B1. If the minimum distance is not zero and less than a predetermined value, the boundary line B1 can be moved to a position where it overlaps with the grid line L1 closest to boundary line B1. Thus, the minimum distance can be reduced by overlapping the boundary line B1 with the grid line L1.Similarly, all the border lines of the first displayed image area R1 can be adjusted according to the positions of their overlap with the corresponding grid lines of the backlight components BLC. In other words, the size of the first displayed image area R1 can be slightly increased to create the second displayed image area R2. Here, the coordinates P1 to P4 of the first displayed image area R1 can each be adjusted to the coordinates P1' to P4' of the second displayed image area R2. However, if the number of backlight components BLC is large, the two aspect ratios of the first displayed image area R1 and the second displayed image area R2 are nearly identical. For example, the first displayed image area R1 comprises 1024 × 768 pixels. The aspect ratio is 4:3.Furthermore, the first displayed image area R1 can be slightly enlarged to create the second displayed image area R2. The second displayed image area R2 can encompass 1080 × 800 pixels.

[0018] The aspect ratio is then 4:2.96. Fortunately, it is difficult for the user to notice slight deviations in the aspect ratio. In this way, the displayed image within the second displayed image area R2 exhibits optimal color tones after the image area adjustment process (also considered the registration process for the backlight grid) has been carried out.

[0019] Fig. Figure 6 is a representation of a second mode for adapting the first displayed image area R1 to the second displayed image area R2 of the display system 100. Fig. In step 6, the first displayed image area R1 is initially defined by the user. After the chip processor 10 has detected several grid lines corresponding to several backlight components BLC, the chip processor 10 determines that the boundary lines of the first displayed image area R1 and the grid lines of the backlight components BLC do not match. For example, the chip processor 10 can generate a minimum distance between a boundary line B2 of the first displayed image area R1 and a grid line L2 closest to boundary line B2. If the minimum distance is not zero and less than a predetermined value, the boundary line B2 can be moved to a position where it overlaps with the grid line L2 closest to boundary line B2. Thus, the minimum distance can be reduced by overlapping the boundary line B2 with the grid line L2.Similarly, all the boundary lines of the first displayed image area R1 can be adjusted according to the positions of their overlap with the corresponding grid lines of the backlight components BLC. In other words, the size of the first displayed image area R1 can be slightly reduced to create the second displayed image area R2. Here, the coordinates P1 to P4 of the first displayed image area R1 can each be adjusted to the coordinates P1' to P4' of the second displayed image area R2. However, if the number of backlight components BLC is large, the two aspect ratios of the first displayed image area R1 and the second displayed image area R2 are nearly identical. For example, the first displayed image area R1 comprises 1024 × 768 pixels. The aspect ratio is 4:3.Furthermore, the first displayed image area R1 can be slightly reduced in size to create the second displayed image area R2. The second displayed image area R2 can be 1000 × 720 pixels. The aspect ratio is then 4:2.88. Fortunately, it is difficult for the user to notice slight deviations in the aspect ratio. In this way, after the image area adjustment process (also considered the registration process for the backlight grid) has been carried out, the displayed image within the second displayed image area R2 exhibits optimal color tones.

[0020] The two embodiments described above can optimize the color tones of the displayed image in the display system 100. To avoid optical interference in the second displayed image area R2, the chip processor 10 can control the backlight control circuit 11 such that several backlight components within the second displayed image area R2 are activated. At this time, several pixels outside the second displayed image area R2 are deactivated. Since the several pixels outside the second displayed image area R2 are deactivated by the display system 100, the user can clearly see the displayed image within the second displayed image area R2 without optical disturbances caused by light leakage from neighboring backlight components or neighboring activated pixels. In this way, the image quality can be further improved.Furthermore, if the minimum distance is greater than the predetermined value, this means that the distance between an edge line of the first displayed image area R1 and one of the grid lines closest to the edge line is too large. As soon as the first displayed image area R1 is forcibly adjusted to a backlight area surrounded by the grid lines, a significant distortion of the aspect ratio occurs. Therefore, the first displayed image area R1 is fixed. Backlight components BLC above the edge line of the first displayed image area R1 can be enabled or disabled. When the backlight components BLC above the edge line of the first displayed image area R1 are enabled, some highlighted areas are introduced at the edges of the displayed image.The aspect ratio of the displayed image can, however, correspond to user configurations that match the first displayed image area R1. Similarly, if the backlight components BLC above the border line of the first displayed image area R1 are disabled, some shadow areas are introduced at the edges of the displayed image. The aspect ratio of the displayed image can, however, correspond to user configurations that match the first displayed image area R1.

[0021] Fig. Figure 7 shows the control of an edge-LED backlight component by the backlight control circuit 11 according to the second displayed image area R2 of the display system 100. As mentioned previously, the backlight control circuit 11 can be a direct backlight control circuit or an edge-LED backlight control circuit. For example, the embodiments in Fig. 4 to Fig. 6 as applications of directly backlit components (i.e., for example, backlighting components BLC in Fig. 4 to Fig. 6) are considered. One embodiment in Fig. Figure 7 can be considered an application of edge-lit LED components. Generally, the direct backlight components can be the LEDs that are evenly distributed as a light source on the back of the display field 15 (i.e., the screen surface). Thus, the backlight can be distributed evenly across the entire display field 15. However, the edge-lit LED components can be the LEDs that are arranged around the perimeter of the display field 15. In addition, some light guide plates can also be introduced to transfer the backlight from the edges of the display field 15 to a central area of ​​the display field 15. In this way, when the edge-lit LED components are activated, the display field 15 can receive sufficient backlighting to display the image. Fig. 7. The second displayed image area R2 can be considered the final area for displaying the image. The second displayed image area R2 can be surrounded by first coordinates P1', second coordinates P2', third coordinates P3', and fourth coordinates P4'. When the edge LED components are introduced into the display system 100, the backlight arrangement BLA can be placed in the Fig. 4 to Fig. 6 is replaced by a linear backlight area BLL. The linear backlight area BLL comprises several backlight components BLC. The linear backlight area BLL can be positioned along an edge of the display field 15. To illuminate the second displayed image area R2, the backlight drive circuit 11 can control an on / off state of each backlight component BLC of the linear backlight area BLL. For example, three backlight components BLC located in a central section of an upper linear backlight area BLL, corresponding to the length of the second displayed image area R2, are activated. Two backlight components BLC at opposite ends of the upper linear backlight area BLL are deactivated.Similarly, three backlight components BLC located in the middle section of a lower linear backlight area BLL, corresponding to the length of the second displayed image area R2, are activated. Two backlight components BLC at opposite ends of the lower linear backlight area BLL are deactivated. Two backlight components BLC located in the middle section of a right linear backlight area BLL, corresponding to the width of the second displayed image area R2, are activated. Two backlight components BLC at opposite ends of the right linear backlight area BLL are deactivated.Similarly, two backlight components BLC located in a central section of a left linear backlight area BLL, corresponding to the width of the second displayed image area R2, are activated. Two backlight components BLC at the two ends of the left linear backlight area BLL are deactivated. However, the structure of an edge backlight source is not based on the structure in . Fig. 7 limited. For example, in display system 100, a single-sided linear backlight area can be used to provide the backlight. Similarly, the backlight drive circuit 11 can use a control method to activate or deactivate some backlight components BLC associated with the single-sided linear backlight area in order to provide the backlight for the second displayed image area R2.

[0022] Fig. Figure 8 shows the setting of the first displayed image area R1 using the Display System 100's On-Screen Display (OSD) UI. As mentioned earlier, the OSD UI can be used to select a configuration for the aspect ratio of the displayed image. Thus, the OSD UI can provide multiple supported diagonal image sizes and multiple aspect ratios for each diagonal size. For example, in one mode, the image size can be full screen with an optional aspect ratio of 4:3 or 16:9. In a second mode, the image size (diagonal length) can be 17 inches with an optional aspect ratio of 4:3 or 16:9. In a third mode, the image size can be 19 inches with an optional aspect ratio of 4:3 or 16:9. In a fourth mode, the image size can be 24 inches with an optional aspect ratio of 4:3 or 16:9.In a fifth mode, the image size can be 27 inches with an optional aspect ratio of 4:3 or 16:9. The user can select one mode from several and additionally choose an aspect ratio. However, the present invention is not limited to the combination of five modes with two aspect ratios in the OSD interface user interface. Fig. 8 limited. For example, the OSD interface user interface can provide the user with more modes and more aspect ratios.

[0023] Fig. Figure 9 is a flowchart of a procedure for adjusting the aspect ratio of the displayed image using the Display System 100. A procedure for adjusting the aspect ratio of the displayed image using the Display System 100 comprises steps S801 through S804. Steps S801 through S804 are explained below. Step S801: Define a first displayed image area R1; Step S802: Creating a second displayed image area R2 of a display panel 15 by selectively adjusting the first displayed image area R1 according to the first displayed image area; Step S803: Addressing multiple pixels within the second displayed image area R2 of display panel 15 to display an image; Step S804: Disable multiple pixels outside the second displayed image area R2 of the display panel 15.

[0024] The processes from step S801 to step S804 have been explained previously; therefore, they are omitted here. In the display system 100, the aspect ratio, size, or resolution of the displayed image can be set by the user via the OSD interface UI of the display panel 15. The chip processor 10 can generate initial pixel sampling coordinates (i.e., the first coordinates P1') and final pixel sampling coordinates (i.e., the second coordinates P2') corresponding to the second displayed image area R2. Therefore, the display system 100 can perform an image resizing process without requiring a scalar image buffer. Thus, a time delay in the video stream or images can be avoided.

[0025] In summary, the present invention discloses a display system for adjusting the aspect ratio of a displayed image. When the display system adjusts the aspect ratio of the displayed image, it can generate multiple coordinates around an image area that corresponds to a user-configured aspect ratio. Furthermore, pixels within the image area corresponding to the aspect ratio are driven by the gate drive circuit and the data drive circuit. Additionally, the display system can easily adjust the image area to optimize the image tones by aligning it with a backlight area in the grid-lined backlight arrangement. Therefore, a final image display area can satisfy the user-configured aspect ratio and optimize the image tones.Instead of using a scalar image memory to perform an image resizing process, the display system of the present invention does not require a scalar image memory. This avoids a time delay in the video stream or images, resulting in an improved visual experience.

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