Storage arrays

Abstract

Storage array (12), comprising: a vertical stack, comprising: a layer (64) comprising conductor material (63); a layer (65) comprising insulating material (66) over the layer (64) comprising conductor material (63); a layer (27A) comprising conductive material (48) over the layer (65) comprising insulating material (66); and alternating insulating layers (20) and word line layers (22) above the layer (65) comprising the insulator material (66) and above the layer (27A) comprising the conductive material (48), wherein the word line layers (22) comprise gate regions (52) of individual memory cells (56), wherein the gate regions (52) individually comprise a part of a word line (29) in individual of the word line layers (22); Channel material (36) extending vertically through the insulating layers (20), the word conduction layers (22), the layer (27A) comprising conductive material (48), and the layer (65) comprising the insulator material (66); wherein the channel material (36) is electrically coupled to the conductor material (63) of the layer (64) comprising the conductor material (63); wherein the individual memory cells (56) comprise a memory structure (95) between the gate region (52) and the channel material (36); wherein the memory structure (95) comprises a charge-blocking region (30) radially inward from individual gate regions (52), a charge storage region (32) radially inward from individual charge-blocking regions (30), and insulating charge-passage material (34) radially inward from individual charge storage regions (32), wherein the charge-blocking regions (30) comprise a charge-blocking material; and a ring-shaped recess (15) in the layer (65) comprising the insulator material (66) and in the layer (27A) comprising the conductive material (48), wherein the annular recess (15) projects radially outwards, and wherein the charge-blocking material is located in the annular recess (15).

Description

TECHNICAL AREA

[0001] The embodiments disclosed herein relate to storage arrays. Also disclosed are exemplary methods used in creating a storage array. BACKGROUND

[0002] Memory is a type of integrated circuit used in computer systems to store data. Memory can be created in one or more arrays of individual memory cells. Memory cells can be written to or read from using bit lines (also called data lines or read lines) and word lines (also called access lines). Read lines connect memory cells along columns of the array, and access lines connect memory cells along rows of the array. Each memory cell can be uniquely addressed by combining a read line with an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods in the absence of power. Non-volatile memory is conventionally specified as having a retention time of at least approximately 10 years. Volatile memory decays and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less.

[0004] Regardless, memory cells are configured to hold or store information in at least two different selectable states. In a binary system, the states are considered either a "0" or a "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

[0005] A field-effect transistor (FET) is a type of electronic component that can be used in a memory cell. These transistors comprise a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include an additional structure, such as a reversibly programmable charge storage region, as part of the gate structure between the gate insulator and the conductive gate.

[0006] Flash memory is a type of storage and has numerous uses in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid-state drives to replace traditional hard disk drives. Yet another example is the popularity of flash memory in wireless electronic devices because it allows manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices for enhanced features.

[0007] NAND can be a basic architecture for integrated flash memory. A NAND cell unit comprises at least one selector coupled in series with a serial combination of memory cells (the serial combination being commonly referred to as a NAND chain). NAND architectures can be configured in a three-dimensional arrangement comprising vertically stacked memory cells, each containing a reversibly programmable vertical transistor. A controller or other circuitry can be formed beneath the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells, each containing a transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic cross-sectional view of a section of a substrate in a manufacturing process and is drawn along line 1-1 in Fig. 2 shown. Fig. 2 is a view along line 2-2 in Fig. 1. Fig. 3 is a view of the substrate from Fig. 1 in a processing step after the in Fig. 1 shown and will be along line 3-3 in Fig. 4 shown. Fig. 4 is a view along line 4-4 in Fig. 3. Fig. 5 is a view of the substrate from Fig. 3 in a processing step after the in Fig. 3 shown and will run along line 5-5 in Fig. 6 shown. Fig. 6 is a view along line 6-6 in Fig. 5. Fig. Figure 7 is a view of the substrate from Fig. 5 in one processing step after the in Fig. 5 shown. Fig. 8 is a view of the substrate from Fig. 7 in a processing step after the in Fig. 7 shown and will be along line 8-8 in Fig. 9 shown. Fig. 9 is a view along line 9-9 in Fig. 8. Fig. 10 is a view of the substrate from Fig. 8 in a processing step after the in Fig. 8 shown and will run along line 10-10 in Fig. 11 shown. Fig. 11 is a view along line 11-11 in Fig. 10. Fig. Figure 12 is a view of the substrate from Fig. 10 in one processing step after the in Fig. 10 shown and will run along line 12-12 in Fig. 13 shown. Fig. 13 is a view along line 13-13 in Fig. 12. Fig. Figure 14 shows a view of the substrate from Fig. 13 in a processing step after the in Fig. 13 shown. Fig. Figure 15 is a view of the substrate from Fig. 13 in a processing step after the in Fig. 13 shown and will be along line 15-15 in Fig. 16 shown. Fig. 16 is a view along line 16-16 in Fig. 15. Fig. Figure 17 is a view of the substrate from Fig. 15 in a processing step after the in Fig. 15 shown and will be along line 17-17 in Fig. 18 shown. Fig. 18 is a view along line 18-18 in Fig. 17. Fig. Figure 19 shows a view of the substrate from Fig. 17 in a processing step after the in Fig. 17 shown and will be along line 19-19 in Fig. 20 shown. Fig. 20 is a view along line 20-20 in Fig. 19. Fig. 21 is a view of the substrate from Fig. 20 in a processing step after the in Fig. 20 shown. Fig. 22 is a view of the substrate from Fig. 21 in a processing step after the in Fig. 21 shown. Fig. 23 is a view of the substrate from Fig. 22 in a processing step after the in Fig. 22 shown and will be along line 23-23 in Fig. 24 shown. Fig. 24 is a view along line 24-24 in Fig. 23. Fig. 25 is an enlarged view of a section from Fig. 24. Fig. 26 is a view of the substrate from Fig. 23 in a processing step after the in Fig. 23 shown and will be along line 26-26 in Fig. 27 shown. Fig. 27 is a view along line 27-27 in Fig. 26. Fig. 28 is a view of the substrate from Fig. 26 in a processing step after the in Fig. 26 shown and will be along line 28-28 in Fig. 29 shown. Fig. 29 is a view along line 29-29 in Fig. 28. Fig. Figure 30 is a schematic cross-sectional view of a section of a substrate in a process according to an exemplary embodiment. Fig. 31 is a view of the substrate from Fig. 30 in one processing step after the in Fig. 30 shown. Fig. Figure 32 is a schematic cross-sectional view of a section of a substrate in a process according to an exemplary embodiment. Fig. 33 is a view of the substrate from Fig. 32 in a processing step after the in Fig. 32 shown. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0008] For example, methods can be used when forming an array of transistors and / or memory cells, such as an array of NAND or other memory cells with a peripheral control circuit beneath the array (e.g., a CMOS subarray). These methods include, for example, so-called "gate-last" or "substitute-gate" processing, so-called "gate-first" processing, and other processing, whether existing or developed in the future, regardless of when transistor gates are formed. Embodiments of the invention include an array of transistors and / or memory cells (e.g., NAND or other memory cells), irrespective of the manufacturing process. First exemplary manufacturing steps are described with reference to the Fig. 1-29 described, which can be viewed as a “gate-last” or “substitute gate” process.

[0009] The Fig. 1 and Fig. Figure 2 shows a substrate construction 10 in an exemplary method for forming an array 12 of vertically extending chains of transistors and / or memory cells (not yet shown). The substrate construction 10 comprises a base substrate 11 with one or more conductive (i.e., electrically conductive here), semiconducting, or insulating (i.e., electrically conductive here) materials. Various materials were formed vertically above the base substrate 11. Materials can be placed to the side, vertically inward, or vertically outward of the substrate. Fig. 1 and Fig. 2 materials shown. For example, other partially or fully fabricated components of the integrated circuit may be provided anywhere above, around, or within the base substrate 11. A controller and / or other peripheral circuit for operating components within an array (e.g., array 12) of vertically extending chains of memory cells may also be fabricated and may or may not be wholly or partially located within an array or subarray. Furthermore, multiple subarrays may also be fabricated and operated independently, in series, or otherwise relative to one another. In this document, a “subarray” may also be considered an array.

[0010] Fig. Figure 2 shows circuit components 60 and 62 as part of the structure 10, formed on top of the base substrate 11. These may include a control and / or other peripheral circuit, as mentioned above, and are otherwise not material for the inventions disclosed herein. The insulator material 59 (e.g., silicon dioxide or silicon nitride) surrounds and is located above components 60 and 62. A layer 64, comprising conductor material 63, was formed above the substrate 11 and components / materials 59, 60, and 62 (e.g., within the array or array region 12). Any suitable conductor material can be used, for example, one or both of the metallic material or conductively doped semiconductor material. In one embodiment, the conductor material 63 comprises conductively doped polysilicon formed on tungsten silicide. The conductive material 63 may form part of the control circuit (e.g.,The peripheral under-array circuit comprises a circuit used to control read and write access to the transistors and / or memory cells formed within the array 12. In one embodiment, the conductor material 63 within layer 64 can be structured as a common source (e.g., a source line) of a NAND circuit, for example, as described in US Patent No. 2017 / 0140833 by Caillat et al., published on May 18, 2017. A layer 65 comprising insulator material 66 (e.g., silicon dioxide and / or silicon nitride) is formed above layer 64.

[0011] With reference to Fig. 3 and Fig. Openings 67 and 68 were formed through the insulator material 66 of layer 65 to the conductor material 63 of layer 64. An opening 69 was also formed through materials 66 and 59 to component 62. Such an opening can be formed by any existing or future technique, for example, photolithography. Openings 67, 68, and 69 are shown individually as having the same respective size and shape (e.g., circular for openings 67 and 69 and elongated grooves for opening 68), although alternative sizes and shapes can be used. The exemplary opening 69 is deeper in the structure 10 than openings 67 and 68. Where such openings are formed by etching, forming materials 62 and 59 from polysilicon and silicon dioxide, respectively, can facilitate the etching of the deeper opening 69 without requiring additional processing steps or considerations.

[0012] With reference to Fig. 5 and Fig. Sacrificial islands 72 comprising etch-stop material 70 were formed directly above the conductor material 63 of layer 64. This can be achieved, for example, by depositing etch-stop material 70 to fill the openings 67 and then planarizing or backpolishing the material 70 at least to a top surface of the insulator material 66. In one embodiment, the etch-stop material 70 comprises conductive material (e.g., conductively doped semiconductor material or metal material). In another embodiment, the etch-stop material 70 comprises a radially outer dielectric material (e.g., silicon dioxide or silicon nitride, not shown) and a radially inner conductive material (e.g., TiN and W, not shown). In one embodiment, the etch-stop material 70 is insulating.In one embodiment, as shown, the conductors 73 of the etch stop material 70 were also formed directly above the conductor material 63 of layer 64, with the sacrificial islands 72 spaced from and between the conductors 73. The conductors 73 can be sacrificial conductors, for example, the etch stop material 70 being conductive. The conductors 73 can be sacrificial or non-sacrificial conductors, for example, the etch stop material 70 being insulating. In an embodiment where the etch stop material 70 is conductive, non-sacrificial landing pads 74 were formed to couple directly with conductive array through-array vias (TAVs) to be formed. In such an embodiment, the conductive etch stop material 70 forms a conductive path from the respective top surfaces to the respective bottom surfaces of the sacrificial islands 72 and the non-sacrificial landing pads 74.

[0013] With reference to Fig. In one embodiment, a stack 18 comprising vertically alternating insulating layers 20 and word-conductor layers 22 was formed over the sacrificial islands 72, the conductors 73, and the layer 64 comprising the conductor material 63. In another embodiment, a stack 21 comprising vertically alternating insulating layers 23* (e.g., 23A, 23B, 23C, generally referred to as 23*) and conductor layers 27* (e.g., 27A, 27B, 27C, generally referred to as 27*) was provided between the stack 18 and the layer 65 comprising the etch-stop material 70 (e.g., by forming the stack 21 prior to forming the stack 18). The layers 22 and 27* may not comprise conductive material, and the layers 20 and 23* may not comprise insulating material or may be insulating at this stage of processing. Only a small number of layers 20 and 22 are shown, with the stack comprising 18 likely dozens, hundreds or more, etc., of layers 20 and 22.Similarly, if present, the stack can comprise more or less vertically alternating layers.

[0014] The exemplary word-conducting layers 22 and conductor layers 27* comprise a first material 26 (e.g., silicon nitride), which may be fully or partially sacrificial. The exemplary insulating layers 20 and 23* comprise a second material 24 (e.g., silicon dioxide) that has a different composition than the first material 26 and may be fully or partially sacrificial. Another circuit, which may or may not be part of a peripheral and / or control circuit (not shown), may be fabricated; for example, several vertically alternating layers of conductive and insulating material (not shown) of such a circuit may be fabricated over a topmost of the word-conducting layers 22.

[0015] With reference to Fig. 8 and Fig. 9 Etching was carried out through the insulating layers 20 and word-conductor layers 22 and the stack 21, if present, to the etch-stop material 70 (i.e., acting as an etch stop) of individual sacrificial islands 72 to form channel openings 25 having individual bases 33 encompassing the etch-stop material 70. The channel openings 25 may extend into the etch-stop material 70 (as shown) or may stop on it (not shown). In one embodiment, and as shown, individual islands 72 are diametrically larger than individual channel openings 25. Alternatively, but less preferably, individual islands 72 may have the same or smaller horizontal dimensions as individual channel openings 25 (not shown).

[0016] With reference to Fig. 10 and Fig. 11 sacrificial islands 72 (not shown) were removed (e.g. by wet or dry isotropic etching, which can be carried out selectively relative to other exposed materials) through individual channel openings 25 of Fig. 8 and Fig. 9, to extend such channel openings (now designated 25E, having bases 33E) to the layer 64. In such an embodiment and as shown, extended channel openings 25E extend to the conductor material 63. The process of removing sacrificial islands 72 (not shown) may cause extended channel openings 25E to extend into the conductor material 63 (not shown) or may stop on it (as shown). In an embodiment and as shown, wherein islands 72 are individually diametrically larger than channel openings 25 prior to the removal of islands 72, the process of removing channel openings 25E forms, individually, an annular recess 15 in the layer 65 comprising insulator material 66 projecting radially outward (e.g., relative to initially formed channel openings 25).

[0017] Transistor channel material is formed in the enlarged channel openings to the layer encompassing the conductor material in order to be electrically coupled to it. In some embodiments, individual memory cells of the array are formed to encompass a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In such an embodiment, the memory structure is formed to encompass a charge-blocking region, charge-storage material, and insulating charge-passage material. The charge-storage material (e.g., floating-gate material such as doped or undoped silicon, or charge-trapping material such as silicon nitride, metal dots, etc.) of the individual memory cells is located vertically along individual charge-blocking regions. The insulating charge-passage material (e.g., a bandgap-constructed structure containing nitrogen-containing material [e.g.,silicon nitride], which is enclosed between two insulator oxides [e.g. silicon dioxide], is located laterally between the channel material and the charge storage material.

[0018] Fig. 12 and Fig. Figure 13 shows an embodiment in which the charge-blocking material 30, the charge-storage material 32, and the charge-passing material 34 are formed vertically in individual enlarged channel openings 25E along insulating layers 20 and word-conducting layers 22 and within annular recesses 15. A sacrificial protection material 35 (e.g., polysilicon) is formed along the charge-passing material 34. Transistor materials 30, 32, and 34 (e.g., memory cell materials) and material 35 can be formed, for example, by depositing thin layers of each above the stack 18 and within individual enlarged channel openings 25E.

[0019] With reference to Fig. 14. Punch etching was performed to remove materials 30, 32, and 34 from bases 33E of enlarged channel openings 25E to expose conductor material 63, and sacrificial protection material 35 (not shown) was removed (e.g., by selective wet etching). Such punch etching can cause enlarged channel openings 25E to extend into the conductor material 63 (as shown) or may stop there (not shown).

[0020] With reference to Fig. 15 and Fig. In 16, channel material 36 was then formed in enlarged channel openings 25E along insulating layers 20 and word-conductor layers 22. In one embodiment, and as shown, no channel material 36 is formed in annular recesses 15. Exemplary channel materials 36 comprise suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An exemplary thickness for each of the materials 30, 32, 34, and 36 is 25 to 100 Ångstroms. Enlarged channel openings 25E are shown comprising a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and only as an example, the radially central section within enlarged channel openings 25E may include one or more cavities (not shown) and / or be free of solid material (not shown).

[0021] With reference to Fig. 17 and Fig. 18 Etching was carried out through insulating layers 20 and word line layers 22 and through stacks 21, if present, to etch-stop material 70 of lines 73 to form horizontally elongated trenches 40 having individual bases 37 that encompass etch-stop material 70 of individual lines 73. In one embodiment, the lines 73 are non-sacrificing and remain in a finished construction of the storage array (not shown), for example, where the etch-stop material 70 is insulating. Alternatively, and as in Fig. 19 and Fig. As shown in Figure 20, the conduits 73 (not shown) are sacrificial and were removed by means of single horizontally elongated trenches 40. Independently, etching through the insulating layers and the word-conductor layers to etch-stop material 70 of conduits 73 can take place before or after the formation of channel material 36 and before or after the formation of channel openings 25 / 25E, with the latter being shown after such formation of channel material 36.

[0022] With reference to Fig. 21 The first material 26 (not shown) of the word conduction layers 22 and layers 27* was selectively etched relative to the second material 24 (e.g. using liquid or vaporous H3PO4 as a primary etchant, where material 26 is silicon nitride and material 24 is silicon dioxide).

[0023] With reference to Fig. 22 Conductive material 48 was formed into word line layers 22 and layers 27* by trenches 40, and the conductive material will comprise the individual word lines and other gate lines that are formed. Any suitable conductive material can be used, for example, one or both of metallic material and / or conductively doped semiconductor material.

[0024] With reference to Fig. 23-25 ​​Conductive material 48 was removed from individual trenches 40. This led to the formation of word lines 29 and vertically extending chains 49 of individual transistors and / or memory cells 56. Approximate positions of transistors and / or memory cells 56 are indicated with a bracket in Fig. 25 and some with dashed outlines in Fig. 23 and Fig. 24, wherein transistors and / or memory cells 56 in the illustrated example are essentially ring-shaped or toroidal. Conductive material 48 can be used as terminal ends 50 ( Fig. 25) are considered to have control gate regions 52 corresponding to individual transistors and / or memory cells 56. In the illustrated embodiment, control gate regions 52 comprise individual sections of individual word lines 29. Materials 30, 32 and 34 can be considered as a memory structure 95 ( Fig. 25) are considered, which is located laterally between control gate region 52 and channel material 36. Individual trenches 40 were filled with material (e.g. 55 [dielectric, such as silicon dioxide or silicon nitride] and e.g. 57 [polysilicon]).

[0025] A charge-blocking region (e.g., charge-blocking material 30) is located between charge storage material 32 and individual control gate regions 52. A charge block can have the following functions in a memory cell: In a programming mode, the charge block can prevent charge carriers from the charge storage material (e.g., floating gate material, charge-capture material, etc.) from reaching the control gate, and in an erasing mode, the charge block can prevent charge carriers from flowing from the control gate into the charge storage material. Accordingly, a charge block can function to block charge migration between the control gate region and the charge storage material of individual memory cells. An exemplary charge-blocking region, as shown, comprises insulator material 30. As further examples, a charge-blocking region can comprise a lateral (e.g., radial) outer section of the charge storage material (e.g.,Material 32) where such a charge storage material is insulating (e.g., in the absence of a material with a different composition between an insulating charge storage material 32 and a conductive material 48). Independently of this, as an additional example, an interface between a charge storage material and a conductive material of a control gate may be sufficient to function as a charge-blocking region in the absence of an insulator material 30 with a different composition. Furthermore, an interface between conductive material 48 and material 30 (if present) in combination with insulator material 30 may together function as a charge-blocking region, and alternatively or additionally, a laterally outer region of an insulating charge storage material (e.g., a silicon nitride material 32) may also function as a charge-blocking region. An exemplary material 30 is silicon dioxide and / or silicon nitride.

[0026] With reference to Fig. 26 and Fig. 27 Etching through insulating layers 20 and word-conducting layers 22 to conductive etch-stop material 70 of individual non-sacrificial landing pads 74 was carried out to form TAV openings 39 having individual bases 41 comprising conductive etch-stop material 70 of individual non-sacrificial landing pads 74. Alternatively and more preferably, the TAV openings 39 can be formed prior to the formation (not shown) of horizontally elongated trenches 40, such that the TAV openings 39 are etched through preferred silicon dioxide material 24 and preferred silicon nitride material 26 as opposed to through preferred silicon dioxide material 24 and conductive material 48.

[0027] With reference to Fig. 28 and Fig. 29 Insulator material 43 (e.g. silicon nitride and / or silicon dioxide) and conductive material 45 (e.g. conductively doped semiconductor material and / or metal material) were formed in the TAV openings 39 and directly electrically coupled to non-sacrificial landing pads 74 to form individual TAVs 47 in individual TAV openings 39.

[0028] As an alternative example, at least part of the etch stop material 70 (regardless of whether it is conductive) could be in Fig. 27 are removed, and then conductive material 45 could be formed in individual TAV openings 39 to form individual TAVs. As an example, and only as an example, an embodiment is considered wherein the etch stop material 70 comprises a radially outer dielectric material (e.g., silicon dioxide) and a radially inner conductive material (e.g., a TiN lining and radially central W). The conductive section of the material 70 consists of Fig. 27 could be etched away after the formation of the TAV openings 39, leaving behind the radially outer dielectric material. Then, insulator material 43 could be deposited, followed by removal of the radially outer dielectric material and insulator material 43 from the bases of the individual TAV openings 39, and followed by deposition of conductive material 45. Any other attributes or aspects, as shown and / or described herein in relation to other embodiments, may be used.

[0029] An alternative exemplary embodiment is described with reference to the Fig. 30 and Fig. 31 and a construction 10a are shown and described. The same reference numerals from the embodiments described above have been used where appropriate, with any design difference being indicated by the suffix “a”. With reference to Fig. In step 30, layer 23A (optional) and the conductor layer 27A above it were formed before the opening 67 was created, and then the opening 67 was formed by layers 27A, 23A, and 65. This can also be done, for example, with respect to openings 68 (not shown) and / or opening 69 to reach component 62 (not shown). Accordingly, the sacrificial islands 72 (not shown) of the Fig. 5 and Fig. 6 (and in one embodiment the lines 73 and / or the non-victim landing pads 74 of the Fig. 5 and Fig. 6) larger than in the Fig. 5 and Fig. 6 shown formed.

[0030] With reference to Fig. 31. Materials 30, 32, 34, 36, and 38 were formed analogously to that described above, wherein, for example, in one embodiment, a minimal charge-blocking material 30 was formed in the annular recess 15a of the enlarged channel openings 25E. Any other attributes or aspects, as shown and / or described herein in relation to other embodiments, may be used.

[0031] The Fig. 32 and Fig. Figure 33 shows an alternative exemplary processing with respect to construction 10b. The same reference numerals from the embodiments described above have been used where appropriate, with any certain design difference being indicated by the suffix “b”. With reference to Fig. Layers 23A (optional), 27A, 23B, 27B, 23C, and 27C were formed prior to the formation of opening 67, and then opening 67 was formed by such layers and 65. This can also occur, for example, with respect to openings 68 and / or 69 (not shown). Accordingly, the sacrificial islands 72 (not shown) of the Fig. 5 and Fig. 6 (and in one embodiment the lines 73 and / or the non-victim landing pads 74 of the Fig. 5 and Fig. 6) larger than in the Fig. 5 and Fig. 6 shown and as above in relation to the Fig. 30 and Fig. 31 described formed.

[0032] With reference to Fig. 33. Materials 30, 32, 34, 36, and 38 were formed analogously to that described above, wherein, for example, in one embodiment, a minimal charge-blocking material 30 was formed in the annular recess 15b of the enlarged channel openings 25E. Any other attributes or aspects, as shown and / or described herein in relation to other embodiments, may be used.

[0033] Embodiments of the invention include storage arrays independent of the manufacturing process. Nevertheless, such a storage array can possess any of the attributes described herein in exemplary manufacturing processes.

[0034] In one embodiment, a memory array (e.g., 12) comprises a vertical stack (e.g., 18, 21 plus material 63 below) that includes a layer (e.g., 64) comprising conductor material (e.g., 63). A layer (e.g., 65) comprising insulator material (e.g., 66) is located above the conductor layer. Alternating insulating layers (e.g., 20) and word line layers (e.g., 22) are located above the insulator layer. The word line layers comprise gate regions (e.g., 52) of individual memory cells (e.g., 56). The gate regions individually comprise a portion of a word line (e.g., 29) in individual word line layers. Channel material (e.g., 36) extends vertically through the insulating layers, the word-conductor layers, and the layer encompassing the insulator material. The channel material is directly electrically coupled to the conductor material of the layer encompassing the conductor material. Individual memory cells (e.g., 36)B. 56) comprise a storage structure (e.g., 95) between the gate region and the channel material. The storage structure comprises a charge-blocking region (e.g., 30, if present, or a section of material 32 if not present) radially inward from each of the gate regions. A charge storage region (e.g., 32) is located radially inward from each of the charge-blocking regions. Insulating charge-pass material (e.g., 34) is located radially inward from each of the charge storage regions. The charge-blocking regions comprise a charge-blocking material (e.g., 30, if present, or a section of material 32 if not present). An annular recess (e.g., 15, 15a, 15b) is located in the layer comprising the insulator material. The ring-shaped recess projects radially outwards to be directly beneath conductive material (e.g. 48) located in the individual word lines (e.g.(where some material 24 is located above the annular recess). The charge-blocking material is located in the annular recess, which is in the layer comprising the insulator material, and is directly beneath the conductive material located in the individual word-line layers. In one embodiment, the conductor material comprises conductively doped semiconductor material over metal material. In one embodiment, the charge-storage region comprises charge-storage material, and this is located in the annular recess, which is in the layer comprising the insulator material, and is directly beneath the conductive material located in the individual word-line layers.In such an embodiment, the insulating charge-transmitting material is located in the annular recess in the layer containing the insulator material and is situated directly beneath the conductive material in the word conduction layers.

[0035] In one embodiment, the annular recess (e.g., 15a, 15b) extends over the layer comprising the insulator material, and the charge-blocking material is located in the annular recess above the layer comprising the insulator material. In such an embodiment, a layer (e.g., one of 27A, 27B, 27C) comprising conductive material (e.g., 48) is located between: (a) the alternating insulating and conductive layers and (b) the layer comprising the conductive material. The annular recess extends into the layer comprising the conductive material, and the charge-blocking material located in the annular recess is directly adjacent to the conductive material of the layer comprising the conductive material.

[0036] In one embodiment, the storage array comprises a layer containing conductive material, sandwiched between (a) the alternating insulating and word-line layers and (b) the layer containing conductive material. The annular recess is located everywhere beneath the layer containing the conductive material (e.g., Fig. 29). In such an embodiment (e.g. Fig. 29) The annular recess is located everywhere below the lowest surface of the conductive material of the layer comprising the conductive material. The charge-blocking material located in the annular recess is thereby not in direct contact with the lowest surface of the conductive material of the layer comprising the conductive material. Any other attribute(s) or aspect(s), as shown and / or described herein in relation to other embodiments, may be used.

[0037] In one embodiment, a memory array (e.g., 12) comprises a vertical stack (e.g., 18, 21 plus material 63 below) that includes a layer (e.g., 64) comprising conductor material (e.g., 63). A layer (e.g., 65) comprising insulator material (e.g., 66) is located above the conductor material layer. A layer (e.g., 27B) comprising conductive material (e.g., 48) is located above the insulator material layer. Alternating insulating layers (e.g., 20) and word-line layers (e.g., 22) are located above the insulator material layer. The word-line layers comprise gate regions (e.g., 52) of individual memory cells (e.g., 56). The gate regions each comprise a portion of a word line (e.g., 29) within individual word line layers. Channel material (e.g., 36) extends vertically through the insulating layers, the word line layers, and the layer containing the insulator material.The channel material is directly electrically coupled to the conductor material of the layer that encompasses the conductor material. Individual memory cells (e.g., 56) comprise a memory structure (e.g., 95) between the gate region and the channel material. The memory structure includes a charge-blocking region (e.g., 30, if present, or a section of material 32 if absent) radially inward from each of the gate regions. A charge storage region (e.g., 32) is located radially inward from each of the charge-blocking regions. Insulating charge-pass material (e.g., 34) is located radially inward from each of the charge storage regions. The charge-blocking regions comprise a charge-blocking material (e.g., 30, if present, or a section of material 32 if absent). An annular recess (e.g. 15, 15a, 15b) is located in the layer that includes the insulator material and in the layer that includes the conductive material.The annular recess projects radially outward to be directly beneath conductive material (e.g., 48) located in the individual word lines. The charge-blocking material is located in the annular recess, which is situated in the layer containing the insulator material and in the layer containing the conductive material, and is located directly beneath the conductive material in the individual word line layers.

[0038] In one embodiment, the layer comprising the conductive material includes a select-gate-source control line (e.g., 91 in layer 27B in Fig. 27, Fig. 29, Fig. 31 and Fig. 33). In one embodiment, the layer containing the conductive material does not include a select-gate-source control line (e.g., conductive material in layer 27A). The embodiment of Fig. 27, Fig. 29, Fig. 31 and Fig. Figure 33 shows examples, where, for instance, the conductive material 48 in layer 27B can be a select-gate-source control line. As an alternative exemplary embodiment, the conductive material 48 in layer 27B can comprise three separate layers with insulating layers in between (not shown), and where such gates are directly electrically coupled in parallel to jointly function as a single select-gate-source control line. Additionally, the exemplary conductive layer 27A can provide primary purpose and function in clearing a memory state in a memory cell chain 49 for the purpose of inducing gate-induced drain leakage. The exemplary conductive layer 27C can be a dummy word line 93 ( Fig. 27, Fig. 29, Fig. 31 and Fig.33) comprise and function as such, which means that such a layer does not contain functional memory cells as part of the chain 49, but is functional as a gate to cause the channel material 36 radially adjacent to it to be conductive in operation.

[0039] In one embodiment, several layers (e.g., 27A, 27B, 27C) comprising the conductive material are located above the layer comprising the insulator material and below the alternating insulating and conductive layers. The annular recess (e.g., 15b) is located within such a plurality of such layers comprising the conductive material. In such an embodiment, at least one of these multiple layers (e.g., 27B) comprises the conductive material, which includes a select-gate-source control line. In such an embodiment, at least one of these multiple layers comprising the conductive material does not include a select-gate-source control line. In such an embodiment, at least one of these multiple layers comprising the conductive material includes a select-gate-source control line.Another at least one of several such layers comprising the conductive material does not include a select-gate-source control line.

[0040] The assemblies and structures discussed above can be used in integrated circuits / switching technology and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multilayer multichip modules. The electronic systems can be any of a wide range of applications, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, watches, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0041] In this document, unless otherwise specified, "height," "higher," "upper," "lower," "above," "below," "over," "below," "below," "below," "up," and "down" generally refer to the vertical direction. "Horizontal" refers to a general direction (i.e., within 10 degrees) along a primary substrate surface and may be relative to the orientation toward which the substrate is processed during manufacturing, and "vertical" is a direction generally orthogonal to it. "Exactly horizontal" refers to the direction along the primary substrate surface (i.e., no degree of it) and may be relative to the orientation toward which the substrate is processed during manufacturing. Furthermore, "vertical" and "horizontal," as used herein, are generally perpendicular directions relative to each other and independent of the substrate's orientation in three-dimensional space.Additionally, "height-extending" and "extending in height" refer to a direction angled at least 45° away from exactly horizontal. Furthermore, with respect to a field-effect transistor, "height-extending," "height-extending," "horizontally extending," and "horizontally extending" refer to the orientation of the transistor's channel length along which current flows between the source / drain regions during operation. For bipolar transistors, "height-extending," "height-extending," "horizontally extending," and "horizontally extending" refer to the orientation of the base length along which current flows between the emitter and collector during operation. In some embodiments, each component, feature, and / or region that extends in height extends vertically or within 10° of vertical.

[0042] Furthermore, "directly above" and "directly below" require at least some lateral (i.e., horizontal) overlap between the two specified regions / materials / components. The use of "above" without "directly" also requires only that a portion of the specified region / material / component located above the other is outward in height from the other (i.e., regardless of whether there is lateral overlap between the two specified regions / materials / components). Similarly, the use of "below" without "directly" requires only that a portion of the specified region / material / component located below the other is inward in height from the other (i.e., regardless of whether there is lateral overlap between the two specified regions / materials / components).

[0043] Each of the materials, regions, and structures described herein may be homogeneous or non-homogeneous and may exist independently, continuously or discontinuously, above any material so superimposed. If one or more exemplary compositions are provided for each material, that material may include, consist substantially of, or be composed of such one or more such compositions. Furthermore, unless otherwise specified, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0044] Additionally, “thickness” alone (without a preceding directional adjective) is defined as the mean straight-line distance through a given material or region perpendicularly from the nearest surface of an immediately adjacent material of a different composition or an immediately adjacent region.

[0045] Additionally, the various materials or regions described herein may be of substantially constant thickness or of variable thickness. If of variable thickness, the thickness refers to the average thickness unless otherwise specified, and such a material or region will have a certain minimum thickness and a certain maximum thickness, being variable. As used herein, "different composition" only requires that the sections of two specified materials or regions, which may be directly adjacent, are chemically and / or physically different, for example, if such materials or regions are not homogeneous.If the two specified materials or regions are not directly adjacent, "different composition" only requires that the sections of the two specified materials or regions that are closest to each other are chemically and / or physically different if such materials or regions are not homogeneous. In this document, a material, region, or structure is "directly adjacent" if there is at least one physical contact between the specified materials, regions, or structures relative to each other. In contrast, "over," "on," "adjacent," "along," and "against" not preceded by "directly" include "directly against" as well as a construction in which an intervening material(s), region(s), or structure does not result in any physical contact between the specified materials, regions, or structures relative to each other.

[0046] In this context, region-material components are "electrically coupled" relative to each other if, under normal operating conditions, electric current is able to flow continuously from one to the other, primarily through the movement of subatomic positive and / or negative charges, provided sufficient quantities are generated. Another electronic component may lie between the region-material components and be electrically coupled to them. In contrast, when region-material components are described as "directly electrically coupled," no intervening electronic component (e.g., no diode, transistor, resistor, converter, switch, fuse, etc.) lies between the directly electrically coupled region-material components.

[0047] Additionally, "metallic material" is any or a combination of an elemental metal, a mixture or alloy of two or more elemental metals and any conductive metal compound.

[0048] In this context, "selective" with respect to etching, deposition, removal, deposition, formation, and / or formation means such an operation on a specified material relative to another specified material(s) at a rate of at least 2:1 by volume. Furthermore, selective deposition, selective waxing, or selective formation means the deposition, waxing, or formation of a material relative to another specified material or materials at a rate of at least 2:1 by volume for at least the first 75 angstroms of the deposition, waxing, or formation. Unless otherwise specified, the use of "or" herein includes one or both.

[0049] For example, a method used in forming a memory array involves forming a layer containing conductor material over a substrate. Sacrificial islands containing etch stop material are formed directly above the conductor material of the layer containing the conductor material. A stack comprising vertically alternating insulating and word-conductor layers is formed over the sacrificial islands and the layer containing the conductor material. Etching is performed through the insulating and word-conductor layers to the etch stop material from individual sacrificial islands to form channel openings, each with individual bases containing the etch stop material. The sacrificial islands are removed through individual channel openings to enlarge the individual channel openings to the layer containing the conductor material. Channel material is formed in the enlarged channel openings to the layer containing the conductor material.The channel material is electrically coupled to the conductor material of the layer that encompasses the conductor material.

[0050] For example, one method used in forming a memory array involves forming a layer containing conductor material over a substrate. Sacrificial islands are formed, spaced from and between conductors. The sacrificial islands and conductors are located directly above the conductor material of the layer containing the conductor material. The sacrificial islands and conductors contain etch stop material. A stack is formed, comprising vertically alternating insulating layers and word-conductor layers over the sacrificial islands, the conductors, and the layer containing the conductor material. Etching is performed through the insulating and word-conductor layers to the etch stop material from individual sacrificial islands to form channel openings that have individual bases containing the etch stop material.Sacrificial islands are removed through individual channel openings to enlarge these openings into the layer containing the conductor material. Channel material is formed within these enlarged openings into the layer containing the conductor material. This channel material is electrically coupled to the conductor material of the layer containing the conductor material. Etching is performed through the insulating and core conductor layers to the etch stop material of the conductors, forming horizontally elongated trenches that feature individual bases encompassing the etch stop material of each conductor.

[0051] For example, a method used in forming a memory array involves forming a layer containing conductor material over a substrate. Sacrificial islands are formed, spaced from and between non-sacrificial conductors. The sacrificial islands and the non-sacrificial conductors lie directly above the conductor material of the layer containing the conductor material. The sacrificial islands and the non-sacrificial conductors contain insulating etch-stop material. A stack is formed comprising vertically alternating insulating layers and word-conductor layers over the sacrificial islands, the non-sacrificial conductors, and the layer containing the conductor material. Etching is performed through the insulating layers and the word-conductor layers to the insulating etch-stop material of individual sacrificial islands to form channel openings that have individual bases containing the insulating etch-stop material.The sacrificial islands are removed through individual channel openings to enlarge these openings into the layer containing the conductor material. Channel material is formed within these enlarged openings into the layer containing the conductor material. This channel material is electrically coupled to the conductor material of the layer containing the conductor material. Etching is performed through the insulating and word-line layers to the insulating etch stop material of the non-sacrificial lines to form horizontally elongated trenches, each with individual bases that encompass the insulating etch stop material of the non-sacrificial lines. The non-sacrificial lines remain in a completed storage array structure.

[0052] For example, a method used in the fabrication of a memory array and conductive array vias (TAVs) involves forming a layer containing conductor material over a substrate. Sacrificial islands and non-sacrificial landing pads are formed. The sacrificial islands are located directly above the conductor material of the layer containing the conductor material. The sacrificial islands and the non-sacrificial landing pads contain conductive etch stop material, forming a conductive path from their respective top surfaces to their respective bottom surfaces. A stack is formed comprising vertically alternating insulating layers and word-conductor layers over the sacrificial islands, the non-sacrificial landing pads, and the layer containing the conductor material.Etching is performed through the insulating and word-conducting layers to the conductive etch stop material of individual sacrificial islands to form channel openings, each containing individual bases that encompass the conductive etch stop material. The sacrificial islands are removed through individual channel openings to enlarge the individual channel openings to the layer containing the conductive material. Channel material is formed in the enlarged channel openings to the layer containing the conductive material. The channel material is electrically coupled to the conductive material of the layer containing the conductive material. Etching is performed through the insulating and word-conducting layers to the conductive etch stop material of the non-sacrificial landing pads to form TAV openings, each containing individual bases that encompass the conductive etch stop material of individual non-sacrificial landing pads.Conductive material is formed in the TAV openings to be directly electrically coupled to the non-sacrificial landing pads in order to form individual TAVs in individual TAV openings.

[0053] For example, a method used in the fabrication of a memory array and conductive array vias (TAVs) involves forming a layer containing conductor material over a substrate. Landing pads and sacrificial islands are formed, with the sacrificial islands located directly above the conductor material of the layer containing the conductor material. The landing pads and sacrificial islands contain etch stop material. A stack comprising vertically alternating insulating and word-conductor layers is formed over the landing pads, the sacrificial islands, and the layer containing the conductor material. Etching is performed through the insulating and word-conductor layers to the etch stop material from individual sacrificial islands to form channel openings that have individual bases containing the etch stop material.The sacrificial islands are removed through individual channel openings to enlarge the individual channel openings to the layer containing the conductive material. Channel material is formed in the enlarged channel openings to the layer containing the conductive material. The channel material is electrically coupled to the conductive material of the layer containing the conductive material. Etching is performed through the insulating layers and the word-conducting layers to the etch-stop material of the landing pads to form TAV openings, each with individual bases that encompass the etch-stop material of individual non-sacrificial landing pads. At least a portion of the etch-stop material is removed, and then conductive material is formed in the TAV openings to create individual TAVs in individual TAV openings.

[0054] In some embodiments, a memory array comprises a vertical stack containing a layer of conductor material, a layer of insulator material above the conductor layer, and alternating insulating layers and word line layers above the insulator layer. The word line layers comprise gate regions of individual memory cells. Each gate region individually comprises a portion of a word line in each of the word line layers. Channel material extends vertically through the insulating layers, the word line layers, and the insulator layer. The channel material is directly electrically coupled to the conductor material of the conductor layer. The individual memory cells comprise a memory structure between the gate region and the channel material.The storage structure comprises a charge-blocking region radially inward from each of the gate regions, a charge-storage region radially inward from each of the charge-blocking regions, and insulating charge-pass material radially inward from each of the charge-storage regions. The charge-blocking regions comprise a charge-blocking material. An annular recess is located in the layer containing the insulating material. The annular recess projects radially outward to be directly beneath the conductive material located in each word-line layer. The charge-blocking material is located in the annular recess in the layer containing the insulating material and is directly beneath the conductive material located in each word-line layer.

[0055] In some embodiments, a memory array comprises a vertical stack containing a layer of conductor material, a layer of insulator material above the conductor material layer, a layer of conductive material above the insulator layer, alternating insulating layers, and word line layers above the conductive layer. The word line layers include gate regions of individual memory cells. The gate regions each contain a portion of a word line in each of the word line layers. Channel material extends vertically through the insulating layers, the word line layers, the conductive layer, and the insulator layer. The channel material is directly electrically coupled to the conductor material of the conductor layer.The individual memory cells comprise a memory structure between the gate region and the channel material. This memory structure includes a charge-blocking region radially inward from each of the gate regions, a charge-storage region radially inward from each of the charge-blocking regions, and insulating charge-passage material radially inward from each of the charge-storage regions. The charge-blocking regions comprise a charge-blocking material. An annular recess is located in the layer containing the insulating material and in the layer containing the conductive material. The annular recess projects radially outward to be directly beneath the conductive material located in each of the word-conductor layers.The charge-blocking material is located in the annular recess that is in the layer containing the insulator material and in the layer containing the conductive material, and is located directly beneath the conductive material that is in each word conduction layer. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 2017 / 0140833

[0010]

Claims

[1] Storage array (12), comprising: a vertical stack, comprising: a layer (64) comprising conductor material (63); a layer (65) comprising insulating material (66) over the layer (64) comprising conductor material (63); a layer (27A) comprising conductive material (48) over the layer (65) comprising insulating material (66); and alternating insulating layers (20) and word line layers (22) above the layer (65) comprising the insulator material (66) and above the layer (27A) comprising the conductive material (48), wherein the word line layers (22) comprise gate regions (52) of individual memory cells (56), wherein the gate regions (52) individually comprise a part of a word line (29) in individual of the word line layers (22); Channel material (36) extending vertically through the insulating layers (20), the word conduction layers (22), the layer (27A) comprising conductive material (48), and the layer (65) comprising the insulator material (66); wherein the channel material (36) is electrically coupled to the conductor material (63) of the layer (64) comprising the conductor material (63); wherein the individual memory cells (56) comprise a memory structure (95) between the gate region (52) and the channel material (36); wherein the memory structure (95) comprises a charge-blocking region (30) radially inward from individual gate regions (52), a charge storage region (32) radially inward from individual charge-blocking regions (30), and insulating charge-passage material (34) radially inward from individual charge storage regions (32), wherein the charge-blocking regions (30) comprise a charge-blocking material; and a ring-shaped recess (15) in the layer (65) comprising the insulator material (66) and in the layer (27A) comprising the conductive material (48), wherein the annular recess (15) projects radially outwards, and wherein the charge-blocking material is located in the annular recess (15). [2] Storage array according to claim 1, wherein the charge-blocking material located in the annular recess projects radially outwards. [3] Storage array according to claim 1 or claim 2, wherein the charge-blocking material located in the annular recess is located directly against the conductive material (48) of the layer (27A) comprising the conductive material (48). [4] Storage array according to one of claims 1 to 3, wherein the charge storage region (32) comprises a charge storage material, wherein the charge storage material is located in the annular recess (15). [5] Storage array according to one of claims 1 to 4, wherein the charge transmission material (34) is located in the annular recess (15). [6] Storage array according to any one of claims 1 to 5, wherein the layer (27A) comprising the conductive material (48) comprises a select-gate-source control line. [7] Memory array according to any one of claims 1 to 6, wherein the layer (27A) comprising the conductive material (48) is configured to induce gate-induced drain leakage to clear a memory state in a memory cell chain. [8] Storage array according to any one of claims 1 to 7, wherein the layer (27A) comprising the conductive material (48) comprises a dummy word line. [9] Storage array according to any one of claims 1 to 8, comprising several of the layers (27A, 27B, 27C) comprising the conductive material (48) above the layer (65) comprising the insulator material (66) and located beneath the alternating insulating layers (20) and word conduction layers (22). [10] Storage array according to claim 9, wherein the annular recess (15) is located in several of the layers (27A, 27B, 27C) comprising the conductive material (48). [11] Storage array according to claim 9 or 10, wherein at least one of the several layers (27A, 27B, 27C) comprising the conductive material (48) comprises a select-gate-source control line (91). [12] Storage array according to one of claims 9 to 11, wherein at least one of the several layers (27A, 27B, 27C) comprising the conductive material (48) does not include a select-gate-source control line. [13] Storage array according to one of claims 9 to 12, wherein the vertical stack further comprises insulating layers (23A, 23B, 23C) arranged between the multiples of the layers (27A, 27B, 27C) comprising the conductive material (48). [14] Storage array according to any one of claims 1 to 13, wherein the channel material extends into the layer (64) which comprises conductor material (63). [15] Storage array according to any one of claims 1 to 14, wherein at least one of the charge-blocking material (30), the charge-storage material (32), the charge-passing material (34) and the channel material (36) has a thickness within a range of 25 to 100 angstroms. [16] Storage array according to any one of claims 1 to 15, further comprising at least one array via. [17] Memory array according to any one of claims 1 to 16, wherein the conductor material (63) is structured as a common source of a NAND circuit.

Images