Battery management system and electronic device

Abstract

A battery management system characterized by comprising: a master control module; a variety of selection modules; and N slave control modules; each slave control module comprising an input unit, an output unit, and a communication unit; the input unit of a first slave control module of the N slave control modules is coupled to the master control module to receive an addressing enable signal sent by the master control module; the input unit of an m-th slave control module of the N slave control modules is coupled to the output unit of an (m-1)-th slave control module of the N slave control modules and the master control module via a corresponding selection module to receive an addressing enable signal sent by the (m-1)-th slave control module or the master control module via the selection module; the communication units of the N slave control modules are each coupled to the master control module 10; where N and m are integers; N ≥ 2, and 2 ≤ m ≤ N.

Description

Technical field

[0001] The present application relates to the technical field of energy storage, and in particular to a battery management system and an electronic device. State of the art

[0002] A battery management system (BMS) is mainly used to monitor parameter information (temperature, voltage, current, state of charge, etc.) of energy storage devices and to manage and control the status of the energy storage devices.

[0003] Since energy storage devices generally include multiple battery clusters, and each battery cluster includes multiple cells, a plurality of slave controllers are generally used to monitor the plurality of battery clusters, respectively, to realize voltage and temperature detection and equalization control functions for individual battery clusters. Then, a master controller is used for overall control, which is responsible for collecting and processing the signals collected by each slave controller and estimating battery status according to the collected signals to implement charge and discharge control and logical operations for each battery cluster.

[0004] When there are many slave controllers, the master controller needs to address the slave controllers to facilitate the management of the slave controllers. Therefore, efficient addressing of the slave controllers has become an urgent problem that needs to be solved. Contents of this application

[0005] To solve the above problem, the present application provides a battery management system and an electronic device that can improve the efficiency of addressing slave modules.

[0006] In a first aspect, the present application discloses a battery management system comprising: a master control module; a plurality of selection modules; and N slave control modules; wherein each slave control module comprises an input unit, an output unit, and a communication unit; the input unit of a first slave control module of the N slave control modules is coupled to the master control module to receive an addressing enable signal sent by the master control module; the input unit of an m-th slave control module of the N slave control modules is coupled to the output unit of an (m-1)-th slave control module of the N slave control modules and the master control module via a corresponding selection module to receive an addressing enable signal sent by the (m-1)-th slave control module or the master control module via the selection module; the communication units of the N slave control modules are each coupled to the master control module 10;where N and m are integers; N ≥ 2, and 2 ≤ m ≤ N.;

[0007] In some embodiments, a first input port of the selection module is coupled to the output unit of the (m-1)th slave control module, a second input port of the selection module is coupled to the master control module, an output port of the selection module is coupled to the input unit of the mth slave control module, and a control port of the selection module is coupled to the master control module to receive an addressing mode signal sent by the master control module; wherein the selection module is configured to enable a connection between the output unit of the (m-1)th slave control module and the input unit of the mth slave control module in accordance with the addressing mode signal in order to perform automatic addressing of the slave control modules;or enables a connection between the master control module and the input unit of the mth slave control module to perform manual addressing of the mth slave control module.;

[0008] In some embodiments, the selection module comprises: a first logical AND gate, wherein a first input terminal of the first logical AND gate serves as the first input terminal of the selection module; a second logical AND gate, wherein a first input terminal of the second logical AND gate serves as the second input terminal of the selection module, and a second input terminal of the second logical AND gate serves as the control terminal of the selection module; a logical NOT gate, wherein an input terminal of the logical NOT gate is coupled to the second input terminal of the second logical AND gate, and an output terminal of the logical NOT gate is coupled to a second input terminal of the first logical AND gate;and a logical OR gate, wherein a first input terminal of the logical OR gate is coupled to an output terminal of the first logical AND gate, a second input terminal of the logical OR gate is coupled to an output terminal of the second logical AND gate, and an output terminal of the logical OR gate serves as the output terminal of the selection module.;

[0009] In some embodiments, each slave control module further comprises a control unit coupled to each of the input unit, the output unit, and the communication unit of the slave control module; wherein the control unit is configured to receive the addressing enable signal via the input unit, receive addressing data via the communication unit, and transmit the addressing enable signal via the output unit.

[0010] In some embodiments, the input unit comprises: a first switch, wherein a first terminal of the first switch is configured to receive a drive signal, and a second terminal of the first switch is coupled to the selection module to output the addressing enable signal to the selection module; and a second switch, wherein a first terminal of the second switch is coupled to a control terminal of the first switch, a second terminal of the second switch is grounded, and a control terminal of the second switch is coupled to the control unit to receive an enable control signal from the control unit.

[0011] In some embodiments, the output unit further comprises: a first resistor, wherein a first terminal of the first resistor is configured to input the drive signal, and a second terminal of the first resistor is coupled to the first terminal of the first switch; a second resistor, wherein a first terminal of the second resistor is coupled to the first terminal of the first resistor, and a second terminal of the second resistor is coupled to the control terminal of the first switch; a third resistor, wherein a first terminal of the third resistor is coupled to the control terminal of the first switch, and a second terminal of the third resistor is coupled to the first terminal of the second switch;a fourth resistor, wherein a first terminal of the fourth resistor is coupled to the control unit and configured to receive the enable control signal, and a second terminal of the fourth resistor is coupled to the control terminal of the second switch; and a fifth resistor, wherein a first terminal of the fifth resistor is coupled to the control terminal of the second switch, and a second terminal of the fifth resistor is grounded.

[0012] In some embodiments, the output unit further comprises: a sixth resistor, wherein a first terminal of the sixth resistor is coupled to the second terminal of the first switch, and a second terminal of the sixth resistor is grounded; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the second terminal of the first switch, and a second terminal of the first capacitor is grounded.

[0013] In some embodiments, the input unit comprises: a seventh resistor, wherein a first terminal of the seventh resistor is configured to input a power supply voltage signal; and a third switch, wherein a first terminal of the third switch is coupled to the second terminal of the seventh resistor and the control unit to output an addressing trigger signal, a second terminal of the third switch is grounded, and a control terminal of the third switch is coupled to the selection module to receive the addressing enable signal.

[0014] In some embodiments, the input unit further comprises: an eighth resistor, wherein a first terminal of the eighth resistor is coupled to the control terminal of the third switch, and a second terminal of the eighth resistor is coupled to the selection module to receive the addressing enable signal; a ninth resistor, wherein a first terminal of the ninth resistor is coupled to the control terminal of the third switch, and a second terminal of the ninth resistor is grounded; a second capacitor, wherein a first terminal of the second capacitor is coupled to the second terminal of the eighth resistor, and a second terminal of the second capacitor is grounded; and a third capacitor, wherein a first terminal of the third capacitor is coupled to the first terminal of the third switch, and a second terminal of the third capacitor is grounded.

[0015] In a second aspect, the present application discloses an electronic device comprising the battery management system.

[0016] The battery management system provided in the embodiment includes a master control module, a plurality of selection modules, and N slave control modules. The slave control module includes an input unit, an output unit, and a communication unit. The input unit of the first slave control module of the N slave control modules is coupled to the master control module to receive the addressing enable signal from the master control module. The input unit of the mth slave control module is coupled to the output unit of the (m-1)th slave control module and the master control module via one of the selection modules to receive the addressing enable signal from the (m-1)th slave control module or the master control module via the selection module. The communication units of the N slave control modules are each coupled to the master control module. Where N and m are integers, N ≥ 2, 2 ≤ m ≤ N.By providing selection modules, the described approach allows different addressing modes to be freely switched among the multiple slave control modules, i.e., automatic or manual addressing can be implemented. On the one hand, the different addressing modes are beneficial for the functionality of the battery management system; on the other hand, the selection can be made according to the application scenario. For example, if one of the slave control modules fails, the slave control module can be addressed independently without having to address all slave control modules sequentially, which improves the addressing efficiency of the slave control modules. Short description of the drawing

[0017] In order to more clearly illustrate the technical solution in the embodiments of the present application, a brief description of the drawings required for describing the embodiments is given below. Of course, the drawings described below are only some embodiments for the present application, and other drawings can be made based on these drawings by a person skilled in the art without requiring any creative work. Fig. 1 is a schematic structural diagram of a battery management system provided in the present application. Fig. 2 is a schematic structural diagram of a slave control module 20 provided in the present application. Fig. 3 is a schematic structural diagram of a selection module 30 provided in the present application. Fig.4 is a flowchart of an addressing method for the battery management system provided in the present application. Fig. 5 is a schematic structural diagram of an output unit 22 provided in the present application. Fig. 6 is a schematic structural diagram of an input unit 21 provided in the present application. Fig. 7 is a schematic structural diagram of an electronic device provided in the present application. Detailed description of the embodiments

[0018] In the following, the technical solution of the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present application. Of course, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments of the present application, all other embodiments obtained by a person skilled in the art without creative effort fall within the scope of the present application.

[0019] In describing the present application, it should be noted that the orientation or positional relationship indicated by terms such as "center," "top," "bottom," "left," "right," "vertical," "horizontal," "inside," and "outside" is based on the orientation or positional relationship shown in the accompanying drawings and is provided for the convenience of describing the present application and simplifying the description, and is not intended to indicate or imply that the device or element in question must have a particular orientation. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or that the number of technical features specified is limited to the number specified.Accordingly, features labeled "first" or "second" may explicitly or implicitly include one or more of the recited features. In the description of the present application, "multiple" means two or more, unless expressly and specifically limited.

[0020] “A and / or B” includes the following three combinations: A only, B only, and A and B together.

[0021] The use of the terms "apply to" or "configured for" in this application is intended to imply open and inclusive language that does not exclude devices that apply to or are configured to perform additional tasks or steps. Furthermore, the use of the term "based on" is intended to be open and inclusive, since processes, steps, calculations, or other acts "based on" one or more of the specified conditions or values ​​may, in practice, be based on additional conditions or exceed the specified values.

[0022] In the present application, the word "illustrative" is used to indicate that it is used "by way of example, illustration, or explanation." Any embodiment described as "illustrative" in the present application is not necessarily to be construed as preferred or more advantageous than other embodiments. The following description is provided so that the present application can be made and used by any person skilled in the art. In the following description, details are set forth for purposes of explanation. It should be understood that one skilled in the art can recognize that the present application may be practiced without using these specific details. In other instances, well-known structures and methods are not described in detail in order not to obscure the description of the present application with unnecessary detail.Therefore, the present application is not intended to be limited to the embodiments shown, but is to be accorded the broadest scope consistent with the principles and features disclosed in the present application.

[0023] With reference to the Fig. 1 and Fig. 2 is Fig. 1 is a schematic structural diagram of a battery management system provided in the present application. The battery management system 100 includes a master control module 10, a plurality of slave control modules 20, and a plurality of selection modules 30. Fig. 2 is a schematic structural diagram of a slave control module 20 provided in the present application.

[0024] The master control module 10 may be a second battery management unit (SBMU), and the slave control module 20 may be a voltage control management unit (VCMU).

[0025] The slave control module 20 includes an input unit 21, an output unit 22, and a communication unit 23. In the embodiment, the number of slave control modules 20 is N, where N is an integer, and the N slave control modules 20 are connected in series. The input unit 21 of the first slave control module 20 of the N slave control modules 20 is coupled to the master control module 10, the input unit 21 of the m-th slave control module 20 is coupled to the output unit 22 of the (m-1)th slave control module 20 and the master control module 10 via a corresponding selection module 30, and the communication units 23 of the N slave control modules 20 are each coupled to the master control module 10. It is understood that the first slave control module 20 is the first in the connection order among the N slave control modules 20. Where m is an integer, N ≥ 2, 2 ≤m≤N.

[0026] The input unit 21 of the first slave control module 20 is configured to receive an addressing enable signal sent from the master control module 10. The input unit 22 of the m-th slave control module 20 is configured to receive an addressing enable signal sent from the output unit 22 of the (m-1)th slave control module 20 via a corresponding selection module 30, or to receive an addressing enable signal sent from the master control module 10 via the corresponding selection module 30. The selection module 30, which is coupled between the m-th slave control module 20 and the (m-1)th slave control module 20, is configured to enable a connection between the m-th slave control module 20 and the (m-1)th slave control module 20 or a connection between the m-th slave control module 20 and the master control module 10.

[0027] In the embodiment of the present application, there are two types of addressing modes: automatic addressing mode and manual addressing mode. The selection of the automatic addressing mode and the manual addressing mode is determined by the master control module 10, which controls the selection module 30 to enable different paths. Specifically, when the master control module 10 controls the selection module 30 to enable the connection between the (m-1)th slave control module 20 and the mth slave control module 20, the N slave control modules 20 are sequentially coupled, thereby achieving automatic addressing of the N slave control modules 20 in sequence. When the master control module 10 controls the selection module 30 to enable the connection between the master control module 10 and the slave control module 20, manual addressing of the slave control module 20 is achieved.

[0028] In the automatic addressing mode, the master control module 10 sends the addressing enable signal to the first slave control module 20, and the first slave control module 20 enters an addressing state after receiving the addressing enable signal via the input unit 21. In the addressing state, the first slave control module 20 receives addressing data (e.g., an addressing message) sent from the master control module 10 via the communication unit 23. After completing addressing based on the addressing data, the first slave control module 20 sends an addressing enable signal to the input unit 21 of the second slave control module 20 via the output unit 22. The addressing method of each subsequent slave control module 20 is the same as that of the first slave control module 20 and will not be repeated here.

[0029] In the embodiment, the slave control module 20 further comprises a control unit 24 coupled to the input unit 21, the output unit 22, and the communication unit 23, respectively. The control unit 24 is configured to receive the addressing enable signal via the input unit 21, receive the addressing data via the communication unit 23, and transmit the addressing enable signal via the output unit 22.

[0030] Optionally, the selection module 30 can be implemented by a selector switch with a "choose one of two" function, which can be a circuit formed by a combination of multiplexer circuits (MUX), metal-oxide-semiconductor field-effect transistors (MOS transistors), etc. A first input terminal of the selection module 30 is coupled to the output unit 22 of the (m-1)th slave control module 20, a second input terminal of the selection module 30 is coupled to the master control module 10, an output terminal of the selection module 30 is coupled to the input unit 21 of the mth slave control module 20, and a control terminal of the selection module 30 is coupled to the master control module 10 to receive an addressing mode signal sent from the master control module.The selection module 30 is configured to enable, according to the addressing mode signal, the connection between the output unit 22 of the (m-1)th slave control module 20 and the input unit 21 of the mth slave control module 20 to perform automatic addressing of the slave control modules 20; or to enable the connection between the master control module 10 and the input unit 21 of the mth slave control module 20 to perform manual addressing of the mth slave control module 20.In particular, the selection module 30 is configured to enable the connection between the output unit 22 of the (m-1)th slave control module 20 and the input unit 21 of the mth slave control module 20 when the addressing mode signal is at a first level to perform automatic addressing of the slave control modules 20; and to enable the connection between the master control module 10 and the input unit 21 of the mth slave control module 20 when the addressing mode signal is at a second level to perform manual addressing of the mth slave control module 20. For example, the first level is a high level while the second level is a low level; or the first level is a low level while the second level is a high level.

[0031] As in Fig. 3, is Fig.3 is a schematic structural diagram of a selection module 30 provided in the present application. The selection module 30 includes a first logical AND gate AND1, a second logical AND gate AND2, a logical NOT gate NO, and a logical OR gate OR. A first input terminal of the first logical AND gate AND1 serves as the first input terminal of the selection module 30, a first input terminal of the second logical AND gate AND2 serves as the second input terminal of the selection module 30, and a second input terminal of the second logical AND gate AND2 serves as the control terminal of the selection module 30. An input terminal of the logical NOT gate NO is coupled to the second input terminal of the second logical AND gate AND2, and an output terminal of the logical NOT gate NO is coupled to a second input terminal of the first logical AND gate AND1.A first input terminal of the logical OR gate OR is coupled to an output terminal of the first logical AND gate AND1, a second input terminal of the logical OR gate OR is coupled to an output terminal of the second logical AND gate AND2, and an output terminal of the logical OR gate OR serves as an output terminal of the selection module 30.

[0032] Below is a truth table for the selection module 30. First input port X Second input terminal Y Control connection SEL Output connection EN 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

[0033] According to the Fig. 3 and the above truth table, the following formula can be obtained. EN=X⋅SEL+Y⋅SEL¯

[0034] That is, when the addressing mode signal received by the control terminal is at the first level (low level "0"), the addressing enable signal output from the output terminal is the addressing enable signal received by the first input terminal; while when the addressing mode signal received by the control terminal is at the second level (high level "1"), the addressing enable signal output from the output terminal is the addressing enable signal received by the second input terminal.

[0035] An addressing process of the slave control module 20 is described below with reference to the Fig. 1 to 4 presented. Fig. 4 is a flowchart of an addressing method for the battery management system provided in the present application.

[0036] (1) After the battery management system is powered on, output signals from the master control module 10 and the output units 22 of the slave control modules 20 are initialized to a low level "0", and each slave control module 20 enters a sleep state by default. After power-on and initialization, the master control module 10 sends a verification broadcast frame (e.g., FlowControlReq=0xAA in 0x0801FF00) to each slave control module 20 according to a specified period of time (e.g., 50 ms). Each slave control module 20 reads internal parameters (e.g., an existing address of the slave control module 20) and performs verification calculations (e.g., CRC8 calculations) after receiving the verification broadcast frame. A polynomial generated according to the CRC8 standard is x^8+x^5+x^4+1, that is, the polynomial is used to perform correlation calculations with the internal parameters and obtain a verification result (e.g., a CRC result).

[0037] (2) After calculating the verification result, each slave control module 20 sends a frame containing the verification result (e.g., a CRC verification result: CfgResp_Type = 1, CfgResp_Crc = CRC8 in 0x1827FExx) back to the master control module 10 within a specified period of time (e.g., 50 ms). The master control module 10 then sequentially verifies the verification result returned by each slave control module 20 with internally calculated verification results. In one embodiment, the master control module 10 and the slave control modules 20 use the same verification algorithm; for example, both use the CRC8 verification algorithm.

[0038] (3) After the master control module 10 verifies that each slave control module 20 has successfully verified the verification, the master control module 10 periodically sends a system operation request broadcast frame (e.g., FlowControlReq = 0x55 in 0x0801FF00, continuously send for 2 seconds, and then stop sending the frame), and the system enters the normal operating state. If the master control module 10 detects that one of the slave control modules 20 has failed the verification, it considers that the slave control module 20 needs to be re-addressed, and then starts the addressing process and stops the verification request (e.g., stops sending the 0x0801FF00 message).

[0039] When automatic addressing is required, the master control module 10 sends the addressing mode signal, which is at the first level, to the control terminal of each selection module 30. The selection module 30 activates a connection path between the output unit 22 of the (m-1)th slave control module 20 and the input unit 21 of the mth slave control module 20, and the slave control modules 20 enter the automatic addressing process of the following steps (4)-(7).

[0040] (4) After entering the automatic addressing process, the master control module 10 outputs a high-level addressing enable signal to the input unit 21 of the first slave control module 20 coupled to the master control module 10 and sends addressing data (e.g., a configuration message) to the communication unit 23 of the first slave control module 20 via a communication link. After the first slave control module 20 coupled to the master control module 10 detects the high-level addressing enable signal via the input unit 21, it enters the standby state. When the first slave control module 20 receives the configuration message from the master control module 10, it stores configuration parameters in an internal memory (e.g.,an EE memory) and sends back a configuration completion flag (CfgResp_Type=2) to the master control module 10 via the communication unit 23 and simultaneously outputs the addressing enable signal at high level to the second slave control module 20 via the output unit 22, then the configuration of the first slave control module 20 is completed, ie, the addressing of the first slave control module 20 is completed.

[0041] (5) After receiving the configuration completion flag from the first slave control module 20, the master control module 10 sends addressing data (e.g., a configuration message) to the communication unit 23 of the second slave control module 20. Similar to the configuration process of the first slave control module 20, the second slave control module 20 receives the configuration parameters and stores the configuration parameters in an internal memory. At the same time, it returns a configuration completion flag (CfgResp_Type=2) to the master control module 10 and outputs the addressing enable signal at a high level to the third slave control module 20 via the output unit 22.

[0042] (6) The configurations of the subsequent slave control modules 20 are then carried out according to the configuration process described above.

[0043] (7) When the master control module 10 receives the configuration completion flag (CfgResp_Type=2) from the last slave control module 20, the master control module 10 sends a system operation request broadcast frame (FlowControl Req = 0x55) for a preset period of time (e.g., 2 seconds), then stops sending this message and turns off the addressing enable signal output by the master control module 10 to high level. After receiving the system operation request broadcast frame from the master control module 10, the slave control modules 20 turn off the addressing enable signal output by the output unit 22 of the slave control modules 20 to high level, transition from the idle state to the running state, and then send and receive communication messages normally.

[0044] When manual addressing is required, the master control module 10 sends the second-level addressing mode signal to the control terminal of the selector module 30 corresponding to the slave control module 20 that requires manual addressing. The selector module 30 then activates a connection path between the master control module 10 and the input unit 21 of the slave control module 20, and the slave control module 20 enters the following manual addressing process:

[0045] The slave control module 20 receives the configuration message from the master control module 10, stores configuration parameters in an internal memory (e.g., an EE memory), and sends a configuration completion flag (CfgResp_Type=2) back to the master control module 10 via the communication unit 23. This completes the configuration of the slave control module 20.

[0046] The addressing process described above can remotely handle various system exceptions as follows.

[0047] (1) The master control module 10 sends the verification broadcast frame to each slave control module 20 and waits for each slave control module 20 to return its calculated CRC result. If, after waiting 5 seconds, all CRC results from the slave control modules 20 have not been received, or if the verification of a returned CRC result fails, the master control module 10 directly proceeds to the automatic addressing process.

[0048] (2) After starting the automatic addressing process, the master control module 10 sends a configuration message (0x0823FF00 and 0x0824FF00) to the slave control modules 20 and waits for the slave control modules 20 to return the configuration completion flags. If a timeout occurs (e.g., 500 ms), the master control module 10 records the number of configuration errors as 1 and resends the configuration message to the slave control modules 20. If the cumulative number of configuration errors exceeds five times, the automatic addressing process is terminated and the configuration fails. The slave control module 20 reports an addressing error of the slave control modules 20 to the master control module 10, and the master control module 10 stores an internal error code.

[0049] (3) The slave control module 20 is powered on and initialized. If the slave control module 20 does not receive the verification broadcast frame from the master control module 10 after a preset period (e.g., 2 seconds), the slave control module 20 reports a configuration addressing error of the slave control module 20 to the master control module 10 and stores an internal error code. The slave control module 20 then automatically enters the operating state and starts up, after which it transmits initial operating data.

[0050] (4) The slave control module 20 enters the standby state. If all configuration messages sent from the master control module 10 are not received after a preset period (e.g., 2 seconds), or if the configuration messages are received but cannot be correctly stored in the EE memory, the slave control module 20 reports an addressing error of the slave control module 20 to the master control module 10 and stores an internal error code. The slave control module 20 then automatically enters the operating state and starts up, after which it sends initial operating data.

[0051] (5) After completing the writing process of the parameter configuration sent by the master control module 10, if a current broadcast frame (0x55) sent by the master control module 10 is still not received after a preset period (e.g., 5 seconds), the slave control module 20 will report an addressing error of the slave control module 20 to the master control module 10 and store an internal error code. The slave control module 20 will then automatically enter the operating state and start up. It will then transmit the initial operating data.

[0052] (6) After entering the operating state, if the system receives a forced automatic addressing instruction from a host computer, it first determines whether the charging and discharging current is below a preset value (e.g., 0.1C) and no charging connection is established. If so, the system returns to the automatic addressing process. The master control module 10 first returns to an automatic configuration stage and sends an instruction to each slave control module 20 to return to the standby state. After receiving the instruction, the slave control module 20 enters the standby state, and the system then performs automatic addressing again.

[0053] The input unit 21 and the output unit 22 are presented below.

[0054] As in Fig. 5 shown, is Fig.5 is a schematic structural diagram of an output unit 22 provided in the present application. The output unit 22 includes a first switch Q1 and a second switch Q2.

[0055] A first terminal of the first switch Q1 is configured to receive a drive signal, and a second terminal of the first switch Q1 is coupled to the selection module 30 to output the addressing enable signal to the selection module 30. A first terminal of the second switch Q2 is coupled to a control terminal of the first switch Q1, a second terminal of the second switch Q2 is grounded, and a control terminal of the second switch Q2 is coupled to the control unit 24 to receive an enable control signal from the control unit 24.

[0056] Optionally, in one embodiment, the output unit 22 further comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first capacitor C1.

[0057] The first terminal of the first resistor R1 is configured to input the drive signal, and the second terminal of the first resistor R1 is coupled to the first terminal of the first switch Q1. The first terminal of the second resistor R2 is coupled to the first terminal of the first resistor R1, and the second terminal of the second resistor R2 is coupled to the control terminal of the first switch Q1. The first terminal of the third resistor R3 is coupled to the control terminal of the first switch Q1, and the second terminal of the third resistor R3 is coupled to the first terminal of the second switch Q2. The first terminal of the fourth resistor R4 is coupled to the control unit 24 and configured to receive the enable control signal, and the second terminal of the fourth resistor R4 is coupled to the control terminal of the second switch Q4.The first terminal of the fifth resistor R5 is coupled to the control terminal of the second switch Q2, and the second terminal of the fifth resistor R5 is grounded. The first terminal of the sixth resistor R6 is coupled to the second terminal of the first switch Q1, and the second terminal of the sixth resistor R6 is grounded. The first terminal of the first capacitor C1 is coupled to the second terminal of the first switch Q1, and the second terminal of the first capacitor C1 is grounded.

[0058] In one embodiment, the first switch Q1 is a PNP transistor. Accordingly, in the first switch Q1, the first terminal is the emitter, the second terminal is the collector, and the control terminal is the base. The second switch Q2 is an NPN transistor. Accordingly, in the second switch Q2, the first terminal is the collector, the second terminal is the emitter, and the control terminal is the base.

[0059] After the slave control module 20 completes addressing, the control unit 24 of the slave control module 20 outputs a high-level enable control signal to the control terminal of the second switch Q2 to turn on the second switch Q2, thereby lowering the base level of the first switch Q1 to a low level, thereby turning on the first switch Q1, and outputting the drive signal as a high-level addressing enable signal to the next slave control module 20. In the embodiment, the drive signal is a high-level addressing enable signal received by the input unit 21 of the slave control module 20 from a previous slave control module 20 or the master control module 10.

[0060] In other embodiments, the first switch Q1 and the second switch Q2 may be replaced by other switches with similar functions, such as MOS transistors of corresponding models. In particular, the first switch Q1 may be a PMOS transistor and the second switch Q2 may be an NMOS transistor.

[0061] As in Fig. 6 shown, is Fig. 6 is a schematic structural diagram of an input unit 21 provided in the present application. The input unit 21 includes a seventh resistor R7 and a third switch Q3.

[0062] The first terminal of the seventh resistor R7 is configured to input a power supply voltage signal; the first terminal of the third switch Q3 is coupled to the second terminal of the seventh resistor R7 and the control unit 24 to output an addressing trigger signal, the second terminal of the third switch Q3 is grounded, and the control terminal of the third switch Q3 is coupled to the selection module 30 to receive the addressing enable signal.

[0063] Optionally, in one embodiment, the input unit 21 further comprises an eighth resistor R8, a ninth resistor R9, a second capacitor C2, and a third capacitor C3.

[0064] The first terminal of the eighth resistor R8 is coupled to the control terminal of the third switch Q3, and the second terminal of the eighth resistor R8 is coupled to the selection module 30 to receive the addressing enable signal. The first terminal of the ninth resistor R9 is coupled to the control terminal of the third switch Q3, and the second terminal of the ninth resistor R9 is grounded; the first terminal of the second capacitor C2 is coupled to the second terminal of the eighth resistor R8, and the second terminal of the second capacitor C2 is grounded; the first terminal of the third capacitor C3 is coupled to the first terminal of the third switch Q3, and the second terminal of the third capacitor C3 is grounded.

[0065] In one embodiment, the third switch Q3 is an NPN transistor. Accordingly, in the third switch Q3, the first terminal is the collector, the second terminal is the emitter, and the control terminal is the base.

[0066] When the addressing enable signal that the slave control module 20 receives from a previous slave control module 20 or the master control module 10 is at a high level, the third switch Q3 is turned on to lower the addressing trigger signal to a low level, and the control unit 24 is triggered to enter the standby state.

[0067] In other embodiments, the third switch Q3 may be replaced by other switches with similar functions, such as MOS transistors of corresponding models. In particular, the third switch Q3 may be an NMOS transistor.

[0068] The battery management system provided in the embodiment includes a master control module, a plurality of selection modules, and N slave control modules. The slave control module includes an input unit, an output unit, and a communication unit. The input unit of the first slave control module of the N slave control modules is coupled to the master control module to receive the addressing enable signal from the master control module. The input unit of the mth slave control module is coupled to the output unit of the (m-1)th slave control module and the master control module via one of the selection modules to receive the addressing enable signal from the (m-1)th slave control module or the master control module via the selection module. The communication units of the N slave control modules are each coupled to the master control module. Where N and m are integers, N ≥ 2, 2 ≤ m ≤ N.Through the described approach, by providing selection modules among the multiple slave control modules, different addressing modes can be freely switched, i.e., automatic or manual addressing can be implemented. On the one hand, the different addressing modes are beneficial for the functionality of the battery management system (BMS), and on the other hand, the selection can be made according to the application scenario. For example, if one of the slave control modules fails, the slave control module can be addressed independently without having to address all slave control modules sequentially, which improves the addressing efficiency of the slave control modules.

[0069] In relation to Fig. 7 is Fig. 7 is a schematic structural diagram of an electronic device provided in the present application.

[0070] It is understood that the electronic device 700 may be a new energy vehicle or a hybrid vehicle or other electronic devices.

[0071] The above contains a detailed description of the display screen provided in the embodiments of the present application. This document uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the methods and core ideas of the present application. At the same time, those skilled in the art will understand changes in specific embodiments and the scope of application based on the ideas of the present application. In summary, the content of this description should not be construed as limiting the present application.

Claims

[1] A battery management system characterized by comprising: a master control module; a variety of selection modules; and N slave control modules; each slave control module comprising an input unit, an output unit, and a communication unit; the input unit of a first slave control module of the N slave control modules is coupled to the master control module to receive an addressing enable signal sent by the master control module; the input unit of an m-th slave control module of the N slave control modules is coupled to the output unit of an (m-1)-th slave control module of the N slave control modules and the master control module via a corresponding selection module to receive an addressing enable signal sent by the (m-1)-th slave control module or the master control module via the selection module; the communication units of the N slave control modules are each coupled to the master control module 10; where N and m are integers; N ≥ 2, and 2 ≤ m ≤ N. [2] The battery management system according to claim 1, wherein a first input terminal of the selection module is coupled to the output unit of the (m-1)th slave control module, a second input terminal of the selection module is coupled to the master control module, an output terminal of the selection module is coupled to the input unit of the m-th slave control module, and a control terminal of the selection module is coupled to the master control module to receive an addressing mode signal sent from the master control module; wherein the selection module is configured to enable a connection between the output unit of the (m-1)th slave control module and the input unit of the m-th slave control module in accordance with the addressing mode signal in order to perform automatic addressing of the slave control modules;or enables a connection between the master control module and the input unit of the mth slave control module to perform manual addressing of the mth slave control module.; [3] Battery management system according to claim 2, wherein the selection module comprises: a first logical AND gate, wherein a first input terminal of the first logical AND gate serves as the first input terminal of the selection module; a second logical AND gate, wherein a first input terminal of the second logical AND gate serves as the second input terminal of the selection module, and a second input terminal of the second logical AND gate serves as the control terminal of the selection module; a logical NOT gate, wherein an input terminal of the logical NOT gate is coupled to the second input terminal of the second logical AND gate, and an output terminal of the logical NOT gate is coupled to a second input terminal of the first logical AND gate; and a logical OR gate, wherein a first input terminal of the logical OR gate is coupled to an output terminal of the first logical AND gate, a second input terminal of the logical OR gate is coupled to an output terminal of the second logical AND gate, and an output terminal of the logical OR gate serves as the output terminal of the selection module. [4] The battery management system of claim 1, wherein each slave control module further comprises a control unit coupled to each of the input unit, the output unit, and the communication unit of the slave control module; the control unit is configured to receive the addressing enable signal via the input unit, receive addressing data via the communication unit, and send the addressing enable signal via the output unit. [5] Battery management system according to claim 4, wherein the input unit comprises: a first switch, wherein a first terminal of the first switch is configured to receive a drive signal, and a second terminal of the first switch is coupled to the selection module to output the addressing enable signal to the selection module; and a second switch, wherein a first terminal of the second switch is coupled to a control terminal of the first switch, a second terminal of the second switch is grounded, and a control terminal of the second switch is coupled to the control unit to receive an enable control signal from the control unit. [6] The battery management system of claim 5, wherein the output unit further comprises: a first resistor, wherein a first terminal of the first resistor is configured to input the drive signal and a second terminal of the first resistor is coupled to the first terminal of the first switch; a second resistor, wherein a first terminal of the second resistor is coupled to the first terminal of the first resistor, and a second terminal of the second resistor is coupled to the control terminal of the first switch; a third resistor, wherein a first terminal of the third resistor is coupled to the control terminal of the first switch, and a second terminal of the third resistor is coupled to the first terminal of the second switch; a fourth resistor, wherein a first terminal of the fourth resistor is coupled to the control unit and configured to receive the enable control signal, and a second terminal of the fourth resistor is coupled to the control terminal of the second switch; and a fifth resistor, wherein a first terminal of the fifth resistor is coupled to the control terminal of the second switch, and a second terminal of the fifth resistor is grounded. [7] The battery management system of claim 5, wherein the output unit further comprises: a sixth resistor, wherein a first terminal of the sixth resistor is coupled to the second terminal of the first switch, and a second terminal of the sixth resistor is grounded; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the second terminal of the first switch, and a second terminal of the first capacitor is grounded. [8] Battery management system according to claim 4, wherein the input unit comprises: a seventh resistor, wherein a first terminal of the seventh resistor is configured to input a power supply voltage signal; and a third switch, wherein a first terminal of the third switch is coupled to the second terminal of the seventh resistor and the control unit to output an addressing trigger signal, a second terminal of the third switch is grounded, and a control terminal of the third switch is coupled to the selection module to receive the addressing enable signal. [9] Battery management system according to claim 8, wherein the input unit further comprises: an eighth resistor, wherein a first terminal of the eighth resistor is coupled to the control terminal of the third switch, and a second terminal of the eighth resistor is coupled to the selection module to receive the addressing enable signal; a ninth resistor, wherein a first terminal of the ninth resistor is coupled to the control terminal of the third switch, and a second terminal of the ninth resistor is grounded; a second capacitor, wherein a first terminal of the second capacitor is coupled to the second terminal of the eighth resistor, and a second terminal of the second capacitor is grounded; and a third capacitor, wherein a first terminal of the third capacitor is coupled to the first terminal of the third switch, and a second terminal of the third capacitor is grounded. [10] An electronic device comprising the battery management system according to any one of claims 1 to 9.

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