oscilloscope

Abstract

Oscilloscope having N sampling channels, the oscilloscope comprising: a first data processing unit configured to send a first synchronization signal to a first multiple output unit; the first multiple output unit configured to output one strand of a second synchronization signal to each of the N sampling channels based on the first synchronization signal, where N is an integer greater than or equal to 2;an analog-to-digital converter unit and a second data processing unit, each corresponding to one of the N sampling channels, wherein the analog-to-digital converter unit is configured to perform a signal sampling to determine first sample data and synchronizes a transmission of the first sample data to the second data processing unit of the respective sampling channel based on the second synchronization signal, wherein the second data processing unit is configured to process the received first sample data and send the second sample data obtained from the processing of the first sample data to the first data processing unit.

Description

Oscilloscope

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2024104822136, filed on April 22, 2024, entitled "Bandwidth Limiting Circuit and Front-End Circuit", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of signal measurement, and in particular to an oscilloscope. Background Technology

[0004] A digital oscilloscope typically consists of a front-end analog circuit, an analog-to-digital converter (ADC), a data processing unit, and a control processor. The data processing unit is often implemented using a field-programmable gate array (FPGA).

[0005] With the development of digital oscilloscopes, bandwidth and sampling rates are increasing, and the number of acquisition channels is also increasing. High-bandwidth, high-sampling-rate oscilloscopes often require the use of real-time digital filters to process data in real time. These are all implemented by FPGAs, which increases the demand for FPGA resources (such as pin resources and logic resources) within the oscilloscope. It is becoming increasingly impossible to use a single FPGA to process data from all ADCs and sampling channels within an oscilloscope.

[0006] Summary of the Invention

[0007] This disclosure provides an oscilloscope.

[0008] According to a first aspect of the present disclosure, an oscilloscope is provided, characterized in that the oscilloscope has N sampling channels, and the oscilloscope includes:

[0009] The first data processing unit is configured to send a first synchronization signal to the first multiple output unit;

[0010] The first multi-output unit is configured to output a second synchronization signal to each of the N sampling channels according to the first synchronization signal, wherein N is an integer greater than or equal to 2;

[0011] The N sampling channels correspond to an analog-to-digital conversion unit and a second data processing unit, wherein the analog-to-digital conversion unit is configured to perform signal sampling to determine first sampling data, and synchronously transmit the first sampling data to the second data processing unit of the corresponding sampling channel according to the second synchronization signal; the second data processing unit is configured to process the received first sampling data, and send the second sampling data obtained from processing the first sampling data to the first data processing unit.

[0012] In some embodiments, the analog-to-digital conversion unit is specifically configured to synchronously transmit the start time of the first sampling data transmission to the second data processing unit of the corresponding sampling channel according to the second synchronization signal.

[0013] In some embodiments, the oscilloscope further includes:

[0014] A reference clock unit is configured to send a first reference clock signal to the first multiple output unit;

[0015] The first multi-output unit is configured to output a first synchronization clock signal to the analog-to-digital conversion units corresponding to the N sampling channels respectively, based on the first reference clock.

[0016] The analog-to-digital conversion unit is further configured to synchronize the sampling frequency of the signal sampling according to the first synchronization clock signal.

[0017] In some embodiments, the first multiple output unit is further configured to synchronize the first synchronization signal using the first reference clock signal.

[0018] In some embodiments, the analog-to-digital conversion unit is further configured to output a second synchronous clock signal to the second data processing unit of the corresponding sampling channel according to the first synchronous clock signal;

[0019] The second data processing unit is further configured to synchronize the processing of the first sampled data according to the second synchronization clock signal.

[0020] In some embodiments, the oscilloscope further includes:

[0021] The second multi-output unit is configured to output a third synchronization signal to the second data processing unit corresponding to each of the N sampling channels and the first data processing unit respectively.

[0022] The third synchronization signal is configured to synchronize the frame clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit and the first data processing unit.

[0023] In some embodiments, the first data processing unit is configured to send a fourth synchronization signal to the second multiple output unit;

[0024] The second multi-output unit is specifically configured to output the third synchronization signal according to the fourth synchronization signal.

[0025] In some embodiments, the oscilloscope further includes:

[0026] The reference clock unit is configured to send a second reference clock signal to the second multiple output unit;

[0027] The second multi-output unit is configured to output a third synchronization clock signal to the second data processing unit and the first data processing unit corresponding to the N sampling channels respectively, according to the second reference clock;

[0028] The third synchronization clock signal is configured to synchronize the transmission clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit and the first data processing unit.

[0029] In some embodiments, the first data processing unit is further configured to output a fifth synchronization signal to the second data processing units corresponding to the N sampling channels respectively;

[0030] The second data processing unit is further configured to synchronously transmit the start time of the second sampling data to the first data processing unit according to the fifth synchronization signal.

[0031] In some embodiments, the oscilloscope further includes:

[0032] The third multi-output unit corresponding to each of the N sampling channels is configured to receive the second synchronization signal and output a sixth synchronization signal to the analog-to-digital conversion unit of the corresponding sampling channel according to the second synchronization signal.

[0033] The analog-to-digital conversion unit is configured to synchronously transmit the frame clock of the data frame corresponding to the first sampled data to the second data processing unit of the sampling channel according to the sixth synchronization signal.

[0034] In some embodiments, the oscilloscope further includes:

[0035] The reference clock unit is configured to send a third reference clock signal to the first multiple output unit;

[0036] The first multi-output unit is configured to output a fourth synchronization clock signal to the third multi-output units corresponding to the N sampling channels respectively, according to the third reference clock;

[0037] The third multi-output unit is further configured to output a fifth synchronous clock signal to the analog-to-digital conversion unit of the corresponding sampling channel according to the fourth synchronous clock signal;

[0038] The analog-to-digital conversion unit is configured to synchronously transmit the transmission clock of the data frame corresponding to the first sampled data to the second data processing unit of the sampling channel according to the fifth synchronization clock signal.

[0039] In some embodiments, the first multiple output unit is further configured to output a seventh synchronization signal to the first data processing unit based on the first synchronization signal;

[0040] The third multi-output unit is further configured to output an eighth synchronization signal to the second data processing unit of its respective sampling channel based on the second synchronization signal.

[0041] The seventh synchronization signal and the eighth synchronization signal are configured to synchronize the frame clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit and the first data processing unit.

[0042] In some embodiments, the oscilloscope further includes:

[0043] The third multi-output unit is further configured to output a sixth synchronous clock signal to the second data processing unit according to the fourth synchronous clock signal;

[0044] The first multi-output unit is configured to output a seventh synchronization clock signal to the first data processing unit according to the third reference clock;

[0045] The sixth synchronization clock signal and the seventh synchronization clock signal are configured to synchronize the transmission clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit and the first data processing unit.

[0046] In some embodiments, the first data processing unit is further configured to output a ninth synchronization signal to the second data processing units corresponding to the N sampling channels respectively;

[0047] The second data processing unit is further configured to synchronously transmit the start time of the second sampling data to the first data processing unit according to the ninth synchronization signal.

[0048] In some embodiments, the second data processing unit is further configured to output a tenth synchronization signal to the analog-to-digital conversion unit of the corresponding sampling channel according to the ninth synchronization signal;

[0049] The analog-to-digital conversion unit is further configured to synchronously transmit the start time of the first sampled data to the second data processing unit according to the tenth synchronization signal.

[0050] According to an embodiment of this disclosure, an oscilloscope includes: a first data processing unit configured to send a first synchronization signal to a first multi-output unit; the first multi-output unit configured to output a second synchronization signal to each of the N sampling channels according to the first synchronization signal, wherein N is an integer greater than or equal to 2; the N sampling channels respectively correspond to: an analog-to-digital conversion unit and a second data processing unit, wherein the analog-to-digital conversion unit is configured to perform signal sampling to determine first sampled data, and synchronously transmit the first sampled data to the second data processing unit of its respective sampling channel according to the second synchronization signal; the second data processing unit is configured to process the received first sampled data, and send the second sampled data obtained from processing the first sampled data to the first data processing unit. Thus, the oscilloscope converts the first synchronization signal into second synchronization signals output to different sampling channels through the first multi-output unit, and is configured to synchronize the start time of the first sampled data transmission by the analog-to-digital conversion unit, thereby achieving synchronization of the start time of the first sampled data transmission across multiple sampling channels, reducing the delay difference in data transmission between the oscilloscope channels, and improving the signal detection accuracy of the oscilloscope. Attached Figure Description

[0051] Figure 1 is a schematic diagram of an oscilloscope structure according to an exemplary embodiment;

[0052] Figure 2 is a schematic diagram of another oscilloscope configuration according to an exemplary embodiment;

[0053] Figure 3 is a schematic diagram of another oscilloscope structure according to an exemplary embodiment;

[0054] Figure 4 is a schematic diagram of another oscilloscope configuration according to an exemplary embodiment;

[0055] Figure 5 is a schematic diagram of another oscilloscope configuration according to an exemplary embodiment;

[0056] Figure 6 is a schematic diagram of another oscilloscope configuration according to an exemplary embodiment;

[0057] Figure 7 is a schematic diagram of another oscilloscope configuration according to an exemplary embodiment. Detailed Implementation

[0058] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0059] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0060] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0061] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this disclosure.

[0062] In this embodiment of the disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0063] In the embodiments disclosed herein, "multiple" refers to two or more.

[0064] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0065] In some embodiments, the notation "at least one of A and B", "A and / or B", "A in one case, B in another", "A in one case, B in another", etc., may include the following technical solutions depending on the situation: in some embodiments, A (A is executed regardless of B); in some embodiments, B (B is executed regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, A and B (both A and B are executed). The same applies when there are more branches such as A, B, C, etc.

[0066] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execution of A regardless of B); in some embodiments, B (execution of B regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, C, etc.

[0067] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects should be found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the value of the descriptive object is not limited by ordinal numbers and can be one or more. For example, in "first device," the value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0068] In some embodiments, “including A,” “containing A,” “for indicating A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0069] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably.

[0070] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0071] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0072] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0073] In some embodiments, each analog channel corresponds to a sampling system, and each sampling system includes an analog front-end, an ADC, a sampling clock, and an FPGA, which independently completes the sampling, storage, and necessary data processing of the channel. The processed data from the FPGAs of multiple channels are aggregated to the common FPGA of the oscilloscope for triggering, display, and other processing.

[0074] In oscilloscopes with multi-channel sampling systems, synchronization between multiple channels becomes a problem that must be solved. Otherwise, there will be an uncertain time delay between the data sampled and the data processed by the oscilloscope, which will seriously affect the oscilloscope's observation and measurement of multi-channel signals.

[0075] Therefore, in multi-channel sampling oscilloscopes, the ADC sampling and data processing of each sampling channel must be synchronized to reduce the latency difference between each channel's sampling. The data transmitted to the common FPGA also has high alignment requirements. Thus, how to reduce the latency difference between the oscilloscope's channels is an urgent problem to be solved.

[0076] Figure 1 illustrates an oscilloscope according to an embodiment of the present disclosure, the oscilloscope having N sampling channels, the oscilloscope comprising:

[0077] The first data processing unit 10 is configured to send a first synchronization signal to the first multiple output unit 20;

[0078] The first multi-output unit 20 is configured to output a second synchronization signal to each of the N sampling channels according to the first synchronization signal, wherein N is an integer greater than or equal to 2;

[0079] The N sampling channels correspond to an analog-to-digital conversion unit 30 and a second data processing unit 40, respectively. The analog-to-digital conversion unit 30 is configured to perform signal sampling to determine first sampling data and transmit the first sampling data synchronously to the second data processing unit 40 of the corresponding sampling channel according to the second synchronization signal. The second data processing unit 40 is configured to process the received first sampling data and send the second sampling data obtained from processing the first sampling data to the first data processing unit 10.

[0080] Here, the oscilloscope can have multiple sampling channels. Each sampling channel can be used to connect an external oscilloscope device.

[0081] In one possible implementation, the external oscilloscope device includes an oscilloscope probe.

[0082] In one possible implementation, an external device for the oscilloscope can be used to probe a signal and transmit the probed signal to the oscilloscope via an electrical connection (such as an analog input port).

[0083] In one possible implementation, the oscilloscope may also include an analog front-end for sending the detected signal to the analog-to-digital conversion unit 30. The analog front-end can be used to perform analog signal processing on the received signal, such as signal amplification.

[0084] The analog-to-digital converter (ADC) 30 is configured to sample the signal processed by the analog front-end, convert the analog signal into a digital signal (i.e., first sampled data), and send the first sampled data to the second data processing unit 40. The second data processing unit 40 is configured to process the first sampled data and send the second sampled data obtained from the data processing to the first data processing unit 10 in the oscilloscope. The ADC 30 may include an analog-to-digital converter (ADC), etc.

[0085] Here, the second data processing unit 40 is configured to perform data processing on the first sampled data, which may include performing at least one of the following on the first sampled data:

[0086] Digital filtering;

[0087] Data packets for transport protocols.

[0088] In one possible implementation, the first data processing unit 10 is configured to perform data processing, display, triggering, etc., on the data acquired from each sampling channel.

[0089] In one possible implementation, the analog-to-digital conversion unit 30 corresponding to each of the N sampling channels may include: an analog-to-digital conversion unit 30 for each of the N sampling channels. Each sampling channel may have one analog-to-digital conversion unit 30.

[0090] In one possible implementation, the second data processing unit 40 corresponding to each of the N sampling channels may include: a second data processing unit 40 for each of the N sampling channels. Each sampling channel may have one second data processing unit 40.

[0091] In one possible implementation, the first data processing unit 10 can be implemented by an FPGA, but is not limited thereto.

[0092] In one possible implementation, the second data processing unit 40 can be implemented by an FPGA, but is not limited thereto.

[0093] In one possible implementation, the first multi-output unit 20 is configured to distribute the oscilloscope's signal to different sampling channels.

[0094] In one possible implementation, the first multi-output unit 20 includes at least one of the following: employing a fanout device, a trigger, or a power divider.

[0095] In one possible implementation, the first multiple output unit 20 can be implemented by an FPGA.

[0096] In one possible implementation, the first multi-output unit 20 can be implemented using an integrated circuit with clock jitter cancellation capability.

[0097] In one possible implementation, different second synchronization signals output by the same first synchronization signal through the first multi-output unit 20 can have the same signal characteristics for controlling the synchronous analog-to-digital converter 30 to transmit the first sampled data, thereby enabling the synchronous analog-to-digital converter 30 to transmit the first sampled data. The signal characteristics of the second synchronization signal may include at least one of the following: pulse frequency, pulse edge duration, and pulse edge time-domain position.

[0098] In one possible implementation, the second synchronization signal can control the analog-to-digital converter 30 to transmit the first sampled data via a signal pulse. The second synchronization signal can control the analog-to-digital converter 30 to transmit the first sampled data via the edge of the signal pulse. The signal pulse edges of the second synchronization signals from different sampling channels are aligned to synchronize the transmission of the first sampled data by the analog-to-digital converter 30.

[0099] In one possible implementation, the second synchronization signal may include one or more signal pulses for controlling the analog-to-digital conversion unit 30 to transmit the first sampled data.

[0100] In one possible implementation, the second synchronization signal can be directly output to the analog-to-digital converter 30 to control the analog-to-digital converter 30 to transmit the first sampled data.

[0101] In one possible implementation, the second synchronization signal can be indirectly output to the analog-to-digital converter (ADC) 30. For example, the ADC can be further divided into multiple synchronization signals by a subsequent multi-output unit to control the ADC 30 in transmitting the first sampled data. Alternatively, the second synchronization signal can be converted to a higher level via a level conversion circuit to control the ADC 30 in transmitting the first sampled data.

[0102] In one possible implementation, the analog-to-digital conversion unit 30 can send the first sampled data to the second data processing unit 40 via a data bus. The data bus may include: an LVDS data bus or a JESD204B data bus.

[0103] In this way, the oscilloscope converts the first synchronization signal into a second synchronization signal, which is output to different sampling channels, through the first multi-output unit 20. This signal is used to synchronize the first sampling data transmission of the analog-to-digital converter 30, thereby achieving synchronization of the first sampling data transmission of the multi-channel analog-to-digital converter 30, reducing the delay difference in data transmission between the channels of the oscilloscope, and improving the signal detection accuracy of the oscilloscope.

[0104] In some embodiments, the analog-to-digital conversion unit 30 is specifically configured to synchronously transmit the start time of the first sampling data transmission to the second data processing unit 40 of the corresponding sampling channel according to the second synchronization signal.

[0105] In one possible implementation, one of the second synchronization signals corresponds to an analog-to-digital converter unit 30 for one sampling channel. For example, one of the second synchronization signals is output to an analog-to-digital converter unit 30 included in a sampling channel.

[0106] In one possible implementation, the second synchronization signal is used to trigger the first sample data transmission of the analog-to-digital converter (ADC) 30. That is, the ADC 30 begins transmitting the first sample data after receiving the second synchronization signal. Since the second synchronization signals of different sampling channels have the same signal characteristics, the timing of the first sample data transmission by the ADC 30 is the same, thus achieving synchronization of the start time of the first sample data transmission.

[0107] In one possible implementation, the analog-to-digital converter (ADC) unit 30 does not have a data buffer. Therefore, triggering the ADC unit 30 to sample means that the ADC unit 30 synchronously performs the first sample data transmission. That is, the second synchronization signal used to trigger the ADC unit 30 to perform the first sample data transmission and the second synchronization signal used to trigger the ADC unit 30 to perform sampling can be interchanged. In other words, the second synchronization signal is used to synchronize the ADC units 30 of multiple sampling channels to perform the first sample data transmission. Alternatively, it can be said that the second synchronization signal is used to synchronize the ADC units 30 of multiple sampling channels to perform sampling.

[0108] For example, as shown in Figure 2, this embodiment is illustrated with N=2, meaning the oscilloscope has two sampling channels. The analog-to-digital conversion units 30 of the two sampling channels, namely ADC1 and ADC2, respectively probe and sample their respective signals to obtain their first sampled data. The oscilloscope's main FPGA (i.e., the first data processing unit 10) sends SYNC2 (i.e., the first synchronization signal) to the ADC sampling clock and synchronization module (i.e., the first multi-output unit 20). The ADC sampling clock and synchronization module fans out SYNC2 into SYNC_ADC1 and SYNC_ADC2 (i.e., two second synchronization signals). SYNC_ADC1 is output to ADC1 (i.e., the analog-to-digital conversion unit 30), and SYNC_ADC2 is output to ADC2 (i.e., the analog-to-digital conversion unit 30). SYNC_ADC1 and SYNC_ADC2 have the same signal characteristics (such as pulses). SYNC_ADC1 and SYNC_ADC2 are used to trigger ADC1 and ADC2 to start transmitting the first sampled data to PFGA1 (the second data processing unit 40) and PFGA2 (the second data processing unit 40), respectively. Since SYNC_ADC1 and SYNC_ADC2 have the same signal characteristics, the starting time for ADC1 and ADC2 to transmit the first sampled data is the same, thus achieving synchronization of the starting time for transmitting the first sampled data.

[0109] In this way, the oscilloscope outputs the first synchronization signal conversion bit to the second synchronization signal of different sampling channels through the first multi-output unit 20, which is used to synchronize the start time of the first sampling data transmission of the analog-to-digital conversion unit 30, thereby realizing the synchronization of the start time of the first sampling data transmission of multiple sampling channels, reducing the delay difference of data transmission between the channels of the oscilloscope, and improving the signal detection accuracy of the oscilloscope.

[0110] Figure 3 illustrates an oscilloscope according to an embodiment of the present disclosure, the oscilloscope further comprising:

[0111] Reference clock unit 50 is configured to send a first reference clock signal to the first multiple output unit 20;

[0112] The first multi-output unit 20 is configured to output a first synchronization clock signal to the analog-to-digital conversion units 30 corresponding to the N sampling channels respectively, according to the first reference clock.

[0113] The analog-to-digital conversion unit 30 is further configured to synchronize the sampling frequency of the signal sampling according to the first synchronization clock signal.

[0114] In one possible implementation, the first multi-output unit 20 can output the first reference clock signal as N first synchronous clock signals with the same clock parameters. The first synchronous clock signals can be input to the analog-to-digital converter 30, which is configured to determine the sampling clock.

[0115] In one possible implementation, the analog-to-digital converter 30 can use the first synchronization clock signal as the sampling clock. Alternatively, the analog-to-digital converter 30 can divide the first synchronization clock signal to use it as the sampling clock.

[0116] In one possible implementation, the first multi-output unit 20 can fan out the first reference clock signal into N first synchronous clock signals with the same clock parameters.

[0117] In one possible implementation, the clock parameters include: clock frequency and clock phase.

[0118] The analog-to-digital conversion unit 30 with N sampling channels uses a first synchronous clock signal with the same clock parameters to sample, thereby achieving sampling synchronization.

[0119] In some embodiments, the first multiple output unit 20 is further configured to synchronize the first synchronization signal with the first reference clock signal. This further improves the synchronization between the second synchronization signal fanned out by the first synchronization signal and the first synchronization clock signal.

[0120] In one possible implementation, synchronizing the first synchronization signal with the first synchronization clock signal may include triggering the first synchronization signal with the first synchronization clock signal.

[0121] In one possible implementation, since the first reference clock signal synchronizes the first synchronization signal, the first multi-output unit 20 uses the first reference clock to fan out the first synchronization clock signal, and the first multi-output unit 20 uses the first synchronization signal to fan out the second synchronization signal. Therefore, the second synchronization signal and the first synchronization clock signal have a first fixed phase difference.

[0122] In one possible implementation, the first synchronization clock signal can be used as the clock for the D flip-flop to trigger the first synchronization signal for synchronization.

[0123] For example, as shown in Figure 2, the ADC sampling clock and synchronization module fans out the reference clock CLK1 (i.e., the first reference clock signal) into two CLK_ADC1 and CLK_ADC2 (i.e., two first synchronization clock signals). CLK_ADC1 is output to ADC1 (i.e., analog-to-digital conversion unit 30), and CLK_ADC2 is output to ADC2 (i.e., analog-to-digital conversion unit 30). CLK_ADC1 and CLK_ADC2 have the same clock parameters, and are used for signal sampling by ADC1 and ADC2, respectively. Since CLK_ADC1 and CLK_ADC2 have the same clock parameters, ADC1 and ADC2 can achieve frequency synchronization.

[0124] SYNC_ADC1 and SYNC_ADC2 (i.e., the two second synchronization signals) and CLK_ADC (CLK_ADC1 and CLK_ADC2) can have a fixed phase relationship. A D flip-flop can be used to synchronize the input synchronization signal SYNC2 with CLK1, and then the Fanout output can be used to obtain SYNC_ADC1 and SYNC_ADC2. The ADC sampling clock CLK_ADC and the synchronization signal SYNC_ADC output to the two sampling channels can have equal delays. If CLK_ADC and SYNC_ADC have delay errors, they can be calibrated during oscilloscope channel delay calibration.

[0125] In some embodiments, the analog-to-digital conversion unit 30 is further configured to output a second synchronization clock signal to the second data processing unit 40 of the corresponding sampling channel according to the first synchronization clock signal; the second data processing unit 40 is further configured to synchronize the processing of the first sampled data according to the second synchronization clock signal.

[0126] The analog-to-digital converter 30 can output a second synchronous clock signal based on the first synchronous clock signal. For example, the analog-to-digital converter 30 can fan out a second synchronous clock signal based on the first synchronous clock signal. The analog-to-digital converter 30 can also obtain the second synchronous clock signal by frequency division of the first synchronous clock signal.

[0127] In one possible implementation, the analog-to-digital conversion unit 30 of each sampling channel outputs the second synchronization clock signal in the same manner. Since the first synchronization clock signal of each sampling channel has the same clock parameters, the second synchronization clock signal of each sampling channel of the oscilloscope also has the same clock parameters.

[0128] The second data processing unit 40 processes the first sampled data, including at least one of the following: the second data processing unit 40 performs digital filtering on the first sampled data; the second data processing unit 40 performs data packetization on the first sampled data according to the transmission protocol.

[0129] Since the second synchronization clock signals of each sampling channel have the same clock parameters, the processing of the first sampled data by the second data processing unit 40 of each sampling channel is synchronized.

[0130] For example, as shown in Figure 2, the synchronization clock for data processing inside FPGA1 and FPGA2 uses the synchronization clock DCLK (i.e., the second synchronization clock signal) of the ADC (i.e., the analog-to-digital converter unit 30) output data. In this way, the data processing in FPGA1 and FPGA2 is synchronized with the ADC sampling, and the data processing in FPGA1 and FPGA2 is also synchronized.

[0131] Figure 4 illustrates an oscilloscope according to an embodiment of the present disclosure, the oscilloscope further comprising:

[0132] The second multi-output unit 60 is configured to output a third synchronization signal to the second data processing unit 40 and the first data processing unit 10 corresponding to the N sampling channels, respectively.

[0133] The third synchronization signal is used to synchronize the frame clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit 40 and the first data processing unit 10.

[0134] In one possible implementation, the signal characteristics of the third synchronization signal corresponding to each of the N sampling channels are the same. The signal characteristics of the third synchronization signal may include at least one of the following: pulse time-domain position, pulse time-domain width, and edge duration (rise time and / or fall time).

[0135] In one possible implementation, the second multi-output unit 60 performs multiple outputs of the signal.

[0136] In one possible implementation, the second multi-output unit 60 includes at least one of the following: employing a fanout device, a trigger, or a power divider.

[0137] In one possible implementation, the second multi-output unit 60 can autonomously output a third synchronization signal. For example, it can generate a pulse signal by dividing a reference clock.

[0138] In one possible implementation, the second data processing unit 40 processes the first sampled data to obtain the second sampled data, and sends the second sampled data to the first data processing unit 10 through the connection between the second data processing unit 40 and the first data processing unit 10 for data processing, etc.

[0139] In one possible implementation, the second data processing unit 40 can send the second sampled data to the first data processing unit 10 via a data bus. The data bus may include: an LVDS data bus or a JESD204B data bus.

[0140] In one possible implementation, the second data processing unit 40 can send the second sampled data to the first data processing unit 10 in the form of data frames. One set of second sampled data can contain multiple data frames, or a data frame can contain multiple sets of second sampled data.

[0141] In one possible implementation, data frames are transmitted within a frame clock. A frame clock pulse may include multiple transmission clocks. Here, the transmission clock may be the fundamental clock signal transmitted between the second data processing unit 40 and the first data processing unit 10. For example, the transmission clock may be the system clock in the JESD204B data bus.

[0142] The third synchronization signal may include a frame clock signal pulse. The second multi-output unit 60 may output one or more frame clock signal pulses.

[0143] The second data processing unit 40 can send the data frame corresponding to the second sampled data within the time domain width of the frame clock signal pulse. Multiple data frames can be sent according to the frame clock signal pulse, thereby realizing the control of the timing of data frame transmission.

[0144] Since the second data processing unit 40 and the first data processing unit 10 with N sampling channels use the same third synchronization signal, the second data processing unit 40 and the first data processing unit 10 with N sampling channels can synchronously transmit the data frames corresponding to the second sampling data.

[0145] In some embodiments, the first data processing unit 10 is configured to send a fourth synchronization signal to the second multiple output unit 60;

[0146] The second multi-output unit 60 is specifically configured to output the third synchronization signal according to the fourth synchronization signal.

[0147] In one possible implementation, the second multi-output unit 60 may output a third synchronization signal based on the fourth synchronization signal of the first data processing unit 10.

[0148] In one possible implementation, the third synchronization signal can be fanned out by the second multi-output unit 60 based on the fourth synchronization signal. Multiple third synchronization signals can have the same signal parameters.

[0149] For example, as shown in Figure 2, FPGA1 and FPGA2 are each connected to the main FPGA via a JESD204B data bus. The data processing clock and synchronization module (i.e., the second multi-output unit 60) outputs SYSREF (i.e., the third synchronization signal) to FPGA1 and FPGA2 respectively to synchronize the data frames corresponding to the second adopted data transmitted on the JESD204B data bus. The data processing clock and synchronization module can also fan out the third synchronization signal based on the SYNC1 (i.e., the fourth synchronization signal) output by the main FPGA, so that the third synchronization signals of each adopted channel have the same signal characteristics.

[0150] In some embodiments, the oscilloscope further includes:

[0151] Reference clock unit 50 is configured to send a second reference clock signal to the second multiple output unit 60;

[0152] The second multi-output unit 60 is configured to output a third synchronization clock signal to the second data processing unit 40 and the first data processing unit 10 corresponding to the N sampling channels respectively, according to the second reference clock.

[0153] The third synchronization clock signal is configured to synchronize the transmission clock of the data frame corresponding to the second sampled data between the second data processing unit 40 and the first data processing unit 10.

[0154] Here, the transmission clock can be the basic clock signal transmitted between the second data processing unit 40 and the first data processing unit 10.

[0155] In one possible implementation, the second multi-output unit 60 can output the second reference clock signal as multiple third synchronous clock signals with the same clock parameters. The third synchronous clock signals can be input to the first data processing unit 10 and each of the second data processing units 40 respectively, and configured as the transmission clock for the data frames corresponding to the second sampled data between the first data processing unit 10 and each of the second data processing units 40.

[0156] In one possible implementation, the second multi-output unit 60 can fan out the second reference clock signal into N+1 third synchronous clock signals with the same clock parameters.

[0157] In one possible implementation, the clock parameters include: clock frequency and clock phase.

[0158] Since the transmission connection (such as the data bus) between the first data processing unit 10 and each of the second data processing units 40 uses the third synchronization clock signal, the transmission clock of the transmission connection data frame between the first data processing unit 10 and each of the second data processing units 40 can be synchronized.

[0159] In one possible implementation, the second multi-output unit 60 may use a second reference clock signal to synchronize the fourth synchronization signal and fan out the third synchronization signal.

[0160] In one possible implementation, the second multi-output unit 60 may use a frequency-divided signal of the second reference clock signal to synchronize the fourth synchronization signal and fan out the third synchronization signal.

[0161] In one possible implementation, the second multi-output unit 60 synchronizing the fourth synchronization signal with the second reference clock signal may include triggering the fourth synchronization signal with the first synchronization clock signal.

[0162] The second multi-output unit 60 uses the second reference clock signal to trigger the fourth synchronization signal, which can make the third synchronization signal and the third synchronization clock signal have a second fixed phase difference.

[0163] In one possible implementation, the first synchronization clock signal can be used as the clock for a D flip-flop to trigger the fourth synchronization signal.

[0164] For example, as shown in Figure 2, FPGA1 and FPGA2 are connected to the main FPGA via a JESD204B data bus. The data processing clock and synchronization module (i.e., the second multi-output unit 60) outputs REFCLK (i.e., the third synchronization clock signal) to FPGA1, FPGA2, and the main FPGA respectively according to CLK2 (the second reference clock signal) to synchronize the data frames corresponding to the second adopted data transmitted on the JESD204B data bus. The data processing clock and synchronization module can also fan out SYSTEF (the third synchronization signal) according to SYNC1 (the fourth synchronization signal) output by the main FPGA, so that the SYSTEF of each adopted channel has the same signal characteristics.

[0165] The data processing clock and synchronization module may also include a synchronization trigger circuit configured to synchronize the SYNC1 output of the main FPGA. This synchronization typically uses the sampling clock CLK2 or its divided clock, and usually employs a high-speed D flip-flop. After synchronization, SYNC1 is used to synchronize the SYSREF output, ensuring a deterministic phase relationship between SYSREF and REFCLK.

[0166] In some embodiments, the first data processing unit 10 is further configured to output a fifth synchronization signal to the second data processing unit 40 corresponding to the N sampling channels respectively;

[0167] The second data processing unit 40 is further configured to synchronously transmit the start time of the second sampling data to the first data processing unit 10 according to the fifth synchronization signal.

[0168] In one possible implementation, the first data processing unit 10 can output N fifth synchronization signals to control the start time of the second data processing unit 40 transmitting the second sampled data. The N fifth synchronization signals can have the same signal characteristics to achieve synchronization of the start time of the second sampled data transmission.

[0169] In one possible implementation, the first data processing unit 10 can be implemented by an FPGA. The FPGA can output N fifth synchronization signals in a fan-out manner, so that the N fifth synchronization signals have the same signal characteristics.

[0170] In one possible implementation, the first data processing unit 10 can be implemented by an FPGA. The FPGA can control the output timing to ensure that the N fifth synchronization signals have the same signal characteristics, thus achieving the start time of synchronous transmission of the second sampled data. This enables the second data processing unit 40 to synchronously transmit the second sampled data to the first data processing unit 10.

[0171] By synchronizing the signal sampling of the analog-to-digital conversion units 30 in each sampling channel, synchronizing the transmission of the first sampled data by the analog-to-digital conversion units 30, synchronizing the processing of the first sampled data by the second data processing unit 40, and synchronizing the transmission of the second sampled data from the second data processing unit 40 to the first data processing unit 10, the synchronization of the complete data processing and transmission process of each sampling channel is achieved. This reduces the delay difference between the channels of the oscilloscope and improves the accuracy of signal measurement and display.

[0172] Here, this embodiment provides another way to implement an oscilloscope.

[0173] As shown in Figures 1 and 5, the oscilloscope has N sampling channels and includes:

[0174] The first data processing unit 10 is configured to send a first synchronization signal to the first multiple output unit 20;

[0175] The first multi-output unit 20 is configured to output a second synchronization signal to each of the N sampling channels according to the first synchronization signal, wherein N is an integer greater than or equal to 2;

[0176] The N sampling channels correspond to an analog-to-digital conversion unit 30 and a second data processing unit 40, respectively. The analog-to-digital conversion unit 30 is configured to perform signal sampling to determine first sampling data and transmit the first sampling data synchronously to the second data processing unit 40 of the corresponding sampling channel according to the second synchronization signal. The second data processing unit 40 is configured to process the received first sampling data and send the second sampling data obtained from processing the first sampling data to the first data processing unit 10.

[0177] As shown in Figure 5, the oscilloscope also includes:

[0178] The third multi-output unit 70 corresponding to each of the N sampling channels is configured to receive the second synchronization signal and output a sixth synchronization signal to the analog-to-digital conversion unit 30 of the corresponding sampling channel according to the second synchronization signal.

[0179] The analog-to-digital conversion unit 30 is configured to synchronously transmit the frame clock of the data frame corresponding to the first sampled data to the second data processing unit 40 of the sampling channel according to the sixth synchronization signal.

[0180] Here, without contradiction, the implementation and working principle of the first data processing unit 10, the first multi-output unit 20, the analog-to-digital conversion unit 30, and the second data processing unit 40 are similar to those in the above embodiments and will not be repeated here.

[0181] In one possible implementation, the analog-to-digital converter (ADC) 30 does not have a data buffer. Therefore, triggering the ADC 30 to sample means that the ADC 30 synchronously performs the first sample data transmission. That is, without contradiction, the use of the sixth synchronization signal to trigger the ADC 30 to perform the first sample data transmission and the use of the sixth synchronization signal to trigger the ADC 30 to perform sampling can be interchanged. In other words, the sixth synchronization signal is used to synchronize the first sample data transmission of the ADC 30 across multiple sampling channels. It can also be said that the sixth synchronization signal is used to synchronize the sampling of the ADC 30 across multiple sampling channels.

[0182] In one possible implementation, the third multiple output unit 70 corresponding to each of the N sampling channels includes: each of the N sampling channels has a third multiple output unit 70.

[0183] In one possible implementation, the third multi-output unit 70 performs multiple outputs of the signal.

[0184] In one possible implementation, the third multi-output unit 70 includes at least one of the following: employing a fanout device, a trigger, or a power divider.

[0185] In one possible implementation, the signal characteristics of the sixth synchronization signal corresponding to each of the N sampling channels are identical. The signal characteristics of the sixth synchronization signal may include at least one of the following: pulse time-domain position, pulse time-domain width, and edge duration (rise time and / or fall time).

[0186] In one possible implementation, the analog-to-digital conversion unit 30 samples the signal to obtain first sampled data, and sends the first sampled data to the second data processing unit 40 for data processing through the connection between the analog-to-digital conversion unit 30 and the second data processing unit 40.

[0187] In one possible implementation, the analog-to-digital conversion unit 30 can send the first sampled data to the second data processing unit 40 via a data bus. The data bus may include: an LVDS data bus or a JESD204B data bus.

[0188] In one possible implementation, the analog-to-digital conversion unit 30 can send the first sampled data to the second data processing unit 40 in the form of data frames. One set of first sampled data may contain multiple data frames, or a data frame may contain multiple sets of first sampled data.

[0189] In one possible implementation, data frames are transmitted within a frame clock. A frame clock pulse may include multiple transmission clocks. Here, the transmission clock may be the fundamental clock signal transmitted between the analog-to-digital conversion unit 30 and the second data processing unit 40.

[0190] The sixth synchronization signal may include a frame clock signal pulse. The third multi-output unit 70 may output one or more frame clock signal pulses.

[0191] The analog-to-digital conversion unit 30 can transmit the data frame corresponding to the first sampled data within the time domain width of the frame clock signal pulse. Multiple data frames can be transmitted according to the frame clock signal pulse, thereby realizing the control of the timing of data frame transmission.

[0192] Since the analog-to-digital conversion units 30 of the N sampling channels use the sixth synchronization signal with the same signal characteristics, the analog-to-digital conversion units 30 of the N sampling channels can synchronize the transmission of the data frame corresponding to the second sampled data.

[0193] As shown in Figure 6, the oscilloscope includes a primary clock and synchronization module (i.e., the first multi-output unit 20), and each sampling channel has a secondary clock and synchronization module (i.e., the third multi-output unit 70). The primary clock and synchronization module fans out SYSREF (the second synchronization signal) to each secondary clock and synchronization module based on SYNC1 (the first synchronization signal). The secondary clock and synchronization module then outputs SYSREF to the ADC (analog-to-digital converter unit 30) based on the received SYSREF. The ADC (ADC1 or ADC2) and FPGA (FPGA1 or FPGA2) in the sampling channel use the JESD204B data bus. SYSREF is used to synchronize the frame clock of the JESD204B data bus between the ADC and FPGA in each channel.

[0194] In some embodiments, as shown in FIG7, the oscilloscope further includes:

[0195] Reference clock unit 50 is configured to send a third reference clock signal to the first multiple output unit 20;

[0196] The first multi-output unit 20 is configured to output a fourth synchronization clock signal to the third multi-output units 70 corresponding to the N sampling channels respectively, according to the third reference clock;

[0197] The third multi-output unit 70 is further configured to output a fifth synchronous clock signal to the analog-to-digital conversion unit 30 of the corresponding sampling channel according to the fourth synchronous clock signal;

[0198] The analog-to-digital conversion unit 30 is configured to synchronously transmit the transmission clock of the data frame corresponding to the first sampled data to the second data processing unit 40 of the sampling channel according to the fifth synchronization clock signal.

[0199] Here, the transmission clock can be the basic clock signal transmitted between the analog-to-digital conversion unit 30 and the second data processing unit 40.

[0200] The first multi-output unit 20 receives the third reference clock signal from the reference clock unit 50 and fans out a fourth synchronization clock signal to the third multi-output unit 70 of each sampling channel. Multiple fourth synchronization clock signals can have the same clock parameters.

[0201] The third multi-output unit 70 can output a fifth synchronous clock signal from the fourth synchronous clock signal. The fifth synchronous clock signal can be input to the analog-to-digital converter 30 and configured as the transmission clock for the data frame corresponding to the first sampled data transmitted by the analog-to-digital converter 30. Multiple fifth synchronous clock signals can have the same clock parameters.

[0202] In one possible implementation, the clock parameters include: clock frequency and clock phase.

[0203] Since each analog-to-digital converter 30 uses the fifth synchronization clock signal for transmission, the transmission clock synchronization of the data frame corresponding to the first sampled data of the analog-to-digital converter 30 can be achieved.

[0204] As shown in Figure 6, the oscilloscope includes a primary clock and synchronization module (i.e., the first multi-output unit 20), and each sampling channel has a secondary clock and synchronization module (i.e., the third multi-output unit 70). The primary clock and synchronization module fans out REFCLK (the fourth synchronization clock signal) to each secondary clock and synchronization module based on CLK3 (the third reference clock signal). The secondary clock and synchronization module then outputs REFCLK to the ADC (analog-to-digital converter unit 30) based on the received REFCLK. The ADC (ADC1 or ADC2) and FPGA (FPGA1 or FPGA2) in the sampling channel use the JESD204B data bus. REFCLK is used to synchronize the transmission clock of the JESD204B data bus between the ADC and FPGA in each channel.

[0205] In some embodiments,

[0206] The first multi-output unit 20 is further configured to output a seventh synchronization signal to the first data processing unit 10 according to the first synchronization signal;

[0207] The third multi-output unit 70 is further configured to output an eighth synchronization signal to the second data processing unit 40 of the corresponding sampling channel according to the second synchronization signal;

[0208] The seventh synchronization signal and the eighth synchronization signal are used to synchronize the frame clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit 40 and the first data processing unit 10.

[0209] Both the seventh and eighth synchronization signals are fanned out step-by-step from the first synchronization signal, and therefore can have the same signal characteristics. The seventh synchronization signal can be input to the first data processing unit 10, and the eighth synchronization signal can be input to each of the second data processing units 40, respectively, to synchronize the frame clock of the data frames corresponding to the second sampled data between the first data processing unit 10 and each of the second data processing units 40.

[0210] The first data processing unit 10 and the second data processing unit 40 can be connected via the JESD204B data bus to transmit the data frame corresponding to the second sampled data.

[0211] The method of transmitting data frames between the first data processing unit 10 and the second data processing unit 40 is similar to the method of transmitting data frames between the analog-to-digital conversion unit 30 and the second data processing unit 40, and will not be described again here.

[0212] In one possible implementation, the sixth synchronization signal is fanned out by the third multi-output unit 70 based on the second synchronization signal; therefore, the sixth synchronization signals of each channel can have the same signal characteristics, enabling synchronization of the first sampled data transmission.

[0213] In one possible implementation, the sixth, seventh, and eighth synchronization signals are all fanned out step-by-step from the first synchronization signal, and therefore can have the same signal characteristics. This enables synchronization of data transmission in the sampling channel.

[0214] As shown in Figure 6, the oscilloscope includes a primary clock and synchronization module (i.e., the first multi-output unit 20), and each sampling channel has a secondary clock and synchronization module (i.e., the third multi-output unit 70). The primary clock and synchronization module fans out SYSREF (the seventh synchronization signal) to the main FPGA (the first data processing unit 10) and SYSREF (the second synchronization signal) to each secondary clock and synchronization module based on SYNC1 (the first synchronization signal). The secondary clock and synchronization module then outputs SYSREF (the eighth synchronization signal) to the FPGA (FPGA1 or FPGA2) (the second data processing unit 40) of each sampling channel based on the received SYSREF. The main FPGA and the FPGA (FPGA1 or FPGA2) in each sampling channel use the JESD204B data bus. SYSREF is used to synchronize the frame clock of the JESD204B data bus between the FPGA (FPGA1 or FPGA2) and the main FPGA in each channel.

[0215] In some embodiments, the oscilloscope further includes:

[0216] The third multi-output unit 70 is further configured to output a sixth synchronous clock signal to the second data processing unit 40 according to the fourth synchronous clock signal;

[0217] The first multi-output unit 20 is configured to output a seventh synchronization clock signal to the first data processing unit 10 according to the third reference clock 50;

[0218] The sixth synchronization clock signal and the seventh synchronization clock signal are used to synchronize the transmission clock of the data frame corresponding to the second sampled data between the second data processing unit 40 and the first data processing unit 10.

[0219] Here, the transmission clock can be the basic clock signal transmitted between the second data processing unit 40 and the first data processing unit 10.

[0220] Both the sixth and seventh synchronization clock signals are fanned out based on the third reference clock signal, and therefore can have the same signal characteristics. The seventh synchronization clock signal can be input to the first data processing unit 10, and the sixth synchronization clock signal can be input to each of the second data processing units 40, respectively, to synchronize the transmission clock of the data frames corresponding to the second sampled data between the first data processing unit 10 and each of the second data processing units 40.

[0221] The first data processing unit 10 and the second data processing unit 40 can be connected via the JESD204B data bus to transmit the data frame corresponding to the second sampled data.

[0222] The method of transmitting data frames between the first data processing unit 10 and the second data processing unit 40 is similar to the method of transmitting data frames between the analog-to-digital conversion unit 30 and the second data processing unit 40, and will not be described again here.

[0223] In one possible implementation, the fifth and sixth synchronization clock signals are fanned out by the third multi-output unit 70 based on the fourth synchronization clock signal, and therefore can have the same clock parameters. This enables synchronization of the first sampled data transmission.

[0224] In one possible implementation, the fifth, sixth, and seventh synchronization clock signals are all fanned out step-by-step from the third reference clock signal, and therefore can have the same clock parameters. This enables synchronization of data transmission in the sampling channel.

[0225] As shown in Figure 6, the oscilloscope includes a primary clock and synchronization module (i.e., the first multi-output unit 20), and each sampling channel has a secondary clock and synchronization module (i.e., the third multi-output unit 70). The primary clock and synchronization module fans out REFCLK (the seventh synchronization clock signal) to the main FPGA (the first data processing unit 10) and REFCLK (the fourth synchronization clock signal) to each secondary clock and synchronization module based on CLK3 (the third reference clock signal). The secondary clock and synchronization module then outputs REFCLK (the sixth synchronization clock signal) to the FPGA (FPGA1 or FPGA2) (the second data processing unit 40) of each sampling channel based on the received REFCLK. The main FPGA and the FPGA (FPGA1 or FPGA2) in each sampling channel use the JESD204B data bus. REFCLK is used to synchronize the transmission clock of the JESD204B data bus between the FPGA (FPGA1 or FPGA2) and the main FPGA in each channel.

[0226] In some embodiments, the first data processing unit 10 is further configured to output a ninth synchronization signal to the second data processing unit 40 corresponding to the N sampling channels respectively;

[0227] The second data processing unit 40 is further configured to synchronously transmit the start time of the second sampling data to the first data processing unit 10 according to the ninth synchronization signal.

[0228] In one possible implementation, the first data processing unit 10 can output N ninth synchronization signals to control the start time of the second data processing unit 40 transmitting the second sampled data. The N ninth synchronization signals can have the same signal characteristics to achieve synchronization of the start time of the second sampled data transmission.

[0229] In one possible implementation, the first data processing unit 10 can be implemented by an FPGA. The FPGA can output N ninth synchronization signals in a fan-out manner, so that the N ninth synchronization signals have the same signal characteristics.

[0230] In one possible implementation, the first data processing unit 10 can be implemented by an FPGA. The FPGA can control the output timing to ensure that the N ninth synchronization signals have the same signal characteristics, thereby achieving the start time of synchronous transmission of the second sampled data.

[0231] As shown in Figure 6, the main FPGA (first data processing unit 10) outputs SYNC4 (ninth synchronization signal) to the FPGAs (FPGA1 and FPGA2) (second data processing unit 40) of each sampling channel to realize the start time of the synchronous second sampling data transmission.

[0232] In some embodiments, the second data processing unit 40 is further configured to output a tenth synchronization signal to the analog-to-digital conversion unit 30 of the corresponding sampling channel according to the ninth synchronization signal;

[0233] The analog-to-digital conversion unit 30 is further configured to synchronously transmit the start time of the first sampled data to the second data processing unit 40 according to the tenth synchronization signal.

[0234] In one possible implementation, the tenth synchronization signal can be triggered based on the ninth synchronization signal. Since each ninth synchronization signal has the same signal characteristics, each tenth synchronization signal can also have the same signal characteristics. N tenth synchronization signals can have the same signal characteristics, achieving synchronization at the start time of the first sampled data transmission.

[0235] As shown in Figure 6, the FPGA (FPGA1 and FPGA2) (second data processing unit 40) of each sampling channel outputs SYNC5 (tenth synchronization signal) to the corresponding ADC (ADC1 and ADC2) to realize the synchronization of the first sampling data transmission start time.

[0236] By synchronizing the sampling and transmission of the first sampled data in the analog-to-digital conversion unit 30 of each sampling channel, synchronizing the processing of the first sampled data in the second data processing unit 40, and synchronizing the transmission of the second sampled data from the second data processing unit 40 to the first data processing unit 10, the synchronization of the complete data processing and transmission process of each sampling channel is achieved. This reduces the delay difference between the channels of the oscilloscope and improves the accuracy of signal measurement and display.

[0237] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

[0238] The following provides several specific examples in conjunction with any of the above embodiments:

[0239] High-bandwidth, high-sampling-rate oscilloscopes, due to their high ADC sampling rate and large data throughput, feature independent sampling channels for each ADC. These sampling channels include analog input, analog front-end, ADC, and FPGA. The outputs from multiple sampling channels are aggregated in the main FPGA for alignment, triggering, and data processing / display of the multi-channel sampled data.

[0240] Multiple sampling channels store and process the ADC's sampling data, then aggregate it to another FPGA for display, analysis, and other processing, typically on the motherboard.

[0241] Multiple sampling channels correspond to multiple independent channels of the oscilloscope. The oscilloscope channels need to ensure very small channel delays and sampling synchronization. After the ADC sampling data is synchronized, the data transmission from multiple independent sampling units to the motherboard also needs to be synchronized to ensure the synchronization of the data finally aggregated from multiple channels to the motherboard FPGA.

[0242] As shown in Figure 2, in this embodiment, the ADC sampling synchronization uses an oscilloscope with an ADC sampling clock and synchronization module. This module has two signal inputs: a reference clock (CLK1) from the oscilloscope and a synchronization signal (SYNC2) from the main FPGA. The ADC sampling clock and synchronization module outputs two ADC sampling clocks, which are synchronized and have the same frequency and phase. These two synchronized clocks are provided to the ADC of each sampling channel as their sampling clocks. The module also outputs two ADC synchronization signals, typically pulse signals with a fixed phase relationship to the sampling clock (CLK_ADC). These signals can generally be generated using a D flip-flop, synchronizing the input synchronization signal (SYNC2) with CLK_ADC, and then fan-out. The ADC sampling clocks and synchronization signals output to the two sampling channels must be functioning correctly, ensuring that the sampling clocks and SYNC2 arriving at ADC1 and ADC2 have equal delays. If errors exist, they can be corrected during oscilloscope channel delay calibration.

[0243] By ensuring equal delay or determining the phase of the ADC sampling clock and synchronization signal, it is possible to guarantee that the sampling of the two ADCs is synchronized, and that the output data of the output ADC is also synchronized through SYNC synchronization. The ADC can be of LVDS type or JESD204B type.

[0244] The synchronization of the sampling clock and the synchronization signal does not affect other calibration items of the two ADCs. After the ADC calibration is complete, the main FPGA should send the synchronization signal SYNC2 to synchronize the ADC output data to ensure that the output data is also synchronized.

[0245] The second aspect of this embodiment is ensuring that data processing and output transmission from FPGA1 and FPGA2 to the main FPGA are synchronized. The synchronization clock for data processing within FPGA1 and FPGA2 uses the synchronization clock DCLK for the ADC output data. This ensures that data processing in FPGA1 and FPGA2 is synchronized with ADC sampling, thus ensuring data synchronization between FPGA1 and FPGA2.

[0246] The oscilloscope also includes a data processing clock and synchronization module configured to generate a reference clock REFCLK and a system synchronization reference signal SYSREF for data transfer between FPGAs. This embodiment addresses the synchronization of data transfer from multiple FPGAs to a master FPGA, using a high-speed serial bus and either the JESD204B or JESD204C protocol. An FPGA with a high-speed serial bus and support for the JESD204B protocol is selected. A JESD 204B serial communication interface is used between the FPGAs in the sampling channels and the master FPGA to transmit JESD204B DATA serial data from the FPGA to the master FPGA. Due to the deterministic delay between devices using JESD204B, the synchronization of data transmitted from multiple FPGAs to the master FPGA is guaranteed.

[0247] In the JESD204B data line, data can be segmented into frames and continuously transmitted to the receiver. By using the System Reference Event Signal (SYSREF), data from multiple serial channel links can be aligned to SYSREF to synchronize the internal frame clocks of the transmitter and receiver, resulting in deterministic latency for devices using JESD204B links. Generally, frame clock alignment, data code synchronization, and frame and link synchronization are completed sequentially using the System Synchronization Reference Signal SYSREF and the synchronization signal SYNC. The synchronized JESD204B data transmission and reception exhibit deterministic latency.

[0248] The focus of this embodiment is on how the clock and synchronization reference signal SYSREF of each sampling channel and the main FPGA are generated and allocated to achieve synchronization of data transmission between the sampling channels and the main FPGA.

[0249] The data processing clock and synchronization module uses another output (CLK2) of the reference clock as its input clock. The two outputs of the reference clock must be at the same frequency and have a deterministic phase; typically, a power-divided output of two channels is used. The output processing clock and synchronization module also uses SYNC1, from the main FPGA, for synchronizing SYSREF. The clock and processing module outputs three reference clocks and a system synchronization reference signal SYSREF, connected to FPGA1, FPGA2, and the main FPGA respectively, serving as the reference clock for the JESD204B communication module. SYSREF is used to synchronize the transceiver's internal frame clock, ensuring that the data transmission delay between FPGA1 and the main FPGA is the same. The data transmission interface between FPGA1 and FPGA2 and the main FPGA is the JESD204B interface. The main FPGA can have a synchronization signal SYNC3 for synchronizing the output transmission start of FPGA1 and FPGA2. This ensures the synchronization of output transmission between the FPGAs.

[0250] The entire oscilloscope multi-sampling channel synchronization process is as follows:

[0251] 1. ADC sampling clock synchronization, sampling SYNC synchronization;

[0252] 2. Data processing within the FPGA and ADC data clock synchronization;

[0253] 3. Establishing and synchronizing links between FPGAs;

[0254] 4. The main FPGA synchronizes the output transmission of FPGA1 / 2 via SYNC.

[0255] In this way, the entire oscilloscope system is strictly synchronized from sampling to output, ensuring that the sampled data transmitted to the main FPGA is an analog signal sampled at the same time, thereby achieving synchronization of multiple sampling channels.

[0256] The multi-channel sampling synchronization solution for oscilloscopes provided in this embodiment can be applied to high-bandwidth, high-sampling-rate oscilloscopes, and is suitable for scenarios where each channel has independent sampling processing, providing a strict sampling channel synchronization effect. Furthermore, the method for generating sampling synchronization is widely applicable, not limited to the type of ADC, and is simpler to use, making it suitable for most mid-to-high-end oscilloscopes. Therefore, this embodiment has very broad application prospects.

[0257] Example 1:

[0258] In this embodiment, the ADC sampling clock and synchronization module, the sampling clock CLK_AD1 / CLK_AD2 are generally implemented using a phase-locked loop and a power divider to ensure that the output frequency and phase noise meet the requirements of the ADC, and the reference clock serves as the input reference of the phase-locked loop.

[0259] In this embodiment, the SYNC signal is generally output by synchronizing the SYNC2 output from the main FPGA with the Fanout output. The synchronization is generally performed using a sampling clock or its frequency division clock, and a high-speed D flip-flop is generally used to ensure a deterministic phase relationship between the SYNC and the sampling clock.

[0260] In this embodiment, the data processing clock and synchronization module typically uses a clock distribution circuit that meets JESD204B standards. This circuit generally includes a phase-locked loop (PLL) and a fanout circuit to generate multiple identical reference clocks, REFCLK. It also generates a synchronization reference signal, SYSREF, typically a pulse or continuous pulse clock. SYSREF and REFCLK are synchronized. A synchronization trigger circuit is also included to synchronize the SYNC2 output from the main FPGA. This synchronization typically uses the sampling clock or its divided clock, usually a high-speed D flip-flop. After synchronization, SYNC2 is used to synchronize the SYSREF output, ensuring a deterministic phase relationship between SYNC and the sampling clock.

[0261] In this embodiment, the data processing clock and synchronization module can be constructed using a combination of multiple devices, such as a clock generation chip and a clock distribution circuit. Alternatively, a clock generator with the above-mentioned functions can be used, such as TI's LMK04826 or LMK04828, or Analog Devices' LTC6852.

[0262] In this embodiment, the ADC can be an ADC with an LVDS parallel output interface.

[0263] In this embodiment, an FPGA that supports the JESD204B serial interface is selected.

[0264] In this embodiment, the analog front-end, ADC, and FPGA1 / FPGA12 all need to be controlled. The analog front-end and ADC can be controlled by the FPGA of the sampling channel or by the main FPGA.

[0265] In this embodiment, the clock and synchronization signals output by the clock and synchronization modules need to be controlled to be of equal length in the PCB design to meet the setup and hold time requirements of the entire circuit board, connectors, backplane and various components.

[0266] In this embodiment, the ADC sampling clock and synchronization module, as well as the data processing clock and synchronization module, also need to be controlled by the main FPGA. They are not shown in Figure 2 and can be controlled by SPI or I2C interfaces.

[0267] Example 2:

[0268] As shown in Figure 6, Example 2 presents a synchronization scheme using a high-speed ADC with a JESD204B interface.

[0269] With the increasing use of JESD204B or JESD204C chips in high-speed ADCs, the requirement for FPGA I / O can be greatly reduced.

[0270] Since the ADC itself is only the JESD204B's reference clock REFCLK and synchronization reference signal SYSREF, synchronization becomes simple.

[0271] Each sampling channel contains a second-level clock and synchronization module. The second-level clock synchronization module outputs multiple reference clocks and synchronization reference signals to synchronize the ADC and FPGA inside each sampling channel.

[0272] Multiple FPGAs can also be cascaded, as long as the FPGAs also use the JESD204B interface to ensure synchronization.

[0273] The REFCLK and SYSREF outputs from the first-stage clock and synchronization module serve as inputs to the second-stage clock and synchronization module. Internally, the second-stage clock and synchronization module only buffers and fanouts REFCLK; it cannot pass through a phase-locked loop (PLL), otherwise the synchronization relationship between the two stages of REFCLK would be disrupted, resulting in uncertain phases. The SYSREF within the second stage can also be directly fanouted, ensuring that it maintains its synchronization relationship. If the second-stage SYSREF passes through a D flip-flop, REFCLK can be used as the clock for the D flip-flop without disrupting the synchronization relationship between SYSREF and REFCLK, and this can also be used.

[0274] In this embodiment, the second-stage clock and synchronization module can be constructed using high-speed Fanout devices and flip-flops, etc.

[0275] 1. The multi-sampling channel oscilloscope synchronization provided in this embodiment can solve the problem that it is impossible to use a single FPGA to receive and process all ADC data under high sampling rates, and provides a two-level FPGA sampling synchronization structure.

[0276] 2. This embodiment can simultaneously ensure the synchronization of high sampling rate ADC and data transmission, and ensure the strict synchronization of independent channel sampling modules.

[0277] 3. The synchronization generation method provided in this embodiment has wide applicability and can be used in different types of ADCs. It is also simple to use.

[0278] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed in this disclosure. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0279] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An oscilloscope having N sampling channels, the oscilloscope comprising: The first data processing unit is configured to send a first synchronization signal to the first multiple output unit; The first multi-output unit is configured to output a second synchronization signal to each of the N sampling channels according to the first synchronization signal, wherein N is an integer greater than or equal to 2; The N sampling channels correspond to an analog-to-digital conversion unit and a second data processing unit, respectively. The analog-to-digital conversion unit is configured to perform signal sampling to determine first sampling data and synchronously transmit the first sampling data to the second data processing unit of the corresponding sampling channel according to the second synchronization signal. The second data processing unit is configured to process the received first sampling data and send the second sampling data obtained from processing the first sampling data to the first data processing unit.

2. The oscilloscope according to claim 1, wherein, The analog-to-digital conversion unit is specifically configured to synchronously transmit the start time of the first sampling data transmission to the second data processing unit of the corresponding sampling channel according to the second synchronization signal.

3. The oscilloscope according to claim 2, wherein, The oscilloscope also includes: A reference clock unit is configured to send a first reference clock signal to the first multiple output unit; The first multi-output unit is configured to output a first synchronization clock signal to the analog-to-digital conversion units corresponding to the N sampling channels respectively, based on the first reference clock. The analog-to-digital conversion unit is further configured to synchronize the sampling frequency of the signal sampling according to the first synchronization clock signal.

4. The oscilloscope according to claim 3, wherein, The first multi-output unit is further configured to synchronize the first synchronization signal using the first reference clock signal.

5. The oscilloscope according to claim 3, wherein, The analog-to-digital conversion unit is further configured to output a second synchronous clock signal to the second data processing unit of the corresponding sampling channel according to the first synchronous clock signal; The second data processing unit is further configured to synchronize the processing of the first sampled data according to the second synchronization clock signal.

6. The oscilloscope according to claim 2, wherein, The oscilloscope also includes: The second multi-output unit is configured to output a third synchronization signal to the second data processing unit corresponding to each of the N sampling channels and the first data processing unit respectively. The third synchronization signal is configured to synchronize the frame clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit and the first data processing unit.

7. The oscilloscope according to claim 6, wherein, The first data processing unit is configured to send a fourth synchronization signal to the second multi-output unit; The second multi-output unit is specifically configured to output the third synchronization signal according to the fourth synchronization signal.

8. The oscilloscope according to claim 6, wherein, The oscilloscope also includes: The reference clock unit is configured to send a second reference clock signal to the second multiple output unit; The second multi-output unit is configured to output a third synchronization clock signal to the second data processing unit and the first data processing unit corresponding to the N sampling channels respectively, according to the second reference clock; The third synchronization clock signal is configured to synchronize the transmission clock of the data frame corresponding to the second sampled data transmitted between the second data processing unit and the first data processing unit.

9. The oscilloscope according to claim 6, wherein, The first data processing unit is further configured to output a fifth synchronization signal to the second data processing unit corresponding to each of the N sampling channels respectively; The second data processing unit is further configured to synchronously transmit the start time of the second sampling data to the first data processing unit according to the fifth synchronization signal.

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