METHOD AND DEVICE FOR BONDING CHIPS

Description

[0001] The invention relates to a method and a device for bonding chips.

[0002] Chip-to-wafer (C2W) or chip-to-chip (C2C) processes are currently carried out using solder balls or copper pillars with solder caps. However, the solder balls or copper pillars with solder caps are extremely large and increase the thickness of the chips produced in this way.

[0003] US 2015 / 0228535 A1 discloses a method for manufacturing semiconductor structures. US 2016 / 0190087 A1 discloses a chip stacking device for stacking a chip on a substrate. US 2003 / 0115747 A1 discloses a receiving tool with a suction element made of elastically deformable material. US 2013 / 0075868 A1 discloses the transfer of a layer of semiconductor material from a first donor structure to a second structure. JP4064808B discloses a liquid crystal cell mounted on a mounting pad.

[0004] It is therefore the object of the present invention to provide an improved bonding method or an improved bonding device.

[0005] This problem is solved by the subject matter of the dependent patent claims.

[0006] The invention provides a method for bonding a chip to a semiconductor substrate or to another chip, wherein the chip is bonded to the semiconductor substrate or the other chip by a direct bond. A direct bond is understood to be a bond that forms directly through the interaction of two surfaces without forming a liquid phase. According to another definition, a direct bond is understood to be a bond that does not require the use of any additional materials. In particular, a direct bond is understood to be a metal-to-metal solid-state bond, especially a diffusion bond, a prebond, a fusion bond resulting from a prebond, or a hybrid bond, i.e., a bond based on fusion bond components and metal bond components.

[0007] Furthermore, according to the invention, a device for bonding a chip to a semiconductor substrate or to another chip is provided, wherein the chip can be bonded to the semiconductor substrate or to the other chip by direct bonding.

[0008] Furthermore, a stack of chips is revealed, the chips being bonded together by a direct bond.

[0009] Furthermore, a substrate with chips (product) is disclosed, wherein the chips are bonded to the substrate by direct bonding.

[0010] According to the invention, direct bonding at the C2C or C2W level is enabled. Advantageously, solder balls or copper columns with solder caps are no longer required. The thickness of the produced chip stacks or products is reduced, the throughput is increased, and the performance of chip communication improves. The direct bonding has a bond strength of more than 0.1 J / m², preferably more than 0.5 J / m², more preferably more than 1.0 J / m², most preferably more than 2.0 J / m², and most preferably more than 2.5 J / m². The direct bonding is carried out particularly at temperatures of less than 400°C, preferably less than 300°C, more preferably less than 2000°C, most preferably less than 150°C, and most preferably less than 100°C. Furthermore, the direct bonding takes place without the generation of a liquid phase.

[0011] It is revealed that the surface of a chip can be kept so clean that a subsequent direct bonding step can take place. The chips prepared in this way, with a contamination-free bonding surface, can then be bonded to the substrate (chip-to-wafer, C2W) or to other chips (chip-to-chip, C2W).

[0012] In the following sections of this document, a substrate or semiconductor substrate is understood to be a semi-finished product of the semiconductor industry that has not yet been separated, and is preferably round. A wafer is particularly advantageous as a substrate. Substrates can have any shape, but are preferably circular. The diameter of the substrates is standardized in the industry. For wafers, the industry-standard diameters are 1 inch, 2 inches, 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, 12 inches, and 18 inches. However, the embodiment according to the invention can, in principle, handle any substrate, regardless of its diameter.

[0013] In the following text, a chip is understood to be a component, usually rectangular, obtained by isolating a semiconductor substrate (wafer). A chip typically contains an integrated circuit that is created during the processing of the semiconductor substrate.

[0014] In this document, a bonding surface is understood to be a surface that, during a process, becomes part of a bonding interface at some point. Specifically, the bonding surface is understood to be the surface of a chip that, according to the invention, must be treated, in particular cleaned, before the chip is bonded. If a chip is bonded to a substrate, the substrate surface can also be referred to as the bonding surface.

[0015] According to the invention, the bonding surfaces are hybrid bonding surfaces. A hybrid bonding surface is defined as a bonding surface consisting of metallic and dielectric areas, and thus of metallic and dielectric bonding surface components. All methods and / or devices mentioned in this publication that relate to direct bonding in general can therefore be applied to bonding hybrid surfaces. Preferably, the metallic and dielectric surface components are largely located in the same plane. In particular, the metallic surface components are recessed by less than 0.5 µm, preferably less than 100 nm, more preferably less than 50 nm, and most preferably less than 10 nm, relative to the dielectric surface components, or they protrude from the dielectric surface components. Cleaning process

[0016] In the following publication, cleaning is understood to mean the removal of contaminants from the bond surface by one and / or more of the following methods: Wet chemical cleaning, in particular: ∘ with water, in particular ▪ CO2-containing water ∘ with alcohols o with acids, in particular ▪ formic acid ▪ citric acid ▪ peroxymonosulfuric acid ▪ Standardelean 1 (SC1) ▪ Standardelean 2 (SC2) o With bases, in particular ▪ NH4OH Plasma cleaning Plasma ashing Mechanical cleaning, in particular o Brushing

[0017] Plasma cleaning is the process of bombarding a surface, generally at high energy, with the ionized components of a plasma. The plasma ions are accelerated by electric and / or magnetic fields and possess a significant penetration depth. Plasma cleaning can be combined with plasma activation of a surface.

[0018] Plasma ashing is a generally low-energy cleaning process for organic substances from a surface. The cleaning is achieved primarily through the oxidation of the organic species, particularly with oxygen and / or fluorine, or any other suitable and ionizable oxidizing agent. The organic components oxidized by the plasma ashing are preferably removed from the reaction chamber. This is accomplished either by a continuous plasma flow or by sequential venting and purging of the plasma chamber. In a more preferred embodiment, however, the ashed and oxidized organic components are bound within the plasma chamber by chemical and / or physical processes, thus preventing their return to the substrate surface. This avoids the need for complex devices that require plasma circulation.

[0019] Optionally, after plasma ashing, a wet chemical cleaning is carried out with one or more of the aforementioned liquids to further improve the surface cleanliness and / or the surface chemistry of the surfaces to be cleaned, in particular by terminating the surface with suitable species known to those skilled in the art for bonding. The process advantageously serves to remove particles that were generated during plasma ashing and / or remained on the surface.

[0020] The cleaning of a bond surface can therefore be carried out using several of the methods mentioned. Cleaning can be performed on a single chip or on multiple chips simultaneously. In particular, individual chips can be cleaned during transport between two stations. Self-alignment

[0021] In a preferred embodiment, the chips are positioned and self-align. Self-alignment is a positioning process of an object, in this case a chip, driven by physical laws of minimization.

[0022] Self-positioning is preferably achieved by driving the chip into a position, particularly a central one, between features of the bonding surface on a bonding surface with extremely low static friction, in particular caused by a liquid deposited on the bonding surface.

[0023] It is conceivable, for example, that the bonding surface has four metallic areas, particularly metallic bonding surfaces such as contact pads, especially as part of a hybrid bonding surface or vias. The chip also has four areas on its bonding surface. If such a chip is placed on a liquid, it can be assumed that more hydrophilic areas will align with more hydrophilic areas and more hydrophobic areas with more hydrophobic areas. This will result in an alignment in which the metallic areas of the hybrid bonding surfaces will coincide.

[0024] Those skilled in the field understand that such self-alignment is more effective the higher the symmetry of the structures involved. This includes the geometry of the chip, the distances between the metallic areas of the hybrid bond surfaces, the shape of the metallic areas, etc. Preferably, the chip should be square. Furthermore, the metallic areas of the hybrid bond surface should preferably also be located at the corners of an imaginary square. A further advantage would be if the difference between the hydrophilicity and hydrophobicity of the corresponding hybrid bond areas were as large as possible. A measure of hydrophobicity or hydrophilicity is the contact angle that forms between a droplet of test liquid, especially water, and the surface being measured.Hydrophilic surfaces flatten the liquid droplet because the adhesive forces between the liquid and the surface dominate over the cohesive forces of the liquid, resulting in low contact angles. Hydrophobic surfaces lead to a more spherical shape of the liquid droplet because the cohesive forces of the liquid dominate over the adhesive forces between the liquid and the surface. Preferably, the contact angle difference between the two different hybrid bond regions mentioned is greater than 1°, preferably greater than 5°, more preferably greater than 25°, most preferably greater than 50°, and most preferably greater than 100°.

[0025] The liquid layer applied to the bond surface has a thickness of less than 2 mm, preferably less than 1.5 mm, more preferably less than 1 mm, most preferably less than 0.5 mm, and most preferably less than 0.1 mm. The liquid is preferably water. However, the use of any other liquid is also conceivable. Alcohols, ethers, acids, bases

[0026] Ethers, in particular, have a very high vapor pressure and therefore evaporate almost completely from the surface, which automatically leads to the removal of the liquid after self-alignment has been achieved. Advantageously, a pre-bond automatically forms between the surfaces after the liquid is removed.

[0027] In a particular embodiment, grooves are provided on the bonding surface of the substrate and / or the chip, especially in the dielectric areas, which facilitate or even enable the removal of the liquid after the chip has self-aligned. These grooves preferably extend from the chip surface to the edge of the chip, allowing the liquid to be removed outwards by flowing and / or evaporating, preferably automatically, and even more preferably with the assistance of gravity, which forces the liquid outwards. Bonding devices and processes

[0028] Several devices and processes for bonding chips are disclosed. These processes can be divided into single-bonding and collective-bonding processes. The corresponding devices are therefore single-bonding and collective-bonding devices, respectively. All methods and devices have in common that the bonding surfaces of the chips must be free of contamination until the bonding process. The process steps and equipment for achieving this goal are described in more detail below. Single bonding devices and methods

[0029] A single-chip bonding process refers to the state-of-the-art methods for placing chips individually, i.e., one after the other, onto other chips (C2C) or onto a wafer (C2W). Such methods have the advantage that chips of different sizes and / or different functionalities can be bonded. Singulation on a foil

[0030] In a first exemplary process, a substrate is fixed to a carrier, in particular a film (tape), and isolated into chips there. The film will be used as an exemplary example in the following sections of this document. However, the use of a rigid carrier is also conceivable. The chips are therefore only created after the substrate has been fixed to the film.

[0031] In the first process step of the procedure, the substrate, in particular the film, is fixed to a fixing device, in particular a dicing frame. If the substrate is rigid, this process step can be omitted, or the rigid substrate can be fixed to a substrate holder / carrier holder. In a second, optional process step, the bonding surface of the substrate, from which the subsequent chip bonding surfaces are created, is cleaned. This cleaning can be carried out using one of the cleaning methods already mentioned. In particular, cleaning is performed using plasma and / or liquids and / or gases. Plasma treatment preferably also results in plasma activation of the bonding surface.The bonding surface only needs to be cleaned if it has been so contaminated by previous processes that the contaminants are transferred to the film, or if contaminants are present that would later prevent and / or impair the formation of a direct bond. Preferably, however, the substrate's bonding surface is always cleaned before fixation.

[0032] In a third process step, the substrate, with its bonding surface (preferably clean and preferably plasma-activated), is fixed to the substrate. The film is designed to minimize contamination of the bonding surface after the substrate is removed from the substrate. If the substrate is rigid, it may be necessary to apply a protective layer to the substrate surface before fixing the substrate. Films usually already have such a protective layer present.

[0033] Furthermore, from the moment of contact with the bonding surface, the carrier also serves to protect it and prevents contamination. Preferably, the carrier is coated, at least in the center of the substrate, to such an extent that there is low adhesion between the bonding surface of the substrate and the carrier, while the carrier may exhibit adhesive properties in the peripheral area of ​​the substrate. The areas with high adhesive strength, i.e., with higher adhesive force, will likely generate contamination at the substrate periphery, which can preferably be neglected as long as no areas of the bonding surface from which chips are later manufactured are affected. The film is preferably designed such that the adhesive force decreases upon energy input into the film (UV, heat), thus making it easier to remove the chips later. Such films are known in the prior art.

[0034] However, films with particularly low contamination levels are preferably used for this process.

[0035] Preferably, the films incorporate adhesives that cannot penetrate the bonding surface, particularly the reservoirs created by the previously performed plasma activation. This is preferably ensured by the adhesives having a very high viscosity, which prevents penetration into the nanoporous surface. Even more preferably, the adhesive molecules are so large that penetration into the pores is impossible due to their size. The pores are particularly smaller than 10 nm, more preferably smaller than 5 nm, most preferably smaller than 1 nm, even more preferably smaller than 0.5 nm, and most preferably smaller than 0.2 nm. The pore sizes are also disclosed in WO2012100786A1. Most preferably, the adhesives are solids bound in a polymer matrix.The advantage of this design is that, after removing the film, the adhesive does not require solvent cleaning, thus preventing solvent from accumulating in the reservoir created by plasma activation on the bonding surfaces. This results in improved bonding outcomes, as solvent outgassing after bonding and the associated bubble formation at the bond interface are prevented.

[0036] The creation of such a reservoir is disclosed in publications WO2012100786A1, WO2012136267A1, WO2012136268A1, WO2012136266A1 and WO2014015899A1.

[0037] In a highly preferred embodiment, however, the carrier is coated in such a way that it can fix the substrate over its entire surface, leaves no contamination on the substrate, and the chips produced later can be easily removed.

[0038] In a fourth process step, the substrate is singulated. Singulation can be carried out using any method, provided it does not contaminate the bonding surface. Several singulation methods that ensure the cleanliness of the bonding surface during singulation will be discussed in more detail later in this publication.

[0039] In a fifth process step, the individual chips are removed from the substrate by a machine, in particular a chip bonder. In a particularly preferred embodiment, during removal and / or during transport of the chip to a further position, in particular the bonding position, the bonding surface of the chip undergoes further, and in particular continuous, cleaning. This cleaning is preferably carried out with plasma. The chips either pass through an area in which this cleaning takes place, or the removal of the chips from the substrate occurs in a chamber where this cleaning process is automated. For example, it is conceivable that the chips are removed from the substrate by the chip bonder in a plasma chamber. More preferably, after removal from the substrate, the chips are moved past an atmospheric plasma source. In particular, oxygen plasma is used, which preferably leads to the ashing of residues.

[0040] In a sixth process step, the bonding surface of the transported, isolated chip is bonded to a second bonding surface by means of a bond, in particular a direct or hybrid bond. This bonding process is preceded by a generally relatively quick alignment process of the chip relative to the second bonding surface to which it is to be bonded. Improvements for optimal bonding are discussed in more detail elsewhere in this document. This alignment process preferably takes less than 5 seconds, preferably less than 2 seconds, and most preferably less than 1 second. Methods for singulation

[0041] A key aspect of the design is maintaining the cleanliness of the bonding surface of a substrate or the chips separated from it. To ensure the cleanliness of the bonding surface, the separation processes must also cause as little contamination as possible. In particular, no burrs may form during substrate separation. This can be achieved through several different processes.

[0042] In one possible process, known as stealth dicing, a focused laser beam alters the material properties in such a way that the chips can be easily separated. The main advantage lies in the elimination of mechanical separating agents such as cutting discs. The basic operating principle of the stealth dicing process is known in the prior art.

[0043] In a second possible process, the chips are separated from each other using plasma.

[0044] In a third possible process, the chips are separated from each other using mechanical separators. In a particularly preferred embodiment, gaps are created on the bonding side before optional cleaning of the bonding surface and fixation of the substrate to the carrier. During the singulation process from the back of the substrate, the mechanical separators then encounter these pre-formed gaps. By allowing the mechanical separators to reach the void before the chips are separated, the gaps prevent contamination of the bonding surface of the individual chips.

[0045] The joints can also be used in the aforementioned separation processes, as these can also lead to contamination at the edge and / or burrs. This is particularly relevant if, for example, due to the layer structure of the chips, the fracture, especially in stealth dicing, does not run continuously vertically through the wafer. Specifically, the joints are created to prevent at least the formation of a burr on the bonding surface.

[0046] The joints can also be the result of a masking process used when depositing a material onto a surface. In such a process, no material is deposited in the masked areas. These masked areas then form the joints. Collective bonding devices and methods

[0047] Under certain circumstances, bonding chips using a single-bonding process can be disadvantageous. In particular, if the chip bonding surfaces need to be cleaned to achieve high bond quality, it can be advantageous to first position all chips on a substrate with the future bonding surface facing upwards. In this pre-fixation, all chip bonding surfaces can then be cleaned and pre-treated simultaneously, especially in a dedicated machine. In a subsequent process step, all chips are then bonded at once to the substrate or chips to be bonded.

[0048] A key quality criterion for such a collective bond is the planarity of the bond plane formed by all bond surfaces of all chips. Ideally, the bond surfaces of all chips must all coincide with each other. Temporary carriers

[0049] The following process describes the fabrication of a temporary carrier with multiple chips whose bonding surfaces coincide to perform a collective bonding process.

[0050] In a first process step, a first carrier, in particular a carrier substrate, most preferably a carrier wafer, even more preferably a film, is coated with a protective layer on a dicing frame. Especially when using a film, it is conceivable that the protective layer has already been applied to the film. Otherwise, the coating of the carrier can be carried out using the usual, known coating processes such as spin coating, spray coating, lamination, etc.

[0051] Alternatively, it is also conceivable to coat the surface of the chips with a protective layer. This can be done before the chips are cut from the wafer.

[0052] In a second process step, several chips are fixed onto the first substrate with very high alignment accuracy. This alignment is achieved primarily using alignment markers and optical systems. The alignment accuracy is better than 1 mm, preferably better than 100 µm, even more preferably better than 10 µm, most preferably better than 1 µm, and most preferably better than 100 nm.

[0053] Fixation occurs via the subsequent bonding surface of the chips. The bonding surfaces of the chips should coincide as closely as possible. Furthermore, the protective layer should be as thin as possible, have the lowest possible viscosity, and possess the highest possible elasticity to prevent the chips from penetrating the layer to different depths and thus disrupting the coincidence of their bonding surfaces. Preferably, the thickness of the protective layer should be as small as possible to largely eliminate elastic behavior. The first support thus acts as an infinitely rigid resistor, while the protective layer serves solely as a separator between the bonding surface and the first support.

[0054] The Young's modulus of a film lies between 1 GPa and 1000 GPa, preferably between 1 GPa and 500 GPa, with greater preference between 1 GPa and 100 GPa, with greatest preference between 1 GPa and 50 GPa, and with absolute preference between 1 GPa and 20 GPa. The Young's modulus of polyamides, for example, lies between 3 and 6 GPa.

[0055] The Young's modulus of a stiffer beam is between 1 GPa and 1000 GPa, preferably between 10 GPa and 1000 GPa, more preferably between 25 GPa and 1000 GPa, most preferably between 50 GPa and 1000 GPa, and most preferably between 100 GPa and 1000 GPa. The Young's modulus of some steel grades, for example, is around 200 GPa.

[0056] In a third process step, a second support, preferably a support substrate (ideally a support wafer), is coated with an adhesive. This second support is the temporary support. Unlike the protective layer from the second process step, the adhesive should be elastic and / or plastically adaptable to compensate for any height differences between the chips, ensuring that the coincidence of the chip bonding surfaces is maintained. Therefore, the adhesive should have the lowest possible viscosity and be capable of permanent deformation.

[0057] The viscosity of the adhesive at room temperature is between 10E6 mPa*s and 1 mPa*s, preferably between 10E5 mPa*s and 1 mPa*s, more preferably between 10E4 mPa*s and 1 mPa*s, and most preferably between 10E3 mPa*s and 1 mPa*s.

[0058] In a fourth process step, the back surfaces of the chips, opposite the bonding surfaces of the chips, are bonded to the temporary carrier. The coincidence of the bonding surfaces of the chips on the first carrier side is maintained, while the back surfaces deform the adhesive on the temporary carrier as necessary, in particular by flowing it due to its preferably low viscosity. After the bonding process, the thickness of the adhesive between a chip and the temporary carrier can therefore vary from chip to chip. In an extension, the adhesive between the chips can be removed. Preferably, alignment between the first carrier and the temporary carrier is achieved via alignment marks located on both. Alternatively, alignment marks can be located on the surfaces of the chips and aligned with alignment marks on the temporary carrier.Alignment systems (engl.: aligner) for aligning substrates are described in detail in the publications US6214692B1, WO2015082020A1, WO2014202106A1.

[0059] In a fifth process step, the first support with the protective layer is removed. In particular, the adhesive strength between the adhesive, the temporary support, and the chips is therefore higher than the static friction between the protective layer and the bonding surface of the chips. In a particularly preferred embodiment, the protective layer is designed such that detachment from the bonding surface of the chip is, in particular, complete and free of contamination. If the first support is a film, it can be peeled off, which facilitates removal. It may also be necessary to remove the protective layer using chemicals and / or electromagnetic radiation, in particular...

[0060] to chemically or mechanically alter UV light, visible light or infrared light and / or heat so that it loses or at least reduces its adhesive properties.

[0061] The bond strength between the protective layer and the chips is less than 1 J / m2, preferably less than 0.1 J / m2, even more preferably less than 0.01 J / m2, most preferably less than 0.001 J / m2, and most preferably less than 0.0001 J / m2.

[0062] In a sixth, optional process step, the exposed bonding surfaces of the chips are cleaned and / or plasma-activated, particularly simultaneously. This step is especially important if the removal of the first carrier from the bonding surfaces of the chips was not completely contamination-free. Cleaning all chips can be performed simultaneously, increasing the throughput of the process.

[0063] In a seventh process step, all chips fixed to the temporary carrier are simultaneously bonded to a product substrate, in particular a wafer. This also includes the possibility of bonding the chips on the temporary carrier to chips already located on the product substrate. This creates a way to successively build a chip stack on a product substrate. Preferably, alignment between the temporary carrier and the product substrate is achieved via alignment marks located on the carrier and the product substrate. It is also conceivable that alignment marks are located on the bonding surfaces of the chips and that these are aligned with alignment marks on the product substrate.

[0064] In an eighth process step, the temporary support is removed from the chips. It may be necessary to chemically modify the adhesive, or alter its mechanical properties, particularly its viscosity, using chemicals and / or electromagnetic radiation, especially UV, visible, or infrared light, and / or heat, so that it loses its adhesive properties. Preferably, the temporary support is transparent to photons from a specific wavelength region of the electromagnetic spectrum. It is preferably a glass support. This allows the use of adhesives that can be destroyed from the back side using a laser, thus enabling debonding of the temporary support from its reverse side.

[0065] In a ninth process step, the back surface of the chip is cleaned of the adhesive using one of the aforementioned cleaning methods. After this process step, any number of additional chips can be stacked on top of the existing chips to build a chip stack on the product substrate.

[0066] The positioning accuracy of the chips on the first substrate according to process step two, as well as the positioning of the chips on the temporary substrate by the collective bonding process according to process step seven, is preferably enabled or at least supported by self-alignment of the chips. The positioning accuracy is better than 1 mm, preferably better than 100 µm, more preferably better than 10 µm, most preferably better than 1 µm, and most preferably better than 100 nm. Support through self-alignment is only possible if lateral displacement of the chips relative to the first substrate and / or relative to the temporary substrate is permitted. For this to occur, the protective layer on the first substrate and / or the adhesive on the temporary substrate must have sufficiently low shear moduli or even allow plastic deformation so that the chips can shift laterally. Fixing bracket

[0067] Instead of using the aforementioned temporary carrier, it is conceivable to fix the chips onto a fixation substrate which has appropriate fixing elements. These fixing elements could be... Vacuum fixation, electrostatic fixation, magnetic fixation, gel pack fixation The chips can be directly fixed to the fixation carrier with their back surfaces. A disadvantage is that, unlike the aforementioned temporary carrier, no adhesive exists that can unify the bonding surfaces of all chips in a single plane. At best, the flexibility of a gel pack used in the aforementioned gel pack fixation allows for a similar effect. In particular, the ejector devices described later can also be used as fixation carriers. Ejector devices

[0068] In the following sections of this publication, several devices and methods are described that require the handling and fixation of chips. All disclosed methods and devices therefore relate to the already separated chips and their handling, which should always be carried out in such a way as to prevent further contamination of the bonding surface. These embodiments, referred to as ejector devices, primarily serve the purpose of fixing a large number of already separated chips in order to perform a cleaning process on them and to prepare their bonding surface for the actual bonding process. Ejector devices with recess design

[0069] One initial ejector device for treating the bonding surface of a chip and directly feeding it into a bonding process consists of storing the chips in a carrier. The carrier has recesses in which chips can be positioned and / or fixed.

[0070] In a preferred embodiment, the contours of the recesses are congruent with the contours of the chips. In another embodiment, the contours of the recesses can also deviate from the contours of the chips. In particular, the recesses are larger than the chips. This facilitates access of a cleaning fluid and / or plasma to the sides of the chips. The distance between the contour of the chip and the contour of the recess is less than 5 mm, preferably less than 1 mm, more preferably less than 0.5 mm, most preferably less than 0.1 mm, and most preferably less than 0.05 mm.

[0071] The bottom surfaces of the recesses have passages (hereinafter also referred to as feedthroughs), in particular bores, through which a lifting device can raise the chips to make them accessible to a gripper (hereinafter also referred to as a gripper head). In a particularly preferred embodiment, the height of a chip corresponds exactly to the depth of the recess. Thus, the bonding surface to be cleaned and the substrate surface coincide. Such an embodiment particularly facilitates a mechanical cleaning process. Since the chips do not protrude from the recess, they cannot be mechanically damaged. Furthermore, they do not sink into the recess and can therefore be optimally accessed by all types of cleaning equipment.Furthermore, this embodiment is ideally suited for plasma cleaning of the chips, as the seamless flatness created between the bonding surface and the substrate surface results in very high homogeneity of the plasma used. This high homogeneity ensures high reproducibility and, above all, uniform cleaning, particularly uniform plasma activation, of the bonding surfaces.

[0072] All supports specified in the publication for use in a plasma chamber should possess specific properties. In particular, the supports must be made of a conductive material. Therefore, the supports preferably consist of An electrical material, in particular ∘ A metal, in particular ∘ An alloy, in particular ▪ steel ▪ aluminum ▪ stainless steel alloys ▪ titanium ∘ A conductive ceramic, in particular ▪ doped SiC ▪ doped Si3N4

[0073] Metallic substrates are preferably coated to prevent contamination of the chips by the metals. Suitable coatings include dielectrics, particularly oxides, nitrides, or carbides. The substrate is preferably designed in two parts, with the chips mounted on a metallic disk and an aperture made of a dielectric, particularly Si, SiC, or Si3N4, placed on top for plasma activation. In this case, the aperture has similar or identical dielectric properties to the chips. This ensures the most uniform plasma possible. In particular, the aperture is even made of the same dielectric material as the chips.

[0074] The absolute value of the difference between chip height h and the depth t of the recess is less than 1 mm, preferably less than 0.5 mm, more preferably less than 0.1 mm, most preferably less than 0.05 mm, and most preferably less than 0.01 mm.

[0075] This design allows the bond surfaces of multiple chips to be treated simultaneously, resulting in an extreme increase in the efficiency of cleaning even individual chips.

[0076] After the chip is ejected to a precisely defined height, a gripper head is used to pick it up and transport it. The gripper head does not fix the chip to the bonding surface that was just cleaned, but rather to the fixing surface opposite the bonding surface. The fixing surface can become contaminated during these process steps. However, in subsequent process steps, the fixing surface can become a new bonding surface on which another chip can be placed, and therefore must then be cleaned accordingly.

[0077] In the described ejector device, the depth t of the recess is predetermined. If chips with slightly different heights h are fixed, their bonding surfaces to be cleaned no longer coincide. In this case, it is conceivable that the lifting devices perform a height correction of some chips, especially those chips whose heights h are smaller than the depths t of the recesses. Ejector device with attachment design

[0078] A second ejector device consists of a carrier containing passages, specifically bores. Unlike the first ejector design, this device has no recesses. The chips to be cleaned are fixed directly to the carrier surface. Seals separate the surrounding atmosphere from the passages. This allows the chips to be cleaned without contaminating the passages with cleaning agents, such as chemicals like fluids or plasma ions. Fixing elements can be located within the sealed space to secure the chips.

[0079] Fixing chips. The fixing elements consist of at least one of the following fixations. Vacuum fixing (preferred), electrostatic fixing, magnetic fixing, adhesive fixing, mechanical fixing (least preferred)

[0080] Vacuum fixation is preferred, as it can evacuate the passage and the space between the seals, thus pressing the chip firmly onto the seals. The seals can be solids, particularly polymers, or polymers, especially highly viscous and / or cured polymers. Preferably, the seals are waxes, adhesives, glues, etc. These polymers must be replaced regularly, as they are removed over time, particularly through cleaning processes. Masks

[0081] In an extension, particularly for the aforementioned ejector devices, a mask with an aperture is used to protect the bond surfaces of chips from contamination. The gripping of the chips always occurs via machine components that necessarily move over them. In addition to the actual gripper head and a corresponding arm at the end of which the gripper head is located, cables and wires must also move. All these machine elements necessarily contribute to the contamination of the chip bond surfaces as they move over them.

[0082] In a particularly preferred embodiment, there is relative movement between the mask with aperture and the chips. Preferably, the device on which the chips are located moves. It is also conceivable that the mask itself moves. To remove a chip, the aperture is positioned over the chip to be removed. The lifting device raises the chip to be bonded over the mask. On the upper side of the mask, a gripper head removes the chip via its back surface without touching its bonding surface and transports it to a position where it is further processed. In particular, the next step involves detecting the chip's alignment marks with a first optical system. The chip is then moved below the position to be bonded and subsequently, particularly with the aid of a second optical system, positioned with high precision relative to the bonding position and bonded.It is therefore possible that the position at which the chip is bonded is located far outside the chip removal area. Furthermore, the chip may pass through several stations before the actual bonding process, in particular alignment and / or measurement and / or cleaning, and / or testing, etc. Only the back surface of the chip is touched during the entire chip transport, but never its bonding surface. The gripper head therefore preferably secures the chip from the moment it is removed from the lifting device until the bonding process is complete.

[0083] In a particular embodiment, the product substrate onto which a chip is to be bonded is located directly above the chips to be bonded. All other chips, and thus their bonding surfaces, are protected from contamination by the mask surface. The ejector unloads the chip from the ejector device and bonds it directly onto a product substrate or onto a chip / chip stack of a product substrate. The bonding surfaces of the product substrate or the chips of the product substrate face directly towards the ejector and therefore point in the direction of gravity. The mask prevents contamination of the bonding surfaces of the chips yet to be ejected onto the ejector device. This embodiment is less preferred than the embodiment described above, in which a gripper head transports the chip to another location and bonds it there, since no further processing steps can be performed on the chip in this variant.

[0084] The mask itself must be free of contamination in all embodiments. In particular, the mask can be cleaned between placement processes using one of the aforementioned cleaning methods. The mask is primarily used for bonding processes in which a substrate to be populated with chips is positioned with its bonding surface in the direction of gravity. The mask prevents the transfer of contamination from the substrate or from moving machine elements to the chips located beneath the substrate. The masks are used particularly with the ejector devices described in detail in this publication. In these embodiments, rotation, and thus contacting of the chips on their bonding surfaces, can be avoided. The precise embodiments are explained in detail elsewhere in this publication, as well as in a figure and its accompanying description.

[0085] Furthermore, cleanrooms exhibit a top-down airflow. The air therefore always circulates from higher to lower levels, carrying dust particles with it. This airflow direction also negatively impacts the contamination of the bond surfaces. It is conceivable that near the fixtures in which multiple chips with exposed bond surfaces are fixed, particularly in the aforementioned ejector devices or fixation carriers, machines are installed that generate a lateral airflow to remove dust particles laterally. Bondhead

[0086] In a further embodiment of the invention, a fixing device for fixing and bonding a chip is described. This fixing device is also referred to as a bond head and describes the machine component responsible for fixing, transporting, and bonding the individual chip to a bonding surface. To take advantage of a clean bonding surface on the chip, it is necessary to be able to control the bonding process as precisely as possible. In particular, it is essential that a chip does not bond first at the edge, but rather that a bond wave propagates outwards from the center of the chip. The concept of the bond wave is already known to those skilled in the art from wafer-to-wafer (W2W) bonding. Reference is made here to publications WO2014191033A1, PCT / EP2016053268, PCT / EP2016056249, and PCTEP2016069307, to name just a few.

[0087] In contrast to the aforementioned W2W methods, C2W methods offer extremely high throughput. The fixation device moves at very high speed from the chip's pickup location to the bonding position and back. Due to the rapidly achieved high speeds, the accelerations are also relatively high. In particular, the acceleration in the z-direction, i.e., normal to the bonding surface, is very high. This desirable physical property can be used to construct a completely new type of fixation device, which makes it possible to shape a chip convexly solely based on inertia, thus ensuring that the center of the chip's bonding surface contacts the second bonding surface first.

[0088] The concept according to the invention is that the fixing device has spring elements at its periphery, the spring constant of which is smaller than the spring constant of a centrally located spring element. In a very particular embodiment of the invention, the fixing surface is not supported peripherally at all, i.e., spring elements are omitted peripherally.

[0089] The ratio of the spring constant of a peripheral spring element to the spring constant of a centrally located spring element is less than 1, preferably less than 0.1, more preferably less than 0.01, most preferably less than 0.0001, and most preferably less than 0.00001.

[0090] Further advantages, features, and details of the invention will become apparent from the following description of preferred embodiments and from the drawings. These show: Figure 1a, first process step of a first process, Figure 1a, second process step of a first process, Figure 1a, third process step of a first process, Figure 1a, fourth process step of a first process, Figure 1a, fifth process step of a first process, Figure 1a, sixth process step of a first process, Figure 1a, seventh process step of a first process, Figure 2a, first process step of a second process, Figure 2a, second process step of a second process, Figure 2a, third process step of a second process, Figure 2a, fourth process step of a second process, Figure 2a, fifth process step of a second process, Figure 2a, sixth process step of a second process, Figure 2a, seventh process step of a second process, Figure 2a, eighth process step of a second process, Figure 2a, ninth process step of a second process,Figure 3 a first ejector device, Figure 4 a second ejector device, Figure 5 a mask with aperture in a first embodiment, Figure 6 a mask with aperture in a second embodiment, Figure 7 a first process step of a self-alignment, Figure 7 a second process step of a self-alignment, Figure 8 a first process step of a bonding process according to the invention with a bonding head according to the invention, Figure 8 a second process step of a bonding process according to the invention with a bonding head according to the invention, ,

[0091] In the figures, identical components or components with the same function are marked with the same reference symbols.

[0092] This description only includes the embodiments that... Figures 8a,b These are embodiments of the invention. All other embodiments and examples serve to illustrate the claimed invention.

[0093] The Figure 1aFigure 1 shows a first process step of a first process for producing an end product 19 after the first process. All preparations for the production of multiple chips are carried out on a substrate 11. These preparations include the creation of all functional properties of the chip, in particular contacts 13. Furthermore, joints 12 can be pre-cut to facilitate the subsequent separation process. Due to the execution of all preparation steps, a bonding surface 7b may already be contaminated.

[0094] The Figure 1b Figure 1 shows a second process step of the first process, a cleaning step of the bonding surface 7b. In particular, the bonding surface 7b is cleaned and / or activated by plasma and / or wet chemical processes.

[0095] The Figure 1cFigure 1 shows a third process step of the first process, in which the substrate 11 is fixed to a carrier, in particular a film 15. Preferably, the film surface 15 is designed such that the substrate 11 is fixed via the bonding surface 7b, but subsequent removal of the film 15 leaves no residue on the bonding surface 7b.

[0096] The Figure 1dFigure 1 shows a fourth process step of the first process, in which the substrate 11 is separated into individual chips 7. The bonding surface 7b of the chips 7 must not be contaminated during this process. Therefore, preferably, especially in the case of mechanical separation by a separating device 16, the joints 12 are provided in the substrate 11 to allow the separation process to be completed above the bonding surface 7b. Separation by laser, especially by the known stealth technique, by chemicals, especially by etching, preferably by dry etching, by plasma, etc., is also conceivable.

[0097] The Figure 1e Figure 1 shows a fifth process step of the first process, in which the chip 7 is removed from the foil 15 by a bonding head 9, which has fixings 6. The bonding head 9 fixes the chip 7 at its back surface 7r, so that no contamination occurs on the bonding surface 7b.

[0098] The Figure 1fFigure 1 shows a sixth process step of the first process, in which the bonding head 9 bonds to the further substrate 11' after the chip 7 has been aligned relative to another substrate 11'. The bonding surface 7b is preferably a hybrid surface consisting of a dielectric surface area 20 and an electric surface area, represented by the contacts 13. In the case of such a hybrid bonding surface, a so-called prebond takes place between the dielectric surface area 20 of the bonding surface 7b of the chip 7 and a dielectric surface area 20' of the substrate 11'.

[0099] The Figure 1g Figure 19 shows the final product of the first process, consisting of the substrate 11' and several chips 7. It is conceivable to repeat the process steps mentioned above in order to stack further layers of chips 7 onto the first layer of chips 7.

[0100] The Figure 2aFigure 1 shows a first process step of a second process in which several already separated chips 7 with bonding surface 7b are fixed onto a substrate, in particular a film 15. The bonding surfaces 7b of the chips 7 must have already been cleaned and / or activated in a previous process. The chips 7 are preferably aligned and positioned by a bonding head 9 of a chip bonder. The magnified view shows the interface between the bonding surface 7b of a chip 7 and the film surface 15o of the film 15. A protective layer 17, which preferably also has adhesive properties, may be located on the film surface 15o.However, the adhesive properties between the protective layer 17 and the film surface 15o are particularly advantageous because they are greater than the adhesive properties between the protective layer 17 and the bonding surface 7b, so that when the film 15 is removed in a later process step, a bonding surface 7b that is as free from contamination as possible remains.

[0101] The Figure 2b Figure 1 shows a second process step of the second process, in which a substrate 11'' is prepared as a temporary carrier. An adhesive 18 is applied to the substrate 11'' by a known method, in particular by a centrifugal coating process.

[0102] The Figure 2cFigure 1 shows a third process step of the second process, in which the back surfaces 7r of the chips 7 are contacted with the bonding adhesive. This contacting is preceded, in particular, by the alignment of all the chips 7 fixed to each other with respect to the substrate 11'. In this process step, it is also conceivable that mechanical pressure is applied from the back of the film 15r, which is intended to ensure that the bonding surfaces 7b of all chips 7 coincide in a plane E. Plane E is the plane in which all bonding surfaces 7b of the chips 7 are to be located. In particular, plane E should be identical to the surface of the protective layer 17, which faces the chips 7. This is especially relevant if the substrate 15 is a film. For example, a roller could be rolled over the back of the film 15r.Preferably, however, full-surface pressure is applied, resulting in a homogeneous pressure distribution.

[0103] The Figure 2dFigure 1 shows a fourth process step of the second process, in which the film 15 has been removed from the bonding surfaces 7b of the chips 7. Preferably, the film 15 is peeled off. Magnification Z1 shows that a residue of the protective layer 17 may remain on the bonding surfaces 7b after removal of the film 15. In this less preferred case, the chips must be cleaned again in a further process step. Preferably, the bonding surfaces 7b are free of contamination after removal of the film 15. Magnification Z2 shows an exaggerated representation of two adjacent chips that differ in their thicknesses d1 and d2. However, the flexibility of the adhesive 18 ensures that the bonding surfaces 7b lie in the same plane E, which is an important aspect of the process.

[0104] The Figure 2eShows an optional, less preferred fifth process step of the second process, in which the bond surfaces 7b of the chips 7 were cleaned by a cleaning procedure. Magnification Z1 no longer reveals a protective layer 17.

[0105] The Figure 2f Figure 6 shows a sixth process step of the second process, in which the temporary carrier 11" equipped with the chips 7 is aligned relative to another substrate 11' and bonded. All chips 7 are bonded simultaneously.

[0106] The Figure 2gFigure 1 shows a seventh process step of the second process, in which the adhesive 18 is treated. The treatment can be chemical and / or thermal and / or carried out using electromagnetic waves, in particular using UV light or infrared. In a particularly preferred embodiment, the treatment is carried out by the temporary carrier 11". The treatment preferably results in the adhesive properties of the adhesive 18 being reduced or even completely eliminated, so that the temporary carrier 11'' can detach from the chips 7.

[0107] The Figure 2h shows an eighth process step of the second process, in which the carrier substrate 11" is removed.

[0108] The Figure 2i Figure 1 shows a ninth process step of a second process, in which the back surfaces 7r of the chips 7 are cleaned. The result is again an end product 19.

[0109] The Figure 3Figure 1 shows a first embodiment for bulk cleaning and / or plasma activation and / or bonding of chips 7. The chips 7 are located in an ejector device 1, which has recesses 2. Through-holes 3, in particular simple bores, are provided at the bottom of the recesses 2, through which a lifting device 4 can raise and lower a chip 7. Loading and / or unloading of the chips 7 can be carried out via a gripper head 5, which can fix a chip 7 exclusively at its rear surface 7r by means of a fixation 6 in order to transport it. Preferably, the bonding surfaces 7b of all chips 7 coincide within the plane E during bulk cleaning and / or plasma activation. The coincidence of all bonding surfaces 7b has the advantage of homogeneous treatment. In particular, during plasma treatment, this ensures that the plasma density is homogeneous over the entire surface.Should the chips 7 differ slightly in their thicknesses, the lifting devices can make a slight correction to ensure the coincidence of the bond surfaces 7b again.

[0110] The Figure 4 Figure 7 shows a second embodiment for mass cleaning and / or plasma activation and / or bonding of chips.

[0111] The chips 7 are located in an ejector device 1' which has seals 8. The chips 7 can be loaded and / or unloaded by a lifting device 4, which can move translationally through feedthroughs 3. Fixation is preferably achieved by fixings 6, in particular by vacuum channels, which, upon contact of the chip 7 with the seal 8, allow the creation of a vacuum in the space between the chips. The gripper head 5 has not been shown in this drawing for clarity.

[0112] The ejector devices 1, 1' therefore serve for general mass cleaning and / or plasma activation and / or bonding of individual chips 7. Furthermore, it is conceivable that the ejector devices 1, 1' themselves are designed to be so compact that they can be used as carrier wafers 11'' in the second process. In this case, the bonding surfaces 7b of the chips 7 must protrude slightly beyond the ejector surfaces 10, 10' at least before the bonding process to the substrate 11, which is automatically fulfilled for the ejector surface 10' of the ejector 1' by design. In particular, the ejector device 1' is thus suitable as a kind of fixation carrier. The fixations 6 can then also be electrostatic, magnetic, or gel pack fixations.

[0113] The Figure 5Figure 1 shows a first extension of an embodiment of the bonding process, in which, for example, the ejector device 1 can be used to pick up a chip 7 through an aperture 24 of a mask 23 by a gripper head 5. The picked-up chip 7 is transported, in particular via several stations. Optics 25 can measure the bonding surfaces 7b and / or the back surfaces 7r of the chips 7 and / or the substrate 11'. In particular, alignment marks (not shown) on the chips 7 and / or the substrate 11' can be searched for to correctly position the transported chip 7. In this extension, the substrate 11' to be mounted is therefore not located directly above the chips.

[0114] The Figure 6Figure 1 shows a second extension of an embodiment of the bonding process, in which, by way of example, the ejector device 1' can be used to bond a chip 7 through an aperture 24 of a mask 23 to a chip 7 of a substrate 11'. The idea is that the mask 23, which is made of a high-purity material that preferably has no surface contamination, protects the chips 7 on the exemplary ejector device 1' from contamination. This again demonstrates how the bonding surface 7b of the chips 7 can be protected from contamination. Of course, instead of the exemplary ejector device 1', any other type of device can be used to guide the chip 7 through the aperture 24 and bond it to the surface of another chip 7 or a substrate 11' located on the other side of the mask 23.

[0115] The Figure 7aFigure 1 shows a first process step of the self-alignment of a chip 7 on a substrate 1'. The chip 7 is deposited onto a liquid film 21 by a bonding head 9. In a particular embodiment, the liquid film 21 is not continuously distributed over the entire substrate 1', but is only present as drops or puddles at the locations where the self-alignment of the chip 7 is to take place.

[0116] It is apparent that the contacts 13 of the chip 7 are not optimally aligned with the contacts 13 of the substrate 1'.

[0117] The Figure 7bFigure 1 shows a second process step of the self-alignment of chip 7 on substrate 1'. The bonding head 9 releases the fixation to chip 7. Due to its lateral mobility caused by the presence of the liquid film 21, chip 7 now aligns itself so that the contacts 13 of chip 7 are as closely aligned as possible with the contacts 13 of substrate 1'. This is due to the different bonding properties of the dielectric and electric regions. Hydrophilic regions preferentially attract other hydrophilic regions. This interaction can preferably propagate through media with at least a partially polar character. Water is a dipole and is therefore particularly well suited for this purpose.

[0118] The Figure 8aFigure 1 shows the bonding head 9 according to the invention, consisting of a fixing surface 22 with fixings 6. Behind the fixing surface 22 are spring elements 10, 10' with different spring constants. Preferably, the spring constant of the centrally installed spring element 10 is greater than the spring constants of the peripherally installed spring elements 10'. Acceleration of the bonding head 9 in a lateral direction has no effect on the shape of the fixing surface 22.

[0119] The Figure 8bFigure 1 shows the bonding head 9 according to the invention during acceleration in the normal direction of a surface to be bonded. Due to the higher spring constant of the central spring element 10, the inertia acts less strongly on the central part of the fixing surface 22, or in other words, the central part of the fixing surface 22 follows and reacts faster than the peripheral part. The curvature is also advantageously achieved by the rapid approach to the contact surface and the existing air cushion. The dynamic pressure on the fixing surface 22 generated by the translational movement would push it symmetrically backwards with identical spring elements. However, since the peripheral spring elements 10' have a lower spring constant than the central spring element 10, they yield more easily because they are more elastic. Thus, in addition to inertia, the resulting dynamic pressure also causes curvature.This mechanical asymmetry causes the fixing surface 22, and thus the chip 7 fixed to it, to be convexly curved, creating an optimal contact point 23 for direct bonding. This eliminates the possibility of the chip 7 making initial contact laterally or directly. Reference symbol list

[0120] 1, 1' Ejector device 10, 10' Ejector surfaces 2 Recess 3 Feedthrough 4 Lifting device 5 Gripping head 6 Fixing 7 Chip 7b Bonding surface 7r Back surface 8 Seal 9 Bonding head 10, 10' Spring elements 11, 11', 11'' Substrate 12 Joints 13 Contacts 14 Frame 15 Film 15o Film surface 15r Film back 16 Separating device 17 Protective layer 18 Adhesive 19 Final product 20 Dielectric surface 21 Liquid 22 Fixing surface 23 Mask 24 Aperture 25 Optics d1, d2 Thickness E Coincidence plane t Depth Z1, Z2 Magnifications

Claims

1. A method for bonding a chip (7) on a semiconductor substrate (11') or on a further chip, wherein the chip (7) is bonded by a direct bond on the semiconductor substrate (11') or the further chip, wherein a bonding head (9) bonds the chip (7) on the semiconductor substrate (11') or the further chip in such a way that the chip (7) is bonded first in the centre and then outwards, wherein the direct bonding takes place at the bonding surfaces (7b) of the chip (7), characterised in that bonding surfaces (7b) are hybrid bonding surfaces, wherein the hybrid bonding surfaces consist of metallic or dielectric regions, wherein the bonding head (9) consists of a fixing surface (22) with fixings (6) for fixing the chip (7), wherein either i) a first concentrically located spring element (10') and peripherally installed spring elements (10) are positioned behind the fixing surface (22), wherein the spring constant of the peripherally installed spring elements (10) is less than the spring constant of the first spring element (10'), or a first concentrically located spring element (10') is located behind the fixing surface (22) and spring elements are omitted at the periphery, and ii) the acceleration of the bonding head (9) is so high in a direction normal to the bonding surface that the fixing surface and the chip (7) are curved only by reason of the mass inertia.

2. A device for bonding chips ((7) on a semiconductor substrate (11') or further chips, wherein the chips (7) can be bonded by a direct bond on the semiconductor substrate (11') or the further chips, wherein the device comprises a bonding head (9), which is designed in such a way that a chip (7) is bonded first in the centre and then outwards, wherein the direct bonding takes place at the bonding surfaces (7b) of the chip (7), characterised in that bonding surfaces (7b) are hybrid bonding surfaces, wherein the hybrid bonding surfaces consist of metallic or dielectric regions, wherein the bonding head (9) consists of a fixing surface (22) with fixings (6) for fixing the chip (7), wherein either i) a first concentrically located spring element (10') and peripherally installed spring elements (10) are positioned behind the fixing surface (22), wherein the spring constant of the peripherally installed spring elements (10) is less than the spring constant of the first spring element (10'), or a first concentrically located spring element (10') is located behind the fixing surface (22) and spring elements are omitted at the periphery, and ii) the bonding head (9) is designed in such a way that it can accelerate so highly in a direction normal to the bonding surface that the fixing surface and the chip can be curved in a convex manner solely by reason of the mass inertia.