GATE STRUCTURE AND METHOD FOR ITS MANUFACTURING

Description

[0001] The present invention relates to a gate structure (i.e., a transistor structure with an associated gate region) and a method for its fabrication. In particular, the present invention relates to a gate structuring of a field-effect transistor (FET) as a depletion type (also known as a "D-type"). State of the art

[0002] In field-effect transistors (FETs), the term "gate" refers to the terminal used to control the FET. Other terminals are the source and the drain. By varying the voltage applied to the gate, the current flow between the drain and source can be controlled. The individual terminals provide electrical contact for the switching element and, as electrodes, conduct the applied voltages and currents into the active switching region. Therefore, the gate terminal is also referred to as the control electrode or control terminal. The structural design of the gate terminal and its integration into the associated switching element is called the gate structure.

[0003] A T-shaped gate structure, a so-called T-gate, is known from US patent 2002 / 0048858 A1. In this patent, a T-gate is defined as the conductive gate region of a semiconductor device (e.g., metal-semiconductor field-effect transistor (MeSFET), high-electron mobility transistor (HEMT), etc.) whose upper region is wider than the region at the base (i.e., in direct contact with the active region of the semiconductor device, or in contact separated by a gate insulator).The advantage of such an arrangement is that an extremely short channel length can be achieved via the narrow area of ​​the gate in the semiconductor device, which allows high operating frequencies and high transconductance (German: "slope") to be achieved, while the high conductivity of the T-gate over the wider upper gate area enables high switching speeds (through virtually lossless charging and discharging of the gate capacitance).

[0004] US Patent 5,053,348 A discloses a method for fabricating a self-aligning T-gate HEMT. US Patent 2013 / 0105817 A1 also discloses a HEMT with a T-gate structure. A strain-balanced nitride heterojunction transistor (HFET) is known from US Patent 7,030,428 B2. US Patent 2017 / 0133471 A1 discloses a power FET and a method for its fabrication. Cho et al. disclose an AlGaN / GaN HEMT with low off-state leakage currents (Cho, S.-J. et al., "Low off-state Leakage Currents in AlGaN / GaN High Electron Mobility Transistors By Employing A Highly Stressed SiNx Surface Passivation Layer", WoDIM, June 27-30, 2016). JP 2008 244001 A discloses a nitride semiconductor device with low gate leakage current. Shigekawa et al. report on a study of stress effects induced by passivation films on the electrical properties of AlGaN / GaN HEMTs (Shigekawa, N. and Suehiro, S.)., "Analysis of passivation-film-induced stress effects on electrical properties in AlGaN / GaN HEMTs", IEICE Transactions on Electronics 93(8), 2010).

[0005] Particularly in so-called short-channel FETs, the blocking field of the Schottky or MIS contact may no longer be sufficient to control the current flowing through the channel when gate lengths are significantly reduced. Therefore, prior art typically employs local gate recesses in the semiconductor material or other methods that either locally reduce the electron density below the gate or allow the gate to be physically positioned closer to the channel region of the FET. However, this also invariably has a negative impact on the electron density below the gate in the on-state.

[0006] Another problem related to the effective electron density below the gate arises in the development of self-blocking HEMTs and HFETs. Typically, an optimal compromise must be achieved between the lowest possible on-resistance and the pinch-off voltage of the transistor. One tuning method is based on depleting the immediate area below the gate using the electric field of a Schottky barrier. For this to work, the gate terminal must be positioned very close to the 2DEG (two-decimal-edge) so that the intrinsically formed space charge region is able to deplete the 2DEG at 0 V gate voltage – thus blocking the transistor.This change in channel geometry reduces the maximum possible electron concentration directly under the gate, significantly increases the gate capacitance, and leads to much higher electric fields in the immediate vicinity of the gate electrode, which in turn poses a reliability problem. Therefore, to bring the gate electrode closer, local gate recesses in the semiconductor material are used, analogous to short-channel HFETs, or complex p-gate structures are employed. However, a disadvantage of these methods is that they also negatively affect the electron density under the gate in the transistor's on-state and the gate capacitance.

[0007] FETs are essentially divided into two types: depletion type (D-type) and enhancement type (E-type). Depletion-type transistors (D-transistors) are typically normally on, while enhancement-type transistors (E-transistors) are typically normally off. These transistors, due to their low parasitic resistance, are used, for example, as RF power transistors in power amplifiers (PAs). For the implementation of integrated electronic logic circuits, it is advantageous to structure and thus fabricate both transistor types on a common substrate. However, such a combination is often difficult because the two transistor types generally differ in both their internal structure and their electrical characteristics.In particular, the integration of self-blocking and self-conducting transistors on a common epitaxial wafer presents a special process technology challenge.

[0008] Typically, for such E / D integration, the epitaxial structures for the self-conducting D-transistors are first grown. Then, during the actual structuring process, the area below the gate is locally modified in the semiconductor material by means of etched gate recesses or ion implantation to alter its electronic properties. Such modifications allow for a reduction in electron density within the conduction channel and also increase the gate capacitance. In combination with the depletion zone of a Schottky or MIS structuring of the gate region, this can lead to a self-blocking behavior of the resulting transistor (E-transistor). However, local ion implantation, in particular, is very time-consuming and expensive.Furthermore, these integrative measures also lead to a negative impact on the electron density below the gate in the on-state of the transistor, and in any case, an increase in the gate capacitance and the electric field near the gate.

[0009] In addition to the previously mentioned enhancement- and depletion-type FETs, another transistor type can be distinguished based on the electron density in the active layer. In this type, the transconductance maximum occurs at a gate voltage UGS of 0 V (LN type or neutral type). The LN transistor is particularly suitable for building low-noise amplifier circuits (LNAs).

[0010] Particularly in the field of monolithic microwave integrated circuits (MMICs), it is desirable to monolithically integrate both power transistors and low-noise small-signal transistors on a single substrate. This capability would allow the integration of transmitter and receiver components (transceivers) on a common chip, i.e., on a common substrate or epitaxy basis. The two transistor types typically differ in their structure. The power transistor (PA) is usually designed to be self-blocking, while the low-noise transistor should exhibit neutral switching behavior. This integration technology (PA / LNA integration) also requires similar technological steps as described above. Furthermore, for complex circuit arrangements, the possibility of integrating all the aforementioned transistor types on a common substrate or epitaxy basis is also relevant.An epitaxial basis (E / D / LN integration) is highly desirable. This would allow, for example, the integration of appropriate logic circuits for direct processing and conversion of the transmitted signals directly on the chip, in addition to the actual transceiver.

[0011] For many microwave applications, self-blocking transistors are also of great interest because they significantly reduce the complexity of the circuit design. Until now, these self-blocking concepts have generally not been used because conventional technologies result in transistors with a significantly reduced maximum current and a considerably increased gate capacitance. These characteristics reduce the cutoff frequencies and thus degrade the microwave performance. Disclosure of the invention

[0012] It is therefore an object of the present invention to provide an alternative gate structure (i.e., a transistor structure with an associated gate region) that overcomes or at least significantly reduces the described disadvantages of the prior art. In particular, a gate structure for a field-effect transistor is to be provided which, with the same active layer, allows the common fabrication of depletion-type, enrichment-type, and / or low-noise transistors on a common substrate using a uniform method. In general, the integration of transistors with variable threshold voltages determined by the technology and not by epitaxy is to be enabled. The measures taken to form the gate structure should have no or only a minor influence on the electron density below the gate in the on-state of the transistor, i.e.,The electron population in the regions between source and gate, as well as between gate and drain, is to be completely decoupled from the choice of the threshold voltage. Thus, a FET and a method for fabricating such a FET are disclosed, wherein the FET according to the invention and the method for fabricating such a FET have a corresponding gate structure (gate structure and fabrication method).

[0013] These problems are solved according to the invention by the features of claims 1 and 2.

[0014] A gate structure (transistor structure) according to the invention comprises, as a basis, a substrate; a piezoelectric active layer with a heterojunction arranged on the substrate; a dielectric passivation layer arranged on the active layer and having a thickness between 10 nm and 1000 nm, wherein the passivation layer has a recess extending through the entire passivation layer towards the active layer, the recess having a width between 10 nm and 500 nm at the boundary with the active layer; a gate contact element arranged within the recess, the contact element extending from the active layer to above the passivation layer; an intermediate layer, the intermediate layer being formed between the contact element and the passivation layer; and a cover layer covering the contact element above the passivation layer.wherein at least one layer arranged above the active layer is formed in the area around the contact element under tensile or compressive stress with a normal stress |σ| > 200 MPa, wherein a resultant force is applied at the interface between the passivation layer and the active layer via the individual stresses in the area around the contact element, which influences the electron density in the active layer in the area below the contact element via the piezoelectric effect, wherein the normal stresses of stressed layers are in the range between ±4 GPa; and the ratio between the thickness of the passivation layer and the width of the recess at the boundary to the active layer is between 1.5:1 and 4:1.

[0015] Preferably, the substrate consists of SiC. Substrates made of Si, sapphire, GaN and AIN are also preferred.

[0016] The active layer is where the essential electrical switching and conduction processes take place. The active layer can comprise a multitude of differently structured regions or zones made of various semiconductor materials with variable doping. Preferably, the active layer can include AlGaN / GaN as the semiconductor material. Other preferred material composites include AlN / GaN, InAlN / GaN, and other ternary or quaternary compounds of Al, N, In, and Ga. In binary composites, the respective material content can range from 0% to 100%. The active layer includes at least one piezoelectric material, which, upon deformation, leads to a change in the electrical polarization of the material.

[0017] A passivation layer is defined in particular as a passive layer that spatially and functionally delimits the active layer on its side facing away from the substrate. "Passive" in this context means that this layer has no or only a minimal influence on charge transport within the switching element. A typical example of a passivation layer is a dielectric passivation layer, preferably made of SiN₂X₅. Such a passivation layer also preferably comprises SiO₂X₅, SiN₂X₅O₅, Al₂O₃, ZnO, fluorosilicate glass (FSG), benzocyclobutene (BCB), or polyimides (PI). The passivation layer can also be a spacer layer. The preferred thickness of the passivation layer is between 10 nm and 1000 nm.

[0018] In an example not covered by the claims, the passivation layer can be configured as a highly compressively or tensilely stressed dielectric layer with a normal stress |σ| > 1 GPa. In particular, the passivation layer can form a base layer covering the entire surface of the active layer for all subsequent structuring steps, with all gate structures according to the invention being built upon the wafer based on this passivation layer. For example, in a method for fabricating integrated structures, the active layer and a highly compressively or tensilely stressed passivation layer arranged thereon can be applied to the substrate in a planar manner and serve as the starting point for the fabrication of a plurality of gate structures according to the invention.

[0019] According to the invention, a recess is arranged within the passivation layer, extending through the entire passivation layer towards the active layer. This recess is a so-called gate trench (also referred to as a gate hole or gate via), which allows electrical access to the active zone through the passivation layer. A contact element is arranged in this opening within the passivation layer. The recess has a width of between 10 nm and 500 nm at the boundary with the underlying layer. The angle of inclination of the recess's side walls is preferably between 90° and 30°, with the side wall of the recess being perpendicular to the underlying layer at an angle of 90°.

[0020] The contact element is arranged within the recess and extends from the active layer to above the passivation layer. Preferably, a gate structure according to the invention is a T-gate, wherein the contact element is T-shaped. "T-shaped" is generally interpreted very broadly; in particular, such structures are often also described as mushroom-shaped, arrow-shaped, or rivet-shaped. Any other configuration of the contact element within the scope of this disclosure is also possible.

[0021] The contact element can be made of a Schottky metal. Preferably, this is ir. Also preferred are Pt, Ni, Al, Os, TiW and WSi.

[0022] Beneath the gate metal, a gate insulator may also be located, preferably consisting of Al₂O₃, SiNₓ, SiOₓ, SiNₓO₅, HfO₂, or other dielectric layers. A preferred thickness of the insulating layer is between 5 nm and 40 nm.

[0023] Preferably, the contact element is completely surrounded by the dielectric cover layer in its upper region. The cover layer can, particularly in the areas adjacent to the contact element, lie directly on the passivation layer and cover the contact element from above. The dielectric cover layer is preferably SiN₂X. SiO₂X, SiN₂XO₅, Al₂O₃, ZnO, fluorosilicate glass (FSG), benzocyclobutene (BCB), and polyimides (PI) are also preferred. The thickness of the cover layer is preferably between 10 nm and 1000 nm.

[0024] In the prior art, the layers lying on the active layer are applied with as little stress as possible. This is intended to prevent the negative effects of mechanical stresses (potentially reduced transistor lifetime, migration effects, influences on electrical charge transport) and to achieve a uniform material deposition. In contrast, according to the invention, at least one layer arranged above the active layer in the area around the contact element is formed under tensile or compressive stress with a normal stress |σ| > 200 MPa. Such stress can be achieved, for example in the passivation layer, particularly by adjusting the stress state within certain limits during the growth of the passivation layer onto the active layer by selecting the process parameters.

[0025] Modern CVD processes, such as those known from silicon technology, allow the production of compressionally or tensilely strained films in the range of ±2 GPa. With special passivation layers, such as CVD diamond layers, even much higher strains up to the range of ±4 GPa can be achieved. At these values, one is already approaching the tensile strain (tensile stress) of an AlGaN barrier on unstrained, i.e., stress-free, GaN, caused by the lattice mismatch between GaN and AlGaN. At an Al concentration of 30%, the tensile strain of such a layer is approximately 3 GPa. A passivation layer applied to the active layer and subjected to very high compression strain is therefore capable of eliminating or even inverting the piezoelectric component of the polarization vector in the active layer.

[0026] The degree of stress in a layer can be adjusted via the selected process parameters during its production. To calibrate the method, different layers are first deposited onto separate test wafers, and the stress generated by the respective process parameters is then determined by observing the wafer's deflection. However, it is also possible to determine the stress of a layer directly. A suitable method for this is fibDAC (D. Vogel, I. Maus and B. Michel, "fibDAC stress relief - A novel stress measurement approach with high spatial resolution", 3rd Electronics System Integration Technology Conference ESTC, Berlin, 2010, pp. 1-5).

[0027] It is possible that even layers applied in a manner that appear stress-free may exhibit slight stress due to manufacturing and material tolerances. Therefore, layers with a normal stress |σ| ≤ 200 MPa are still considered stress-free. Layers with a normal stress of 200 MPa < |σ| ≤ 1 GPa are considered moderately stressed, and layers with a normal stress |σ| > 1 GPa are considered highly stressed. The normal stress is positive in tensile stressed layers and negative in compressive stressed layers.

[0028] The specified values ​​for the stress (mechanical stress) preferably refer to the arithmetic mean of the local stress values ​​of a layer in the vicinity of the gate. The local stress values ​​preferably result from the vectorially added local normal stresses for different directions within a layer (e.g., for the three normal stress components σxx, σyy, σzz). Preferably, only normal stress components parallel to the active layer are considered, and these are arithmetically averaged over the layer depth. Preferably, the local stresses of a layer have a uniform magnitude and direction, at least in the vicinity of the gate; that is, the stress of the layer corresponds (at least in the vicinity of the gate) to the local stress value at every point. The vicinity of the gate is defined as a region of space immediately adjacent to the gate, i.e., surrounding the gate, e.g., within a layer.Preferably, the extent of this environment in a plane centrally enclosing the recess in the passivation layer corresponds to a maximum of 2 times, more preferably to a maximum of 3 times, more preferably to a maximum of 5 times, and even more preferably to a maximum of 10 times the area of ​​the recess. However, a property defined in the vicinity of the gate can also extend beyond this extent defined as the environment.

[0029] The passivation layer has a thickness between 10 nm and 1000 nm. The recess has a width between 10 nm and 500 nm at the interface with the underlying layer. The ratio between these two parameters (aspect ratio of thickness to width) is between 1.5:1 and 4:1, preferably between 1.75:1 and 2.25:1, and more preferably between 1.9:1 and 2.5:1. For example, the passivation layer can have a thickness between 275 nm and 325 nm, and the recess at the interface with the underlying layer can have a width between 125 nm and 175 nm. The aspect ratio, in conjunction with the geometric dimensions of the metallic T-gate, influences the parasitic properties of the transistors. Transistors for very high frequencies can have an aspect ratio of up to 4:1.

[0030] The idea of ​​the present invention is that, particularly in heterojunction-based heterojunction transistors (HFETs), the gate structure can be modified by a targeted combination with piezoelectric materials (e.g., AIN, GaN, InN, or their ternary or quaternary compounds) in the active layer such that a local reduction or even an inversion of the piezoelectric vector can be achieved in the region below the gate. This allows for both a reduction and an increase in the local electron density in the 2DEG within this region.

[0031] The functionality of the transistor depends on the type of piezoelectric materials used. For example, an AlGaN / GaN active layer allows such a wide variation in density parameters that depletion-type (D-type), enrichment-type (E-type), and / or low-noise-type (LN-type) transistors (or corresponding intermediate stages) can be built on the same material platform, i.e., without the usually necessary local structural or material modifications in the active layer, solely through the piezoelectric properties of the materials used. The electrical properties of these materials, especially their electrical polarization, can then be tailored by selectively introducing mechanical stresses into the active layer.Such local material stresses can be generated by applying and / or structuring dielectric layers under compression or tension on the active layer. These external stresses can influence the local polarization vector of the underlying active layer.

[0032] For example, in an HFET with an AlGaN / GaN heterojunction in the active layer, local tensile stress in the AlGaN layer (caused by corresponding stress in the overlying layers, which generate a corresponding "pulling" force on the surface of the active layer) can lead to a local increase in electron density within the 2DEG of the transistor channel at the boundary between the AlGaN and GaN layers. Conversely, corresponding local compressive stress can lead to a local reduction in electron density in the channel region.

[0033] If the local compression of a piezoelectric layer is combined with a depletion zone generated by a Schottky barrier, then a nearly complete depletion of the channel region can be achieved without requiring a reduction in the thickness of the epitaxial layers of the active layer. Therefore, the input and output resistances of such self-blocking transistors (E-type) not covered by the claims are not affected by their gate structure or the manufacturing method. In particular, the use of local gate recesses in the semiconductor material or complex p-gate structures according to the prior art can be dispensed with for their fabrication. Since the gate-channel spacing remains unchanged, neither the gate capacitance nor the electric fields in the immediate vicinity of the gate change.

[0034] Furthermore, by locally adjusting the piezoelectric properties of the active layer via selective structuring with applied dielectric layers, self-conducting transistors (D-type) as defined in the claims can be structured and fabricated in the same process pass using additional local tensile strain. This enables a significantly simplified E / D integration of these two types of transistors compared to the prior art, without requiring local gate recesses in the semiconductor material or ion implantation processes for integration.

[0035] If the electron density within the 2DEG of the transistor channel at the boundary between the AlGaN and GaN layers is adjusted by the strains introduced into the active layer from above, such that the maximum transconductance occurs at a gate voltage UGS of 0 V, then a particularly low-noise transistor (LN transistor), not covered by the claims, can be realized. The electron density within the 2DEG of an LN transistor thus lies between that of E and D transistors. This demonstrates that, by appropriately adjusting the strains in the gate environment, all three transistor types can be easily integrated together in the same material system.

[0036] By directly piezoelectrically influencing the channel region, a significant improvement in the electronic properties can be achieved, even in short-channel HFETs, thus overcoming the disadvantages encountered in the prior art. In particular, by reducing the polarization charges in the active layer according to the invention, such a strong reduction in electron density in the formed 2DEG can be achieved that the depletion zone below the Schottky gate extends into the buffer layer of a conventional active layer, suppressing the occurrence of typical short-channel effects and enabling simpler pinch-off of the transistor. An additional reduction in the distance between the channel and the gate is not required.

[0037] The use of piezoelectric materials to change the local electron density within the active layer or within the channel region of a transistor offers the following advantages over the prior art: 1) No additional steps are necessary for generating gate recesses, reducing the distance between the gate and the active layer, or for ion implantation. Therefore, the crystal structure in the active layer below the gate is not damaged by unnecessary material changes, which contributes to an increase in the lifetime and reliability of the transistor. 2) The effects of local compressive or tensile stress depend on the gate length, so that an increase in the technical effect can be observed, especially with short gate lengths. This allows for a particularly wide range of electronic properties, especially in short-channel HFETs. A gate structure according to the invention is therefore particularly suitable for very fast-switching transistors.3) Since the self-conducting behavior is not adjusted by reducing the gate channel spacing, the gate capacitance of self-blocking transistors not covered by the claims does not increase compared to self-conducting transistors covered by the claims. This enables extremely fast switching self-conducting transistors. 4) The deposition of layers with varying strains is technologically quite simple to implement in existing manufacturing processes. In particular, no additional process steps are required for its realization. 5) The epitaxial layers can have a greater thickness, which reduces the overall capacitance of the gate connection. This allows the switching times of the transistors to be further reduced. Integration of the different transistor types can therefore be carried out directly.6) The epitaxial layers can be designed to establish a higher electron concentration in the lead-in and lead-out regions of the gate. By incorporating a compressively strained passivation layer, the area under the gate can be specifically adjusted to optimize the gate's control behavior and prevent pinch-off problems. This makes it possible to reduce parasitic resistances such as the source or drain resistance of power transistors, thereby increasing efficiency. 7) When integrating the individual transistor types, the lead-in resistance from source to gate and from gate to drain is not affected in the case of blocking transistors compared to the application of conventional integration methods.8) Due to the improved adjustability of the switching behavior of the produced transistors by means of strained layers, the distance between the gate and channel can be greater than in the structures previously used in the prior art. This is because the electric fields near the gate scale with the distance to the channel, and thus decrease significantly according to the invention. This reduces the leakage currents and increases the reliability of the element. Furthermore, with an increased distance between the gate and channel, the input capacitance of the blocking transistors can be of the same order of magnitude as that of the conducting transistors. E / D integrated circuits are therefore particularly suitable for applications in the micro- and mm-wave range. 9) The technological implementation of the manufacturing process is comparatively simple, cost-effective, and compatible with most production lines.

[0038] In a first embodiment of a gate structure not covered by the claims, the contact element directly contacts the active layer (however, the contact element and the active layer can also be separated from each other by an intermediate gate insulator), is completely enclosed laterally by the passivation layer and is covered above the passivation layer by the cover layer.

[0039] In a second embodiment encompassed by the claims, a gate structure according to the invention further comprises an intermediate layer, wherein the intermediate layer is formed between the contact element and the passivation layer. In particular, the intermediate layer can provide complete spatial separation between the contact element and the passivation layer. Preferably, the intermediate layer completely covers the side walls of the recess in the passivation layer, with at least a portion of the bottom of the recess (i.e., the surface of the active layer) being in direct contact with the contact element. The intermediate layer can extend above the passivation layer. In particular, a section of the intermediate layer extending above the passivation layer can also contribute to spatial separation between the contact element and the passivation layer in the region above the passivation layer.In this embodiment, the top layer can also lie directly on the intermediate layer, particularly in the areas adjacent to the contact element, and cover the contact element from above.

[0040] The intermediate layer is preferably a dielectric layer made of SiN₂X. SiO₂X, SiN₂XO₅, Al₂O₃, ZnO, fluorosilicate glass (FSG), benzocyclobutene (BCB), and polyimides (PI) are also preferred. The thickness of the top layer is preferably between 10 nm and 1000 nm. The intermediate layer can also be a spacer layer.

[0041] A first embodiment of an E-transistor not covered by the claims preferably has a gate structure without an intermediate layer (first embodiment of a gate structure not covered by the claims), wherein the passivation layer is designed as a highly stressed dielectric layer with a normal voltage σ < -1 GPa and the cover layer as a stressed dielectric layer with a normal voltage σ < -200 MPa. The individual stresses in the two layers interact and generate a directed force at the surface of the active layer, which leads to a local change in the electrical polarization within the active layer via the direct piezoelectric effect. The strength of this effect can be determined, among other things, by theThe properties of the individual layer materials (active layer, passivation layer, cover layer), their thickness ratio, the geometric dimensions of the individual structural elements, and the respective degree of compressive stress achieved can be set and controlled. In particular, this also allows for complete depletion of the transistor channel, since the depletion zone can extend into the semi-insulating buffer layer of a conventional active layer.

[0042] A second embodiment of an E-transistor, also not covered by the claims, preferably has a gate structure with an intermediate layer (a second embodiment of a gate structure not covered by the claims), wherein the passivation layer is configured as a stress-free or moderately compression- or moderately tension-stressed dielectric layer with a normal voltage of -1 GPa ≤ σ ≤ 1 GPa, the intermediate layer is configured as a highly compression-stressed dielectric layer with a normal voltage of σ < -1 GPa, and the top layer is configured as a compression-stressed dielectric layer with a normal voltage σ < -200 MPa. In this embodiment as well, the electrical polarization within the active layer is locally modified via the individual compression stresses.In particular, mechanical stresses are mainly introduced into the active layer via the intermediate and top layers, while the passivation layer makes little to no contribution to the stress introduction.

[0043] A first embodiment of a D-transistor not covered by the claims preferably has a gate structure without an intermediate layer (first embodiment of a gate structure not covered by the claims), wherein the passivation layer is formed as a moderately strained dielectric layer with a normal voltage of 200 MPa < σ ≤ 1 GPa and the cover layer is formed as a strained dielectric layer with a normal voltage σ > 200 MPa.

[0044] A second embodiment of a D-transistor according to the invention, as defined by the claims, has a gate structure according to the invention with an intermediate layer (a second embodiment of a gate structure according to the invention as defined by the claims), wherein the intermediate layer and the top layer are formed as highly tensile-stressed dielectric layers with normal voltages σ > 1 GPa and the passivation layer is formed as a stress-free or moderately compression- or moderately tensile-stressed dielectric layer with a normal voltage of -1 GPa ≤ σ ≤ 1 GPa.

[0045] In both of the exemplary embodiments of a D-transistor mentioned, the individual stresses in the layers interact and also generate a directed force at the surface of the active layer. This force, via the direct piezoelectric effect, leads to a local change in the electrical polarization within the active layer. In a D-transistor, the strength of this effect can also be adjusted and controlled, among other things, by the type of individual layer materials (active layer, passivation layer, intermediate layer, top layer), their thickness ratio, the geometric dimensions of the individual structural elements, and the respective degree of applied compressive stress.

[0046] By selectively straining at least one layer located above the active layer in the region around the contact element, the force acting on the surface of the active layer can be specifically influenced in the immediate vicinity of the contact element. In particular, by locally varying the electrical polarization within the active layer, the depletion region below the gate can be reduced compared to an E-transistor not covered by the claims, which may be based on the same epitaxial structure, thus enabling depletion-type (D-type) transistor behavior.

[0047] A first embodiment of an LN transistor not covered by the claims preferably has a gate structure without an intermediate layer (first embodiment of a gate structure not covered by the claims), wherein the passivation layer and the cover layer are formed as moderately stressed dielectric layers with normal voltages -1 GPa ≤ σ < -200 MPa.

[0048] A second embodiment of an LN transistor, also not included in the claims, preferably has a gate structure with an intermediate layer (second embodiment of a gate structure not included in the claims), wherein the intermediate layer and the top layer are formed as moderately compression-stressed dielectric layers with normal voltages -1 GPa ≤ σ < -200 MPa, and the passivation layer is formed as a stress-free or moderately tension-stressed dielectric layer with a normal voltage of 0 GPa ≤ σ ≤ 1 GPa.

[0049] In an LN transistor, the maximum transconductance occurs at a gate voltage UGS of 0 V. Therefore, in addition to the voltage stresses specified for the individual layers, an LN transistor also exhibits the corresponding switching behavior of an LN transistor. In particular, the voltage stresses in the individual layers are chosen such that the switching behavior of an LN transistor is achieved.

[0050] A further aspect of the present invention, not covered by the claims, relates to a circuit arrangement comprising at least one E-transistor and at least one D-transistor, wherein the E-transistor and the D-transistor are arranged on a common substrate (E / D integration). Such an integrated circuit arrangement has, among other advantages, that the included self-conducting and self-blocking transistors can be built up, in particular, on the common substrate in one and the same epitaxial structure as the active layer. A local modification of the epitaxial structure, dependent on the transistor type, by, for example, etching, thinning, or ion implantation, is not required. The differences in switching behavior are generated solely by the layers deposited on the active layer via their local mechanical stresses and their interaction with the piezoelectric polarization vectors within the active layer.The expression "arranged on a common substrate" is preferably synonymous with "arranged on a common active layer".

[0051] Furthermore, the invention enables the realization of a D-transistor in conjunction with an LN-transistor (D / LN integration). LN-transistors are suitable as low-noise amplifier stages and enable the monolithic integration of receivers and transmitters on a single chip (transceiver). Therefore, another aspect of the present invention relates to a circuit arrangement comprising at least one D-transistor and at least one LN-transistor, wherein the D-transistor and the LN-transistor are arranged on a common substrate.

[0052] However, it is also possible to integrate an E-transistor in conjunction with an LN-transistor (E / LN integration). A corresponding circuit arrangement comprises at least one E-transistor and at least one LN-transistor, with the E-transistor and the LN-transistor arranged on a common substrate.

[0053] For complex circuit arrangements, all previously mentioned transistor types can also be integrated on a common substrate or epitaxy basis (E / D / LNA integration). In addition to the actual transceiver, corresponding logic circuits for direct processing and conversion of the transmitted signals can also be integrated on the chip. A corresponding circuit arrangement comprises at least one E-transistor, at least one D-transistor, and at least one LN-transistor, with the transistors arranged on a common substrate.

[0054] A first embodiment of a method for manufacturing a gate structure (transistor structure), not covered by the claims, comprises providing a substrate with a piezoelectric active layer having a heterojunction arranged on the substrate; applying a dielectric passivation layer with a first strain value to the active layer, wherein the passivation layer has a thickness between 10 nm and 1000 nm; creating a recess in the passivation layer, wherein the recess extends through the entire passivation layer in the direction of the active layer and has a width between 10 nm and 500 nm at the boundary with the active layer, wherein the ratio between the thickness of the passivation layer and the width of the recess at the boundary with the active layer is between 1.5:1 and 4:1;Forming a gate contact element arranged within the recess, the contact element extending from the active layer to above the passivation layer; and applying a cover layer with a second strain value, covering the contact element above the passivation layer; wherein the formation of at least one layer arranged above the active layer in the region around the contact element is subjected to tensile or compressive strain with a normal stress |σ| > 200 MPa, wherein the individual strains in the region around the contact element establish a resultant force at the interface between the passivation layer and the active layer, which influences the electron density in the active layer in the region below the contact element via the piezoelectric effect, wherein the normal stresses of strained layers are in the range between ±4 GPa.

[0055] Creating a recess in the passivation layer can be achieved by applying a suitable resist for electron beam lithography or optical lithography to the intermediate layer and then etching a mask into the resist layer to form the recess. Preferred resist materials include ZEP 520A, PMMA, PMGI, copolymers, and LOR.

[0056] The recess in the passivation layer can then be created using a structuring process suitable for the passivation layer. Due to the internal stress of a layer located above the active layer, the surface of the active layer in the area of ​​the lower corners of the recess is locally either compressed or pulled, depending on the type of stress. This external mechanical stress can lead to a local increase or decrease in the piezoelectric vector within the material of the active layer.

[0057] For the advantages and technical effects of the method, reference is made to the relevant sections in the description of the gate structure and the transistor types derived from it, or their integration. The embodiments mentioned therein and their preferred features can be directly incorporated into the corresponding method.

[0058] Particularly in structures with an AlGaN / GaN heterojunction, the polarization of the active material plays a crucial role in the formation of a 2DEG, so that those areas of the active layer which, due to the stress caused by mechanical strain, have a changed polarization vector relative to their surroundings, are enriched or depleted with charge carriers (electrons or holes, depending on the original orientation of the piezoelectric vector in the materials and material systems used).

[0059] In a second embodiment encompassed by the claims, the method for producing a gate structure, prior to forming a contact element arranged within the recess, further comprises applying an intermediate layer with a third stress value within the recess, wherein the intermediate layer is formed between the contact element and the passivation layer; and creating a second recess in the intermediate layer, wherein the second recess extends through the entire intermediate layer towards the active layer. Creating a recess in the intermediate layer can be carried out analogously to creating a recess in the passivation layer as previously described.

[0060] The stress values ​​specified in the procedure refer to the normal stresses σ in the layer. Numbering was done solely for clarity regarding the individual layers. In particular, stress values ​​not specified by the procedure can assume any value. Specifically, the stress value of a layer can also be zero (stress-free layer).

[0061] A further aspect of the present invention, not covered by the claims, relates to an integration method for manufacturing a circuit arrangement, wherein at least two different transistor types (E, D or LN transistor) are manufactured on a common substrate according to a method. Brief description of the drawings

[0062] The invention is explained below using exemplary embodiments with reference to the accompanying drawing. The drawing shows: Fig. 1 shows a schematic diagram of a conventional gate structure according to the prior art, Fig. 2 shows a schematic diagram of a first embodiment of a gate structure (E-transistor) not covered by the claims, Fig. 3 shows a schematic diagram of a second embodiment of a gate structure (E-transistor) not covered by the claims, Fig. 4 shows a schematic diagram of an alternative second embodiment of a gate structure (E-transistor) not covered by the claims, Fig. 5 shows a schematic representation of the spontaneous and piezoelectric polarization vectors in the prior art (left) and the polarization vectors of an embodiment of a gate structure not covered by the claims (right), and Fig. 6 shows a schematic diagram of an embodiment of a circuit arrangement (E / D integration) not covered by the claims. Detailed description of the drawings

[0063] Fig. 1Figure 1 shows a schematic diagram of a conventional gate structure according to the prior art. Specifically, it is a T-gate, as typically used in a HEMT or HFET. The diagram shows a gate structure with a substrate 10; an active layer 12 arranged on the substrate 10; a passivation layer 20 arranged on the active layer 12, the passivation layer 20 having a recess extending through the entire passivation layer 20 towards the active layer 12; a contact element 40 arranged within the recess, the contact element 40 extending from the active layer 12 to above the passivation layer 20; and a cover layer 50 covering the contact element 40 above the passivation layer 20.

[0064] The active layer 12 typically consists of an epitaxial structure supported by the substrate, exhibiting particularly high purity and quality. During the subsequent structuring process, the passivation layer 20 and the top layer 50 are applied with minimal stress, thus preventing mechanical stress in the materials. Point loads, in particular, can disrupt the electrical properties of the transistor and negatively impact production yield and the service life of individual components. The stress-free state of layers 20 and 50 is indicated by the points (vanishing stress vectors).

[0065] Furthermore, a typical depletion region 60 of an AlGaN / GaN HFET fabricated using conventional technology based on relaxed dielectric layers 20, 50 is shown as an example. The depletion region 60 extends only moderately into the active layer 12. To achieve a significant influence on the depletion region 60 with the same feature size, it is generally necessary to intervene in the epitaxial structure of the active layer using process technology, for example, through structural modifications or ion implantation. Particularly in short-channel transistors, such interventions can mitigate short-channel effects. However, the usual methods for adjusting the depletion region 60 are very time-consuming (additional process steps) and can reduce the initially very high quality of the epitaxial layer.

[0066] Fig. 2Figure 1 shows a schematic diagram of a first embodiment of a gate structure not covered by the claims. This can also be, in particular, a T-gate for a HEMT or HFET.The illustration shows a gate structure comprising a substrate 110; an active layer 112 arranged on the substrate 110; a passivation layer 120 arranged on the active layer 112, the passivation layer 120 having a recess extending through the entire passivation layer 120 towards the active layer 112; a contact element 140 arranged within the recess, the contact element 140 extending from the active layer 112 to above the passivation layer 120; and a cover layer 150 covering the contact element 140 above the passivation layer 120, the passivation layer 120 being configured as a highly stressed dielectric layer with a normal stress σ < -1 GPa. The cover layer 150 is also configured as a highly stressed dielectric layer with a normal stress σ < -1 GPa.In particular, the depicted gate structure can be a gate structure of an E-transistor 100 (a first embodiment of a gate structure not covered by the claims). However, by adjusting the voltage values ​​in the layers, the switching behavior of a D-transistor can also be set while maintaining the same structural design.

[0067] The active layer 112 can exist as an epitaxial structure supported by the substrate 110, exhibiting particularly high purity and quality. The passivation layer 120 and the cover layer 150 generate a directed force on the surface of the active layer, which, depending on the type of tension, either pushes or pulls the surface of the active layer, especially in the area of ​​the lower corners of the recess. Due to the depicted compression-stressed dielectric layers 120 and 150, the surface of the active layer is therefore compressed in these areas, which in Fig. 2 This is illustrated by the drawn tension vectors.

[0068] The compressive stress of the passivation layer 120 causes it to press towards the recess 122. The stress effect is therefore primarily evident in the area below the gate. Even if, as in the case of a T-gate, the material of the contact element 140 (e.g., a Schottky metal) partially covers the passivation layer 120, the stress effect remains essentially limited to the area below the gate. Similarly, the additional covering of the contact element 140 above the passivation layer 120 with a similarly stressed dielectric cover layer 150 does not alter this limitation of the effect. However, the influence of the stressed passivation layer 120 can be further increased by additional stress on the cover layer 150, or, if necessary (by reversing the polarity of the stress vector), it can also be weakened.The strengths of the individual stresses can be combined to form a resulting overall force effect on the surface of the active layer 112.

[0069] Compared to the representation of the in Figure 1In contrast to the typical depletion region 60 of an AlGaN / GaN HFET fabricated using conventional technology based on relaxed dielectric layers 20, 50, the depletion region 160 of a gate structure of the first embodiment with otherwise identical parameters shows significantly more efficient charge carrier depletion within the transistor channel. Due to the increased efficiency of charge carrier depletion, the short-channel effects that would otherwise occur in short-channel transistors can be attenuated or suppressed without any process-related modifications to the active layer. In particular, complete depletion of the transistor channel can also be achieved by combining two pressure-stressed dielectric layers 120, 150. This is possible if the depletion region extends into the semi-insulating buffer layer of a conventional active layer 112.

[0070] Fig. 3Figure 1 shows a schematic diagram of a second embodiment of a gate structure not covered by the claims. This can also be, in particular, a T-gate for a HEMT or HFET.The illustration shows a gate structure with a substrate 210; an active layer 212 arranged on the substrate 210; a passivation layer 220 arranged on the active layer 212, the passivation layer 220 having a recess extending through the entire passivation layer 220 towards the active layer 212; a contact element 240 arranged within the recess, the contact element 240 extending from the active layer 212 to above the passivation layer 220; and a cover layer 250 covering the contact element 240 above the passivation layer 220, the passivation layer 220 being configured as a stress-free or moderately compression- or tension-stressed dielectric layer with a normal stress of -1 GPa ≤ σ ≤ 1 GPa.The depicted gate structure further comprises an intermediate layer 230, which is formed between the contact element 240 and the passivation layer 220. The intermediate layer 230 is designed as a highly stressed dielectric layer with a normal voltage σ < -1 GPa. The top layer 250 is designed as a stressed dielectric layer with a normal voltage σ < -200 MPa. In particular, the depicted gate structure can be the gate structure of an E-transistor 200 (a second embodiment of a gate structure not covered by the claims). However, by adjusting the stress values ​​in the layers, the switching behavior of a D-transistor according to the invention can also be set while maintaining the same structural design.

[0071] The structure of the active layer 212 and the descriptions of the effect of the individual stresses can be analogous to the corresponding description for Figure 2 can be extracted. However, compressive stress comes into play in the area of ​​the intermediate layer 230, the effects of which on the active layer 212 are generally exactly the opposite of the effects of tensile stress. Due to the compressively stressed intermediate layer 230, the surface of the active layer 212 is mechanically stressed, especially in the area of ​​the lower corners of the second recess 232, which is also evident in Fig. 3 This is illustrated by the drawn tension vectors.

[0072] The compressive stress of the intermediate layer 230 causes it to press in the direction of the recess 232. Here, too, the stress effect is primarily evident in the area below the gate. Even the additional covering of the contact element 240 above the passivation layer 220 with a similarly stressed dielectric cover layer 250 does not alter this limitation of the exploited effect. However, the effect of the stressed passivation layer 220 can be further enhanced by additional stress on the cover layer 250, or, if necessary (by reversing the polarity of the stress vector), it can also be weakened. The strengths of the individual stresses can be combined to form a resulting overall force on the surface of the active layer 212, even in this embodiment of a gate structure.

[0073] Compared to the representation of the in Figure 2In the depletion region 160 of a gate structure of the first embodiment, the depletion region 260 of a gate structure of the second embodiment, with otherwise identical parameters, demonstrates a similarly efficient method for controlling charge carrier depletion within the transistor channel. Complete depletion of the transistor channel (E-transistor) can be achieved by applying pressure to the dielectric intermediate layer 230. This method for controlling charge carrier depletion is particularly advantageous in the context of E / D integration, as it allows E- and D-transistors to be fabricated on a common substrate in the same epitaxial structure as the active layer 212 without any process-related modifications to the active layer.

[0074] Fig. 4Figure 1 shows a schematic diagram of an alternative second embodiment of a gate structure not covered by the claims. The representation shown largely corresponds to that in Figure 2. Figure 3 The reference symbols and their assignments shown in the illustration apply accordingly. Unlike Figure 3 In the depicted gate structure, the intermediate layer 230 extends to above the passivation layer 220 and at least partially rests on it. This allows any potential tensile stress in the underlying passivation layer 220 to be at least partially compensated, so that the geometric shape of the intermediate layer 230 can also be considered as an additional tuning parameter.

[0075] Fig. 5Figure 1 shows a schematic representation of the spontaneous and piezoelectric polarization vectors in the prior art and the polarization vectors of an embodiment of a gate structure not covered by the claims. This can, in particular, be a transistor with a Ga-side AlGaN / GaN heterojunction in the active layer. If no external forces act on the active layer by means of external strain (left), then intrinsic tensile strain of the AlGaN can occur due to the lattice mismatch with GaN. The GaN layer, however, is generally strain-free due to its comparatively high material thickness (typically between 1 µm and 6 µm). In this case, only a spontaneous polarization vector can be defined in the GaN layer, while in the strained AlGaN layer, the spontaneous and the piezoelectric polarization vectors are collinearly aligned.

[0076] If an additional external pressure is applied to the active layer (right), the piezoelectric polarization vector in the AlGaN layer can be locally weakened or even inverted. This weakens the overall polarization in the AlGaN layer, resulting in fewer polarization charges at the AlGaN / GaN heterojunction. However, the pressure also locally densifies the GaN layer, so the resulting additional polarization vector further reduces the overall polarization at the AlGaN / GaN heterojunction. The resulting local reduction in polarization charges at the AlGaN / GaN heterojunction, in turn, reduces the electron density σ in the 2DEG, which can lead to an expansion of the depletion region below a Schottky gate into the buffer layer of a conventional active layer.If the pressure-induced strain extends into the GaN buffer layer, the effect may cancel itself out, as the electron density in the channel depends on the difference in the sum of the respective polarization charges in the AlGaN and GaN. If the GaN and the AlGaN are similarly pressure-strained and the spontaneous and piezoelectric piezo coefficients are similar, then no effect is observed, or it is only slight. However, the piezo constants in AlGaN are higher than those in GaN, so the effect tends to be weaker. It is preferable, however, for the active layer itself to be strain-free.

[0077] Furthermore, the piezoelectric polarization vectors exhibit a completely analogous, inverse behavior under external tensile stress at the surface of the active layer. A local increase in polarization charges at the AlGaN / GaN heterojunction leads to an increase in the electron density σ in the 2DEG. The extent of the depletion region below a Schottky gate can thus be reduced compared to an identical, stress-free design. This enables flexible local control of the electron density σ in the 2DEG below the transistor gate, which can be used particularly for simple E / D integration.

[0078] Fig. 6 Figure 1 shows a schematic diagram of an embodiment of a circuit arrangement not covered by the claims. In particular, this is an E / D integration in which an E-transistor 100, in particular a first embodiment of an E-transistor 100, is used. Fig. 2(with a gate structure without an intermediate layer 230 not included in the claims), and a D-transistor, in particular a first embodiment of a D-transistor (gate structure without an intermediate layer 230 not included in the claims) are arranged on a common substrate 110. Since the corresponding embodiments of the two transistors do not differ structurally from each other, the reference numerals and their respective assignments correspond to those in the description to Fig. 2 information provided.

[0079] The present illustration, particularly the depletion zones 160 shown, demonstrates that varying the voltages in the individual layers allows the switching behavior of adjacent transistors to be modified without requiring additional structuring effort to locally influence the electron density within the active layer 112. Thus, E / D integration can be performed on a common substrate 100 or on a common active layer 112. Accordingly, the circuit arrangement can also include the integration of LN transistors with E or D transistors 100, or a joint integration of all listed transistor types. The use of embodiments with or without an intermediate layer 230 results from the required voltage values ​​at the individual gate structures and from specifications for the layer systems used. Reference symbol list

[0080] 10 Substrate 12 Active layer 20 Passivation layer 40 Contact element 50 Cover layer 60 Depletion region 100 E-transistor 110 Substrate 112 Active layer 120 Passivation layer 122 Recess 140 Contact element 150 Cover layer 160 Depletion region 200 E-transistor 210 Substrate 212 Active layer 220 Passivation layer 222 Recess 230 Intermediate layer 232 Second recess 240 Contact element 250 Cover layer 260 Depletion region

Claims

1. D-transistor with a transistor structure, comprising: a) a substrate (110, 210); b) a piezoelectric active layer (112, 212) with a heterojunction arranged on the substrate (110, 210); c) a dielectric passivation layer (120, 220) arranged on the active layer (112, 212) and having a thickness between 10 nm and 1,000 nm, wherein the passivation layer (120, 220) has a recess (122, 222) extending through the entire passivation layer (120, 220) towards the active layer (112, 212), wherein the recess (122, 222) has a width between 10 nm and 500 nm at the boundary with the active layer (112, 212) and the ratio between the thickness of the passivation layer (120, 220) and the width of the recess (122, 222) at the boundary with the active layer (112, 212) is between 1.5:1 and 4:1; d) a gate contact element (140, 240) arranged within the recess (122, 222), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); e) an intermediate layer (230), wherein the intermediate layer (230) is formed between the contact element (240) and the passivation layer (220); and f) a cover layer (150, 250) that covers the contact element (140, 240) above the passivation layer (120, 220); g) wherein at least one layer (120, 220, 150, 250, 230) arranged above the active layer (112, 212) is tensile-stressed or compressively stressed in the area around the contact element (140, 240) with a normal stress of |σ| > 200 MPa, h) wherein a resultant force is applied at the interface between the passivation layer (120, 220) and the active layer (112, 212) via the individual stresses in the area around the contact element (140, 240), which influences the electron density in the active layer (112, 212) in the area below the contact element (140, 240) via the piezoelectric effect, wherein the normal stresses of stressed layers are in the range between ±4 GPa, characterized in that i) the intermediate layer (230) and the top layer (250) are formed as highly tensile-stressed dielectric layers with normal stresses of σ > 1 GPa, and the passivation layer (220) is formed as a stress-free or moderately compressively or moderately tensile-stressed dielectric layer with a normal stress of -1 GPa < σ < 1 GPa.

2. A method for fabricating a D-transistor with a transistor structure, comprising the following steps: a) providing a substrate (110, 210) with a piezoelectric active layer (112, 212) having a heterojunction arranged on the substrate (110, 210); b) applying a dielectric passivation layer (120, 220) with a first stress value to the active layer (112, 212), wherein the passivation layer (120, 220) has a thickness between 10 nm and 1000 nm; c) creating a recess (122, 222) in the passivation layer (120, 220), wherein the recess (122, 222) extends through the entire passivation layer (120, 220) towards the active layer (112, 212) and has a width between 10 nm and 500 nm at the boundary with the active layer (112, 212), wherein the ratio between the thickness of the passivation layer (120, 220) and the width of the recess (122, 222) at the boundary with the active layer (112, 212) is between 1.5:1 and 4:1; d) applying an intermediate layer (230) with a third stress value within the recess (222), wherein the intermediate layer (230) is formed between a gate contact element (140, 240) to be formed and the passivation layer (220); e) creating a second recess (232) in the intermediate layer (230), wherein the second recess (232) extends through the entire intermediate layer (230) towards the active layer (212); f) forming the gate contact element (140, 240) arranged within the second recess (232), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); g) applying a cover layer (150, 250) with a second stress value, which covers the contact element (140, 240) above the passivation layer (120, 220); h) wherein at least one layer (120, 220, 150, 250) arranged above the active layer (112, 212) is tensile-stressed or compressively stressed in the area around the contact element (140, 240) with a normal stress of |σ| > 200 MPa, wherein a resultant force is applied at the interface between the passivation layer (120, 220) and the active layer (112, 212) via the individual stresses in the area around the contact element (140, 240), which influences the electron density in the active layer (112, 212) in the area below the contact element (140, 240) via the piezoelectric effect, wherein the normal stresses of the stressed layers are in the range between ±4 GPa, characterized in that i) the intermediate layer (230) and the top layer (250) are formed as highly tensile-stressed dielectric layers with normal stresses of σ > 1 GPa, and the passivation layer (220) is formed as a stress-free or moderately compressively or moderately tensile-stressed dielectric layer with a normal stress of -1 GPa < σ < 1 GPa.