CIRCUIT FOR BUFFERED DATA TRANSMISSION

Description

AREA

[0001] The present invention relates to a circuit for buffered data transmission from multiple transmitters to one receiver. In particular, the present invention relates to a circuit with four data buffers (hereinafter referred to as buffers) and control logic that controls write and read accesses of the transmitter / receiver to the buffers. BACKGROUND

[0002] Circuits for buffered data transmission are known from the prior art, which feature three buffers per channel. These circuits provide a buffer for writing data and a buffer for reading data, while another buffer allows the buffer into which data is written to be swapped with the buffer from which data is read. Thus, a total of six buffers are required for two channels.

[0003] US 2017 / 293587 A1 discloses a network with routers connected to a large number of endpoints. At least one of the routers includes multiple interposers with a number of queues. At least one of the routers has a demultiplexer for each interposer, which is configured to receive multiplexed data from the interposer and forward the demultiplexed data to multiple queues. SUMMARY

[0004] The invention enriches the prior art in this respect, as circuits according to claim 1 enable a transmission of data from two transmitters to a receiver with four buffers, without restricting the write access of the transmitters to the circuit.

[0005] The term "data input," as used in the description and claims, refers in particular to a communication connection via which data can be transmitted to the circuit. Furthermore, the term "data output," as used in the description and claims, refers in particular to a communication connection via which data can be output from the circuit. The communication connections can be, for example, electrically conductive connections, by means of which current and / or voltage levels (e.g., logic levels) representing data can be transmitted to the circuit or output from the circuit.

[0006] Furthermore, the term "buffer," as used in the description and claims, refers in particular to a memory element (component) or an addressable area within a memory element (component). This means that a distinction between buffers can refer both to a logical distinction, e.g., with regard to addressable areas within a memory element, and to a distinction with regard to the memory elements (components) involved. Furthermore, the term "control logic," as used in the description and claims, refers in particular to a circuit configured to control the circuit based on an analysis of the state of the circuit or the read and / or write requests ("read / write requests") submitted to the circuit, and in particular to select from which buffer a data packet is to be provided and into which buffer a data packet is to be written.

[0007] Furthermore, the terms "valid" and "invalid," as used in the description and claims, refer specifically to the correctness of data. An invalid data packet is, for example, a data packet that was written to a buffer with a write error (and thus deviates erroneously in form and / or content from a notified data packet), or a data packet that was correctly written to the buffer but contains incorrect information (due to a previous error).

[0008] A circuit according to the invention thus enables a continuous flow of data from the transmitters (or the data generator(s)) to the receiver (or the data consumer(s)) by writing data packets to the buffers connected to the data inputs and making them available when read from the buffers. Furthermore, a circuit according to the invention enables the reception of data transmitted via redundant data channels. Redundant data channels are, in particular, data channels over which the same payload data is transmitted, with the payload data being transmitted, for example, along different (physical) transmission paths or with a time delay over the same (physical) transmission path.

[0009] The circuit can be used, for example, as a 4-buffer FIFO in automation technology, where it can be implemented in a transceiver. The transceiver can be used, for example, to forward process data from a local bus to a fieldbus (e.g., in a bus coupler or bus controller). For example, the local bus can have a logical ring topology in which data is exchanged in both ring directions (redundantly) between the bus devices.

[0010] The process data can be written to the buffers in the form of data packets / data blocks (of fixed length). The control logic can monitor that the data does not exceed a previously configured data block length. After the data has been written to a buffer, the respective sender can mark the data as "valid" or "invalid." In the event of an error, the receiver can then be supplied with data from the other buffer.

[0011] Preferably, the control logic is configured to read out data, instead of exchanging the buffer currently connected to the data output with the non-connected buffer, connect the buffer currently connected to the first data input to the data output when a read request is signaled and at the same time it is signaled that writing of first data into the buffer connected to the first data input has been completed, and connect the buffer currently connected to the second data input to the data output when a read request is signaled and at the same time it is signaled that writing of second data into the buffer connected to the second data input has been completed.

[0012] The phrase "signaled simultaneously", as used in the description and the claims, is to be understood in particular to mean that a time offset between two signals is so small that the control logic receives the later signal before the circuit has generated a control command based on the earlier signal, or that the time interval lies within an interval which the control logic waits for before generating the control command.

[0013] The first data input or the second data input can be prioritized and the control logic can be further configured to connect the buffer currently connected to the prioritized data input to the data output for reading data when a read request is signaled and at the same time it is signaled that a writing of data to the buffer connected to the first data input and a writing of data to the buffer connected to the second data input has been completed.

[0014] Thus, if data is received via both data inputs simultaneously, the data received via the prioritized data input is forwarded (first or only).

[0015] Connecting a buffer to the first data input, to the second data input, or to the data output may involve changing an address offset.

[0016] Connecting a buffer to the first data input, to the second data input, or to the data output may also involve switching between signal paths.

[0017] Preferably, the circuit is integrated into a bus participant, in particular a bus transceiver.

[0018] Preferably, the control logic is configured to set a flag when data has been validly written to a buffer and the buffer has been swapped, and to cyclically reset the flag, wherein, when the flag is set, swapping of the buffers currently connected to the first and second data inputs with another buffer is suppressed.

[0019] Preferably, the circuit is arranged in a system having a first transmitter, a second transmitter and a receiver, wherein the first transmitter is connected to the first data input, the second transmitter is connected to the second data input and the receiver is connected to the data output, and the transmitters are configured to transmit data packets to the circuit via the data inputs and to signal the end of a write operation to the circuit.

[0020] The term "data packet," as used in the description and claims, refers in particular to binary-coded information that is sent / received in a block, with the information typically being meaningfully related. Furthermore, a data packet often has a fixed structure that allows a corresponding section of the data packet to be assigned to a piece of binary-coded information.

[0021] Preferably, the receiver is configured to signal a read request to the circuit and to read a data packet via the data output of the circuit.

[0022] Preferably, the circuit comprises s+2 buffers, where s indicates the number of transmitters. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The invention is explained below in the detailed description using exemplary embodiments, with reference to drawings in which: Fig. 1 shows a circuit according to the invention according to an embodiment; Fig. 2 Processes in the circuit of the Fig. 1 illustrated for write and read accesses; Fig. 3 a flow chart for the operation of the Fig. 1 shown circuit; Fig. 4a a state diagram of the Fig. 1 shown circuit; Fig. 4b Pseudocode for Fig. 4a shown state diagram; and Fig. 5 a possible use of the Fig. 1 illustrated circuit for redundant data transmission.

[0024] In the drawings, identical and functionally similar elements are identified by the same reference symbols. DETAILED DESCRIPTION

[0025] Fig. 1 shows an exemplary circuit 100 with a first buffer A, a second buffer B, a third buffer C, and a fourth buffer D. The buffers AD can be configured as multiple addressable areas in one memory element (e.g., "DPRAM pages") or as multiple independent memory elements (e.g., multiple DPRAMs). The circuit 100 includes a first data input P1 for first data D1, a second data input P2 for second data D2, and a data output P3 for outputting data D3. A first transmitter 200 is connected to the first data input P1, a second transmitter 300 is connected to the second data input P2, and a receiver 400 is connected to the data output P3.

[0026] The circuit 100 further comprises a control logic 130. The control logic 130 is configured to connect the first data input P1 to one of the buffers AD, to connect the second data input P2 to one of the buffers AD, and to connect the data output P3 to one of the buffers AD. In particular, as shown in Fig. 1 As shown, a first switch 110 may be provided between the data inputs P1, P2 and the buffers AD, which allows a first data connection to be established between the first transmitter 200 and one of the buffers AD and, at the same time, a second data connection to be established between the second transmitter 300 and one of the buffers AD. The switchable connections allow the transmitters 200, 300 to alternately write data to each of the buffers AD. As shown in Fig. 1 As indicated, the first switch 110 (or the switch position) can be controlled by the control logic 130 via a control line.

[0027] Furthermore, as in Fig. 1 As shown, a second switch 120 may be provided between the data output P3 and the buffers AD, which makes it possible to establish a third data connection between the receiver 400 and one of the buffers AD. Through the switchable connection, data can be provided to the receiver 400 from each of the buffers AD. Like the first switch 110, the second switch 120 can also be controlled by the control logic 130 via a control line, for example, by the control logic 130 transmitting a control signal to the switches 110, 120 via the control line, which signal to the switches 110, 120 which of the buffers AD is to be connected to the transmitters 200, 300 and the receiver 400 and which of the buffers AD is not to be connected.

[0028] It is understood that the Fig. 1 The switches 110, 120 shown primarily serve to illustrate switching between different connections. However, the invention is not limited to the use of specific switches 110, 120. Rather, the switches 110, 120 shown in Fig. 1 The switches 110, 120 shown may be implemented in the form of any devices that enable switching between the buffers, ie, disconnecting an existing connection and establishing a new connection.

[0029] As in Fig. 2 As illustrated, the first transmitter 200 and the second transmitter 300 can write data to the buffer AD connected to them, and data can be provided to the receiver 400 from the buffer AD connected to it. After writing data to a buffer AD connected to a transmitter 200, 300, the respective transmitter 200, 300 can trigger a buffer swap. To do this, the respective transmitter 200, 300 can signal the logic circuit 130 that a write operation was successfully completed and the data written to the buffer AD is valid. The buffer swap can then be performed between the written buffer AD and the unconnected buffer AD.

[0030] Thus, if first data D1 has been validly written via the first data input P1 into the buffer AD currently connected to the first data input P1, the buffer AD currently connected to the first data input P1 can be swapped with the unconnected buffer AD. And if second data D2 has been validly written via the second data input P2 into the buffer AD currently connected to the second data input P2, the buffer AD currently connected to the second data input P2 can be swapped with the unconnected buffer AD. To read the data D3, the buffer AD currently connected to the data output P3 can then be swapped with the unconnected buffer AD (whereby this can be made dependent on whether the unconnected buffer AD has more recently validly written data than the buffer AD currently connected to the data output P3).

[0031] If control logic 130 is simultaneously signaled that first data D1 has been validly written via the first data input P1 into the buffer AD currently connected to the first data input P1 and second data D2 has been validly written via the second data input P2 into the buffer AD currently connected to the second data input P2, control logic 130 can further be configured to cause the buffer AD currently connected to the first data input P1 or the second data input P2 to be directly swapped with the currently unconnected buffer AD, depending on whether the first data input P1 or the second data input P2 is prioritized by circuit 100. The data input P1, P2 to be prioritized can be (fixedly) fixed or determined by control logic 130 on a case-by-case basis based on a control signal or randomly.

[0032] If the control logic 130 is simultaneously signaled that data D3 are to be made available to the receiver 400 and first data D1 has been validly written via the first data input P1 into the buffer AD currently connected to the first data input P1 or second data D2 has been validly written via the second data input P2 into the buffer AD currently connected to the second data input P2, the control logic 130 can also be configured to cause the buffer AD currently connected to the first data input P1 or the buffer AD currently connected to the second data input P2 to be directly swapped with the buffer AD currently connected to the data output P3.

[0033] In addition, if the control logic 130 is simultaneously signaled that data D3 are to be provided to the receiver 400 and first data D1 have been validly written via the first data input P1 into the buffer AD currently connected to the first data input P1 and second data D2 have been validly written via the second data input P2 into the buffer AD currently connected to the second data input P2, the control logic 130 can be configured to cause the buffer AD currently connected to the first data input P1 or the second data input P2 to be directly swapped with the buffer AD currently connected to the data output P3, depending on whether the first data input P1 or the second data input P2 is prioritized by the circuit 100.

[0034] Depending on the use of the circuit 100, the control logic 130 may implement one, several, or all of the preceding rules described in Fig. 3 illustrated by way of example using a flow chart. The transmitters 200, 300 can write data into the circuit 100 at any time, and the receiver 400 can read data from the circuit 100 at any time.

[0035] As in Fig. 4a and 4b As shown, circuit 100 has two states: "empty" and "filled." After a restart or reset, circuit 100 is in the "empty" state. If a transmitter 200, 300 and a receiver 400 simultaneously request a buffer swap in this state, the buffers AD connected to the respective transmitter 200, 300 and receiver 400 are swapped directly, and circuit 100 remains in the "empty" state. However, if only one transmitter 200, 300 requests a buffer swap in this state, the buffer AD connected to the respective transmitter 200, 300 is swapped with the free buffer ("swap buffer"), and circuit 100 switches to the "filled" state.

[0036] If, in this state, only one transmitter 200, 300 (but not the receiver 400 at the same time) requests a buffer swap, the buffer AD connected to the respective transmitter 200, 300 is swapped with the free buffer AD ("swap buffer"), and the circuit 100 remains in the "filled" state. However, if the receiver 400 requests a buffer swap, the buffer AD connected to the receiver 400 is swapped with the free buffer AD ("swap buffer") or, in the case of a simultaneous buffer swap request by the receiver 400 and a transmitter 200, 300, directly with the buffer AD connected to the respective transmitter 200, 300, and the circuit 100 transitions to the "empty" state.

[0037] In addition to the Fig. 3 , Fig. 4a and Fig. 4b In addition to the rules illustrated, the control logic 130 can also be configured to follow (arbitrary) further rules. For example, the control logic 130 can be configured to divide the operation of the circuit 100 into cycles and, after writing to and swapping a buffer AD connected to a data input P1, P2, to suppress swapping of a buffer AD subsequently written to in the same cycle. For example, the control logic 130 can be configured to set a flag (i.e., an indicator value) after writing to and swapping a buffer AD connected to a data input P1, P2 and, while the flag is set, to suppress swapping of the buffers AD connected to a data input P1, P2, wherein the flag is reset at the end of each cycle. The end of a cycle can be defined by the expiration of a time interval or by the receipt of a cycle signal.This can ensure that a faster one of two redundant data channels is prioritized.

[0038] For example, the first transmitter 200 and the second transmitter 300 may transmit redundant data D1, D2, such that, in error-free operation, the first data D1 and the second data D2 are consistent with each other and are received (essentially) simultaneously. For example, the first transmitter 200 and the second transmitter 300, as shown in Fig. 5As shown, the data producer 500 and the circuit 100 can be arranged in a ring topology, with the transmission of the data D1, D2 (in both ring directions) being redundant. For example, the data producer 500 can be configured, during error-free operation, to transmit data packets at regular intervals via the transmitters 200, 300 (which can be designed, for example, as transceivers) and the circuit 100 to the receiver 400, wherein the receiver 400 requests data packets from the circuit 100 at regular intervals or reads data packets from the circuit 100 at regular intervals. LIST OF REFERENCE SYMBOLS

[0039] 100Circuit 110First switch 120Second switch 130Control logic 200First transmitter 300Second transmitter 400Receiver 500Data producer 1000System ABuffer BBuffer CBuffer DBuffer P1First data input P2Second data input P3Data output

Claims

1. Circuit (100) with four buffers (A, B, C, D), a first data input (P1) for first data (D1), a second data input (P2) for second data (D2), a data output (P3) and a control logic (130), wherein the control logic (130) is configured to connect the first data input (P1) to a first buffer (A) of the four buffers (A-D), connect the second data input (P2) to a second buffer (B) of the four buffers (A-D), connect the data output (P3) to a third buffer (C) of the four buffers (A-D), characterized in that to disconnect the connection between the first data input (P1) and the buffer (A-D) currently connected to the first data input (P1) and establish a connection between the first data input (P1) and the currently unconnected buffer (A-D) when first data (D1) is validly written to the buffer (A-D) currently connected to the first data input (P1) via the first data input (P1), to disconnect the connection between the second data input (P2) and the buffer (A-D) currently connected to the second data input (P2) and establish a connection between the second data input (P2) and the currently unconnected buffer (A-D) when second data (D2) is validly written to the buffer (A-D) currently connected to the second data input (P2) via the second data input (P2), and to read data (D3), to disconnect the connection between the data output (P3) and the buffer (A-D) currently connected to the data output (P3) and establish a connection between the data output (P3) and the currently unconnected buffer (A-D) when the unconnected buffer (A-D) has newer validly written data.

2. Circuit (100) according to claim 1, wherein the first data input (P1) or the second data input (P2) is prioritized and the control logic (130) is also configured, when a read request is signaled and it is simultaneously signaled that first data (D1) is being written to the buffer (A-D) connected to the first data input (P1), and writing of second data (D2) to the buffer (A-D) connected to the second data input (P2) has been completed, to read data (D3), to connect the buffer (A-D) currently connected to the prioritized data input (P1, P2) to the data output (P3).

3. Circuit (100) according to claim 1 or 2, wherein connecting a buffer (A-D) to the first data input (P1), to the second data input (P2) or to the data output (P3) includes changing an address offset.

4. Circuit (100) according to claim 1 or 2, wherein connecting a buffer (A-D) to the first data input (P1), to the second data input (P2) or to the data output (P3) includes switching between signal paths.

5. Circuit (100) according to any one of claims 1 to 4, wherein the circuit (100) is integrated into a bus subscriber, in particular a bus transceiver.

6. Circuit (100) according to any one of claims 1 to 5, wherein the control logic (130) is configured to set a flag when data has been validly written to a buffer (A-D) and the connection to the buffer (A-D) has been disconnected, and cyclically reset the flag, wherein, when a flag is set, disconnection of the connection to the buffer (A-D) currently connected to the first and second data input (P1, P2) and establishment of a connection to another buffer (A-D) is disabled.

7. System (1000), with a first transmitter (200), a second transmitter (300), a receiver (400), and a circuit (100) according to any one of claims 1 to 6, wherein the first transmitter (200) is connected to the first data input (P1), the second transmitter (300) is connected to the second data input (P2) and the receiver (400) is connected to the data output (P3), wherein the transmitters (200, 300) are configured to transfer data packets via the data inputs (P1, P2) to the circuit (100) and to signal an end of a write operation to the circuit (100).

8. System (1000) according to claim 7, wherein the receiver (400) is configured to signal a read request to the circuit (100) and to read a data packet via the data output (P3) of the circuit (100).

9. System (1000) according to any one of claims 7 or 8, wherein the circuit (100) has s+2 buffers (A-D), wherein s indicates the number of transmitters (200, 300).