Device for limiting power loss when sampling a digital signal

Description

AREA

[0001] The present invention relates to a device for limiting power loss when sampling a digital signal. BACKGROUND

[0002] Sample and hold circuits are known from DE 697 37 573 T2, US 2008 / 0150590 A1, US 2011 / 002062 A1 and US 5 410 269 A.

[0003] When sampling a digital signal, the voltage or current representing the digital signal is measured at specific times and assigned to a signal value representing a range of values, e.g. a high level or a low level. SUMMARY

[0004] The invention enriches the state of the art in this respect, as devices according to the invention reduce the power loss when sampling a digital signal by reducing the current flow along the signal path during sampling pauses.

[0005] For this purpose, a device according to the invention comprises a circuit arranged in the signal path of the digital signal, wherein the circuit is configured to reduce a current flow along the signal path in response to a control signal indicating a sampling pause, wherein the circuit has a current limiting circuit, wherein the current limiting circuit has an input resistor and the current flow through the current limiting circuit is limited by the input resistor to reduce the power loss.

[0006] The term "signal path," as used in the description and claims, refers in particular to an electrically conductive connection (during sampling) between a circuit generating the digital signal (transmitter) and a circuit receiving the digital signal (receiver), through which the sampling is performed. For example, the circuit can be connected upstream of a digital input and only "pass" the digital signal when the signal present at the input is actually read.

[0007] Furthermore, the term "control signal," as used in the description and claims, is to be understood in particular as an electrical signal that, for example, controls an electronic component (e.g., a transistor) by which the circuit can be switched from a first mode, in which the digital signal is (essentially) "passed through," to a second mode, in which the current flow to the input is reduced. The control signal can, for example, have a first voltage during (sampling) pauses and a second voltage (which, for example, is greater than the first voltage) at read-in times.

[0008] Furthermore, the term "sampling," as used in the description and claims, refers specifically to the measurement and assignment of a digital signal to a signal value. In this context, the term "sampling pause," as used in the description and claims, refers specifically to a period of time during which no measurement and assignment of a digital signal to a signal value is performed, or during which an assignment made is not further used (i.e., ignored and continuously overwritten).

[0009] Preferably, the current consumption of the current limiting circuit is varied by a switching element which is controlled by the control signal.

[0010] Preferably, the digital signal comprises current / voltage levels in a lower current / voltage level range and an upper current / voltage level range. The device is configured to generate the control signal indicating a sampling pause when a sample value lies in the upper current / voltage level range and not to generate the control signal indicating a sampling pause when a sample value lies in the lower current / voltage level range.

[0011] Preferably, the device is configured to sample the digital signal at specific times, acquire a sample value, and generate the control signal indicating a sampling pause when the sample value is in the upper current / voltage level range, wherein the current / voltage level of the digital signal is reduced during the sampling pause along the signal path to limit power dissipation by the device.

[0012] Preferably, the current level of the digital signal is reduced during the sampling pause along the signal path to limit the power dissipation by the device.

[0013] The device preferably further comprises a microcontroller and a memory element and is configured to store a sample value in the memory element in response to a request signal from the microcontroller and, after storage, to display a sample pause until the microcontroller generates a next request signal.

[0014] Preferably, the device is arranged to generate the control signal indicating a sampling pause when a sampling pause is indicated and the sample value stored in the memory element corresponds to a high level.

[0015] Preferably, the device comprises a switching element which, when the control signal indicating a sampling pause is present at a control input of the switching element, switches an electrically conductive connection between the signal path and ground.

[0016] Preferably, the device is configured to generate a sample value while the control signal indicates the sampling pause and to determine, on the basis of the sample value, whether the device is operating incorrectly. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The invention is explained below in the detailed description using exemplary embodiments, with reference to drawings in which: Fig. 1 a block diagram of a device according to the invention; Fig. 2 a block diagram of another device according to the invention; Fig. 3 a circuit diagram of a current limiting circuit included in a device according to the invention; Fig. 4 a process for detecting errors; Fig. 5 a procedure for generating the control signal; and Fig. 6 shows another procedure for generating the control signal. In the drawings, identical or functionally similar elements are identified by the same reference numerals. DETAILED DESCRIPTION

[0018] Fig. 1 shows a block diagram of a device 10, which does not fall under the subject matter of the claims. The device 10 comprises a receiver 12 (e.g., a microcontroller) and a circuit 16 connected upstream of an input 14 of the receiver 12. The circuit 16 is configured, in response to a control signal S from the receiver 12 indicating a sampling pause P, to reduce a current flow I along the signal path 18 by interrupting the signal path 18 using a switch 16a. This allows the power loss during sampling of a digital signal D output by a transmitter 20 to be reduced.

[0019] This procedure is particularly advantageous when switching off the transmitter 20 (e.g. a sensor) during sampling pauses P is not possible / reasonable, for example because the transmitter 20 requires a constant power supply to function correctly. According to the invention, as in Fig. 2 As shown, a resistor is arranged parallel to switch 16a so that the current flow does not completely cease even during sampling pauses P, and input 14 does not become de-energized even during sampling pauses P. The read sample value can then be stored in a memory element 30 of receiver 12, whereby memory element 30 can be overwritten with a new (current) value with each sampling. Receiver 12 can also read the sample value from memory element 30 at any time and process it further.

[0020] Fig. 3 shows a circuit diagram of a possible embodiment of a current-limiting circuit 22 included in a device 10 according to the invention. The current-limiting circuit 22 comprises a first transistor 24 placed in the signal path, which can be opened and closed by means of a control signal S. Thus, when a sufficiently high switching voltage is applied to the base of a second transistor 26, the second transistor 26 becomes conductive, thereby reducing the voltage applied to the base of the first transistor 24. Due to the reduced base voltage, the first transistor 24 becomes high-impedance, and the current flow I through the first transistor 24 is reduced (sampling pause P).

[0021] If, however, the voltage applied to the base of the second transistor 26 is reduced during a sampling phase A, the second transistor 26 becomes high-impedance, which increases the voltage applied to the base of the first transistor 24. As a result, the first transistor 24 becomes low-impedance and the current flow I through the first transistor 24 increases. The resulting current flow I through the first transistor 24 can be adapted to the input 14 of the receiver 12 by dimensioning the resistor 28. For example, an input voltage of 220 volts can be converted into an output voltage of 11 volts, whereby the input 14 can be implemented with less powerful components.

[0022] In addition, as in Fig. 4 As illustrated, it can be checked whether input 14 of receiver 12 is functioning correctly. For example, if no change is observed in the signal Iein read by receiver 12 despite switching between sampling pauses P and sampling phases A, it can be concluded that input 14 of receiver 12 is not functioning correctly. This can be particularly advantageous for safety-related receivers 12.

[0023] Furthermore, as in Fig. 5 As illustrated, the display of individual sampling pauses P (using the control signal S) can be suppressed if the sample value I corresponds to a low level. This allows the switching effort to be reduced without a significant increase in power dissipation, since at a low level, where the current / voltage level of the digital signal D lies in a lower current / voltage level range, significantly less power dissipation occurs than at a high level, where the digital signal lies in an upper current / voltage level range. In addition, as shown in Fig. 6 As shown, a sampling phase A can be terminated immediately when a high level has been read in and stored in the memory 30 of the receiver 12, whereby the power loss can be reduced even further. LIST OF REFERENCE SYMBOLS

[0024] 10Device 12Receiver (microcontroller) 14Input 16Circuit 18Signal path 20Transmitter (sensor) 22Current limiting circuit 24Transistor 26Transistor 28Resistance 30Storage element ASample phase DDigital signal ICurrent flow PSample pause SControl signal U1Input voltage U2Output voltage

Claims

1. Device (10) for limiting a loss of performance when sampling a digital signal (D), comprising a circuit (16) arranged in the signal path (18) of the digital signal (D), wherein the circuit (16) is configured to reduce a current flow (I) along the signal path (18) in response to a control signal (S), which indicates a sampling pause (P), wherein the circuit has a current limiting circuit (22), characterized in that the current limiting circuit (22) has an input resistor (28) and the current flow (I) is limited by the current limiting circuit (22) to reduce the loss of performance through the input resistor (28).

2. Device (10) according to claim 1, wherein the power consumption of the current limiting circuit (22) is varied by a switching element, which is controlled by the control signal.

3. Device (10) according to claim 1 or 2, wherein the digital signal (D) comprises current / voltage levels in a lower current / voltage level range and an upper current / voltage level range and the device is configured to generate the control signal (S), which indicates a sampling pause (P), when a sample value is in the upper current / voltage level range and not to generate the control signal (S), which indicates a sampling pause (P), when a sample value is in the lower current / voltage level range.

4. Device (10) according to claim 3, wherein the device (10) is configured to sample the digital signal (D) at certain times, to record a sample value and to generate the control signal (S), which indicates a sampling pause, when the sample value is in the upper current / voltage level range, wherein the current / voltage level of the digital signal (D) is reduced during the sampling pause (P) along the signal path (18) to limit the loss of performance by the device (10).

5. Device (10) according to claim 4, wherein the current level of the digital signal (D) is reduced during the sampling pause (P) along the signal path (18) to limit the loss of performance by the device (10).

6. Device (10) according to any one of claims 1 to 5, further comprising: a microcontroller (12), and a memory element (30), wherein the device (10) is configured to store a sample value in the memory element (30), in response to a request signal from the microcontroller (12), and to indicate a sampling pause (P) after storage until the microcontroller (12) generates a subsequent request signal.

7. Device (10) according to claim 6, wherein the device (10) is configured to generate the control signal (S), which indicates a sampling pause (P), when a sampling pause (P) is indicated and the sample value stored in the memory element (30) corresponds to a high level.

8. Device (10) according to any one of claims 1 to 7, wherein the device (10) comprises a switching element, which switches an electrically conductive connection between the signal path (18) and the ground when the control signal (S), which indicates a sampling pause (P), is present at a control input of the switching element.

9. Device (10) according to any one of claims 1 to 8, wherein the device (10) is configured to generate a sample value, while the control signal (S) indicates the sampling pause (P), and to determine whether the device (10) is malfunctioning, on the basis of the sample value.