SLAVE DEVICE, BUS SYSTEM AND PROCEDURES

Description

TECHNICAL AREA

[0001] This application concerns slave devices, bus systems and related procedures. BACKGROUND

[0002] Bus systems enable communication between multiple bus participants. One application example is sensor systems, where several sensors, acting as slave devices, communicate with a control unit as the master device, for example, in an automotive system. In some applications, it is necessary to assign unique addresses to the different sensors so that the control unit can address each sensor individually via a shared bus.

[0003] In some conventional approaches, such addresses are often assigned to slaves, such as sensors, at the end of production or during configuration when setting up a bus system. This means that pre-configured slave devices are used. This is relatively inflexible and, moreover, can be very complex and costly in cases where multiple sensors share a single physical interface.

[0004] An address assignment method within the company is disclosed in US patent 2001 / 030904. Slaves are connected in a daisy-chain fashion, and the address assignment is sequential. SUMMARY

[0005] A method according to claim 1, a slave device according to claim 11, and a system according to claim 13 are provided. The dependent claims define further embodiments.

[0006] According to one embodiment, a method is provided comprising: In a slave device, receiving an initialization signal, in response to the initialization signal, sending an identification of the slave device via a bus, checking if a collision occurs on the bus when sending the initialization identification, if a collision occurs, setting the slave device to an inactive state, and if no collision occurs, receiving an address for the slave device after sending the identification.

[0007] According to another embodiment, a slave device is provided, comprising: A communication circuit for sending signals to a bus and receiving signals from a bus, wherein the slave device is configured to: receive an initialization signal, in response to the initialization signal, send an identification of the slave device via a bus, check if a collision occurs on the bus when sending the identification, if a collision occurs, put the slave device into an inactive state, and if no collision occurs, receive an address for the slave device after sending the identification.

[0008] The above summary serves only as a brief overview of some exemplary embodiments and should not be interpreted as limiting. In particular, other exemplary embodiments may have different features than those discussed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Fig. 1 is a diagram of a bus system according to an exemplary embodiment. Fig. 2 is a flowchart to illustrate procedures according to some exemplary embodiments. Fig. 3 shows examples of signals to illustrate implementation examples. Fig. 4 shows a driver circuit with collision detection, as used in some embodiments. Fig. 5 shows a diagram of a system according to a further embodiment. Fig. 6 shows a diagram of a system according to a further embodiment. Fig. 7 shows example signals to illustrate some implementation examples. DETAILED DESCRIPTION

[0010] The following section details various exemplary embodiments. These examples serve only for illustration and are not to be interpreted as limiting. Features or components in the described embodiments can be replaced by alternative features or components, or even omitted. Additional features or components may also be present beyond those described.

[0011] In particular, the exemplary embodiments described below primarily relate to the assignment of addresses to slave devices of a bus system during initialization. Other features of the communication system, such as details of the signaling, the protocols used, and the like, can be implemented in any conventional manner known for bus systems and are therefore not specifically described. For example, in some embodiments, communication can take place via a CAN bus, and apart from the described address assignment and its associated features and components, communication can occur as with conventional CAN bus communication.

[0012] Features and components of different embodiments can be combined. For example, variations and modifications described for one embodiment can also be applied to other embodiments and are therefore not explained again.

[0013] The Fig. 1 Figure 10 shows a block diagram of a system 10 according to an exemplary embodiment. The system of Figure 10 comprises a master device 11 and several slave devices 12 connected via a bus 13. Three slave devices 12A, 12B, and 12C are shown as an example. The number of three slave devices 12 serves only as an example, and a different number of slave devices can also be provided. The bus 13 can be any wired bus, for example, a CAN bus, a FlexRay bus, or the like. The bus 13 can be provided in various configurations, for example, a star configuration, another branched configuration like the component shown, a daisy chain configuration, and the like.

[0014] In some embodiments, as will be explained in more detail later, several slave devices can be arranged in a cluster. For example, slaves 12A and 12B are arranged in a cluster 14, which has a single connection for bus 13. A conversion from bus 13 to another communication protocol within cluster 14 is possible. Examples of this will also be explained in more detail later.

[0015] In some embodiments, the slave devices 12 are sensors, and the master device 11 is a control unit. In some embodiments, the system 10 is arranged in a vehicle, for example, a motor vehicle. In this case, the slave devices 12 can, for example, be sensors of the motor vehicle. The master device can also be referred to simply as the master, and the slave devices can be referred to simply as the slaves.

[0016] During an initialization phase of system 10, the master device 11 assigns addresses to the slave devices 12 so that they can be addressed separately, for example, to selectively read or control individual sensors. A method for such address assignment, according to some embodiments, is now described with reference to Fig. 2 explained. The procedure of Fig. 2 For example, in system 10 of the Fig. 1 or subsequent systems, and is carried out with reference to the following for better understanding. Fig. 1 described. The procedure of Fig. 2 However, it can also be done in other systems.

[0017] The procedure of Fig. 2 It starts at 20. At 21, a master facility, for example master facility 11, transmits to Fig. 1 , an initialization signal via the bus, for example bus 13 of the Fig. 1 The initialization signal signals the slave devices, for example slave devices 12 of the Fig. 1 , that the initialization is now beginning. The initialization signal can be any predetermined sequence of signals, for example, a predetermined sequence of values ​​corresponding to a logical 0 and values ​​corresponding to a logical 1, which enables the slave devices to recognize that the initialization is now about to begin.

[0018] The slave devices 12 each have a predetermined identification, which is programmed in, for example, during manufacturing. In some embodiments, a unique 32-bit sequence can be used, although other sequence lengths are also possible. The number of possible different identifications is chosen so that each manufactured slave device can be assigned a unique identification. Different ranges of identifications can be reserved for different manufacturers of slave devices.

[0019] At 22, all slaves respond simultaneously with their assigned identification. For example, all slaves send their respective assigned bit sequence.

[0020] In exemplary embodiments, a communication protocol is used that has two possible levels on the bus, assigned to a logical 0 and a logical 1. One of the levels is dominant over the other; that is, if different bus participants drive different levels, the dominant level "wins." In CAN buses, this can be implemented, for example, by actively driving one of the levels (in this case, a voltage difference between the bus lines above a threshold value corresponding to a logical 0), while the other value corresponds to a voltage difference at or near 0, which is passively established by connecting the bus lines via a resistor and corresponds to a logical 1. In this assignment, the logical 0 is dominant over the logical 1. This application also refers to a slave device "setting" a level on a bus.Depending on the implementation, this can be achieved either through active driving or by "letting it adjust itself," where the slave device is passive and, for example, the level is adjusted via a resistor without active driving.

[0021] At point 23, the slave devices detect a collision on the bus. From the perspective of a slave device, a collision occurs when the value present on the bus, e.g., voltage level, does not correspond to the identification it sends. In the above embodiment with dominant and recessive states, this occurs when another slave sends a more dominant identification than the slave that detects a collision.

[0022] Those slave devices that detect a collision are then excluded from the current "initialization round" at step 23, that is, from the loop of the Figur 2 The process currently being traversed is completed. One of the slave devices will not detect a collision (e.g., because no other slave device is driving a "more dominant" level during the transmission of identifications). The master device then assigns an address to this slave device at step 24. This slave device is thus configured with respect to its address and is removed from the initialization process at step 25, e.g., by being muted.

[0023] At step 26, it is checked whether all slave devices have received an address. If so, the process ends at step 27; otherwise, the process jumps to step 21 for the next initialization round.

[0024] An example of such collision detection will now be given with reference to the Fig. 3 briefly explained. In the Fig. 3 The signals shown serve only as a simple example for better illustration and should not be interpreted as restrictive, as signal shapes may differ depending on the implementation.

[0025] In Fig. 3 This assumes a situation where a low bus level is dominant and a high bus level is recessive, so that if one participant wants to send a low bus level and another participant wants to send a high bus level, the overall bus level will be low. This is the case, for example, with a CAN bus.

[0026] In the example of the Fig. 3 is operated by three slave devices (in Fig. 1 The diagram assumes the following: Slave 1, Slave 2, Slave 3. Data sent by Slave 1 is illustrated by curve 30, data sent by Slave 2 by curve 31, and data sent by Slave 3 by curve 32. Curve 33 shows the signal level on a bus.

[0027] After receiving the initialization signal (for example, at 21 of the Fig. 2 ) all participants begin to send their identification. This phase is also known as the arbitration phase. In the example of Fig. 3 This begins with a first bit indicating the start of a data frame (SOF, start of frame), at which all slave devices pull the bus to a low level. The bus level is therefore low at this point. Then, all participants send their identification, which in the example of... Fig. 3 It comprises 11 bits. In the example of... Fig. 3 Starting with the most significant bit number 10, down to the least significant bit 0.

[0028] Those skilled in the art will immediately recognize that in a CAN bus, arbitration ensures maximum prioritization of the bus access procedure for the lowest-priority identifier, as explained below. The participant with the highest priority (represented by a dominant address) prevails over all other participants and is permitted to transmit. This procedure is also known as CSMA-CR (Carrier Sense Multiple Access Collision Resolution) and is used here to perform address assignment. It is therefore possible to assign graded priorities to individual participants.

[0029] In the example of the Fig. 3 For all slave devices, address 1 begins with the bit sequence 11001, meaning that the slave devices send a high level for bits 10 and 9, a low level for bits 8 and 7, and a high level again for bit 6. Accordingly, the bus is also at a high level for bits 10 and 9, a low level for bits 8 and 7, and a high level again for bit 6.

[0030] The identification of Slave 1 and Slave 3 continues at bit 5 with a 0, corresponding to a low level, while for Slave 2 the identification continues with a 1, i.e., a high level. As mentioned above in the example of the Fig. 3 Since the low level is dominant, the bus level at bit 5 is low. Slave 2 can therefore detect a collision at 35, i.e., at bit 5, because the bus level does not correspond to its transmitted identification. Slave 2 is thus excluded, as is the case for 23. Fig. 2 explained. In this example, Slave 2 remains in the recessive state, that is, at the high level.

[0031] The identification of Slave 1 and 3 continues with bits 4 and 3, respectively, with bit sequence 11, meaning a high level, and the bus level is also high. For the next bit (bit 2), the bit value for Slave 1 is 1 (high level) and for Slave 3 it is low (low level). The bus level is therefore low, and as indicated by arrow 34, Slave 1 now detects a collision (low bus level, while it wants to send a high bus level corresponding to bit 1) and is eliminated. Slave 3 has thus "won" this round and sends its complete identification (0 for bit 1 and 1 for bit 0), followed by a termination bit (RPR) with a value of 0.

[0032] Subsequently, Slave 3, the only one for which no collision is detected, is assigned an address using control data and data bytes (corresponding to 24 of the Fig. 2 For the next round, Slave 3 is muted, and only Slaves 1 and 2 send their identifications. In this case, Slave 1 will win next, as Slave 2 will again detect a collision at 35. Finally, Slave 2 will be assigned an address. As can be seen, in the Fig. 3 In the approach shown, where 0 is dominant and the most significant bit is sent first, the slave device with the lowest identification always wins. In other implementations, the least significant bit can also be sent first, in which case the lowest address does not automatically "win".

[0033] Even if the identification in Fig. 3 While the representation is shown as 11-bit values ​​(bits 0 to 10), more or fewer bits can also be used. For example, some implementations can use a 32-bit value, resulting in over 4,000,000,000 possible identifications. Different manufacturers of slave devices can be assigned different ranges of identifications that they can use for their products. Here, a portion of the bits can be assigned a code that identifies the manufacturer.

[0034] The following section explains various collision detection methods and corresponding systems in more detail. Fig. 4 Figure 1 shows a transmit and collision detection circuit with collision detection via a transmit line TxD, on which a transmit signal is sent by a slave device, in particular for identification purposes. The transmit signal can then be converted to a bus signal by a line driver.

[0035] When switching the Fig. 4 A PMOS transistor 42 is connected between a transmit terminal 47 and a positive supply voltage 45, and an NMOS transistor 43 is connected between the transmit terminal 47 and ground 46. In normal operation (after the initialization phase described above), the PMOS transistor 42 acts as a push transistor and the NMOS transistor 43 as a pull transistor, selectively connecting the transmit terminal 47 to either the positive supply voltage 45 or ground 46. For example, the positive supply voltage 45 can correspond to a logic 1 and ground 46 to a logic 0. The transistor 42 exhibits similar behavior to the transistor 43, for example, through appropriate dimensioning, so that in this case the push transistor and pull transistor are approximately equal in strength, i.e., they have a similar current-driving capability.

[0036] For transmitting the identification during the initialization phase, a PMOS transistor 41 is used instead of PMOS transistor 42. This transistor is also connected between the positive supply voltage 45 and the transmit output 47. PMOS transistor 41 has a lower current conductance than PMOS transistor 42, meaning it has a lower current conductance and / or a higher resistance Ron when switched on. This means that when transmitting the identifications, the PMOS transistor 45, acting as a push transistor, is weaker than the NMOS transistor 43, acting as a pull transistor. If a transmit circuit like the one shown in... Fig. 4 As shown, during identification, one slave sends a logic 1 corresponding to a high level of the supply voltage 45 (by closing transistor 45 and opening transistor 43), and another slave sends a logic 0 corresponding to the low level of ground 46 using a similar transmitting circuit (by closing the corresponding transistor 43 and opening transistor 41). Therefore, the overall logic 0 on the transmit line TxD corresponds to the ground level (since the transistor 45 used here is weaker). In the slave sending the logic 1, this is detected as a collision by a collision detection circuit 40, 44. Specifically, an inverter 40 supplies a logic gate 44 with an inverted version of the signal on the transmit line TxD, as well as a control signal s, which is used to control transistors 41, 43.The logic gate 44 then determines whether the level on the transmit line TxD corresponds to the level intended based on the control signal s.

[0037] In particular, in the event of a collision, the signal s controls transistor 41 to be closed and transistor 43 to be open, while a low voltage corresponding to ground potential is still present at the transmit output 47. In this case, logic gate 44 outputs a corresponding collision signal c.

[0038] It should be noted that, in principle, a reverse logic is also possible in other embodiments, with a weaker pull transistor that replaces transistor 43 during initialization.

[0039] Distinguishing between the initialization phase and a later operating phase, in which transistor 42 is used, can be achieved, for example, by means of an address flag in a slave device. Once an address has been assigned to the slave device, the address flag is set, and transistor 42 is used instead of transistor 41.

[0040] The transmit and collision detection circuit of the Fig. 4 This can be used particularly in cases where several slave devices are arranged in a cluster, sharing a single line driver for a bus, such as a CAN bus. An example of such a system 50 is shown in Fig. 5 depicted.

[0041] The System 50 of Fig. 5 The system comprises a master unit 51 and several slave clusters 52, of which a first slave cluster 52A and a second slave cluster 52B are shown. The number of two slave clusters 52A, 52B is only an example; there may be only one slave cluster or more than two. The slave clusters 52 can, for example, each be implemented on a single chip.

[0042] The master unit 51 is connected to the slave clusters 52 via a bus 53. In the example of the Fig. 5 Bus 53 is a CAN bus with two lines: BusH and BusL.

[0043] The master unit 51 includes a microcontroller 54 (MC) and a line driver 55 for driving the BusH and BusL lines of the bus 53. The microcontroller 54 sends data to be transmitted via a transmit line TxD and a receive line TxD to the line driver 55 and receives data from the line driver via a receive line RxD. The transmitted data includes the data described in 21. Fig. 2 initialization signal sent, as well as the one at 24 in Fig. 2 assigned address, and the received data includes the identifications sent by the slave devices.

[0044] In the exemplary embodiment of the Fig. 2 Slave clusters 52A and 52B are essentially identical in design. Therefore, only slave cluster 52A will be described in detail below, and the explanations apply accordingly to slave cluster 52A. Other configurations may have different slave clusters, for example, comprising different numbers or types of slave devices.

[0045] The slave cluster 52A comprises a line driver 56 for communication via the bus 53 and a number of sensors 57, which serve as examples of slave devices. In the example shown in Fig. 5A, the slave cluster 52A includes a first sensor 57A and a second sensor 57B. In other embodiments, more than two sensors 57 may be provided. The sensors 57A and 57B communicate with the line driver 56 via a transmit line TxD and a receive line RxD. Data to be sent via the bus 53, such as the identification described above, is transmitted via the transmit line TxD. Data is received via the bus 53 via the receive line RxD, for example, the initialization signal, which the master device 51 sends at 21 of the Fig. 2 sends, as well as the assigned address (24 of the Fig. 2 ).

[0046] If sensors 57A and 57B transmit different levels on the transmit line TxD, this can occur as described in the following: Fig. 4 explained by the transmission and collision detection circuit located there. Collision detection is performed in the same way for slaves of different slave clusters 52, whereby the corresponding level that a slave of one slave cluster sends is also transmitted to the transmission lines TxD of the other slave clusters 52 via the line drivers 56 of the slave clusters 52 (in the example of the Fig. 5 is transmitted with two slave clusters of the other slave cluster.

[0047] The addresses assigned using the method discussed here are then stored in the respective address registers 58A, 58B of the sensors 57A, 57B.

[0048] In other embodiments, collision detection can be achieved through a feedback function, in which the transmitted signal sent to the bus is fed back onto receive lines. Collision detection can then be performed by comparing the transmitted signal with the signal on the receive line. An example system for this is shown in Fig. 6 depicted.

[0049] A System 60 of Fig. 6 It comprises a master unit 61 and a plurality of slave units 62, of which four slave units 62A, 62B, 62C and 62D are shown as an example. The slave units 62 are connected to the master unit 61 via a bus 63, which in the example of the Fig. 6 is designed as a two-wire bus with two bus lines BusH, BusL, in particular as a CAN bus.

[0050] The master unit 61 has a microcontroller 64 and a line driver 65, which, like the microcontroller 54, are referred to as line driver 55 of the master unit 51. Fig. 5 They are being worked on and therefore cannot be described in detail again.

[0051] In system 60, the slave devices 62A to 62D are identically configured. Therefore, only slave device 62A will be explained in detail below, and the description applies accordingly to slave devices 62B to 62D. In other embodiments, the slave devices may be configured differently.

[0052] The slave device 62A comprises a line driver 66 and a sensor 67. In other versions, other components may be provided instead of the sensor 67.

[0053] The sensor 67 sends incoming signals via a transmit line TxD to the line driver 66 and receives receive signals via a receive line RxD from the line driver 66, which accordingly converts signals between the bus 63 and the lines TxD and RxD. In particular, the sensor 67 sends in response to an initialization signal as described in 21. Fig. 2 his identification (at 22 in Fig. 2 ) and, if it does not detect a collision, receives an assigned address (for example, at 24 of the Fig. 2 This address is then stored in an address register 68.

[0054] For collision detection, during the initialization phase, when the identification is sent, the corresponding value on bus 63 is looped back onto the receive line RxD as a received signal. By comparing a transmitted signal on the transmit line TxD with this received signal, a collision can be detected if the received signal differs from the transmitted signal (for example, if sensor 67 sends a recessive value and another sensor sends a dominant value). In this way, collisions can be detected. The transmission speed for sending the identification is chosen so that collision detection can still occur even with a loop delay during the feedback process. This delay depends, for example, on the cable length used. It should be noted again that the signals of the Fig. 7 These are just one example and should not be seen as limiting.

[0055] To further illustrate, the Fig. 7 a more detailed example of signals, such as those used in the system by the Fig. 6 These signals may be present. For simplicity, the signals for one master device and two slave devices are shown.

[0056] In the example of Fig. 7 The master facility (for example, master facility 51 of the Fig. 5 or the master facility 61 of the Fig. 6 ) first an initialization signal (for example at 21 of the Fig. 2 ). In the example of the Fig. 7 The initialization signal consists of three hexadecimal repetitions of 0x55h (corresponding to 3 bytes), alternating between 1 and 0, each byte separated by a start / stop bit. This threefold repetition provides redundancy in case a slave fails to correctly identify the initialization signal on the first attempt. However, any other bit sequence that can be uniquely identified as an initialization signal by the slave devices can also be used. During this phase, in Fig. 7 When a device is designated as "Master," a corresponding signal is present on the bus.

[0057] After the initialization signal is received, the slave devices respond with their identifications. These begin with a start bit followed by a 4-byte (32-bit) identification, with the 4 bytes separated by a stop bit. In the example of the Fig. 7 The first byte, containing the most significant bits (MSB) for both slave devices, is 00011011, so there is no collision here. The next byte of the identification (in Fig. 7 The third byte (referred to as the 3rd byte) is 11111000 for the first slave and 11111001 for the second slave, resulting in a collision at the last bit. Again, it is assumed that 0 is dominant over 1, so a level corresponding to 0 is present on the bus. The second slave thus detects a collision (it wants to drive a 1 onto the bus, but the bus shows a 0) and therefore disengages, muting itself, for example, to the recessive state. This is in Fig. 7 marked with reference number 70.

[0058] The first slave continues to send its identification (in Fig. 7 (designated with the 2nd byte and 1st byte) and is then assigned its address, as already explained. The first slave is then eliminated in the following round, so that in the case of two slave devices as in Fig. 7 The second slave device is assigned an address.

[0059] Thus, with the embodiments discussed here, an address can be assigned to a large number of slaves, whereby collision detection ensures that only one slave receives an identification at any given time.

Claims

1. A method comprising: in a slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D), - receiving an initialization signal, - in response to the initialization signal, transmitting an identification of the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) via a bus (13; 53; 63), characterized in that the method further comprises: - checking whether a collision occurs on the bus (13; 53; 63) when transmitting the initialization identification, - if a collision occurs, setting the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) in an inactive state, and - if no collision occurs, receiving an address for the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) after transmitting the identification.

2. The method of claim 1, wherein checking whether a collision exists on the bus (13; 53; 63) comprises determining that a collision exists if a level on the bus (13; 53; 63) does not correspond to an expected value based on the transmitted identification.

3. The method of claim 1 or 2, wherein the bus (13; 53; 63) has a dominant level or a recessive level, and wherein a collision exists on the bus (13; 53; 63) if, when transmitting the identification, the recessive level is set on the bus (13; 53; 63) by the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) and the dominant level is present on the bus (13; 53; 63).

4. The method of claim 3, wherein the method comprises transmitting a further identification by a further slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) in response to the initialization signal, and wherein the collision exists on the bus (13; 53; 63) if the further slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) sets the dominant level on the bus (13; 53; 63).

5. The method of any one of claims 1 to 4, wherein the checking whether a collision exists on the bus (13; 53; 63) is based on a signal on a transmit line (TxD) of the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D).

6. The method of any one of claims 1 to 5, wherein the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) is located in a slave cluster (52A, 52B) in which multiple slave devices (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) share a bus interface (56).

7. The method of claim 5 or 6, wherein the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) uses a push-pull driver to transmit the identification, wherein one push transistor or push-pull transistor of the push-pull driver is weaker than the other one of the push transistor or pull transistor.

8. The method of any one of claims 1 to 7, wherein the checking whether a collision exists is based on a signal on a receive line (RxD) of the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D).

9. The method of any one of claims 1 to 8, further comprising transmitting the initialization signal by a master device (11; 51; 61) and transmitting the address by the master device (11; 51; 61).

10. The method of any one of claims 1 to 9, wherein the method is repeated at least until an address is assigned to the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) .

11. A slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) comprising: a communication circuit for transmitting signals to a bus (13; 53; 63) and for receiving signals from the bus (13; 53; 63), wherein the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) is configured to: - receive an initialization signal, characterized in that the slave device is further configured to: - in response to the initialization signal, transmit an identification of the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) via the bus (13; 53; 63), - check whether a collision occurs on the bus (13; 53; 63) when transmitting the identification, - if a collision occurs, set the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) in an inactive state, and - if no collision occurs, receive an address for the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) after transmitting the identification.

12. Slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) according to Claim 11, wherein the slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) is configured to carry out the method according to one of Claims 2 to 8.

13. System (10; 50; 60) comprising a slave device (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) according to Claim 11 or 12, and a master device (11; 51; 61) which is configured to transmit the initialization signal and to transmit the address.

14. System (10; 50; 60) according to Claim 13, comprising a plurality of slave devices (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D), wherein the master device (11; 51; 61) is configured to transmit the initialization signal again after transmitting the address until all slave devices (12A, 12B, 12C; 57A, 57B; 62A, 62B, 62C, 62D) are assigned an address.