CHARGE TRANSFER DEVICE WITH AN OPENER FOR CLOCK FREQUENCIES FROM 100 MHz

Description

[0001] The invention relates to a semiconductor structure with a charge transfer channel for clock frequencies in the range from 100 MHz, preferably from 250 MHz, particularly preferably up to 400 MHz.

[0002] At clock frequencies above 100 MHz, especially above 250 MHz and especially up to 400 MHz, increased losses can occur during the transport of charge carriers through a charge transfer channel.

[0003] US 2009 / 075419 A1 discloses a charge transfer device in the form of a CCD with two charge transfer channels and a mouth region of one charge transfer channel into the other.

[0004] It is an object of the invention to provide improved charge transfer at clock frequencies above 100 MHz, preferably from 250 MHz, particularly preferably up to 400 MHz.

[0005] The object is achieved by the features of claim 1. Advantageous embodiments and further developments of the invention are possible by the measures mentioned in the subclaims.

[0006] The charge transfer device according to the invention utilizes, among other things, a charge carrier channel. A charge transfer channel can be an overlap of the possible electrostatic effect of adjacent gates with a conduction layer in a semiconductor. The charge transfer channel can thus be the intersection volume resulting from the projection of the electrostatic effect of the gates onto the volume structure of the conduction layer.

[0007] The conduction layer, in which charge carrier transport or transfer takes place, can be located in a semiconductor substrate and doped differently than the surrounding semiconductor substrate, allowing charge carriers to move within the conduction layer and prevent them from escaping into the surrounding semiconductor substrate. A conduction layer can be buried or located on the surface of the semiconductor substrate.

[0008] The gates can be electrodes arranged along the conduction layer and separated from the conduction layer by a thin, non-conductive separating layer, so that a change in the potential of the gates results in a change in the electric field in the overlapping region of the conduction layer. The gates can be insulated on the semiconductor substrate by a thin separating layer.

[0009] Charge carriers can be electrons or holes.

[0010] By appropriately changing the potential of adjacent gates, charge carriers can be transported in the charge-transfer channel, allowing the charge-transfer channel to act as a conducting channel for a directed flow of charge carriers. The potential change generally follows a clock frequency. The potential changes can follow a clock frequency. The clock frequency determines the speed of charge transport and thus the temporal resolution and performance of surrounding or connected systems, such as sensors or computing units.

[0011] The boundaries, shape, and layout of the gates, the conduction layer, and the charge-transfer channel are always shown in a plan view from the gates toward the conduction layer, unless otherwise specified. The layout of the charge-transfer channel and spatial relationships are always shown in the direction of charge carrier flow in the charge-transfer channel, unless otherwise specified.

[0012] If the width of the arrayed gates is narrower than the width of the associated conduction layer, then the limits of the charge-transfer channel width are determined by the limits of the arrayed gate width. If the width of the arrayed gates is wider than the width of the associated conduction layer, then the limits of the charge-transfer channel width are determined by the limits of the arrayed gate width.

[0013] In connection with the invention, it was recognized that at higher clock frequencies above 150 MHz or 250 MHz, a portion of the charge carriers located under a gate often does not transfer to the next gate as desired when the potential changes accordingly; this effect can advantageously be reduced or avoided by the charge transfer device according to the invention.

[0014] The charge transfer device according to the invention is a charge transfer device according to claim 1.

[0015] This charge transfer channel according to the invention can have the advantage that charge carriers can flow with less resistance and / or less losses.

[0016] The length of the orifice region along the conduction channel is smaller than the length of the region of the associated two neighboring gates along the charge transfer channel and corresponds to 45-75%, 55-65%, or 60% of the length of the region of the associated two neighboring gates along the charge transfer channel in order to enable the transfer of charge carriers from gate to gate with as little loss as possible.

[0017] Furthermore, the following measures have been taken to reduce losses: The mouth region borders, with its length along the line transmission channel, over a greater length to the region of the assigned gate lying opposite the flow direction than to the region of the assigned gate lying in the flow direction, wherein the gates are arranged electrically separated at intervals, and in particular borders more than 50%, more than 60%, between 60% and 75%, or 2 / 3 to the region of the assigned gate lying opposite the flow direction.

[0018] Preferably, the mouth region has a bulge in which the cross-section first increases in the direction of flow (in particular by more than 20%, 40%, 80% or 100%) and then decreases again (in particular by more than 20%, 40%, or 80%), which extends in its length in the direction of flow at least, substantially or exactly over the mouth region, wherein the length of the bulge in the direction of flow is smaller than the width of the increase in the cross-section, in particular less than 50%, less than 25%, or less than 12%, and wherein the bulge is in particular substantially rectangular.

[0019] Preferably, the charge transfer channel has a region of a constriction in which the cross section decreases in the flow direction and which is arranged opposite to the flow direction in front of the orifice and at least partially in the region of the associated gate lying opposite to the flow direction and is in particular bevelled and / or funnel-shaped in order in particular to reduce the spillback or the flow resistance or the loss of the charge carriers in the flow direction.

[0020] Preferably, the semiconductor substrate is p+ doped and / or the conduction layer is weakly n- doped and / or the gates are formed of metal and / or a non-conductive layer is arranged between the gates and the conduction layer. Overview of the drawings:

[0021] Embodiments of the invention are illustrated in the drawings and explained in more detail below. Like reference numerals in the individual figures denote corresponding elements. They show: Fig. 1 Line transmission channel according to an example that contributes to the understanding of the invention in section along flow direction Fig. 2 Line transmission channel according to an example that contributes to the understanding of the invention in section vertical flow direction Fig. 3 Line transmission channel according to an example that contributes to the understanding of the invention with constriction in plan view Fig. 4 Line transmission channel according to an embodiment of the claimed invention with bulge in plan view Fig. 5 Line transmission channel according to an embodiment of the claimed invention with junction in plan view Detailed description of the drawings:

[0022] Fig. 1 shows a charge transfer channel 10 in side view along the flow direction 31 of the charge carriers in the following figures. The structure is analogous to CCD technology. The surrounding semiconductor substrate 20 is p+ doped. A buried conduction layer 30 is arranged in the semiconductor substrate 20. The conduction layer is lightly n- doped. This has the consequence that electrons are freely mobile as charge carriers in the conduction layer and do not penetrate into the semiconductor substrate. An insulation layer 43 is applied to the conduction layer, and metal gates 40, 41, 50 are arranged thereon. The gates are electrically separated from one another by gaps. The clock generator (not shown) alternately applies a positive potential to the neighboring gates at a clock frequency of 250 MHz, so that conduction electrons in the conduction layer are attracted from one gate to the next and thus shifted in the flow direction.The clock frequency could also be just over 100 MHz, over 150 MHz, or over 200 MHz. Generally, the clock frequency is no higher than 300 MHz. The conduction electrons can, for example, be photoinduced electrons from an image sensor connected to the conduction channel.

[0023] The semiconductor substrate 20 is p+ doped, and the conduction layer 30 is n- doped. The insulation layer 43 is made of SiO2, and the gates are made of metal.

[0024] Fig. 2 shows the charge transfer channel in a side view perpendicular to the flow direction of the charge carriers in the following figures. The conduction layer 30 is buried so that it is enclosed from above and to the side by the semiconductor substrate 20. The semiconductor substrate 20 and the conduction layer 30 are provided with an insulating layer at the top. The gates 40, 41, 50 are arranged in the region above the conduction layer 30 on the insulating layer 43. The gates are designed to be narrower in width than the conduction layer along the flow direction.

[0025] Fig. 3 shows a top view of a charge transfer channel. The conduction layer 30 is embedded in the semiconductor substrate 20. The overlying insulation layer is not shown. Above the area of ​​the conduction layer 30, separated by the insulation layer (not shown), the gates 40, 50, 41 are arranged in the electron flow direction 31 and electrically separated at intervals 42. Overall, the gates exhibit a narrowing of the cross-section in the flow direction. The first gate 40 has a wide cross-section, while the last gate 41 has a comparatively narrower cross-section. The two gates 50 have a cross-section that narrows in the flow direction 31. The narrowing gate 50 initially has a wide area with a constant cross-section without a constriction 51 in the flow direction 31, then a region with a narrower cross-section and a constriction 52, and then a narrower area with a constant cross-section and without a constriction 51.Gate 50 has regions with a constant cross-section at the transition to the adjacent gates. The region with a constant cross-section and no constriction, arranged against the flow direction, is shorter than the region with a constant cross-section and no constriction, arranged in the flow direction. As a result, the narrowing region with constriction 52 is offset from the center of gate 50, counter to the flow direction. The narrowing region with constriction 52 is beveled on both sides, so that it has a funnel shape. By designing a constriction as shown, the spillback and / or the flow resistance and / or the losses of the charge carriers in the flow direction can be minimized.

[0026] Fig. 4 shows the gates of a charge transfer channel in plan view. The conduction layer located beneath the gates is not shown. The maximum width of the gates 40 located in the flow direction at the beginning and end of the gate sequence shown forms the typical width of the cross-section of the conduction transfer channel. In contrast, the two gates 60 have a contiguous region of a bulge 61, in which the cross-section is approximately 25% larger by the width 62 compared to the typical width. Immediately adjacent to the bulge, the first gate 60 with the bulge has a constriction 62, in which the cross-section of the charge transfer channel is narrower compared to the typical width.

[0027] As a result, the inlet into the bulge is narrower than the outlet from the bulge. The constriction 62 is already implemented in the preceding gate 40 in the flow direction, which, through a funnel-shaped area, reduces the cross-section from the typical cross-section to the reduced cross-section of the constriction. The design of the bulge shown in this way can minimize spillback and / or flow resistance and / or charge carrier losses in the flow direction.

[0028] Fig. 5 shows the arrangement of the gates of a conduction transfer channel with a right and a left lateral opening region 70 in plan view. A first charge transfer channel is formed in the flow direction 31 of the charge carriers by the sequence of gates 40, 71, 72 and 40. The conduction layer located beneath the gates is not shown. The gates 71 and 72 have bulges perpendicular to the flow direction in the direction of the gates 73, wherein the first charge transfer channel has a raised cross-section relative to the previous and following gates 40. A second charge transfer channel is formed in the flow direction 32 of the charge carriers by the sequence of gates 73 on 71 and 72 to the right and left of the first charge transfer channel. The .Charge carriers from the second charge carrier channels flow from gate 73 partly into gate 71 and partly into gate 72, and then move further together with the charge carriers from the first charge carrier transfer channel in its flow direction 31. The mouth region 70 is formed by the transition between the first gate 73 of the second charge transfer channel outside the first charge transfer channel and the two adjacent gates 71 and 72 of the first charge transfer channel. The cross-section of the mouth region 70 corresponds to approximately 60% of the length of the two adjacent gates 71 and 72 in the flow direction. Overall, the mouth region overlaps by two-thirds with the adjacent gate 71 of the first charge transfer channel, which lies opposite to the flow direction 31, and by one-third with the adjacent gate 72 of the first charge transfer channel, which lies in the flow direction 31.Thus, the orifice region is shifted relative to the two adjacent gates of the first charge transfer channel, counter to the flow direction 31. By designing a orifice region as shown, the spillback and / or the flow resistance and / or the losses of the charge carriers in the flow direction can be minimized.

[0029] Fig. 6 shows the arrangement of Figur 5 , wherein the first gate 50 has a constriction. The design of the orifice region shown in this way allows the spillback and / or flow resistance and / or losses of the charge carriers in the flow direction to be further minimized. List of reference symbols:

[0030] 10Charge transfer channel 20Semiconductor substrate 30Conduction layer 31Flow direction 32Flow direction 40Gates, wide 41Gates, narrow 42Insulating distance between the gates 43Insulating layer 50Gate with constriction 51Area without constriction 52Area with constriction 60Gate with bulge 61Area with bulge 62Width of bulge 62Narrowing 70Mouth area 71First gate of the first duct with mouth area 72Second gate of the first duct with mouth area 73Gate of another duct

Claims

1. Charge transfer device - having a charge transfer channel in a semiconductor substrate - having a doped conduction layer - for movably accepting the charge carriers, - having a sequence of at least two electrically isolated gates - which adjacently succeed one another - for transferring the charge carriers in the conduction layer - in a flow direction, - wherein the charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer, and - having a clock generator - having a clock frequency of more than 100 MHz, preferably of more than 150 MHz, more than 200 MHz or more than 250 MHz and particularly preferably up to 300 MHz or 400 MHz, - which applies changes in potential at the clock frequency to the gates, - for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer to adjacent regions of the overlap between adjacent gates and the conduction layer, wherein - the charge transfer channel has an influx region - which, in the flow direction, is arranged at a lateral outer boundary of the charge transfer channel and - which at least partly extends over the regions of exactly two adjacent gates of the charge transfer channel - in order to supply charge carriers to the charge transfer channel from a region outside the charge transfer channel that adjoins the influx region, in particular from a second charge transfer channel, and - in order to reduce the spillback or the flow resistance or the loss of the charge carriers in the flow direction of the charge transfer channel or of the region supplying charge carriers to the charge transfer channel, preferably of a second charge transfer channel, wherein - the length of the influx region along the conduction channel - is less than the length of the region of the assigned two adjacent gates along the charge transfer channel and - corresponds to 45-75% or 55-65% or 60% of the length of the region of the assigned two adjacent gates along the charge transfer channel, wherein - the influx region - with its length along the conduction transfer channel - adjoins in an offset manner the region of the assigned gate situated counter to the flow direction over a greater length than the region of the assigned gate situated in the flow direction, wherein the gates are arranged with spacings in an electrically isolated manner, and - preferably adjoins the region of the assigned gate situated counter to the flow direction to an extent of more than 50%, more than 60%, between 60% and 75%, or 2 / 3.

2. Charge transfer device according to Claim 1, wherein - the influx region - has a protuberance - in which the cross section with respect to the flow direction first increases, preferably by more than 20%, 40%, 80% or 100%, and then decreases again, preferably by more than 20%, 40%, or 80%, - which extends in terms of its length in the flow direction at least or exactly over the influx region, - wherein the length of the protuberance in the flow direction is less than the width of the increase in the cross section, preferably less than 50%, less than 25%, or less than 12%, - wherein the protuberance is preferably rectangular.

3. Charge transfer device according to either one of the preceding claims, wherein - the charge transfer channel has a region of a constriction - in which the cross section decreases in the flow direction and - which is arranged counter to the flow direction upstream of the influx location and - at least partly in the region of the one assigned gate situated counter to the flow direction and - is embodied preferably as bevelled and / or funnel-shaped - in order to reduce the spillback or the flow resistance or the loss of the charge carriers in the flow direction.

4. Charge transfer device according to any one of the preceding claims, wherein - the semiconductor substrate is p+ doped and / or - the conduction layer is weakly n- doped and / or - the gates are formed from metal and / or - a nonconducting layer is arranged between the gates and the conduction layer.