EFFICIENTLY TRANSMITTABLE BIT SEQUENCE WITH LIMITED DISPARITY

Description

[0001] The present invention is directed to a method for generating an efficiently transmittable bit sequence with limited disparity and a limited run length. The proposed method allows data to be transmitted particularly efficiently over a transmission channel. Optimized disparity represents a quality characteristic for data transmissibility. Detrimental disparity can lead to data not being transmitted properly over a data channel because it cannot be properly interpreted by the receiver. Another quality characteristic is data efficiency, which refers to the ratio of transmitted payload data to a further data volume whose content is not directly related to the payload data. This includes so-called header data.The proposed invention allows the generation of data streams that can be read out particularly efficiently and are also very efficient with regard to overhead data. This minimizes the so-called overhead of the user data, which in turn creates a particularly efficient method. The unambiguous interpretability on the receiver side also ensures that data does not have to be transmitted repeatedly; instead, it can be read out on the receiver side with a high degree of error reliability. Furthermore, the proposed method is particularly efficient because the conversion of data segments into subsymbols or into symbols composed of subsymbols can be carried out in parallel. Furthermore, this parallel execution only requires units that are technically simple to manufacture. Thus, the efficiency gain in this case also relates to the hardware and runtime to be used.The invention is further directed to a correspondingly configured system arrangement as well as to a computer program product and a memory-readable medium with control commands which carry out the method.

[0002] Boye Jeffrey et al: "11b / 14b Encoding - A Fault Tolerant, DC-Balanced Line Code for AC-Coupled Channel Link Transceivers", 2019 IEEE Aerospace Conference, IEEE, March 2, 2019, pages 1-11, XP033561728, DOI: 10.1109 / AERO.2019.8741859 shows a single disparity controller coupled to a plurality of encoding units.

[0003] US 6 691 275 B1 shows coding units, each with a disparity logic.

[0004] EP 3323219 A1 describes a method that enables the particularly fail-safe reading of an analog data stream over a data line. Among other things, the signal amplitude is monitored, and the signal is preferably measured at the point where the amplitude is maximum. This converts an analog data stream into a digital data set, and the maximum amplitude ensures that the threshold value between 0 and 1 on the line is reliably exceeded or undershot.

[0005] The state of the art includes different coding methods or

[0006] Data transmission methods are known, but they all relate to application scenarios that are disadvantageous for use in an automobile. The state of the art often assumes that high computing power is available and that high real-time requirements are not required. Furthermore, the state of the art often assumes that the weight or reliability of the components used plays a subordinate role. The state of the art often refers to conventional computer networks, where reliability or low technical complexity are less important.

[0007] Based on this state of the art, there is a need to create a method or system arrangement that enables data to be processed as quickly as possible due to safety requirements in automobiles. Furthermore, it involves minimal technical effort and minimizes the error rate during transmission, since retransmission is not possible if an error is detected. The minimal technical effort should consist of installing the simplest possible components, which are lightweight and can also be efficiently manufactured in large quantities. Known methods and system arrangements from computer network technology are typically not applicable here, since weight savings and real-time operation are not crucial for a desktop PC or server.While heat removal generally presents a challenge in computer systems, energy efficiency in an automobile is even more important, as in electromobility, for example, power consumption even influences the range of the vehicle.

[0008] Further prior art relates to the transmission of data in a serial data stream. For example, the prior art provides for extensive descriptive data to be sent along with the payload, indicating where the payload is located and how it should be interpreted. Furthermore, it is known in the prior art to discard individual data packets if they are not transmitted correctly. Furthermore, it is known in the prior art to resend data packets if they do not arrive at a sender in a timely manner or in an unexpected format.

[0009] When transmitting data serially, it is necessary to keep the number of ones and zeros in the serial data stream as equal as possible. This is called disparity. A disparity of zero on average, but also over a short period of time, is desirable to prevent baseline drift during transmission. Baseline drift (DC voltage fluctuation) of the serial signal leads to bit errors. In extreme cases, transmission is not possible.

[0010] To reliably recover the serial bits in the serial data stream on the receiving side without the need to transmit a clock pulse, a minimum number of 0->1 or 1->0 transitions is required. This allows the clock pulse for recovering the serial data to be generated locally at the receiver from the serial data stream. The so-called run length specifies how many identical bits (ones or zeros) can occur consecutively without a change. A short run length is always desirable, as long run lengths make it impossible to reliably recover the clock pulse from the serial data stream.

[0011] The task of the line code (in this case, a block code) is to generate a symbol with guaranteed disparity and guaranteed run length from arbitrary data words with arbitrary disparity and infinite run length. This leads to transmission overhead. More bits (in the form of symbols) must be transmitted than appear in the net data word to be transmitted. This means that the required transmission speed (bandwidth) must be greater than the data rate of the data to be transmitted. This, in turn, leads to systems requiring higher error rates or more overhead, power, etc., than would be necessary to transmit the raw data.

[0012] The state of the art either has a high overhead (8B10B) or the quality of the coded signal in terms of disparity and run length is very poor, so that additional measures (complexity) such as scramblers are often necessary to improve the quality in terms of disparity or run length.

[0013] Accordingly, it is an object of the present invention to create a method which generates a particularly efficiently transmittable bit sequence. Efficiency can refer to hardware efficiency, efficient decryption on the receiver side, the lack of need for redundant data transmission due to uninterpretable signals and / or the ratio of payload data to overhead data. Furthermore, the invention should make it possible to create or use particularly efficient hardware which enables runtime optimization through parallel processing. Furthermore, it is an object to provide a correspondingly configured system arrangement, as well as a computer program product and a computer-readable storage medium with control commands which carry out the method or operate the system arrangement.

[0014] The problem is solved by the features of patent claim 1. Further advantageous embodiments are specified in the subclaims.

[0015] Accordingly, a method is proposed in an automobile for generating an efficiently transmittable bit sequence with a restricted disparity and a restricted run length, comprising providing an arbitrary bit sequence; segmenting the provided bit sequence into a predefined sequence of segments according to a respective predefined bit length; and encoding each segment into a respective subsymbol, using one coding unit per segment from a plurality of coding units, wherein a first subset of coding units actively controls a sign of the disparity of the subsymbol by inverting the disparity of the generated subsymbol to compensate for a disparity of a second subset of coding units, wherein the disparity of the second subset of coding units is not controllable and wherein a concatenation of the subsymbols results in the efficiently transmittable bit sequence.

[0016] In a preparatory method step, it is possible to provide a potentially infinitely long bit stream comprising any desired bit sequence. Depending on the application scenario, the data stream is already configured to be of any desired length and can in turn be divided into words or any desired bit sequence. Thus, an output data stream is provided which has a bit sequence that is potentially of any desired length. However, this arbitrary length can be defined in a preparatory method step and can preferably be defined as 112 bits. As soon as the length or bit length of the arbitrary bit sequence is defined, it is fixed according to one aspect of the present invention. In this respect, an arbitrary length of the bit sequence cannot be understood as arbitrary within the meaning of the present invention.Rather, according to the invention, a bit sequence can be provided as a synonym for the arbitrary bit sequence, the length of which can be freely selected in advance and / or the content of which corresponds to the data to be transmitted or at least to a part of the data to be transmitted.

[0017] In a preparatory method step, it is therefore possible to provide an output data stream containing any desired bit sequence. This desired bit sequence is then read from the output data stream and provided in a first method step.

[0018] Typically, the output data stream or output bit sequence can have so many bits that the process is performed iteratively that several arbitrary bit sequences are generated from the output bit sequence, segmented, converted into subsymbols, optimized for disparity, and then transmitted. Thus, the output bit sequence can also be of any length and can ultimately be transmitted as several total symbols.

[0019] There are multiple coding units, with each segment, which in turn corresponds to a portion of the arbitrary or pre-selectable bit sequence, being assigned a coding unit. This coding unit then converts the segment into a subsymbol, with the set of subsymbols concatenated to correspond to the symbol or the entire symbol of the bit sequence to be transmitted efficiently. Thus, according to one aspect of the present invention, a coding unit is located in a logical path of the processing chain or the structural arrangement between a segment and a subsymbol.

[0020] The proposed method is particularly efficient because the transmittable bit sequence has a particularly high degree of payload compared to the prior art. For example, it is possible to transmit 128 bits which have 112 bits of payload. Thus, the proposed method is already superior to the prior art in this aspect. Furthermore, the creation of the transmittable bit sequence is particularly efficient because it can be done in parallel and because coding units that are particularly simple in design can be used for this purpose. In this context, simple means, for example, that very few circuits need to be installed in the coding units. The coding units do not need to have extensive logic and can even be optimized for a specific number of bits. Thus, according to the invention, it is possible for the input and output of the respective coding unit to be fixed with regard to the number of bits.

[0021] Due to the optimized disparity of the bit sequence to be transmitted, errors can be avoided during interpretation on a serial channel. Thus, efficiency also refers to the bit sequence being particularly error-robust, meaning it can be reliably transmitted only once. Redundant transmission is avoided due to the high detectability, again due to the optimized disparity.

[0022] During serial data transmission, it is advantageous to maintain an equal number of ones and zeros in the serial data stream, if possible. This is generally referred to as disparity. For reliable clock recovery at the receiver, a run-length restriction can be imposed on the generated channel sequence. This limits the maximum number of consecutive ones and zeros. Thus, the proposed method can also be referred to as a method for efficient coding of a bit sequence. According to the invention, the disparity is optimized by skillfully adjusting partial disparities. This can be particularly advantageous when the run length of the bit sequence is limited. The restricted disparity and the restricted run length can also refer to the arbitrary bit sequence provided. Thus, this does not have to be the efficiently transmittable bit sequence.Overall, the provided arbitrary bit sequence can be transmitted efficiently or a bit sequence to be transmitted is generated or created from this bit sequence, which can then be transmitted efficiently.

[0023] In a preparatory process step, an arbitrary bit sequence is provided that encodes payload data. Problems can arise in this arbitrary bit sequence, for example, due to unfavorable disparity. For example, too many zeros can lead to problems during transmission. This must be avoided, and in subsequent process steps, the arbitrary bit sequence is optimized so that it can now be transmitted efficiently. The provided arbitrary bit sequence therefore represents any payload data that is to be sent from a sender to a receiver via a serial data channel. The arbitrary bit sequence could, for example, be control data in an automobile.

[0024] According to the invention, the provided bit sequence is segmented into a predefined sequence of segments, each with a predefined bit length. Thus, the input data stream, i.e., the arbitrary bit sequence, is divided according to a predefined method, resulting in individual data segments. The segments cumulatively result in the arbitrary bit sequence. The predefined bit length has the advantage that coding units can be optimized to take the respective bit length into account. This allows for the creation of particularly efficient, highly specialized circuits. Defined bit lengths are mentioned below, but these are merely examples.

[0025] Each segment is encoded into a sub-symbol using one coding unit per segment from a plurality of coding units. The encoding itself takes place in one coding unit each, which receives a segment at the input and then converts this segment into a sub-symbol. The sub-symbol is also a bit sequence. Overall, any given bit sequence is divided into segments, each of these segments is converted into a sub-symbol by a coding unit, and the totality of the sub-symbols results in the encoding of the given bit sequence to be transmitted. Overall, it is advantageous for the number of segments to correspond to the number of coding units and thus to the number of sub-symbols. This makes it possible for each segment to have exactly one coding unit, which in turn generates exactly one sub-symbol from the segment.The plurality of coding units describes all coding units to be used, which corresponds to the number of segments. The number of segments is predefined, since a predefined bit length is specified. Thus, the method is deterministic overall.

[0026] In order to achieve an advantageous disparity overall, there is a first subset of coding units which actively controls a sign of the disparity of the subsymbol by inverting the disparity of the generated subsymbol to compensate for a disparity in a second subset of coding units. This means that there are subsets of coding units which either control the sign of the disparity or not. Coding units in the first subset control this sign, and coding units in the second subset do not. Thus, coding units in the first subset can be referred to as active, and coding units in the second subset as passive. The different subsets or types of coding units make it possible to connect the coding units in series in such a way that coding units in the first subset also advantageously shape the overall disparity of the subsymbols from the coding units in the second subset.

[0027] According to the invention, coding units are used which have any desired disparity with regard to the subsymbol. A coding unit of the first subset can then be connected in parallel, which, depending on the disparity of the coding unit of the second subset, controls the sign of the disparity of the preceding coding unit and its own coding unit or its subsymbols. Thus, a specific number of coding units of the second subset is used, and then a further specific number of coding units of the first subset is used. As a result, the types or subsets of the coding units alternate such that the next coding unit connected in parallel adapts the disparity of the preceding subsymbol(s) and / or its own subsymbol. This prevents uncontrollable coding units from being connected in parallel in such a way that an unfavorable disparity arises.Each coding unit of the first subset thus corrects the sign of the previously parallel coding units or their subsymbols. This parallel connection of coding units will be discussed in more detail below with reference to . Figure 4 described.

[0028] In summary, it can be concluded that coding units of the first subset each optimize coding units of the second subset with respect to disparity. Optimizing a disparity means that the disparity is 0. How to calculate disparities or adjust them, for example, by changing the sign, is well known to those skilled in the art.

[0029] According to the proposed method, subsymbols are created whose sequence is optimized with respect to disparity. Since each segment is converted into a subsymbol, the (total) symbol to be transmitted can be generated by stringing the subsymbols together. This can be transmitted particularly efficiently and with error tolerance because the disparity or subdisparities are optimized. This results in a particularly advantageous bit sequence for transmission.

[0030] According to one aspect of the present invention, any bit sequence is unrestricted in its disparity and run length. This has the advantage that any amount of payload data can be transmitted or converted into a bit sequence that is restricted in disparity and restricted in run length. Thus, any bit sequence is encoded into a bit sequence for transmission that is optimized in its disparity and run length.

[0031] According to a further aspect of the present invention, the disparity of the second subset of coding units is not controllable. This has the advantage that any subsymbol can be generated using the coding units of the second subset, whereby particularly simple coding units can be used. These can be designed particularly simply because the generated subsymbol of this coding unit is not subject to any restrictions regarding disparity or run length.

[0032] According to a further aspect of the present invention, the active control of the sign is carried out by conditionally inverting the subsymbol. This has the advantage that the corresponding subsymbol of the coding units of the first subset can be controlled in a simple manner. Only the disparity or individual bits of the subsymbol need to be inverted. The sign refers to the disparity of the subsymbol, which can be positive or negative.

[0033] According to a further aspect of the present invention, the conditional inversion is performed depending on the disparity of an overall symbol formed from all subsymbols. This has the advantage that not only are subsymbols optimized, but also the entire, i.e., the combined subsymbols, i.e., the entire symbol, are optimized with respect to disparity. This results in a particularly advantageous overall symbol.

[0034] According to a further aspect of the present invention, the dependency is influenced in such a way that a magnitude value of the disparity is minimized. This has the advantage of achieving the lowest possible disparity, preferably 0. Thus, disparities are linked in such a way that the magnitude of the disparities is as close to 0 or as small as possible.

[0035] According to a further aspect of the present invention, the magnitude value is minimized such that a positive overall symbol disparity is counteracted by a negative parity of the subsymbols. This has the advantage that the positive overall symbol disparity is minimized or eliminated.

[0036] According to a further aspect of the present invention, the magnitude value is minimized such that negative overall symbol disparity is counteracted by positive parity of the subsymbols. This has the advantage that the overall symbol disparity is minimized or eliminated altogether.

[0037] According to a further aspect of the present invention, the active control is performed depending on the total symbols already transmitted, such that the disparity of all total symbols is minimized. This has the advantage that several total symbols are minimized with respect to their disparity or the disparity is eliminated, thus optimizing the transmittability of several sequences of total symbols.

[0038] According to a further aspect of the present invention, coding units of the first subset encode 11-bit segments into 13-bit subsymbols. This has the advantage that 11 bits are encoded particularly efficiently, resulting in only an additional effort of 2 bits. This is particularly advantageous when a total symbol of 128 bits is to be created. In general, the specific values ​​of the proposed technical teaching mentioned here were empirically determined and can be demonstrated by the fact that only an additional effort of 128 - 112 bits, i.e., 14%, is necessary. Thus, the values ​​listed here are demonstrably advantageous when transmitting 112 bits.

[0039] According to a further aspect of the present invention, coding units of the first subset have a disparity between +3 and +9, which is specifically inverted to -3 to -9 by inversion. This has the advantage that, for example, a disparity of +3 is canceled out with a disparity of -3, which occurs analogously when adjusting the disparity of +9 with a disparity of -9. This is particularly advantageous for any bit sequence of 112 bits that is to be encoded as 128 bits.

[0040] According to a further aspect of the present invention, the run length in subsymbols is a maximum of 7. This has the advantage that a maximum of 7 identical instances of zeros and ones are generated, which is particularly advantageous in the proposed scenario of 112 bits or 128 bits.

[0041] According to a further aspect of the present invention, the run length of the subsymbol for coding units of the first subset is a maximum of 5, starting from the most significant and / or least significant bit. This has the advantage that a maximum of 5 identical bits can be present at the end or beginning of a subsymbol. This has also proven particularly advantageous in the described scenario.

[0042] According to a further aspect of the present invention, in coding units of the second subset, 11-bit segments are encoded into 12-bit subsymbols, or 7-bit segments into 8-bit subsymbols, or 6-bit segments into 8-bit subsymbols. This has the advantage that, based on this encoding, in the scenario of 112 bits to be transmitted in a 128-bit symbol, particularly advantageous values ​​are created, which exhibit a minimized overhead of only 14%.

[0043] According to a further aspect of the present invention, a disparity between -2 and +2 is generated in coding units of the second subset. This has the advantage that particularly advantageous disparities are generated.

[0044] According to a further aspect of the present invention, in coding units of the second subset, the run length in the generated subsymbol is 6. This has the advantage that particularly optimized subsymbols are again generated.

[0045] According to a further aspect of the present invention, coding units of the second subset generate subsymbols having a maximum run length of 3 at the edge. This has the advantage that subsymbols created by the second subset of coding units have a maximum run length of 3 at the beginning or end, which is a particularly advantageous value.

[0046] According to a further aspect of the present invention, the coding units are addressed in parallel, and each segment is encoded into a subsymbol. This has the advantage that a segment is converted into exactly one subsymbol with exactly one coding unit. Thus, the coding units can be addressed in parallel, since segments are formed from any bit sequence, which can be converted into subsymbols in parallel.

[0047] According to a further aspect of the present invention, the coding units are addressed in the order 21212221212, where a 1 represents a coding unit of the first subset and a 2 represents a coding unit of the second subset. This has the advantage that a non-actively controlled number of coding units is always followed by a single coding unit that can be actively controlled. For this purpose, it has been empirically determined that a particularly advantageous overall symbol results precisely with the proposed coding units.

[0048] According to a further aspect of the present invention, when a data stream with positive disparity and a data stream with negative disparity are applied, a multiplexer selects the data stream that contributes to minimizing the overall disparity of the entire symbol. This has the advantage that the appropriate data stream can be selected that has a sign that minimizes or eliminates the disparity. If, for example, the disparity to be optimized is negative, a data stream with positive disparity is selected, which then minimizes or compensates for this data stream with respect to its disparity.

[0049] One aspect of the present invention is to bundle multiple data streams (video, audio, and data) into a transport frame and transmit them serially. The different data formats have not only different bandwidth requirements, but also different latency, reassembly sublayer, and bit error rate requirements. In particular, the transmission of today's video data formats requires not only the transmission of the pure video data and its frame information, but also support for encryption methods such as HDCP. All of this requires many different data channels with very different requirements for bandwidth, latency, reassembly sublayer, etc. Added to this is the desire for far more complex network architectures than a simple transmitter-receiver architecture offers.Architectures with multiple repeaters, where data paths can start and end, branches (Y) also with the possibility of integrating data paths back into a link, are advantageous.

[0050] According to one aspect of the present invention, the technology consistently follows the basic idea of ​​bundling services, but offers completely new possibilities regarding network architectures and allows for new approaches to implementing today's video interfaces. Furthermore, it can be used as a universal data transport layer, for example, for transmitting Ethernet or camera data or any type of sensor data.

[0051] With a virtual path, all packets / cells take the same path, unlike IP, where a packet could reach its destination via a different route than previous and subsequent packets. Latency and the reassembly sublayer across a virtual path are thus constant.

[0052] Virtual paths also have the advantage that they can be used as multiplexing offshoots for different services (video, audio, Ethernet), since the properties of the virtual paths can be configured differently without the different virtual paths interfering with each other.

[0053] Virtual paths only consume bandwidth when data is actually being transferred.

[0054] The concept of virtual paths also makes it possible to implement complex and extensive diagnostic and network configuration functions at runtime using dedicated (virtual) data channels.

[0055] According to one aspect of the present invention, a virtual path layer is provided between the physical layer (serializer and framer) and the various application data interfaces.

[0056] According to one aspect of the present invention, this is used to multiplex the various data paths and support more complex architectures with repeaters and branches. This occurs primarily in the cell layer.

[0057] According to one aspect of the present invention, another part of the virtual path layer is an application adaptation layer, which performs the conversion of video (stream) or, for example, Ethernet (packet) data into cells. This application adaptation layer also includes the OAM functions for network diagnostics and management.

[0058] According to one aspect of the present invention, the technology can form the basis for transmitting a variety of data formats over a serial connection in the car (and elsewhere). It thus forms the basis for a new generation of devices.

[0059] The high serial bandwidths make it necessary to define architectures, cell formats and interfaces that enable flexible internal data bus widths in order to adapt the speed of the internal timing system to the capabilities of the chip technology.

[0060] According to one aspect of the present invention, the virtual path layer is the physical layer, which consists of the transmission sublayer and the physical medium sublayer, the cell layer and the application adaptation layer, which contains the segmentation and reassembly sublayers and the functions for adapting the data formats to the corresponding application.

[0061] The main task is to establish the physical connection to other physical layers. This connection is fundamentally bidirectional. Theoretically, this connection can be realized using a variety of media. In practice, two serial differential GBps connections are used. Line coding, the insertion of dummy cells to decouple the cell rate from the link rate, and the integration of the cell stream into the serial frame take place in this layer.

[0062] In the cell layer, the segmented data (cell payload) of the overlying Segmentation & Reassembly sublayer is assembled into complete cells with a header, VP identifier, and CRC, or cells are CRC-checked, and the payload is passed on to the Segmentation & Reassembly sublayer. This is also where the various cell streams of the application adaptation functions are multiplexed, or the cell payloads are distributed among the application adaptation functions according to the VP identifier (feeding in / feeding out). According to one aspect of the present invention, the cell layer also multiplexes and demultiplexes cell streams in repeaters and splitters (forwarding).

[0063] According to one aspect of the present invention, the task of the application adaptation functions is to adapt the data of the application interfaces to the format of the payload field of the cell and to transmit control information to the other side or to use control information of the other side for the adaptation (time generation, frame formation).

[0064] According to one aspect of the present invention, all virtual data paths are unidirectional, meaning they start at an initiator and end at one or more destinations. If virtual data paths belong together logically, e.g., HDCP for a video channel, and thus form a bidirectional data path, these paths should have the same VP identifiers.

[0065] The virtual data path begins at an initiator and ends at one or more targets. Implementation is carried out by the cell sublayer and performs the following functions on the virtual path: Add / delete multiplexing VP translation Stream data (continuous data stream)

[0066] The Stream Data function combines time-domain traversal and bit-width conversion of data from the application interface to the N bits of the cell rows. The cell row payload is preformatted so that the cell footer and header fit into the first and last cell rows.

[0067] Streamed data is (usually) source-synchronous. This is where clock domain crossing of the data path occurs, from the application clock domain to the Virtual Path Layer clock domain.

[0068] In the transmit direction, a data buffer is provided into which the source-synchronous data is written using the source clock. The segmentation layer retrieves the data from this buffer as needed to perform the data format conversion into the N-bit-wide rows of cells. Frame data (e.g., Hsync, Vsync, DE) is encoded in payload info bits, allowing frame reconstruction on the receiver side.

[0069] In the receive direction, the reassembly sublayer writes the cell data into a data buffer with a cell row bit width of 1. The frame information is reconstructed based on the payload info bits. The source clock is regenerated, for example, using buffer fill level and clock synthesis.

[0070] If data encryption is required (HDCP), the cell data is encrypted or decrypted in this function.

[0071] Due to the different types of streamed data, such as audio, video with and without encryption, there may be different implementations of this basic function (e.g.: VStream In / Out; AStream In / Out; EncVStream In / Out).

[0072] The interface to the segmentation & reassembly sublayer is the same for all functions. Burst data (discontinuous data stream)

[0073] The Burst Data function combines clock domain crossing and data bit-wide conversion of data from the application interface to the N bits of the cell rows. The cell row payload is preformatted so that the cell footer and header fit into the first and last cell rows.

[0074] Burst data is (usually) synchronous to an external time and has different identification signals for direction and data type (Address / Data / ByteEnable).

[0075] This data is usually accompanied by control lines to implement a specific protocol.

[0076] In the transmit direction, a data buffer is provided into which the burst data is written with the interface clock. The segmentation layer retrieves the data from this buffer as needed to perform the data format conversion into the N-bit-wide rows of cells.

[0077] In the receive direction, the cell data is written by the reassembly sublayer into a data buffer, with the cell string being bit-wide. The interface control signals are reconstructed based on the payload info bits.

[0078] The payload info bits are used to generate the control signals of the application-specific interfaces or to synchronize the protocol state machines in the application-specific interfaces.

[0079] Due to the different interfaces that provide burst-like data (SPI, I2C, MII), there may be different implementations of this basic function (e.g.: SPIBurst, I2CBurst, MIIBurst).

[0080] Accordingly, there will also be (slightly) different stream in / out interfaces, but their structure should be the same.

[0081] The object is also achieved by a system arrangement in an automobile for generating an efficient transmittable bit sequence with a limited disparity and a limited run length, comprising an interface unit configured to provide any desired bit sequence; a segmentation unit configured to segment the provided bit sequence into a predefined sequence of segments according to a respective predefined bit length;and a coding arrangement configured to encode each segment into a respective subsymbol, using one coding unit per segment from a plurality of coding units, wherein a first subset of coding units actively controls a sign of the disparity of the subsymbol by inverting the disparity of the generated subsymbol to compensate for a disparity of a second subset of coding units, wherein the disparity of the second subset of coding units is not controllable and wherein a concatenation of the subsymbols results in the efficiently transmittable bit sequence.;

[0082] The problem is also solved by a computer program product with control commands which implement the proposed method or operate the proposed device.

[0083] According to the invention, it is particularly advantageous that the method can be used to operate the proposed devices and units. Furthermore, the proposed devices and units are suitable for implementing the method according to the invention. Thus, each device implements structural features suitable for executing the corresponding method. However, the structural features can also be configured as method steps. The proposed method also provides steps for implementing the function of the structural features. Furthermore, physical components can also be provided virtually or in a virtualized form.

[0084] Further advantages, features, and details of the invention will become apparent from the following description, in which aspects of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. Likewise, the features mentioned above and those further explained here may be used individually or in combinations. Parts or components with similar functions or identical components are sometimes provided with the same reference numerals. The terms "left," "right," "top," and "bottom" used in the description of the exemplary embodiments refer to the drawings in an orientation with a normally legible figure designation or normally legible reference numerals.The embodiments shown and described are not intended to be exhaustive, but rather are exemplary in nature to illustrate the invention. The detailed description is intended to inform those skilled in the art; therefore, known circuits, structures, and methods are not shown or explained in detail in order not to obscure the understanding of the present description. The figures show: . Figure 1 : a schematic flow diagram of a method for generating an efficient transmittable bit sequence with a restricted disparity and a restricted run length according to one aspect of the present invention; Figure 2 : a basic frame format and the application of a so-called block code according to one aspect of the present invention; Figure 3 : a schematic diagram of a layout and structure of the so-called block code according to another aspect of the present invention; Figure 4: a schematic block diagram of the system arrangement for generating an efficiently transmittable bit sequence with a limited disparity and a limited run length according to a further aspect of the present invention; Figure 5 : a schematic diagram of a frame format as may be used according to the invention; and Figure 6A , 6B , 6C , 6D : exemplary encodings of data segments to symbols such that the disparity is optimized according to one aspect of the present invention.

[0085] Some of the figures present parameters which are familiar to the person skilled in the art in their English terminology and which are used as parameters and therefore cannot be translated.

[0086] Figure 1shows, in a schematic flow diagram, a method in an automobile for generating an efficiently transmittable bit sequence with a restricted disparity and a restricted run length, comprising providing 100 any desired bit sequence; segmenting 101 the provided bit sequence into a predefined sequence of segments according to a respective predefined bit length; and coding 102 each segment into a respective subsymbol, using one coding unit per segment from a plurality of coding units, wherein a first subset of coding units actively controls a sign of the disparity of the subsymbol by inverting the disparity of the generated subsymbol to compensate for a disparity of a second subset of coding units, wherein the disparity of the second subset of coding units is not controllable and wherein a concatenation of the subsymbols results in the efficiently transmittable bit sequence.

[0087] Figure 2 shows a data format that displays any bit sequence on the left and subsymbols on the right. The data to be encoded has 112 bits and the subsymbols have 128 bits. In this way, any bit sequence of 112 bits is encoded into a total symbol of 128 bits. The encoded 128 bits are optimized with regard to disparity. The arrow in the middle indicates that the coding units translate the data segments on the left into subsymbols on the right. This figure also shows that the method can be applied multiple times, so that any number of bit sequences can be translated into any number of total symbols. Furthermore, the data can be divided into different data cells or data frames.

[0088] Even if the data on the left side has semantically the same content as the data on the right side, the data on the right side is encoded in such a way that its disparity is optimized. In general, this method can be applied to any data, hence the arbitrary bit sequence, and both payload and header data can be converted.

[0089] The entered data fields are to be understood as examples only and form an application example of the present invention.

[0090] Figure 3The center shows the coding units, including the inputs and outputs. The output data consists of 112 bits, which in this case have an index of 0-111. These are broken down into segments with bit lengths of 11, 6, 7, or other assignments. In the present example, these segments are translated into subsymbols of 12, 13, 8, or other data lengths. The proposed example is particularly advantageous because it encodes 112 bits into 128 bits, thereby achieving a particularly high degree of efficiency. Thus, the 128 bits have the same content as the bit sequence to be encoded and are only 16 bits longer.

[0091] In the present figure, it is shown on the left that the arbitrary bit sequence of 112 bits is segmented into, among other things, data segments of 11 bits and then encoded into 12 bits by means of the encoding unit 11B12B.

[0092] Figure 4The figure above shows any 112-bit bit sequence being segmented into 11, 6, or 7 bits. The coding units are then addressed in parallel, converting the bits into subsymbols in such a way that they are optimized with respect to disparity. For example, 11 bits are encoded to 12 bits, or 11 bits to 13 bits.

[0093] In the present Figure 4On the far left in the middle there is a coding unit from the second subset, designated 11B12B. This supplies a subsymbol with any sign, i.e. with any disparity. To compensate for this disparity, the coded unit 11B13B is connected downstream in parallel with the bit sequence. This means that a data stream is formed which converts the most significant bits of twice 11 into two subsymbols. Firstly, 11B12B converts the 11-bit data segment into a 12-bit subsymbol with any sign, i.e. disparity, and secondly, the data segment of 11 bits is coded into 13 bits using the coding unit 11B13B. In the figure below the coding units, the second coding unit from the left, 11B13B, is a coding unit from the first subset. It has an inverter and a multiplexer.The first 13 bits are therefore present as a data stream, which is divided in such a way that it is inverted once with respect to its sign, i.e., its disparity, and once remains unchanged. Further down, it is shown that, with disparity feedback, the positive or negative—i.e., the original or inverted—data stream is used to compensate for the sign from the leftmost coding unit. Therefore, two data streams are applied to the first multiplexer on the left, each representing the subsymbol: once with the conventional sign, as output from the 11-bit 13-bit coding unit, and once with an inverted sign or inverted disparity.

[0094] Based on the feedback from the unit at the very top, the disparity resulting from the leftmost encoder 11B12B is determined, and thus the multiplexer, at the very bottom left, compensates for or minimizes the disparity of the subsymbol of the leftmost encoder 11B12B. This is carried out in parallel in such a way that the coding units from the second subset are followed by coding units from the first subset, which minimize or eliminate the disparity. Finally, the overall symbol is output at the very bottom right. This overall symbol has 128 bits and is made up of the subsymbols, as inserted into the bold line below using the slanted arrows. Thus, the subsymbols whose disparity is optimized or minimized are present on this output line, and these subsymbols form the overall symbol, which can then be output and transmitted.

[0095] According to one aspect of the present invention, a 112-bit data word with any disparity (maximum disparity: 112) and any run length (maximum run length: 112) is encoded into a 128-bit symbol. The overhead resulting from the encoding is thus 14.2%.

[0096] The maximum run length occurring in the symbol, as well as in any sequencing of any symbols, is 8 equal bits.

[0097] The maximum disparity in the long mean is 0. The disparity in a symbol is less than 9.

[0098] The complexity of the logic is minimal, comparable to 10 8B / 10B encoders (with the well-known disadvantage of the large overhead).

[0099] This is achieved by the use, or parallel use, of several "small" encoders whose characteristics regarding disparity and run length are optimally matched to one another.

[0100] The encoders 11B12B, 7B8B and 6B8B all generate symbols with a guaranteed maximum run length of 6, even with arbitrary sequencing of the (sub)symbols.

[0101] According to one aspect of the present invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7 or 5 at the beginning or end of the symbol. Due to the sequencing (Fig. 2) of the (11B13B) with the other encoders, a maximum run length of 8 can be created in the symbol.

[0102] See encoder properties as follows: 11B13B: 11 bits of data are mapped to 2048 13-bit symbols. The symbols can be transmitted inverted or non-inverted. Disparity: +3... +9 or controllable -3...-9 Run length in word: 7 Run length at edge: 5. 11B13B: 11 bits of data are mapped to 2048 13-bit symbols. The symbols can be transmitted inverted or non-inverted. Disparity: +3... +9 or controllable -3...-9 Run length in word: 7 Run length at edge: 5 11B12B: 11 bits of data are mapped to 2048 12-bit symbols. The symbols are only transmitted non-inverted. Disparity: -2, -1, 0, 1, 2 Run length in word: 6 Run length at edge: 3 7B8B: 7 bits of data are mapped to 128 8-bit symbols. The symbols are transmitted only inverted. Disparity: -2, -1, 0, 1, 2 Word length: 6 Edge length: 3 6B8B: 6-bit data is mapped to 64 8-bit symbols. The symbols are transmitted only inverted. Disparity: 0 Word length: 6 Edge length: 3

[0103] With the four 11B13B encoders, a disparity of at least +-12 can be controllably generated to compensate for the uncontrollable disparity of a maximum of +-12 (6 x +-2) of the 11B12B and 7B8B encoders, so that a balanced disparity can be reliably achieved regardless of the data to be transmitted.

[0104] To further reduce the complexity of the hardware, according to one aspect of the present invention, 4 small encoders (11B13B) are used, the disparity of which can be controlled with respect to sign (+-).

[0105] According to one aspect of the present invention, symbol disparity is controlled by each encoder calculating the parity of "its" subsymbol. This is done with little effort, since the subsymbol has only a few bits.

[0106] For four of the eleven encoders, the sign of the disparity of the subsymbol can be actively controlled by inverting the generated subsymbol. The encoders (11B13B) have the special feature that their symbols generate a symbol with positive disparity (+3... +9) for all input data. Inverting the subsymbol produces a symbol with negative disparity (-3...-9).

[0107] This allows the disparity (-2, -1, 0, 1, 2) of the subsymbols of the other encoders (11B12B and 7B8B) to be compensated. The 6B8B encoder generates symbols whose disparity is always 0. Then, all (sub)parities of the encoders (11B12B and 7B8B) are added together, and the result determines how many inverted and non-inverted symbols of the encoder (11B13B) are used.

[0108] The minimum (smallest) disparity of the encoder is 11B13B +-3. Thus, in total, these four encoders can reliably compensate for a disparity of +-12 (4*+-3) per symbol.

[0109] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, each with a maximum disparity of +-2. Thus, in the extreme case, these six encoders produce a disparity of exactly +-12 (2*+-6). This can be reliably compensated by the 11B13B encoders.

[0110] According to one aspect of the present invention, the method achieves the same quality as an 8B10B code but with half the overhead (loss due to coding).

[0111] The implementation of the encoding and decoding hardware requires only minimal resources (logic) due to the use of several small encoders instead of one large one.

[0112] The encoding can typically be done entirely in one clock cycle of the parallel data path (no pipelining necessary).

[0113] The control of the disparity of the 128-bit symbol can be realized with (very) little logic, and can be realized entirely within one clock of the data path (slowly), instead of calculating the disparity by counting the one and zero bits in the serial data stream with the very fast serial clock.

[0114] Due to the deterministic disparity and run length, further scrambling is not necessary, thus enabling fast synchronization to the data stream on the receiver side (no scrambler synchronization required).

[0115] This is very useful, among other things, for power-save modes, where the link can be turned off for energy-saving purposes and then turned back on when needed. Fast synchronization between transmitter and receiver is essential for this.

[0116] According to one aspect of the present invention, a 112-bit data word with any disparity (maximum disparity: 112) and any run length (maximum run length: 112) is encoded into a 128-bit symbol. The overhead resulting from the encoding is thus 14.2%.

[0117] The maximum run length occurring in the symbol, as well as in any sequencing of any symbols, is 8 equal bits.

[0118] The maximum disparity in the long mean is 0. The disparity in a symbol is less than 9.

[0119] The complexity of the logic is minimal, comparable to 10 8B / 10B encoders (with the well-known disadvantage of the large overhead).

[0120] This is achieved by the use, or parallel use, of several "small" encoders whose characteristics regarding disparity and run length are optimally matched to one another.

[0121] The encoders 11B12B, 7B8B and 6B8B all generate symbols with a guaranteed maximum run length of 6, even with arbitrary sequencing of the (sub)symbols.

[0122] According to one aspect of the present invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7 or 5 at the beginning or end of the symbol. Due to the sequencing (Fig. 2) of the (11B13B) with the other encoders, a maximum run length of 8 can be created in the symbol.

[0123] See encoder properties as follows: To further reduce hardware complexity, four small encoders (11B13B) are used, whose disparity can be controlled with respect to sign (+-).

[0124] According to one aspect of the present invention, symbol disparity is controlled by each encoder calculating the parity of "its" subsymbol. This is done with little effort, since the subsymbol has only a few bits.

[0125] For four of the eleven encoders, the sign of the disparity of the subsymbol can be actively controlled by inverting the generated subsymbol. The encoders (11B13B) have the special feature that their symbols generate a symbol with positive disparity (+3... +9) for all input data. Inverting the subsymbol produces a symbol with negative disparity (-3...-9).

[0126] This allows the disparity (-2, -1, 0, 1, 2) of the subsymbols of the other encoders (11B12B and 7B8B) to be compensated. The 6B8B encoder generates symbols whose disparity is always 0. Then, all (sub)parities of the encoders (11B12B and 7B8B) are added together, and the result determines how many inverted and non-inverted symbols of the encoder (11B13B) are used.

[0127] The minimum (smallest) disparity of the encoder is 11B13B +-3. Thus, in total, these four encoders can reliably compensate for a disparity of +-12 (4*+-3) per symbol.

[0128] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, each with a maximum disparity of +-2. Thus, in the extreme case, these six encoders produce a disparity of exactly +-12 (2*+-6). This can be reliably compensated by the 11B13B encoders.

[0129] The method achieves the same quality as an 8B10B code but with half the overhead (loss due to coding).

[0130] The implementation of the encoding and decoding hardware requires only minimal resources (logic) due to the use of several small encoders instead of one large one.

[0131] The encoding can typically be done entirely in one clock cycle of the parallel data path (no pipelining necessary).

[0132] The control of the disparity of the 128-bit symbol can be realized with (very) little logic, and can be realized entirely within one clock of the data path (slowly), instead of calculating the disparity by counting the one and zero bits in the serial data stream with the very fast serial clock.

[0133] Due to the deterministic disparity and run length, further scrambling is not necessary, thus enabling fast synchronization to the data stream on the receiver side (no scrambler synchronization required).

[0134] This is very useful, among other things, for power-save modes, where the link can be turned off for energy-saving purposes and then turned back on when needed. Fast synchronization between transmitter and receiver is essential for this.

[0135] Figure 5 shows a data format as it is used for example in Figure 2 , 3and / or 4 can be used. Again, the 128-bit total symbol is shown, as well as the arbitrary 112-bit data sequence. Overall, the arbitrary bit sequence and the total symbol can have different header data or frame data.

[0136] The following presents some concrete options for translating segments of any bit sequence into subsymbols to minimize or eliminate disparity. A first table shows a conversion from 6 bits to 8 bits, a second table shows a conversion from 7 bits to 8 bits, a third table shows a conversion from 11 bits to 12 bits, and a fourth table shows a conversion from 11 bits to 13 bits. Thus, segments of 6, 7, or 11 bits are converted into subsymbols of 8, 12, or 13 bits. The encodings shown are examples and illustrate the technical effect achieved here. The present invention has been empirically evaluated, and the proposed encoding achieves the disparity optimization of 112 bits so that only 128 bits are required. This corresponds to an overhead of just 14%.

[0137] Here, cells are used as a synonym for frames. These can also refer to packets. Cell format / frame format

[0138] According to one aspect of the present invention, the cell consists of a header with a fixed bit length, a payload area with 4 selectable bit lengths and a footer again with a fixed bit length.

[0139] The cell structure is a sequence of bits as follows: A 7-bit virtual path identifier (VP), which represents a unique address of the virtual path. A 3-bit sequence number (SN), which numbers the cells consecutively in their sequence. A 2-bit cell type (CT) identifier, which specifies the length of the payload. A 3-bit payload information (PI), which contains additional information about the payload. This can also be used to synchronize payload data with frame data or control data. A 10-bit CRC polynomial (HCRC) for error protection of the header information. The polynomial has a Hamming distance of 5 up to a bit sequence of 21 bits (P=0x2B9). The payload (PL) area has a length of 187, 411, 635, or 859 bits, depending on the CT value. The shortest payload is chosen so that it is still larger than the largest supported (video) streaming bus width. (Should simplify the mapping of current data to cell payload).Finally, a 12-bit CRC polynomial (PCRC) provides error protection for the payload data. The polynomial has a Hamming distance of 4 up to a bit sequence of 2035 bits (P=0x8F3). Format of the transmission frames

[0140] According to one aspect of the present invention, the transmission frame consists of a sequence of M-bit words. The frame begins with an M-bit "comma" word from a defined sequence of comma words for frame alignment. This is followed by K cells. The cells consist of 2, 4, 6, or 8 N-bit words containing the header, payload, and footer. These N-bit words are encoded into M-bit symbols (line encoding).

[0141] This format is chosen to allow processing of cell data at reasonable time frequencies, provided that the serializer / deserializer always processes a block of M bits.

[0142] Figure 6Ashows an excerpt of an example coding of data segments to symbols, where 6 bits are coded to 8 bits in such a way that the disparity is optimized according to one aspect of the present invention. For example, a segment 000000 is coded to a subsymbol 00101011, i.e., a 6B8B coder. Furthermore, Figure 6B a 7B8B encoder, Figure 6C an 11B12B encoder and Figure 6D an 11B13B encoder.

Claims

1. A method in an automobile for generating an efficiently transferable bit sequence with a restricted disparity and a restricted run length, comprising - providing (100) an arbitrary bit sequence; - segmenting (101) the provided bit sequence into a predefined sequence of segments according to a respective predefined bit length; - encoding (102) each segment into a respective sub-symbol, using one encoding unit per segment from a plurality of encoding units, wherein a first subset of encoding units actively controls a sign of a disparity of the sub-symbol by inverting the disparity of the generated sub-symbol to equalise a disparity of a second subset of encoding units, wherein the disparity of the second subset of coding units is not controllable and wherein a juxtaposition of the partial symbols results in the efficiently transmittable bit sequence.

2. The method according to claim 1, characterised in that the arbitrary bit sequence is unrestricted in its disparity and run length.

3. The method according to claim 1 or 2, characterised in that the active control of the sign is carried out in each case by means of conditional bitwise inversion of the symbol.

4. The method according to one of the preceding claims, characterised in that conditional inversion takes place as a function of the disparity of an overall symbol, which is formed from all partial symbols.

5. The method according to claim 4, characterised in that the dependency is influenced in such a way that a magnitude value of the disparity is minimised.

6. The method according to one of the preceding claims, characterised in that an amount value is minimised in such a way that, in the case of a positive overall symbol disparity, it is counteracted by a negative parity of the partial symbols.

7. The method according to one of the preceding claims, characterised in that an amount value is minimised in such a way that, in the event of a negative overall symbol disparity, it is counteracted by a positive parity of the sub-symbols.

8. The method according to one of the preceding claims, characterised in that the active control takes place as a function of total symbols already transmitted in such a way that the disparity of all total symbols is minimised.

9. The method according to one of the preceding claims, characterised in that coding units of the first subset code segments of 11 bits to subsymbols of 13 bits.

10. The method according to one of the preceding claims, characterised in that coding units of the first subset have a disparity between +3 and +9, which are specifically inverted to -3 to -9 by bitwise inversion of the partial symbol.

11. The method according to one of the preceding claims, characterised in that a run length in partial symbols is at most 7.

12. The method according to one of the preceding claims, characterised in that a run length of the sub-symbol in coding units of the first subset is at most 5 starting from the most significant and / or the least significant bit.

13. The method according to one of the preceding claims, characterised in that, in the case of coding units of the second subset, 11 bit segments are coded to 12 bit sub-symbols or 7 bit segments are coded to 8 bit sub-symbols or 6 bit segments are coded to 8 bit sub-symbols.

14. The method according to one of the preceding claims, characterised in that a disparity between -2 and +2 is generated for coding units of the second subset.

15. The method according to one of the preceding claims, characterised in that a run length in the generated partial symbol is 6 for coding units of the second subset.

16. The method according to one of the preceding claims, characterised in that coding units of the second subset generate partial symbols which have a maximum run length of 3 at the edge.

17. The method according to one of the preceding claims, characterised in that the coding units are addressed in parallel and each encode a segment into a partial symbol.

18. The method according to one of the preceding claims, characterised in that the coding units are addressed in the sequence 21212221212, wherein a 1 stands for a coding unit of the first subset and a 2 stands for a coding unit of the second subset.

19. The method according to one of the preceding claims, characterised in that a multiplexer selects the data stream which contributes to minimising the overall disparity of the overall symbol when a positive data stream and a negative data stream are present with respect to the disparity.

20. A system arrangement in an automobile for generating an efficiently transferable bit sequence with a limited disparity and a limited run length, comprising - an interface unit arranged to provide (100) an arbitrary bit sequence; - a segmentation unit set up for segmenting (101) the provided bit sequence into a predefined sequence of segments according to a predefined bit length in each case; - an encoding arrangement arranged for encoding (102) each segment into a respective partial symbol, using one encoding unit per segment from a plurality of encoding units, wherein a first subset of encoding units actively controls a sign of a disparity of the subsymbol by inverting the disparity of the generated subsymbol to compensate for a disparity of a second subset of encoding units, wherein the disparity of the second subset of encoding units is not controllable, and wherein a juxtaposition of the subsymbols results in the efficiently transmittable bit sequence.

21. A computer program product comprising instructions which, when the program is executed by at least one computer, cause the computer to perform the steps of the method according to any one of claims 1 to 19.

22. A computer-readable storage medium comprising instructions which, when executed by at least one computer, cause the computer to perform the steps of the method according to any one of claims 1 to 19.