DEVICE AND METHOD FOR DETECTING AN ELECTRIC CONDITIONAL CURRENT WITH OPTIMIZED SAMPLING RATE

Description

[0001] The invention relates to a device and a method for measuring the current value of a line current using a shunt resistor. Very small currents also occur. These very small currents lead to very small voltage drops across the shunt resistor.

[0002] When converting such very small input signals with very small voltage drops across the shunt resistor to analog-to-digital, the averaging of multiple measurements required for noise reduction leads to long conversion times. These long conversion times are critical in many applications.

[0003] During analog-to-digital conversion of very small input signals, noise leads to varying digital values ​​even with a constant input signal. Oversampling by averaging over several cycles can reduce this effect (oversampling and decimation - OSR). However, this increases the time until a valid measurement value is available. For input signals with a larger amplitude, this effect is less significant, as other disturbances, such as the reference, temperature drift, and gain error, determine the overall accuracy in this range.

[0004] To increase the signal-to-noise ratio (SNR) for small input signals, the device increases the number of measurements (oversampling rate [OSR]), subsequently averaging the measurements. For every doubling of accuracy, the device requires four times the number of measurements needed to determine the measurement result. This quickly leads to a very high number of required samples (measurements), which the device averages for a single measurement run. This high number of measurements results in very long conversion times.

[0005] DE 10 2011 078 698 B3 discloses a device for detecting an electrical current in a line. However, with the device disclosed in DE 10 2011 078 698 B3, it is not possible to achieve a current measurement with a good signal-to-noise ratio, even with small input signals.

[0006] The object of the invention is to provide a solution that does not have the aforementioned disadvantages of the prior art and offers further advantages. In particular, it aims to provide an improved device for measuring current.

[0007] To solve the problem, a device and a method according to the independent claims are proposed.

[0008] Further advantageous embodiments of the invention can be found in the dependent claims, the description, and the figures.

[0009] The invention comprises a dynamic adjustment of the averaging of the measured values, which measured values ​​are recorded by an evaluation electronics at a sensor element of a sensor.

[0010] The evaluation electronics include an analog-to-digital converter.

[0011] During the acquisition of the measured values, the evaluation electronics dynamically adjusts the speed of its analog-to-digital converter according to the size of an input signal to the evaluation electronics, so that an optimal conversion for the input signal takes place.

[0012] The number of measurements that the evaluation electronics perform on the sensor element per unit of time is therefore dependent on the magnitude of the input signal, i.e., the level at the sensor element. For small input signals, the evaluation electronics select a significantly larger number of sampling points and thus measured values ​​in order to achieve good noise suppression (signal-to-noise ratio [SNR]) in this range. In the range of larger input voltages, the evaluation electronics select a lower sampling rate and thus a lower oversampling rate (OSR). Simultaneously, with a suitable architecture, the evaluation electronics can change the speed of its subsystem consisting of the analog-to-digital converter and the subsequent oversampling and decimation filter inversely to the oversampling rate (OSR).The speed of the device is determined by multiplying the sampling rate of the analog-to-digital converter by the number of samples used for averaging by the subsequent oversampling and decimation filter. This is possible because, at low input voltages, the settling time to 1 LSB is also shorter than at high input voltages.

[0013] The invention relates to a device for detecting an electrical current ILTG in a conductor. The electrical current ILTG flows from a first node to a third node. The device includes a shunt resistor. The device comprises a first resistor. The value of the first resistor can be 0 ohms. The first resistor can therefore also be just a segment of an electrical conductor. The device comprises a second resistor. The value of the second resistor can also be 0 ohms. The second resistor can therefore also be just a segment of an electrical conductor.

[0014] The shunt resistor typically has a first terminal and a second terminal. The first resistor has a first terminal and a second terminal. The second resistor has a first terminal and a second terminal.

[0015] The first node connects the first terminal of the shunt resistor directly or indirectly electrically to the first terminal of the first resistor.

[0016] The third node connects the second terminal of the shunt resistor directly or indirectly to the first terminal of the second resistor.

[0017] The electrical conduction current I LTG flows through the shunt resistor.

[0018] The purpose of the device is to determine the value of the electrical line current I LTG.

[0019] In particular, the device comprises an amplifier and an analog-to-digital converter. The device also includes a reworking and decimation filter.

[0020] In particular, the reworking and decimation filter is a linear filter. This means that an increase in the input signal results in a corresponding proportional change in the output signal.

[0021] In particular, the device comprises a signal path. Specifically, the signal path extends from the shunt resistor to the output of the oversampling and decimation filter. The shunt resistor serves as the signal source, and the oversampling and decimation filter as the measured value output.

[0022] In particular, the signal path includes the amplifier and the analog-to-digital converter. Specifically, the amplifier is located between the shunt resistor and the output of the oversampling and decimation filter.

[0023] In particular, the analog-to-digital converter is located between the shunt resistor and the output of the oversampling and decimation filter.

[0024] The amplifier has a positive input (+). It also has a negative input (-). Furthermore, the amplifier has an output in the form of an amplifier output signal.

[0025] The analog-to-digital converter has an analog input and a digital output signal.

[0026] The revision and decimation filter has a digital input and an output with an output signal.

[0027] A second node connects the second terminal of the first resistor directly or indirectly, via a pre-filter, to the positive input + of the amplifier.

[0028] A fourth node connects the second terminal of the second resistor directly or indirectly, electrically via the pre-filter, to the negative input of the amplifier.

[0029] The amplifier output is electrically connected to the input of the analog-to-digital converter (ADC). The digital output of the ADC is electrically connected to the input of the oversampling and decimation filter. The digital output of the ADC typically comprises multiple electrical lines. The ADC samples the analog value of its input signal at specified sampling times. Preferably, these sampling times are periodic with a defined sampling period. For the purposes of this document, the reciprocal of the sampling period is the sampling frequency. The sampling frequency divided by 2π is, for the purposes of this document, the sampling rate. To determine a sampling period, for the purposes of this document, a suitable measuring device records the time interval between a first sampling time and a second sampling time immediately following it.At these sampling points, the analog-to-digital converter (ADC) converts the analog value of its input signal into a digital value. The ADC outputs this digital value as a digital output signal. After this sampling, the ADC uses the digital output signal to indicate the corresponding sample value to the input of the oversampling and decimation filter.

[0030] The output values ​​of the reworking and decimation filter's output signal represent, at least temporarily, the current values ​​for a line current ILTG through the shunt resistor as detected by the device. The limitation to "temporary" arises from the fact that the analog-to-digital converter can only detect the current value of the line current ILTG at the sampling times. In contrast to the prior art, this document proposes that the device additionally include a timing unit. Specifically, the timing unit detects at least one timing input signal. This document will hereinafter refer to the value of such a timing input signal as the timing input value.

[0031] In particular, the timer unit records at least one respective timer input value. Preferably, the timer unit records several timer input values.

[0032] The nature of the exemplary proposed timer input value signals and the associated exemplary proposed timer input value will be discussed in more detail in the following sections. The core idea of ​​the invention is that the timer unit influences at least one signal transmission property of a sub-device within the signal path between the shunt resistor and the output signal of the oversampling and decimation filter, at least temporarily, depending on at least one detected respective timer input value.

[0033] For the purposes of this document, the exemplary sub-devices are those within the signal path between the shunt resistor and the output signal of the oversampling and decimation filter. a) a pre-filter, b) the amplifier and c) the analog-to-digital converter and the oversampling and decimation filter.

[0034] Possible timer input signals within the meaning of this document are: the input voltage U e of the amplifier, the amplifier output signal of the amplifier, the input signal of the analog-to-digital converter, the output signal of the analog-to-digital converter, the input signal of the oversampling and decimation filter or the decimation filter input signal, and the output signal of the oversampling and decimation filter or the decimation filter output signal.

[0035] In particular, the use of the following timer input value signals is preferred: the amplifier output signal of the amplifier, the input signal of the analog-to-digital converter, and the output signal of the oversampling and decimation filter or the decimation filter output signal.

[0036] This device has the advantage that it can increase the sampling rate for small signal amplitudes, while allowing for a longer settling time for large signal amplitudes. This optimizes the relative resolution, or rather the time it takes to achieve that resolution.

[0037] In one embodiment of the device, the timing unit can influence at least one, and in particular several, and especially all sampling times of the analog-to-digital converter. This influence is an influence on a signal transmission property in a sub-device within the aforementioned signal path. In this embodiment, the aforementioned sub-device is the analog-to-digital converter. According to the proposal, the device, in this embodiment, performs this influence on the signal transmission property of the analog-to-digital converter depending on the at least one detected respective timing input value. Possible timing input values ​​are described above.In this configuration of the device, the timing unit can, for example, also influence a filter or amplifier characteristic in the signal path between the shunt resistor and the output signal of the oversampling and decimation filter as a signal transmission characteristic, depending on the at least one detected respective timing input value. This allows the timing unit of the device to adapt the sampling rate to a level of the input signal, i.e., to the current value of the line current I LTG. Furthermore, this allows the timing unit of the device to reconfigure the filters. This enables optimal adaptation of the filtering in the pre-filter and / or optimal adaptation of the filtering in the oversampling and decimation filter to the sampling rate of the analog-to-digital converter.

[0038] Another embodiment of the device deals with individual sampling times.

[0039] In this configuration of the device, the timing unit detects the sampling times of the analog-to-digital converter as a function of at least one detected respective timing input value. This allows the timing unit of the device to optimally adapt a) the sampling rate to the level of the input signal, i.e., to the current value of the line current I LTG.

[0040] In a further embodiment of the device, the timing unit influences the properties of the oversampling and decimation filter depending on the at least one detected timing input value. Possible timing input values ​​are explained above. This allows the timing unit to reconfigure the oversampling and decimation filter so that the filtering in the oversampling and decimation filter is optimally adapted to, for example, the sampling rate of the analog-to-digital converter.

[0041] In a further embodiment of the device, the timing unit influences properties of the oversampling and decimation filter in the form of filter frequencies and / or attenuations and / or gains of the oversampling and decimation filter, depending on the at least one detected timing input value. Possible timing input values ​​are explained above. This allows the timing unit to reconfigure the oversampling and decimation filter so that the filtering in the oversampling and decimation filter is optimally adapted to, for example, the sampling rate of the analog-to-digital converter.

[0042] In a further embodiment of the device, the timer unit influences properties of the pre-filter depending on the at least one detected respective timer input value.

[0043] In a further embodiment of the device, the timing unit influences properties of the pre-filter in the form of filter frequencies and / or attenuations and / or gains of the pre-filter depending on the at least one detected respective timing input value. Preferably, for the purposes of this document, the pre-filter is a low-pass or band-pass filter with an upper cutoff frequency f0V.

[0044] In another embodiment of the device, a timer input signal serves as the input signal of the analog-to-digital converter (ADC). The corresponding timer input value is then preferably an ADC input value of the analog-to-digital converter's input signal. In this variant as well, the device can adjust the relative error to the signal level.

[0045] In a further embodiment of the device, the timing unit, for example, acquires values ​​of the analog-to-digital converter's input signal, at least temporarily, in the form of acquired ADC input values ​​as timing input values ​​of a timing input signal. The timing unit preferentially influences the sampling times of the analog-to-digital converter depending on the acquired ADC input values. In this variant as well, the device can adjust the relative error to the signal level.

[0046] In a further embodiment of the device, the timing unit at least temporarily acquires values ​​of the input signal of the analog-to-digital converter in the form of acquired ADC input values ​​as timing input values ​​of a timing input signal. The timing unit preferably influences properties of the rework and decimation filter, in particular the filter frequencies and / or the gain and / or the attenuation of the rework and decimation filter, depending on the acquired ADC input values. This enables optimal adaptation of the rework and decimation filter to the optimized sampling rate and the signal level of the line current value ILTG.

[0047] In a further embodiment of the device, the timing unit at least temporarily acquires values ​​of the analog-to-digital converter's input signal in the form of acquired ADC input values ​​as timing input values ​​of a timing input signal. The timing unit thereby influences the properties of the pre-filter, in particular the filter frequencies and / or the gain and / or the attenuation of the pre-filter, depending on the acquired ADC input values. In this way, the device adapts the pre-filter to any changes in the sampling rates of the analog-to-digital converter.

[0048] In a further embodiment of the device, the timing unit at least intermittently acquires values ​​of the analog-to-digital converter's input signal in the form of ADC input values. These acquired ADC input values ​​then serve, for example, as timing input values ​​for a timing input signal. These timing input values ​​then influence the amplifier's characteristics depending on the acquired ADC input values. The affected amplifier characteristics can include, in particular, the amplifier's gain and / or attenuation. This allows the device to better adapt the amplifier's behavior and characteristics to potentially changed sampling rates of the analog-to-digital converter and / or the amplitude of the line current ILTG.

[0049] In a further embodiment of the device, a timer input signal is the output signal of the analog-to-digital converter. A corresponding timer input value of the timer input signal is then an ADC output value of the analog-to-digital converter's output signal.

[0050] In a further embodiment of the device, the timing unit preferably acquires at least intermittent values ​​of the analog-to-digital converter's output signal in the form of acquired ADC output values ​​as timing input values ​​of a timing input signal and influences sampling times depending on the acquired ADC output values. Preferably, the timing unit influences several or all sampling times depending on the acquired ADC output values.

[0051] In a further embodiment of the device, the timing unit at least intermittently detects values ​​of the analog-to-digital converter's output signal. These detected values ​​of the analog-to-digital converter's output signal are preferably in the form of detected ADC output values. These detected ADC output values ​​serve as timing input values ​​for a timing input signal. These timing input values ​​influence the properties of the rework and decimation filter depending on the detected ADC output values. The influenced properties of the rework and decimation filter can, in particular, include the filter frequencies and / or the gain and / or the attenuation of the rework and decimation filter.

[0052] In a further embodiment of the device, the timing unit preferably acquires values ​​of the analog-to-digital converter's output signal, at least intermittently. The acquired values ​​of the analog-to-digital converter's output signal are preferably in the form of acquired ADC output values. These acquired ADC output values ​​preferably serve as timing input values ​​for a timing input signal. The timing input values ​​of the timing input signal preferably influence the properties of the pre-filter depending on the acquired ADC output values. The influenced properties of the pre-filter can, in particular, include the filter frequencies and / or the gain and / or the attenuation of the pre-filter.

[0053] In a further embodiment of the device, the timing unit at least intermittently acquires values ​​of the analog-to-digital converter's output signal. The values ​​of the analog-to-digital converter's output signal are preferably in the form of acquired ADC output values. These acquired ADC output values ​​preferably serve as timing input values ​​for a timing input signal. The acquired timing input values ​​influence amplifier characteristics depending on the acquired ADC output values. The influenced amplifier characteristics can, in particular, include the amplifier's gain and / or attenuation.

[0054] In a further embodiment of the device, a timer input signal is the input signal of the oversampling and decimation filter. In this case, a corresponding timer input value is a decimation filter input value of the input signal of the oversampling and decimation filter.

[0055] In a further embodiment of the device, the timing unit at least intermittently detects values ​​of the input signal of the oversampling and decimation filter. The detected values ​​of the input signal of the oversampling and decimation filter are preferably in the form of detected decimation filter input values. These detected decimation filter input values ​​preferably serve as timing input values ​​of a timing input signal. The timing input values ​​of the timing signal influence the sampling times depending on the detected decimation filter input values.

[0056] In a further embodiment of the device, the timing unit at least intermittently detects values ​​of the input signal of the oversampling and decimation filter. The detected values ​​of the input signal of the oversampling and decimation filter are preferably in the form of detected decimation filter input values. These detected decimation filter input values ​​preferably serve as timing input values ​​for a timing input signal. These timing input values ​​preferably influence properties of the oversampling and decimation filter depending on the detected decimation filter input values. Such properties of the oversampling and decimation filter can, in particular, be the filter frequencies and / or the gain and / or the attenuation of the oversampling and decimation filter.

[0057] In a further embodiment of the device, the timing unit at least intermittently detects values ​​of the input signal of the oversampling and decimation filter. Preferably, the detected values ​​of the input signal of the oversampling and decimation filter are in the form of detected decimation filter input values. These detected decimation filter input values ​​preferably serve as timing input values ​​of a timing input signal. These timing input values ​​of the timing input signal influence the properties of the pre-filter depending on the detected decimation filter input values. These properties of the pre-filter can include, in particular, the filter frequencies and / or the gain and / or the attenuation of the pre-filter.

[0058] In a further embodiment of the device, the timer unit at least intermittently detects values ​​of the input signal of the oversampling and decimation filter. The values ​​of the input signal of the oversampling and decimation filter are preferably in the form of detected decimation filter input values. These detected decimation filter input values ​​preferably serve as timer input values ​​of a timer input value signal. The timer unit influences the characteristics of the amplifier by means of these timer input values ​​of the timer input value signal. Thus, the timer unit influences the characteristics of the amplifier depending on the detected decimation filter input values. Such an influenced characteristic of the amplifier can be, for example, the gain and / or the attenuation of the amplifier.

[0059] In a further embodiment of the device, a timer input signal is the output signal of the oversampling and decimation filter. In this embodiment, for example, a corresponding timer input value is a decimation filter output value of the output signal of the oversampling and decimation filter.

[0060] In a further embodiment of the device, the timing unit at least intermittently detects values ​​of the output signal of the oversampling and decimation filter. This detection of the output signal values ​​of the oversampling and decimation filter preferably takes the form of detected decimation filter output values. These detected decimation filter output values ​​preferably serve as timing input values ​​of a timing input signal and influence sampling times depending on the detected decimation filter output values.

[0061] In a further embodiment of the device, the timer unit at least intermittently detects values ​​of the output signal of the oversampling and decimation filter. The values ​​of the oversampling and decimation filter's output signal are preferably in the form of detected decimation filter output values. These detected decimation filter output values ​​preferably serve as timer input values ​​for a timer input signal. The timer input values ​​of the timer input signal preferably influence properties of the oversampling and decimation filter as a function of the detected decimation filter output values. Such properties of the oversampling and decimation filter can, for example, include the filter frequencies and / or the gain and / or the attenuation of the oversampling and decimation filter.

[0062] In a further embodiment of the device, the timing unit at least temporarily acquires values ​​of the output signal of the oversampling and decimation filter in the form of acquired decimation filter output values ​​as timing input values ​​of a timing input signal. In this embodiment, the timing unit influences properties of the pre-filter depending on the acquired decimation filter output values. Such properties of the pre-filter can, for example, include the filter frequencies and / or the gain and / or the attenuation of the pre-filter.

[0063] For the purposes of this document, a sampling period represents the time between a first sampling point and a second sampling point. The first sampling point is the point in time at which the analog value of the input signal to the analog-to-digital converter is sampled by the analog-to-digital converter. The second sampling point is the second point in time at which the analog value of the input signal to the analog-to-digital converter is sampled by the analog-to-digital converter, with the second sampling point immediately following the first sampling point.

[0064] In a further embodiment of the device, the timer unit influences the sampling period of the analog-to-digital converter depending on the at least one detected respective timer input value.

[0065] According to a further embodiment of the device, the duration of the sampling period exceeds the value of a sampling period limit if the magnitudes of the detected ADC input values ​​are below a first ADC input threshold. Conversely, the duration of the sampling period is below the value of the sampling period limit if the magnitudes of the detected ADC input values ​​exceed the first ADC input threshold.

[0066] According to a further embodiment of the device, the sampling period exceeds a sampling period limit when the magnitudes of the detected ADC output values ​​are below a first ADC output threshold. Conversely, in this embodiment of the device, the sampling period is preferably below the sampling period limit when the magnitudes of the detected ADC output values ​​exceed the first ADC output threshold.

[0067] According to a further embodiment of the device, the sampling period exceeds a sampling period limit if the magnitudes of the detected decimation filter input values ​​are below a first decimation filter input threshold. In particular, the sampling period is below the sampling period limit if the magnitudes of the detected decimation filter input values ​​exceed the first decimation filter input threshold.

[0068] According to a further embodiment of the device, the sampling period exceeds a sampling period limit if the magnitudes of the detected decimation filter output values ​​are below a first decimation filter output threshold. In particular, the sampling period is below the sampling period limit if the magnitudes of the detected decimation filter output values ​​exceed the first decimation filter output threshold.

[0069] Preferably, the oversampling and decimation filter has an upper cutoff frequency fo.

[0070] According to a further embodiment of the device, the oversampling and decimation filter attenuates signal components with a signal component frequency above the upper cutoff frequency fo more strongly than signal components with a signal component frequency immediately below the upper cutoff frequency fo. This means that the oversampling and decimation filter behaves similarly to a low-pass filter with signal components with a signal component frequency at least near the cutoff frequency fo of the oversampling and decimation filter. The technical teaching presented here expressly points out that the oversampling and decimation filter can, for example, also be a band-pass filter or another filter with partial low-pass characteristics. Preferably, in this embodiment of the device, the timer unit influences the upper cutoff frequency fo of the oversampling and decimation filter depending on the at least one detected respective timer input value.

[0071] According to a further embodiment of the device, in a first subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is above a decimation cutoff frequency limit when the magnitudes of the detected ADC input values ​​are below a second ADC input threshold. In a second subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is below the decimation cutoff frequency limit when the magnitudes of the detected ADC input values ​​are above the second ADC input threshold.

[0072] According to a further embodiment of the device, in a first subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is above a decimation cutoff frequency limit when the magnitudes of the detected ADC output values ​​are below a second ADC output threshold. In a second subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is below the decimation cutoff frequency limit when the magnitudes of the detected ADC output values ​​are above the second ADC output threshold.

[0073] According to a further embodiment of the device, in a first subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is above a decimation cutoff frequency threshold when the magnitudes of the detected decimation filter input values ​​are below a second decimation filter input threshold. In a second subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is below the decimation cutoff frequency threshold when the magnitudes of the detected decimation filter input values ​​are above the second decimation filter input threshold.

[0074] According to a further embodiment of the device, in a first subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is above a decimation cutoff frequency threshold when the magnitudes of the detected decimation filter output values ​​are below a second decimation filter output threshold. In a second subconfiguration, the upper cutoff frequency fo of the oversampling and decimation filter is above the decimation cutoff frequency threshold when the magnitudes of the detected decimation filter output values ​​are above the second decimation filter output threshold.

[0075] According to a further embodiment of the device, the pre-filter preferably has an upper cutoff frequency f0V. Preferably, the pre-filter attenuates signal components with a signal component frequency above the upper cutoff frequency f0V more strongly than signal components with a signal component frequency immediately below the upper cutoff frequency f0V. According to this embodiment of the device, the timer unit influences the upper cutoff frequency f0V of the pre-filter depending on the at least one detected respective timer input value.

[0076] According to a further embodiment of the device, in a first subconfiguration the upper cutoff frequency foV of the pre-filter is above a pre-filter cutoff frequency limit when the magnitudes of the detected ADC input values ​​are below a third ADC input threshold. In a second subconfiguration, the upper cutoff frequency foV of the pre-filter is below the pre-filter cutoff frequency limit when the magnitudes of the detected ADC input values ​​are above the third ADC input threshold.

[0077] According to a further embodiment of the device, in a first subconfiguration the upper cutoff frequency foV of the pre-filter is above a pre-filter cutoff frequency limit when the magnitudes of the detected ADC output values ​​are below a third ADC output threshold. In a second subconfiguration, the upper cutoff frequency foV of the pre-filter is below the pre-filter cutoff frequency limit when the magnitudes of the detected ADC output values ​​are above the third ADC output threshold.

[0078] According to a further embodiment of the device, in a first subconfiguration, the upper cutoff frequency foV of the pre-filter is above a pre-filter cutoff frequency limit value when the magnitudes of the detected decimation filter input values ​​are below a third decimation filter input threshold value. In a second subconfiguration, the upper cutoff frequency foV of the pre-filter is below a pre-filter cutoff frequency limit value when the magnitudes of the detected decimation filter input values ​​are above the third decimation filter input threshold value.

[0079] According to a further embodiment of the device, in a first subconfiguration, the upper cutoff frequency foV of the pre-filter is above a pre-filter cutoff frequency limit value when the magnitudes of the detected decimation filter output values ​​are below a third decimation filter output threshold value. In a second subconfiguration, the upper cutoff frequency foV of the pre-filter is above a pre-filter cutoff frequency limit value when the magnitudes of the detected decimation filter output values ​​are above the third decimation filter output threshold value.

[0080] According to a further embodiment of the device, the amplifier has properties with defined values. The timing unit influences this property of the amplifier depending on the at least one detected timing input value. Such properties of the amplifier can, in particular, be gain and / or attenuation.

[0081] A further embodiment of the device is possible in two different sub-elaborations. In the first sub-elaboration, a property value of an amplifier lies above an amplifier property threshold if the magnitudes of the detected ADC input values ​​are below a fourth ADC input threshold. In the second, alternative sub-elaboration, a property value of an amplifier lies below an amplifier property threshold if the magnitudes of the detected ADC input values ​​are below a fourth ADC input threshold.In the second, alternative sub-model, the property value of the amplifier's characteristic exceeds the amplifier characteristic limit if the magnitudes of the detected ADC input values ​​exceed the fourth ADC input threshold. The document presented here therefore explicitly considers variants a) and b) of this model as alternatives to each other.

[0082] According to a further embodiment of the device, the device controls a property value of an amplifier property in a first way and a second way. In the first way, in a first subconfiguration, a property value of an amplifier property is above an amplifier property threshold if the magnitudes of the detected ADC output values ​​are below a fourth ADC output threshold. In a second subconfiguration, in the first way, a property value of an amplifier property is below the amplifier property threshold if the magnitudes of the detected ADC output values ​​are above the fourth ADC output threshold.In a control configuration of the second type, in a first subconfiguration, a property value of an amplifier property is below an amplifier property threshold if the magnitudes of the detected ADC output values ​​are below a fourth ADC output threshold. In a control configuration of the second type, in a second subconfiguration, a property value of an amplifier property is above the amplifier property threshold if the magnitudes of the detected ADC output values ​​are above the fourth ADC output threshold. The document presented here therefore explicitly provides the control variants of an amplifier property value according to the first type and according to the second type as alternatives to each other.

[0083] According to a further embodiment of the device, the device controls a property value of an amplifier property in a first way and a second way. In the first way, in a first subconfiguration, a property value of an amplifier property is above an amplifier property threshold if the magnitudes of the detected decimation filter input values ​​are below a fourth decimation filter input threshold. In a second subconfiguration, in the first way, a property value of an amplifier property is below the amplifier property threshold if the magnitudes of the detected decimation filter input values ​​are above the fourth decimation filter input threshold.In a control scheme of the second type, in a first subconfiguration, a property value of an amplifier property is below an amplifier property threshold if the magnitudes of the detected decimation filter input values ​​are below a fourth decimation filter input threshold. In a control scheme of the second type, in a second subconfiguration, a property value of an amplifier property is above the amplifier property threshold if the magnitudes of the detected decimation filter input values ​​are above the fourth decimation filter input threshold. The document presented here therefore explicitly provides the variants of controlling a property value of an amplifier property according to the first type and according to the second type as alternatives to each other.

[0084] According to a further embodiment of the device, the device controls a property value of an amplifier property in a first way and a second way. In the first way, in a first subconfiguration, a property value of an amplifier property is below an amplifier property threshold if the magnitudes of the detected decimation filter output values ​​are below a fourth decimation filter output threshold. In a second subconfiguration, in the first way, a property value of an amplifier property is above the amplifier property threshold if the magnitudes of the detected decimation filter output values ​​are above the third decimation filter output threshold.In a control scheme of the second type, in a first subconfiguration, a property value of an amplifier property is above an amplifier property threshold if the magnitudes of the detected decimation filter output values ​​are below a fourth decimation filter output threshold. In a control scheme of the second type, in a second subconfiguration, a property value of an amplifier property is below the amplifier property threshold if the magnitudes of the detected decimation filter output values ​​are above the third decimation filter output threshold. The document presented here therefore explicitly provides the variants of controlling a property value of an amplifier property according to the first type and according to the second type as alternatives to each other.

[0085] The above device corresponds to a method. This method is for detecting an electric current ILTG in a line. The electric current flows through a shunt resistor. As a result of this current flow, a shunt resistance voltage US drops across the shunt resistor.

[0086] The method involves capturing and pre-filtering the shunt resistance voltage US to an amplifier input voltage U e using a pre-filter.

[0087] Furthermore, the method includes capturing and amplifying the amplifier input voltage U e to the said amplifier output signal by means of an amplifier.

[0088] Furthermore, the method in the signal path includes sampling the amplifier output signal at a sampling rate to a decimation filter input signal using an analog-to-digital converter.

[0089] Furthermore, the method in the signal path includes filtering the decimation filter input signal to a decimation filter output signal using an oversampling and decimation filter.

[0090] Furthermore, the method includes providing the decimation filter output signal as a measured value signal for at least one value of the electrical line current ILTG in a line. The typically digital value of the decimation filter output signal represents the current value of the electrical line current ILTG.

[0091] The method presented here is characterized in its first iteration by the fact that the pre-filtering of the shunt resistance voltage US to an amplifier input voltage U e depends on a value of the amplifier output signal as a timer input value.

[0092] The method presented here is characterized in a second embodiment by the fact that the pre-filtering of the shunt resistance voltage US to an amplifier input voltage U e depends on a value of the decimation filter input signal as a timer input value.

[0093] The method presented here is characterized in a third embodiment by the fact that the pre-filtering of the shunt resistance voltage US to an amplifier input voltage U e depends on a value of the decimation filter output signal as a timer input value.

[0094] The method presented here is characterized in a fourth embodiment by the fact that the detection and amplification of the amplifier input voltage U e to an amplifier output signal depends on a value of the amplifier output signal as a timer input value.

[0095] The method presented here is characterized in a fifth embodiment by the fact that the detection and amplification of the amplifier input voltage U e to an amplifier output signal depends on a value of the decimation filter input signal as a timer input value.

[0096] The method presented here is characterized in a sixth iteration by the fact that the detection and amplification of the amplifier input voltage U e to an amplifier output signal depends on a value of the decimation filter output signal as a timer input value.

[0097] The method presented here is characterized in a seventh iteration by the fact that the sampling of the amplifier output signal at a sampling rate to a decimation filter input signal depends on a value of the amplifier output signal as a timer input value.

[0098] The method presented here is characterized in an eighth iteration by the fact that the sampling of the amplifier output signal with a sampling rate to a decimation filter input signal depends on a value of the decimation filter input signal as a timer input value.

[0099] The method presented here is characterized in a ninth iteration by the fact that the sampling of the amplifier output signal with a sampling rate to a decimation filter input signal depends on a value of the decimation filter output signal as a timer input value.

[0100] The method presented here is characterized in a tenth iteration by the fact that the filtering of the decimation filter input signal to a decimation filter output signal depends on a value of the amplifier output signal as the timer input value.

[0101] The method presented here is characterized in an eleventh iteration by the fact that the filtering of the decimation filter input signal to a decimation filter output signal depends on a value of the decimation filter input signal as a timer input value.

[0102] The method presented here is characterized in its twelfth iteration by the fact that the filtering of the decimation filter input signal to a decimation filter output signal depends on a value of the decimation filter output signal as a timer input value.

[0103] A revision of the technical principles presented here may allow for the combination of the first through twelfth iterations of the method. Some of these iterations exhibit feedback loops that can lead to instabilities. Therefore, it is advisable for the timing unit in these cases to have a low-pass filter characteristic and not to react arbitrarily quickly to changes.

[0104] In a thirteenth iteration of the method presented here, a filter property of the pre-filtering of the shunt resistance voltage US to an amplifier input voltage U e, in particular a pre-filter cutoff frequency f oV, depends on the timer input value. With regard to the timer input values, this document refers again to the preceding text.

[0105] In a fourteenth embodiment of the method presented here, a property of the detection and amplification of the amplifier input voltage U e to an amplifier output signal, in particular an amplification or an attenuation, depends on the timer input value.

[0106] In a fifteenth embodiment of the method presented here, a property of the sampling of the amplifier output signal to a decimation filter input signal, in particular a sampling time and / or a sampling period, depends on the timer input value.

[0107] In a sixteenth embodiment of the method presented here, a property of filtering the decimation filter input signal to a decimation filter output signal, in particular a filter cutoff frequency fo , depends on the timer input value.

[0108] In a seventeenth iteration of the method presented here, the pre-filtering step is performed in either a first or a second way. When the pre-filtering step is performed in the first way, in the case of a first subconfiguration, the pre-filter cutoff frequency f0V is above a pre-filter threshold if the magnitudes of timer input values ​​are below a first input threshold. In the case of a second subconfiguration, when the pre-filtering step is performed in the first way, the pre-filter cutoff frequency f0V is below a pre-filter threshold if the magnitudes of timer input values ​​are below the first input threshold. In the case of a first subconfiguration, when the pre-filtering step is performed in the second way, the pre-filter cutoff frequency f0V is below a pre-filter threshold if the magnitudes of timer input values ​​are below the first input threshold.

[0109] In particular, the first input threshold consists of two different thresholds. Specifically, the first input threshold comprises a higher threshold for switching on and a lower threshold for resetting. This prevents continuous switching when the magnitudes of timer input values ​​are close to the first input threshold.

[0110] When the pre-filtering step is performed in the second manner, in the case of a second subconfiguration, the pre-filter cutoff frequency f0V is higher than the pre-filter limit value if the magnitudes of timer input values ​​exceed the first input threshold. This document therefore explicitly presents the variants of performing the pre-filtering step according to the first and second methods as alternatives to each other.

[0111] In an eighteenth iteration of the method presented here, the amplification step is performed in either a first or a second way. When the amplification step is performed in the first way, in the case of a first subconfiguration, the amount of amplification exceeds a limit value if the values ​​of the timer inputs are below a second input threshold. Conversely, when the amplification step is performed in the first way, in the case of a second subconfiguration, the amount of amplification is below the limit value if the values ​​of the timer inputs exceed the second input threshold.When performing the amplification step in the second way, in the case of a first subconfiguration, the amount of amplification is below an amplification limit if the amounts of timer input values ​​are below the second input threshold.

[0112] In particular, the second input threshold consists of two different thresholds. Specifically, the second input threshold comprises a higher threshold for switching on and a lower threshold for resetting. This prevents continuous switching when the magnitudes of timer input values ​​are close to the second input threshold.

[0113] When the amplification step is performed in the second manner, in the case of a second subconfiguration, the amount of amplification exceeds the amplification limit if the values ​​of the timer inputs exceed the second input threshold. The document presented here therefore explicitly presents the variants of performing the amplification step according to the first and second methods as alternatives to each other.

[0114] In a nineteenth iteration of the method presented here, the procedure performs the sampling step in either a first or a second way. When the sampling step is performed in the first way, in the case of a first subconfiguration, the sampling period exceeds a sampling period limit if the magnitudes of timer input values ​​are below a third input threshold.

[0115] In particular, the third input threshold consists of two different thresholds. Specifically, the third input threshold comprises a higher threshold for switching on and a lower threshold for resetting. This prevents continuous switching when the values ​​of timer inputs are close to the third input threshold.

[0116] When performing the sampling step in the first manner, in the case of a second subconfiguration, the sampling period is below the sampling period limit if the magnitudes of timer input values ​​exceed the third input threshold. Similarly, when performing the sampling step in the second manner, in the case of a first subconfiguration, the sampling period is below the sampling period limit if the magnitudes of timer input values ​​are below the third input threshold. Conversely, when performing the sampling step in the second manner, in the case of a second subconfiguration, the sampling period is above the sampling period limit if the magnitudes of timer input values ​​exceed the third input threshold. This document therefore explicitly presents the variants of performing the sampling step according to the first and second methods as alternatives to each other.

[0117] In a twentieth iteration of the method presented here, the filtering step is performed in either a first or a second way. When the filtering step is performed in the first way, in the case of a first subconfiguration, the magnitude of the filter cutoff frequency fo is above a filter cutoff frequency limit value if the magnitudes of timer input values ​​are below a fourth input threshold. When the filtering step is performed in the first way, in the case of a second subconfiguration, the magnitude of the filter cutoff frequency fo is below the filter cutoff frequency limit value if the magnitudes of timer input values ​​are above the fourth input threshold.When performing the filtering process step in the second way, in the case of a first subconfiguration, the magnitude of the filter cutoff frequency fo is below the filter cutoff frequency limit if the magnitudes of timer input values ​​are below a fourth input threshold.

[0118] In particular, the fourth input threshold consists of two different thresholds. Specifically, the fourth input threshold comprises a higher threshold for switching on and a lower threshold for resetting. This prevents continuous switching when the values ​​of timer inputs are close to the fourth input threshold.

[0119] When performing the filtering step in the second manner, in the case of a second subconfiguration, the magnitude of the filter cutoff frequency fo exceeds the filter cutoff frequency limit value if the magnitudes of timer input values ​​exceed the fourth input threshold. This document therefore explicitly presents the variants of performing the filtering step according to the first and second methods as alternatives to each other.

[0120] The device and method according to the invention enable sensor measurements with very small voltage drops across the sensor element and consequently very small input voltages.

[0121] By combining these two principles, the time until the averaged result is obtained remains independent of the input voltage.

[0122] At low input voltages, the signal-to-noise ratio (SNR) is increased compared to the state of the art, without increasing the measurement time.

[0123] For high input voltages, the SNR is no longer the limiting parameter for accuracy. In the attached example, the time for a measurement without loss of accuracy is reduced from 5.6 ms to approximately 2.05 ms.

[0124] Further advantageous embodiments, features and functions of the invention are explained in connection with the examples shown in the figures.

[0125] This shows: Fig. 1 a schematic representation of a device according to the prior art; Fig. 2 an embodiment of the device according to the invention in a schematic representation; Fig. 3 a further embodiment of the device according to the invention in a schematic representation; Fig. 4 a further embodiment of the device according to the invention in a schematic representation; Fig. 5 a further embodiment of the device according to the invention in a schematic representation; Fig. 6 a further embodiment of the device according to the invention in a schematic representation; Fig. 7 a further embodiment of the device according to the invention in a schematic representation; Fig. 8 an example of dynamic oversampling as a function of the amplifier input voltage U e at the amplifier of a device according to the invention; Fig.9 a total conversion time TG as a function of the amplifier input voltage U e and operating ranges of a device according to the invention; and Fig. 10 a residual error e due to noise as a function of the amplifier input voltage U e . .

[0126] Fig. 1 shows, by way of example, the use of an oversampling and decimation filter 300 according to the state of the art (SdT).

[0127] The example application shown includes a circuit unit 100, an analog-to-digital converter 200, and an oversampling and decimation filter 300.

[0128] The circuit unit 100 according to the prior art comprises a first node 101, a second node 102, a third node 103 and a fourth node 104.

[0129] Furthermore, the circuit unit 100 includes a first resistor 111, a second resistor 112 and a shunt resistor 113.

[0130] The first resistor 111 can have a value of 0 ohms. Therefore, the first resistor 111 can also simply be a section of an electrical conductor.

[0131] The second resistor 112 can have a value of 0 ohms. Therefore, the second resistor 112 can also simply be a section of an electrical conductor.

[0132] The first node 101 is connected to a first terminal of the first resistor 111 and a first terminal of the shunt resistor 113.

[0133] A second connection of the first resistor 111 is connected to the second node 102.

[0134] A second connection of the shunt resistor 113 is connected to the third node 103.

[0135] Furthermore, a first terminal of the second resistor 112 is connected to the third node 103. Furthermore, a second terminal of the second resistor 112 is connected to the fourth node 104.

[0136] Thus, the first terminal of shunt resistor 113 is directly or indirectly electrically connected to the first terminal of the first resistor 111 and to the first node 101. Furthermore, the second terminal of shunt resistor 113 is directly or indirectly electrically connected to the first terminal of the second resistor 112 and to the third node 103.

[0137] The circuit unit 100 further includes a capacitor C and an amplifier 130.

[0138] The analog-to-digital converter 200 is electrically connected to the amplifier 130. Furthermore, the oversampling and decimation filter 300 is electrically connected to the analog-to-digital converter 200.

[0139] A signal path extends from the shunt resistor 113 to an output of the oversampling and decimation filter 300. The signal path includes the shunt resistor 113, the amplifier 130, the analog-to-digital converter 200, and the oversampling and decimation filter 300. The output of the amplifier 130 is electrically connected to the input of the analog-to-digital converter 200. Furthermore, the output of the analog-to-digital converter 200 is electrically connected to the input of the oversampling and decimation filter 300.

[0140] In particular, the shunt resistor 113 serves as a signal source.

[0141] In particular, the output of the oversampling and decimation filter 300 serves as a measured value output.

[0142] Circuit unit 100 is a circuit for shunt measurement of a current I LTG in a line. The line could, for example, be a data bus line. For instance, shunt resistor 113 could be a bus shunt resistor for an auto-addressing device for use in an auto-addressing procedure of a LIN data bus, CAN data bus, or another automotive data bus.

[0143] The electrical conduction current I LTG flows from the first node 101 via the shunt resistor 113 to the third node 103. A shunt resistance voltage US drops across the shunt resistor 113.

[0144] A first terminal of capacitor C is connected to the second node 102 and a second terminal of capacitor C is connected to the fourth node 104.

[0145] A first amplifier input 131 of amplifier 130 is connected to the second node 102, and a second amplifier input 132 of amplifier 130 is connected to the fourth node 104. Thus, the second terminal of the first resistor 111 and the first terminal of capacitor C are connected to the first amplifier input 131 via the second node 102.

[0146] Furthermore, the second terminal of the second resistor 112 and the second terminal of the capacitor C are connected via the fourth node 104 to the second amplifier input 132. Specifically, the first amplifier input 131 is a positive input (+) of the amplifier 130. Specifically, the second amplifier input 132 is a negative input (-) of the amplifier 130.

[0147] The capacitor C forms a circuit with the first resistor 111, the second resistor 112, and the shunt resistor 113 in the circuit shown. Fig. 1 The example shown uses a pre-filter 120.

[0148] The pre-filter 120 filters the shunt resistance voltage US to an amplifier input voltage U e of the amplifier 130.

[0149] The amplifier input voltage Ue drops between the positive input (+) 131 and the negative input (-) 132 of amplifier 130. Amplifier 130 has an amplifier output 133. The amplifier output 133 outputs an amplifier output signal 134. Amplifier 130 generates the value of the amplifier output signal 134 from the amplifier input voltage Ue using a linear mapping. The amplifier output signal 134 serves as the input signal for the analog-to-digital converter 200.

[0150] In particular, the amplifier output signal 134 corresponds to an analog input signal 201 of the analog-to-digital converter 200.

[0151] The analog-to-digital converter 200 samples the analog value of the input signal 201 at sampling points. Preferably, the sampling points are periodic with a sampling period of . The reciprocal of the sampling period is, for the purposes of this document, the sampling frequency. The sampling frequency divided by 2π is, for the purposes of this document, the sampling rate. To determine a sampling period, a suitable measuring device records the time interval between a first sampling point and a second sampling point immediately following it.

[0152] The analog-to-digital converter 200 converts the analog input signal 201 into a digital output signal 202.

[0153] The analog-to-digital converter 200 converts the analog value of the input signal 201 into a digital value of the digital output signal 202 at these sampling times.

[0154] The output of the Analog-to-Digital Converter 200 can include multiple electrical lines.

[0155] The revision and decimation filter 300 has one digital input and one output.

[0156] The digital output signal 202 of the analog-to-digital converter 200 serves as the decimation filter input signal 301.

[0157] In this process, the analog-to-digital converter 200 signals the relevant sample value to the input of the oversampling and decimation filter 300 by means of the digital output signal 202 after sampling.

[0158] At its output, the revision and decimation filter 300 outputs a decimation filter output signal 302.

[0159] In particular, the output values ​​of the decimation filter output signal 302 represent, at least temporarily, the current values ​​detected by the device for a line current I LTG through the shunt resistor 113. The limitation to "temporary" arises from the fact that the analog-to-digital converter 200 can only detect the current value of the line current I LTG at the sampling times.

[0160] In particular, the revision and decimation filter 300 is a linear filter. This means that, preferably, an increase in the input signal results in a corresponding proportional change in the output signal.

[0161] According to the state of the art, the first node 101 can be connected to further circuits not shown here or to one or more voltage and / or current sources, also not shown. For example, the one in Fig. 1 The device, shown schematically and in a simplified manner, may be connected to one or more subsequent and / or preceding bus nodes or a bus master if the shunt resistor 113 is a bus shunt resistor in a LIN data bus with auto-addressing.

[0162] Fig. 2 This demonstrates in an exemplary manner the basic principle of the device according to the invention.

[0163] The in Fig. 2 The device according to the invention, as illustrated, comprises, in contrast to the one shown in Fig. 1 The depicted state of the art additionally includes a timer unit 400. The timer unit 400 detects at least one timer input value signal 401.

[0164] In the Fig. 2 In the illustrated embodiment of the invention, the amplifier output signal 134 serves as a timer input value signal or as a timer input value 401.

[0165] The amplifier output signal 134 corresponds to the one in Fig. 2 The example shown also serves as the analog input signal 201 of the analog-to-digital converter 200. It is conceivable that further signal processing devices, such as filters or similar components, are arranged in the signal path between the amplifier output 133 and the input of the analog-to-digital converter 200. The analog input signal 201 of the analog-to-digital converter 200 includes the amplifier output signal 134. If further signal processing devices are used, the analog input signal 201 of the analog-to-digital converter 200 does not necessarily correspond to the amplifier output signal 134.

[0166] In the Fig. 2 In the example shown, the timer unit 400 controls the sampling rate and / or the sampling times of the analog-to-digital converter 200 depending on the value of the timer input signal 401.

[0167] The timer unit 400 signals operating parameters of the analog-to-digital converter 200 to the analog-to-digital converter 200 via a sampling control line 402. In the simplest case, the sampling control line 402 can signal a clock signal to the analog-to-digital converter 200. For example, the clock signal could be a sampling clock with a clock rate. This clock rate is then typically the sampling rate of the analog-to-digital converter 200. The analog-to-digital converter 200 can also convert this clock rate into a sampling rate of its own sampling clock, for example, using a PLL or similar device. However, depending on the implementation, it could also be a serial or parallel data bus or the like with a data bus protocol.

[0168] Sampling usually requires adherence to the Nyquist theorem.

[0169] The resistance value of the first resistor 111 and the second resistor 112 are preferably different from 0 ohms, so that the Nyquist condition remains satisfied by sampling in the analog-to-digital converter 200 following the circuit unit 100.

[0170] Sampling the input signal 201 of the analog-to-digital converter 200 or the amplifier output signal 134 by the analog-to-digital converter 200 generates artifacts. To avoid these artifacts, a pre-filter 120 and an oversampling and decimation filter 300 are provided.

[0171] When changing the sampling rate, the device or the proposed method should preferably adjust the cutoff frequencies.

[0172] The timer unit 400 therefore adapts the filter characteristics of the oversampling and decimation filter 300 to the sampling rate of the analog-to-digital converter 200. Since the sampling rate of the analog-to-digital converter 200 depends on the timer input value 401, the filter characteristics of the oversampling and decimation filter 300 also depend on the timer input value 401. Preferably, a relevant filter characteristic of the oversampling and decimation filter 300 is an upper cutoff frequency fo of the oversampling and decimation filter 300.

[0173] In particular, the oversampling and decimation filter 300 is a low-pass filter. However, more complex frequency-dependent spectral filter responses for the oversampling and decimation filter 300 are also conceivable, which then typically always exhibit an upper cutoff frequency f0.

[0174] Preferably, the timer unit 400 controls at least one filter property of the oversampling and decimation filter 300 by means of a decimation filter control line 403. The decimation filter control line 403 can comprise one or more lines. Typically, the oversampling and decimation filter 300 is a digital filter. Preferably, the lines of the decimation filter control line 403 represent a control word that the oversampling and decimation filter 300 configures. It is also conceivable that the decimation filter control line 403 is a serial or parallel data bus.

[0175] In the Fig. 2 In the example shown, the timer unit 400 controls parameters of the oversampling and decimation filter 300 via the decimation filter control line 403. These parameters of the oversampling and decimation filter 300, which the timer unit 400 controls via the decimation filter control line 403, include, for example, the frequency response and / or the gain or the attenuation of the oversampling and decimation filter 300. In particular, this includes the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0176] Furthermore, the timer unit 400 controls the in Fig. 2 The example shown shows parameters of the analog-to-digital converter 200 via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timer unit 400 controls via the sampling control line 402, include, for example, the sampling rate or sampling times of the analog-to-digital converter 200.

[0177] In one variant, the pre-filter 120 does not include the second resistor 112. In a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly called ground).

[0178] In another variant, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0179] In another variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

[0180] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, in front of the amplifier 130.

[0181] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0182] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, behind the amplifier 130.

[0183] Fig. 3 shows a further embodiment of the device according to the invention. The in Fig. 3 The illustrated embodiment essentially corresponds to the one described in Fig. 2 illustrated embodiment.

[0184] The in Fig. 3 The illustrated embodiment differs from the one in Fig. 2 The illustrated embodiment is characterized by the fact that the timer input value signal 401 of the timer unit 400 is not as in the example of the Fig. 2 which corresponds to the analog input signal 201 of the analog-to-digital converter 200 or the amplifier output signal 134. In the Fig. 3 In the illustrated embodiment, the timer input signal 401 of the timer unit 400 corresponds to the decimation filter output signal 302.

[0185] In a preferred embodiment, in which all components, i.e., the amplifier 130, the analog-to-digital converter 200, and the oversampling and decimation filter 400, are linear, the control behavior of a device according to the Figur 3 into a system of Figur 2 and vice versa.

[0186] While in the Fig. 2 In the illustrated embodiment, the timer input value signal 401 is an analog signal, which is contained in the Fig. 3 In the illustrated embodiment, the timer input signal 401 is a digital signal. Consequently, the spectral properties of the timer input signal 401 differ.

[0187] In the Fig. 2 In the illustrated embodiment, the timer unit 400 typically comprises comparators and, if necessary, analog threshold generators for comparing the input signal 201 of the analog-to-digital converter 200 or the amplifier output signal 134 with threshold values ​​of such generated threshold signals of the analog threshold generators.

[0188] When using the decimation filter output signal 302 as the timer input value signal 401, the behavior of the timer unit 400 must take into account the artifacts caused by the sampling.

[0189] In the Fig. 3 In the example shown, the timer unit 400 controls parameters of the oversampling and decimation filter 300 via the decimation filter control line 403. These parameters of the oversampling and decimation filter 300, which the timer unit 400 controls via the decimation filter control line 403, include, for example, the frequency response and / or the gain or the attenuation of the oversampling and decimation filter 300. In particular, this includes the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0190] Furthermore, the timer unit 400 controls the in Fig. 3 The example parameters of the analog-to-digital converter 200 shown are transmitted via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timer unit 400 controls via the sampling control line 402, include, for example, the sampling rate or sampling times of the analog-to-digital converter 200.

[0191] In one variant, the pre-filter 120 does not include the second resistor 112. In a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly called ground).

[0192] In another variant, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0193] In another variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

[0194] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, in front of the amplifier 130.

[0195] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0196] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, behind the amplifier 130.

[0197] Fig. 4 shows a further embodiment of the device according to the invention.

[0198] Fig. 4 essentially corresponds to the Figur 2 and the Figur 3 .

[0199] Fig. 4 differs from the Fig. 2 and Fig. 3 by the fact that the timer input value signal 401 of the timer unit 400 in the in Fig. 4 The illustrated embodiment corresponds to the output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301.

[0200] In the Fig. 4 In the example shown, the timer unit 400 controls parameters of the oversampling and decimation filter 300 via the decimation filter control line 403. These parameters of the oversampling and decimation filter 300, which the timer unit 400 controls via the decimation filter control line 403, include, for example, the frequency response and / or the gain or the attenuation of the oversampling and decimation filter 300. In particular, this includes the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0201] In the Fig. 4 In the example shown, the timer unit 400 controls parameters of the analog-to-digital converter 200 via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timer unit 400 controls via the sampling control line 402, include, for example, the sampling rate or sampling times of the analog-to-digital converter 200.

[0202] In one variant, the pre-filter 120 does not include the second resistor 112. In a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly called ground).

[0203] In another variant, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0204] In another variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

[0205] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, in front of the amplifier 130.

[0206] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0207] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, behind the amplifier 130.

[0208] Fig. 5 shows a further embodiment of the device according to the invention.

[0209] In the Fig. 5 In the illustrated embodiment, the timer unit 400 records several timer input values ​​401.

[0210] In the Fig. 5 In the example shown, a first timer input value 401a of the timer unit 400 corresponds to the amplifier output signal 134 or the analog input signal 201 of the analog-to-digital converter 200. A second timer input value 401b of the timer unit 400 corresponds in the Fig. 5 In the example shown, the digital output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301 corresponds to the digital output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301. A third timer input value 401c of the timer unit 400 corresponds in the example shown. Fig. 5 The example shown is the decimation filter output signal 302.

[0211] The timer unit 400 controls the in Fig. 5 The illustrated example parameters of the analog-to-digital converter 200 and / or the oversampling and decimation filter 300 are shown as a function of the timer input values ​​of the timer input value signals 401. A controlled parameter of the analog-to-digital converter 200 can be sampling points and / or sampling rates. A controlled parameter of the oversampling and decimation filter 300 can, for example, be the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0212] In the Fig. 5 In the example shown, the timer unit 400 controls parameters of the amplifier 130 via an amplifier control line 404. These parameters of the amplifier 130, which the timer unit 400 controls via the amplifier control line 404, are, for example, the frequency response and / or the gain or the attenuation of the amplifier 130.

[0213] In the Fig. 5 In the example shown, the timer unit 400 controls parameters of the oversampling and decimation filter 300 via the decimation filter control line 403. These parameters of the oversampling and decimation filter 300, which the timer unit 400 controls via the decimation filter control line 403, include, for example, the frequency response and / or the gain or the attenuation of the oversampling and decimation filter 300. In particular, this includes the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0214] In the Fig. 5 In the example shown, the timer unit 400 controls parameters of the analog-to-digital converter 200 via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timer unit 400 controls via the sampling control line 402, include, for example, the sampling rate or sampling times of the analog-to-digital converter.

[0215] Preferably, the timing behavior of the timer unit 400 during the generation of the signal of the amplifier control line 404 is set such that oscillation of the system is excluded.

[0216] It is therefore recommended to model the behavior of the system using a system simulation, for example with a program like Maple, and to determine the natural frequencies of the open control loop and thus to manipulate the poles of the loop function appropriately.

[0217] In one variant, the pre-filter 120 does not include the second resistor 112. In a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly called ground).

[0218] In another variant, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0219] In another variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

[0220] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, in front of the amplifier 130.

[0221] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0222] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, behind the amplifier 130.

[0223] Fig. 6 shows a further embodiment of the device according to the invention.

[0224] Fig. 6 essentially corresponds to the one in Fig. 5 illustrated embodiment, wherein the Fig. 6 The illustrated embodiment comprises a switchable pre-filter 120.

[0225] In the Fig. 6 In the illustrated embodiment, the timer unit 400 not only configures the cutoff frequency fo of the oversampling and decimation filter 300, but also one or more parameters of the pre-filter 120. For this purpose, the timer unit 400 signals to the pre-filter 120 via a pre-filter control line 405 which parameters the pre-filter 120 should use for filtering.

[0226] Preferably, the timer unit 400 records several timer input values ​​401.

[0227] In the Fig. 6 In the example shown, the timer unit detects the first timer input value 401a, which corresponds to the analog input signal 201 of the analog-to-digital converter 200 or the amplifier output signal 134. The second timer input value 401b of the timer 400 corresponds in the Fig. 6 In the example shown, the digital output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301 corresponds to the third timer input value 401c of the timer 400. Fig. 6 The example shown is the decimation filter output signal 302.

[0228] The timer unit 400 controls the in Fig. 6 The illustrated example parameters of the analog-to-digital converter 200 and / or the oversampling and decimation filter 300 are shown as a function of the timer input values ​​of the timer input value signals 401. A controlled parameter of the analog-to-digital converter 200 can be sampling points and / or sampling rates. A controlled parameter of the oversampling and decimation filter 300 can, for example, be the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0229] In the Fig. 6 In the example shown, the timer unit 400 controls parameters of the amplifier 130 via the amplifier control line 404. These parameters of the amplifier 130, which the timer unit 400 controls via the amplifier control line 404, include, for example, the frequency response and / or the gain or the attenuation of the amplifier 130.

[0230] In the Fig. 6 In the example shown, the timer unit 400 controls parameters of the oversampling and decimation filter 300 via the decimation filter control line 403. These parameters of the oversampling and decimation filter 300, which the timer unit 400 controls via the decimation filter control line 403, include, for example, the frequency response and / or the gain or the attenuation of the oversampling and decimation filter 300. In particular, this includes the aforementioned upper cutoff frequency fo of the oversampling and decimation filter 300.

[0231] In the Fig. 6 In the illustrated example, the timer unit 400 controls parameters of the prefilter 120 via the prefilter control line 405. These parameters of the prefilter 120, which the timer unit 400 controls via the prefilter control line 405, are, for example, the frequency response and / or the gain or the attenuation and / or the upper prefilter cutoff frequency f0V of the prefilter 120. Preferably, the timer unit 400 increases the upper prefilter cutoff frequency f0V of the prefilter 120 when the timer unit 400 increases the sampling rate of the analog-to-digital converter 200. Preferably, the timer unit 400 decreases the upper prefilter cutoff frequency f0V of the prefilter 120 when the timer unit 400 decreases the sampling rate of the analog-to-digital converter 200.

[0232] In one variant, the pre-filter 120 does not include the second resistor 112. In a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly called ground).

[0233] In another variant, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0234] In another variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

[0235] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, in front of the amplifier 130.

[0236] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0237] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, behind the amplifier 130.

[0238] Figur 7 shows a further embodiment of the device according to the invention.

[0239] This shows Figur 7 an exemplary implementation of a switchable pre-filter 120 according to the one in Fig. 6 illustrated embodiment.

[0240] In the Fig. 7 In the illustrated embodiment, the switchable pre-filter 120 comprises an analog multiplexer or an analog interconnect switch 140 and a plurality of capacitors C 1 -C n .

[0241] The analog multiplexer or an analog connecting switch 140 is connected to the timer unit 400 via a pre-filter control line 405.

[0242] In accordance with a signal from the timer unit 400 via the pre-filter control line 405, the analog multiplexer or analog connection switch 140 connects the second node 102 to one or more capacitors C1 to Cn. This connection allows the capacitance value of capacitor C to be adjusted depending on a value transmitted via the pre-filter control line 405.

[0243] In one variant, the pre-filter 120 does not include the second resistor 112. In a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly called ground).

[0244] In another variant, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0245] In another variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

[0246] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, in front of the amplifier 130.

[0247] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is at least partially, and in particular completely, integrated into the amplifier 130.

[0248] In particular, when using a non-clocked amplifier 130, the pre-filter 120 is arranged at least partially, and in particular completely, behind the amplifier 130.

[0249] Figur 8 shows an example of dynamic oversampling as a function of the amplifier input voltage U e at the amplifier of a device according to the invention.

[0250] The in Figur 8 The diagram shown illustrates a settling time TS at the amplifier of a device according to the invention as a function of the amplifier input voltage U e. Furthermore, the diagram in Fig. 8 The diagram shown represents a sampling period T smp of the device according to the invention as a function of the amplifier input voltage U e compared to a corresponding sampling period T smpSDT of a device according to the prior art.

[0251] The in Fig. 8 The diagram shown illustrates the settling time TS at the amplifier and the sampling period T smp of the device according to the invention, as well as the sampling period T smpSDT of a prior art device for an amplifier input voltage U e in a range from 0mV to 80mV.

[0252] In the Fig. 8 In the example diagram shown, the analog-to-digital converter has a resolution of 12 bits without oversampling. The measurement error, in this example, lies within a gain error of ±0.5% plus ±4 LSB as an offset. The noise level of the measurement in this example is approximately 32 LSB / sigma. The required oversampling rate for 1 LSB / sigma is 1024 in this example.

[0253] The settling time Ts at the amplifier is strongly dependent on the amplifier input voltage Ue. Therefore, measuring the settling time Ts at low amplifier input voltages Ue and thus at low line currents ILTG can be significantly faster than with conventional devices.

[0254] Due to the strong dependence of the settling time T s on the amplifier of a device according to the invention, the sampling period T smp set by the timer unit can be significantly smaller at small amplifier input voltages U e than at large amplifier input voltages U e .

[0255] In the in the in Fig. 8 In the example shown in the diagram, the sampling period Tsmp of the analog-to-digital converter (ADC) is at a first value, for example 2 µs, in a first operating range OA 1. In a second operating range OA 2, the sampling period Tsmp of the ADC is at a second value, for example 3 µs. In a third operating range OA 3, the sampling period Tsmp of the ADC is at a third value, for example 5.5 µs.

[0256] In contrast, the sampling period T smpSDT of a device according to the prior art depends on the necessary sampling rate for the maximum possible amplifier input voltage U e .

[0257] This results in the disadvantage for a prior art device that, for small amplifier input voltage U e and thus for small line currents I LTG, the sampling rate T smpSDT in prior art devices is worse than the sampling period T smp in the device according to the invention.

[0258] In the range of low amplifier input voltage Ue, noise error is dominant, but plays a subordinate role at high amplifier input voltages Ue. This allows for adjustment of the oversampling of the analog-to-digital converter, so that the device according to the invention can average over a larger number of measurements at low amplifier input voltages Ue than at high amplifier input voltages Ue. For example, the oversampling and decimation filter can perform this averaging.

[0259] In particular, the timer unit of the device according to the invention parameterizes the oversampling and decimation filter depending on the sampling period T smp set by the timer unit in order to optimize the evaluation of the measured values.

[0260] In particular, the analog-to-digital converter (ADC) transmits the respective samples of its input signal to the oversampling and decimation filter, each sample accompanied by a timestamp. This timestamp represents the sampling point and allows the oversampling and decimation filter to process samples from the ADC that were not sampled at equidistant times. The oversampling and decimation filter can, for example, be implemented in two stages. Thus, the ADC transmits temporally non-equidistant samples to the oversampling and decimation filter via its output signal.A first stage of the oversampling and decimation filter generates a data stream of interpolated, and preferably temporally equidistant, samples from the analog-to-digital converter's temporally non-equidistant samples, for example, using polynomial interpolation. A second stage of the oversampling and decimation filter then generates a data stream of filtered and temporally equidistant interpolated samples from these now temporally equidistant samples. The oversampling and decimation filter then outputs the data stream of filtered and temporally equidistant interpolated samples as the decimation filter output signal.

[0261] In particular, the total conversion time per measurement remains identical to minimize effort. This is important for further processing. Preferably, the timing unit adjusts the sample time inversely to the number of averaging measurements.

[0262] As previously stated, the device or method according to the invention can also use equivalent values ​​at other points in the signal path.

[0263] Figur 9 The figure shows the total conversion time TG as a function of the amplifier input voltage Ue and the associated operating ranges OA0, OA1, OA2, OA3 for an amplifier input voltage Ue from 0 mV to 80 mV. The operating ranges OA1, OA2, OA3 correspond to the Fig. 9 those in Fig. 8 The total conversion time TG is the time between the first output of a first measured value via the decimation filter output signal and the second output of the first measured value via the decimation filter output signal. The total conversion time TG is calculated by multiplying the current sampling period T smp of the analog-to-digital converter by the number of samples taken by the analog-to-digital converter over which the oversampling and decimation filters average for the output of a measured value via the decimation filter output signal.

[0264] A zero operating range OA 0 below a minimum conversion time of, for example, 2.05 ms is not possible for either the proposed device or a prior art device in the context described in Fig. 9 The range of amplifier input voltage Ue shown is achievable.

[0265] In the first operating range OA 1 of a device according to the invention, the oversampling and decimation filter averages over, for example, 1024 samples from the analog-to-digital converter. In this first operating range OA 1, the timing unit adjusts the oversampling and decimation filter such that it averages over these 1024 samples. The timing unit adjusts the oversampling and decimation filter in this first operating range OA 1 in the manner specified in Fig. 9 In the example shown, the analog-to-digital converter is simultaneously set such that the sampling period TSMP of the analog-to-digital converter in this first operating area OA 1 has an exemplary duration of 2 µs. The total conversion time TG is then calculated by multiplying the 1024 samples by the 2 µs per sample, i.e., the sampling period Tsmp, resulting in an example of 2.05 ms.

[0266] In the Fig. 9 In the example shown, an exemplary upper input voltage limit of approximately 21 mV limits the first operating range OA 1 to higher input voltage values ​​of the amplifier's input voltage U e. An exemplary amplifier input voltage of 0 V limits the range shown in the example. Fig. 9 The example shown shows the first input voltage range of the amplifier input voltage U e in the first operating range OA 1 downwards.

[0267] In a second operating range OA 2 of a device according to the invention, the oversampling and decimation filter averages over, for example, 682 samples from the analog-to-digital converter. In this second operating range OA 2, the timing unit sets the oversampling and decimation filter so that it averages over the aforementioned 682 samples from the analog-to-digital converter. The timing unit sets the oversampling and decimation filter in this second operating range OA 2 in the manner specified in Fig. 9 In the example shown, the analog-to-digital converter is simultaneously set such that the sampling period TSMP of the analog-to-digital converter in this second operating area OA 2 has an exemplary duration of 3 µs. The total conversion time TG is then calculated by multiplying the 682 samples by the 3 µs per sample, i.e., the sampling period Tsmp, again resulting in an example of 2.05 ms. Therefore, the total conversion time TG in the second operating area OA 2 does not change significantly compared to the total conversion time TG in the first operating area OA 1.

[0268] In the Fig. 9 In the example shown, an exemplary upper second input voltage limit of approximately 48mV limits the second operating range OA 2 to higher input voltage values ​​of the amplifier input voltage U e.

[0269] In the Fig. 9 In the example shown, the exemplary upper first input voltage limit of approximately 21mV limits the second operating range OA 2 to lower input voltage values ​​of the amplifier input voltage U e.

[0270] In a third operating range OA 3 of a device according to the invention, the oversampling and decimation filter averages over, for example, 372 samples from the analog-to-digital converter. In this third operating range OA 3, the timing unit sets the oversampling and decimation filter so that it averages over the aforementioned 372 samples from the analog-to-digital converter. The timing unit sets the oversampling and decimation filter in this third operating range OA 3 in the manner specified in Fig. 9 In the example shown, the analog-to-digital converter is simultaneously set such that the sampling period TSMP of the analog-to-digital converter in this third operating area OA 3 has an exemplary duration of 5.5 µs. The total conversion time TG is then calculated by multiplying the 372 samples by the 5.5 µs per sample, i.e., the sampling period Tsmp, again resulting in an example of 2.05 ms. Therefore, the total conversion time TG in the third operating area OA 3 does not change significantly compared to the total conversion time TG in the first operating area OA 1 or compared to the total conversion time TG in the second operating area OA 2.

[0271] In the Fig. 9 In the example shown, an exemplary upper third input voltage limit of approximately 80mV limits the third operating range OA 3 to higher input voltage values ​​of the amplifier input voltage U e.

[0272] In the Fig. 9 In the example shown, the exemplary upper second input voltage limit of approximately 48mV limits the third operating range OA 3 to lower input voltage values ​​of the amplifier input voltage U e.

[0273] In the Fig. 9 In the example shown, the third input voltage limit of approximately 80mV is simultaneously the exemplary specification limit for the input voltage value of the amplifier input voltage U e .

[0274] Preferably, the timing unit evaluates a total conversion time specification. Depending on this total conversion time specification and the respective timing input values ​​of the timing input signals used, the timing unit calculates the number of samples and the sampling period Tsmp.

[0275] As before, the number of samples corresponds to the number of samples from the analog-to-digital converter. The oversampling and decimation filter uses this number of samples to calculate an output value for the measurement signal via the decimation filter output signal.

[0276] When using multiple timer input values ​​from different timer input signals, the timer unit can, for example, use a polynomial with several different variables for this calculation. The different variables of this polynomial can then be the different timer input values ​​of the different timer input signals.

[0277] Therefore, in a proposed variant, the device according to the invention preferably behaves like a prior art device if the total conversion time TG specified to the timer unit in the form of said total conversion time specification is above a total conversion time limit.

[0278] An operating range OA SDT of a device according to the state of the art lies above a total conversion time TG of 5.5ms.

[0279] This overall conversion time limit is derived from a sampling period Tsmp = TSDT of 5.5 µs and averaging over 1024 samples from the analog-to-digital converter in the oversampling and decimation filter. Multiplying the example sampling period Tsmp = TSDT of 5.5 µs by the number of 1024 samples from the analog-to-digital converter used for averaging in the oversampling and decimation filter yields this overall conversion time limit of essentially 5.5 ms.

[0280] Preferably, the specified total conversion time TG is set vis-à-vis the timing unit by means of data transmission from a higher-level computer system to the timing unit and the associated programming of a corresponding register in the timing unit. Typically, the total conversion time limit results from the design of the proposed device and the properties of the technical teaching used to manufacture the device according to the invention (semiconductor technology used). Furthermore, the properties of the application system in which the device according to the invention is used also play a role. Another influencing factor is the specific implementation of the analog-to-digital converter and its associated properties. Of course, it is also conceivable to predefine the total conversion time TG vis-à-vis the timing unit during the manufacturing process.

[0281] Figur 10 shows an example that fits the Figuren 8 and 9 a residual error e due to noise as a function of the amplifier input voltage U e . The in Fig. 10 The solid line shown represents an exemplary specification limit, serving only for clarification.

[0282] The dashed line represents an increase in noise for a device according to the invention due to the reduction in the number of sampling points with increasing amplifier input voltage U e.

[0283] The dotted line represents the noise for a state-of-the-art device.

[0284] Although the noise for a device according to the invention increases due to the reduction of the number of samples of the analog-to-digital converter used for averaging in the oversampling and decimation filter from the first operating range OA 1 to the second operating range OA 2 and from the second operating range OA 3 to the third operating range OA 3, the noise is still below the specification limit.

[0285] In particular, the resulting noise must be taken into account in the design of the device according to the invention in comparison to the respective prescribed specification. This concerns, for example, the selection of the oversampling and decimation filter, the selection of the design and conversion method of the analog-to-digital converter, and the requirements mentioned above.

[0286] In contrast to the prior art, in the device according to the invention, noise increases with an increase in the amplifier input voltage Ue. However, at a large amplifier input voltage Ue, the noise plays a subordinate role.

[0287] The device according to the invention offers the advantage of dynamic oversampling as a function of the amplifier input voltage Ue. At low amplifier input voltages Ue, the sampling period can be chosen to be very small. The sampling period Tsmp set by the timing unit can be significantly smaller at low amplifier input voltages Ue than at high amplifier input voltages Ue.

[0288] In contrast, the sampling period T smpSDT of a device according to the prior art depends on the necessary sampling rate for the maximum possible amplifier input voltage U e .

[0289] This results in the disadvantage for a prior art device that, for small amplifier input voltage U e and thus for small line currents I LTG, the sampling rate T smpSDT in prior art devices is worse than the sampling period T smp in the device according to the invention. Bezugszeichenliste

[0290] 100 Circuit unit 101 First node 102 Second node 103 Third node 104 Fourth node 111 first resistor 112 second resistor 113 shunt resistor 120 pre-filters 130 Amplifier 131 First amplifier input 132 Second amplifier input 133 Amplifier output 134 Amplifier output signal 140 Analog multiplexer or analog interconnect switch 200 Analog-to-digital converter 201 Analog input signal 202 Digital output signal 300 Oversampling and decimation filter 301 Decimation filter input signal 302 Decimation filter output signal 400 Timer unit 401 Timer input signal / Timer input value 401a First timer input value 401b Second timer input value 401c Third timer input value 402 Sampling control line 403 Decimation filter control line 404 Amplifier control line 405 Prefilter control line I LTG Line current C Capacitor US Shunt resistance voltage U e Amplifier input voltage fo Upper cutoff frequency of the oversampling and decimation filter f oV Upper cutoff frequency of the pre-filter T s Settling time at the amplifier T smp Sampling period of a device according to the invention T smpSDT Sampling period of a prior art device OA Operating range OA 0 Zeroth operating range OA 1 First operating range OA 2 Second operating range OA 3 Third operating range OA SDT Operating range of a prior art device

Claims

1. Device for detecting an electrical line current (ILTG ) in a line, wherein the electrical line current (ILTG ) flows from a first node (101) of the device to a third node (103) of the device, wherein the device comprises - a prefilter (120) - an amplifier (130), wherein the amplifier (130) has a first amplifier input (131), a second amplifier input (132) and an amplifier output (133), - an analog-to-digital converter (200), the analog-to-digital converter (200) having an input and an output, and - an oversampling and decimation filter (300), the oversampling and decimation filter (300) having an input and an output, wherein the analog-to-digital converter (200) is designed to sample an analog value of an analog input signal (201) of the analog-to-digital converter (200) at sampling times, and wherein the analog-to-digital converter (200) is designed to convert the analog value of the analog input signal (201) of the analog-to-digital converter (200) into a digital value at these sampling times, and wherein the analog-to-digital converter (200) is designed to signal this digital value via a digital output signal (202) of the digital-to-analog converter (200) to the input of the oversampling and decimation filter (300), and wherein a plurality of output values of a decimation filter output signal (302) represent, at least temporarily, the current values for the line current (ILTG) detected by the device, characterized in that the device comprises a timer unit (400), wherein the timer unit (400) is designed to detect at least one timer input value signal (401) with at least one respective timer input value, and wherein the timer unit (400) is designed to at least temporarily influence at least one signal transmission property of the prefilter (120) and / or the amplifier (130) and / or the analog-to-digital converter (200) and / or the oversampling and decimation filter (300) in dependence on the at least one detected respective timer input value at least temporarily.

2. Device according to claim 1, characterized in that the at least one signal transmission characteristic influenced by the timer unit (400) as a function of the at least one detected respective timer input value is at least one sampling time and / or at least one filter characteristic and / or at least one amplifier characteristic.

3. Device according to one of claims 1 to 2, characterized in that the at least one signal transmission property influenced by the timing unit (400) as a function of the at least one detected respective timing input value is at least one filter frequency and / or at least one attenuation and / or at least one amplification of the prefilter (120) and / or the oversampling and decimation filter (300).

4. Device according to one of the preceding claims, characterized in that that the at least one clock input value signal (401) corresponds to the analog input signal (201) of the analog-to-digital converter (200), wherein the at least one respective timer input value is an ADC input value of the analog input signal (201) of the analog-to-digital converter (200).

5. Device according to claim 4, characterized in that the timer unit (400) is designed to at least temporarily detect values of the analog input signal (201) of the analog-to-digital converter (200) in the form of detected ADC input values as timer input values, and wherein the timer unit (400) is designed to influence sampling times as a function of the detected ADC input values.

6. Device according to one of claims 4 to 5, characterized in that that the timer unit (400) is designed to at least temporarily detect values of the analog input signal (201) of the analog-to-digital converter (200) in the form of detected ADC input values as timer input values, wherein the timer unit (400) is designed to influence at least one property of the prefilter (120) and / or the amplifier (130) and / or the oversampling and decimation filter (300) as a function of the detected ADC input values, wherein the property influenced by the timer unit (400) is, in particular, at least one filter frequency and / or at least one gain and / or at least one attenuation of the prefilter (120) and / or the oversampling and decimation filter (300) , and / or the property influenced by the timer unit (400) is, in particular, at least one gain and / or at least one attenuation of the amplifier (130).

7. Device according to one of the preceding claims, characterized in that that the timer input value signal (401) corresponds to the digital output signal (202) of the analog-to-digital converter (200), wherein the at least one respective timer input value is an ADC output value of the digital output signal (202) of the analog-to-digital converter (200).

8. Device according to claim 7, characterized in that the timer unit (400) is designed to at least temporarily detect values of the output signal (202) of the analog-to-digital converter (200) in the form of detected ADC output values as timer input values, wherein the timer unit (400) is designed to influence sampling times as a function of the detected ADC output values of the digital output signal (202).

9. Device according to one of claims 7 to 8, characterized in that the timer unit (400) is designed to at least temporarily detect values of the digital output signal (202) of the analog-to-digital converter (200) in the form of detected ADC output values as timer input values, wherein the timer unit (400) is designed to influence at least one property of the prefilter (120) and / or the amplifier (130) and / or the oversampling and decimation filter (300) depending on these detected ADC output values, wherein the property influenced by the timer unit (400) is, in particular, at least one filter frequency, and / or at least one gain, and / or at least one attenuation of the prefilter (120) and / or the oversampling and decimation filter (300), and / or the property influenced by the timer unit (400) is, in particular, at least one gain and / or at least one attenuation of the amplifier (130).

10. Device according to one of the preceding claims, characterized in that that the timer input value signal (401) corresponds to a decimation filter input signal (301) of the oversampling and decimation filter (300), wherein the at least one respective clock input value is a decimation filter input value of the oversampling and decimation filter (300).

11. Device according to claim 10, characterized in that that the timer unit (400) is designed to at least temporarily detect values of the decimation filter input signal (301) in the form of detected decimation filter input values as timer input values of the timer input value signal (401), wherein the timer unit (400) is designed to influence sampling times as a function of detected decimation filter input values.

12. Device according to one of claims 10 to 11, characterized in that that the timer unit (400) is designed to at least temporarily detect values of the decimation filter input signal (301) in the form of detected decimation filter input values as timer input values of the timer input value signal (401), wherein the timer unit (400) is designed to influence at least one property of the prefilter (120) and / or the amplifier (130) and / or the oversampling and decimation filter (300) as a function of detected decimation filter input values, wherein the property influenced by the timer unit (400) is, in particular, at least one filter frequency, and / or at least one gain, and / or at least one attenuation of the prefilter (120) and / or the oversampling and decimation filter (300), and / or the property influenced by the timer unit (400) is, in particular, at least one gain and / or at least one attenuation of the amplifier (130).

13. Device according to one of the preceding claims, characterized in that that the timer input value signal (401) corresponds to the decimation filter output signal (302) of the oversampling and decimation filter (300), wherein the at least one respective time base input value is a decimation filter output value of the decimation filter output signal (302).

14. Device according to claim 13, characterized in that the timer unit (400) is designed to at least temporarily detect values of the decimation filter output signal (302) in the form of detected decimation filter output values as timer input values of the timer input value signal (401), wherein the timer unit (400) is designed to influence sampling times as a function of detected decimation filter output values.

15. Device according to one of claims 13 to 14, characterized in that the timer unit (400) is designed to at least temporarily detect values of the decimation filter output signal (302) in the form of detected decimation filter output values as timer input values of a timer input value signal (401), wherein the timer unit (400) is designed to influence at least one property of the prefilter (120) and / or the amplifier (130) and / or the oversampling and decimation filter (300) as a function of detected decimation filter output values, wherein the property influenced by the timer unit (400) is, in particular, at least one filter frequency and / or at least one gain and / or at least one attenuation of the prefilter (120) and / or the oversampling and decimation filter (300), and / or the property influenced by the timer unit (400) is, in particular, at least one gain and / or at least one attenuation of the amplifier (130).

16. Device according to one of the preceding claims, characterized in that that a sampling period of a time between a first sampling time of the sampling of the analog value of the analog input signal (201) of the analog-to-digital converter (200) by the analog-to-digital converter (200) and an immediately subsequent second sampling time of the sampling of the analog value of the analog input signal (201) of the analog-to-digital converter (200) by the analog-to-digital converter (200), wherein the timer unit (400) is designed to influence the sampling period of the analog-to-digital converter (200) depending on the at least one detected respective timer input value.

17. Device according to claim 16, characterized in that that the sampling period is above a sampling period limit value when amounts of the detected ADC input values are below a first ADC input threshold value and wherein the sampling period is below the sampling period limit value when amounts of the detected ADC input values are above the first ADC input threshold value.

18. Device according to one of claims 16 to 17, characterized in that that the sampling period is above a sampling period limit value when amounts of the detected ADC output values are below a first ADC output threshold value, and the sampling period is below the sampling period limit value when amounts of the detected ADC output values are above the first ADC output threshold value.

19. Device according to any one of claims 16 to 18, characterized in that that the sampling period is above the sampling period limit value when amounts of the detected decimation filter input values are below a first decimation filter input threshold value, and the sampling period is below the sampling period limit value when amounts of the detected decimation filter input values are above the first decimation filter input threshold value.

20. Device according to one of claims 16 to 19, characterized in that that the sampling period is above a sampling period limit value when amounts of the detected decimation filter output values are below the first decimation filter output threshold value and the sampling period is below the sampling period limit value when amounts of the detected decimation filter output values are above the first decimation filter output threshold value.

21. Device according to one of the preceding claims, characterized in that that the oversampling and decimation filter (300) has an upper cut-off frequency (fo), wherein the oversampling and decimation filter (300) is designed to attenuate signal components with a signal component frequency above the upper cut-off frequency (fo) more strongly than signal components with a signal component frequency immediately below the upper cut-off frequency (fo) and wherein the clock unit (400) is designed to influence the upper cut-off frequency (fo) of the oversampling and decimation filter (300) as a function of the at least one detected respective clock input value.

22. Device according to claim 21, characterized in that the upper limit frequency (fo) of the oversampling and decimation filter (300) is above a decimation limit frequency limit value when amounts of the detected ADC input values are below a second ADC input threshold value, and the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is below the decimation cut-off frequency limit value when amounts of the detected ADC input values are above the second ADC input threshold value.

23. Device according to one of claims 21 to 22, characterized in that the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is above the decimation cut-off frequency limit value when amounts of the detected ADC output values are below a second ADC output threshold value, and the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is below the decimation cut-off frequency limit value when amounts of the detected ADC output values are above the second ADC output threshold value.

24. Device according to one of claims 21 to 23, characterized in that that the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is above the decimation cut-off frequency limit value when amounts of the detected decimation filter input values are below a second decimation filter input threshold value, and the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is below the decimation cut-off frequency limit value when amounts of the detected decimation filter input values are above the second decimation filter input threshold value.

25. Device according to any one of claims 21 to 24, characterized in that the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is above the decimation cut-off frequency limit value when amounts of the detected decimation filter output values are below a second decimation filter output threshold value, and the upper cut-off frequency (fo) of the oversampling and decimation filter (300) is above the decimation cut-off frequency limit value when amounts of the detected decimation filter output values are above the second decimation filter output threshold value.

26. Device according to one of the preceding claims, characterized in that the prefilter (120) has an upper cut-off frequency (foV), wherein the prefilter (120) is designed to attenuate signal components with a signal component frequency above the upper cut-off frequency (foV) more strongly than signal components with a signal component frequency immediately below the upper cut-off frequency (foV), and wherein the timer unit (400) is designed to influence the upper cut-off frequency (foV) of the prefilter (120) depending on the at least one detected respective timer input value.

27. Device according to claim 26, characterized in that that the upper limit frequency (foV) of the prefilter (120) is above a prefilter limit frequency limit value when amounts of the detected ADC input values are below a third ADC input threshold value, and the upper limit frequency (foV) of the prefilter (120) is below the prefilter cut-off frequency limit value when amounts of the detected ADC input values are above the third ADC input threshold value.

28. Device according to one of claims 26 to 27, characterized in that that the upper cut-off frequency (foV) of the prefilter (120) is above the prefilter cut-off frequency limit value when amounts of the detected ADC output values are below the third ADC output threshold value, and the upper cut-off frequency (foV) of the prefilter (120) is below the prefilter cut-off frequency limit value when amounts of the detected ADC output values are above the third ADC output threshold value.

29. Device according to one of claims 26 to 28, characterized in that that the upper cut-off frequency (foV) of the prefilter (120) is above the prefilter cut-off frequency limit value when amounts of the detected decimation filter input values are below the third decimation filter input threshold value, and the upper cut-off frequency (foV) of the prefilter (120) is below the prefilter cutoff frequency limit value when amounts of the detected decimation filter input values are above the third decimation filter input threshold value.

30. Device according to one of claims 26 to 29, characterized in that that the upper limit frequency (foV) of the prefilter (120) is above the prefilter limit frequency limit value when amounts of the detected decimation filter output values are below the third decimation filter output threshold value, and the upper limit frequency (foV) of the prefilter (120) is above the prefilter cutoff frequency limit value when amounts of the detected decimation filter output values are above the third decimation filter output threshold value.

31. Device according to one of the preceding claims, characterized in that the amplifier (130) has properties, in particular an amplification and / or an attenuation of the amplifier (130), with respective property values, wherein the time-giver unit (400) is designed to influence this property of the amplifier (130) as a function of the at least one detected respective time-giver input value.

32. Device according to claim 31, characterized in that the characteristic value of the respective characteristic of the amplifier (130) is above an amplifier characteristic limit value when amounts of the detected ADC input values are below a fourth ADC input threshold value, and the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected ADC input values are above the fourth ADC input threshold value, or the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected ADC input values are below the fourth ADC input threshold value, and the property value of the respective property of the amplifier (130) is above the amplifier property limit value when amounts of the detected ADC input values are above the fourth ADC input threshold value.

33. Device according to any one of claims 31 to 32, characterized in that that the characteristic value of the respective characteristic of the amplifier (130) is above the amplifier characteristic limit value when amounts of the detected ADC output values are below a fourth ADC output threshold value, and the characteristic value of the respective characteristic of the amplifier (130) is below the amplifier characteristic limit value when amounts of the detected ADC output values are above the fourth ADC output threshold value, or the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected ADC output values are below the fourth ADC output threshold value, and the property value of the respective property of the amplifier (130) is above the amplifier property limit value when amounts of the detected ADC output values are above the fourth ADC output threshold value.

34. Device according to one of claims 31 to 33, characterized in that that the property value of the respective property of the amplifier (130) is above the amplifier property limit value when amounts of the detected decimation filter input values are below a fourth decimation filter input threshold value, and the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected decimation filter input values are above the fourth decimation filter input threshold value, or the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected decimation filter input values are below the fourth decimation filter input threshold value, and the property value of the respective property of the amplifier (130) is above the amplifier property limit value when amounts of the detected decimation filter input values are above the fourth decimation filter input threshold value.

35. Device according to any one of claims 31 to 34, characterized in that that the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected decimation filter output values are below a fourth decimation filter output threshold value, and the characteristic value of the respective characteristic of the amplifier (130) is above the amplifier characteristic limit value when amounts of the detected decimation filter output values are above the fourth decimation filter output threshold value, or the property value of the respective property of the amplifier (130) is above the amplifier property limit value if amounts of the detected decimation filter output values are below the fourth decimation filter output threshold value, and the property value of the respective property of the amplifier (130) is below the amplifier property limit value when amounts of the detected decimation filter output values are above the fourth decimation filter output threshold value.

36. Device for detecting an electrical line current (ILTG) in a line, comprising - a shunt resistor (113), - a prefilter (120), - an amplifier (130), - an analog-to-digital converter (200), and - an oversampling and decimation filter (300), wherein the electrical line current (ILTG) flows through the shunt resistor (113), and wherein a shunt resistance voltage (US) drops across the shunt resistance (113), and wherein the prefilter (120) is designed to prefilter the shunt resistance voltage (US) to an amplifier input voltage (Ue), and wherein the amplifier (130) is designed to detect the amplifier input voltage (Ue) and amplify it to an amplifier output signal (133), and wherein the analog-to-digital converter (200) is designed to sample the amplifier output signal (133) at a sampling rate and convert it into a decimation filter input signal (301), and wherein the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to produce a decimation filter output signal (302), and wherein the device is designed to provide the decimation filter output signal (302) as a measured value signal for at least one value of the electrical line current (ILTG) in a line, characterized in that the prefilter (120) is designed to filter the shunt resistance voltage (US) to the amplifier input voltage (Ue) as a function of a value of the amplifier output signal (133) as a time base input value, and / or the prefilter (20) is designed to filter the shunt resistance voltage (US) to the amplifier input voltage (Ue) as a function of a value of the decimation filter input signal (301) as a timer input value, and / or the prefilter (120) is designed to filter the shunt resistance voltage (US) to the amplifier input voltage (Ue) as a timer input value depending on a value of the decimation filter output signal (302), and / or that the amplifier (130) is designed to detect and amplify the amplifier input voltage (Ue) to the amplifier output signal (133) as a function of the value of the amplifier output signal (133) as a timer input value, and / or the amplifier (130) is designed to detect and amplify the amplifier input voltage (Ue) to the amplifier output signal (133) as a timer input value depending on the value of the decimation filter input signal (301), and / or the amplifier (130) is designed to detect and amplify the amplifier input voltage (Ue) to the amplifier output signal (133) as a timer input value depending on the value of the decimation filter output signal (302), and / or the analog-to-digital converter (200) is designed to sample the amplifier output signal (133) at the sampling rate with respect to the decimation filter input signal (301) as a clock input value depending on the value of the amplifier output signal (133), and / or the analog-to-digital converter (200) is set up to sample the amplifier output signal (133) at the sampling rate to the decimation filter input signal (301) depending on the value of the decimation filter input signal (301) as a timer input value, and / or that the analog-to-digital converter (200) is designed to sample the amplifier output signal (133) at the sampling rate to the decimation filter input signal (301) as a time clock input value depending on the value of the decimation filter output signal (302), and / or that the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to the decimation filter output signal (302) as a clock input value depending on the value of the amplifier output signal (133), and / or that the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to the decimation filter output signal (302) as a function of the value of the decimation filter input signal (301) as a timer input value, and / or the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to the decimation filter output signal (302) as a time clock input value depending on the value of the decimation filter output signal (302).

37. Device according to claim 36, characterized in that that a filter characteristic of the prefilter (120), in particular a prefilter cutoff frequency (foV), depends on the timer input value.

38. Device according to claim 36, characterized in that that a property of the amplifier (130), in particular a gain or attenuation, depends on the timer input value.

39. Device according to claim 36, characterized in that that a property of the analog-to-digital converter (200), in particular a sampling time point and / or the sampling period, depends on the timer input value.

40. Device according to claim 36, characterized in that that a property of the oversampling and decimation filter (300), in particular a filter cutoff frequency (fo), depends on the timer input value.

41. Device according to claim 37, characterized in that that the prefilter cut-off frequency (foV) is above a prefilter cut-off value when amounts of timer input values are below a first input threshold value, and the prefilter limit frequency (foV) is below the prefilter limit value when amounts of timer input values are above the first input threshold value, or the prefilter cutoff frequency (foV) is below the prefilter cutoff value when amounts of timer input values are below the first input threshold value, and the prefilter limit frequency (foV) is above the prefilter limit value when amounts of timer input values are above the first input threshold value.

42. Device according to claim 38, characterized in that that a gain amount is above a gain limit value when amounts of timer input values are below a second input threshold value, and the amount of amplification is below the amplification limit value when amounts of timer input values are above the second input threshold value, or the amount of amplification is below the amplification limit value when amounts of timer input values are below the second input threshold value, and the amount of amplification is above the amplification limit value when amounts of timer input values are above the second input threshold value.

43. Device according to claim 39, characterized in that that the sampling period is above a sampling period limit value when amounts of clock input values are below a third input threshold value, and the sampling period is below the sampling period limit value when amounts of clock input values are above the third input threshold value, or the sampling period is below the sampling period limit value when amounts of timer input values are below the third input threshold value, and the sampling period is above the sampling period limit value when amounts of timer input values are above the third input threshold value.

44. Device according to claim 40, characterized in that that an amount of the filter cutoff frequency (fo ) is above a filter cutoff frequency limit value when amounts of timer input values are below a fourth input threshold value, and the amount of the filter cutoff frequency (fo ) is below the filter cutoff frequency limit value when amounts of timer input values are above the fourth input threshold value, or the amount of the filter cutoff frequency (fo ) is below the filter cutoff frequency limit value when amounts of timer input values are below a fourth input threshold value, and the amount of the filter cutoff frequency (fo ) is above the filter cutoff frequency limit value when amounts of timer input values are above the fourth input threshold value.

45. Device for detecting an electrical line current (ILTG) in a line, comprising - a first circuit unit (100), - an analog-to-digital converter (200), and - an oversampling and decimation filter (300), wherein the electrical line current flows through the first circuit unit (100), and wherein the first circuit unit (100) is designed to detect the temporal progression of the value of the electrical line current (ILTG ) in the line and convert it into an amplifier output signal (133), and wherein the analog-to-digital converter (200) is designed to sample the amplifier output signal (133) at a sampling rate and convert it into a decimation filter input signal (301), and wherein the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to a decimation filter output signal (302), and wherein the device is designed to provide the decimation filter output signal (302) as a measured value signal for at least one value of the electrical line current (ILTG) in a line, characterized in that the analog-to-digital converter (200) is designed to sample the amplifier output signal (133) at the sampling rate to the decimation filter input signal (301) as a clock input value depending on a value of the amplifier output signal (133) that is , and / or that the analog-to-digital converter (200) is designed to sample the amplifier output signal (133) at the sampling rate to the decimation filter input signal (301) as a function of a value of the decimation filter input signal (301) as a clock input value, and / or the analog-to-digital converter (200) is set up to sample the amplifier output signal (133) at a sampling rate to the decimation filter input signal (301) depending on a value of the decimation filter output signal (302) as a clock input value, and / or that the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to the decimation filter output signal (302) as a clock input value depending on the value of the amplifier output signal (133), and / or that the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to the decimation filter output signal (302) as a function of the value of the decimation filter input signal (301) as a timer input value, and / or the oversampling and decimation filter (300) is designed to filter the decimation filter input signal (301) to the decimation filter output signal (302) depending on the value of the decimation filter output signal (302) as a clock input value.

46. Device according to claim 45, characterized in that the first circuit unit (100) comprises - a shunt resistor (113) - a prefilter (120), and - an amplifier (130), wherein the electrical line current (ILTG) flows through the shunt resistor (113), and wherein a shunt resistance voltage (US) drops across the shunt resistor (113), wherein the prefilter (120) is designed to prefilter the shunt resistor voltage (US) to an amplifier input voltage (Ue), and wherein the amplifier (130) is designed to detect the amplifier input voltage (Ue) and amplify it to the amplifier output signal (133).

47. Device according to one of claims 45 to 46, characterized in that that a property of the analog-to-digital converter (200), in particular a sampling time and / or the sampling period, depends on the clock input value.

48. Device according to one of claims 45 to 46, characterized in that that a property of the oversampling and decimation filter (300), in particular a filter cutoff frequency (fo), depends on the timer input value.

49. Device according to claim 47, characterized in that that the sampling period is above a sampling period limit value when amounts of clock input values are below a third input threshold value, and the sampling period is below the sampling period limit value when amounts of clock input values are above the third input threshold value, or the sampling period is below the sampling period limit value when amounts of timer input values are below the third input threshold value, and the sampling period is above the sampling period limit value when amounts of timer input values are above the third input threshold value.

50. Device according to claim 48, characterized in that that an amount of the filter cutoff frequency (fo) is above a filter cutoff frequency limit value when amounts of clock input values are below a fourth input threshold value, and the amount of the filter cutoff frequency (fo) is below the filter cutoff frequency limit value when amounts of timer input values are above the fourth input threshold value, or the amount of the filter cutoff frequency (fo) is below the filter cutoff frequency limit value when amounts of timer input values are below a fourth input threshold value, and the amount of the filter cutoff frequency (fo) is above the filter cutoff frequency limit value when amounts of timer input values are above the fourth input threshold value.

51. Method for detecting an electrical line current (ILTG) in a line by means of a device according to one of the preceding claims, wherein the electrical line current (ILTG) flows through a shunt resistor (113) and a shunt resistor voltage (US) drops across the shunt resistor (113), wherein the method comprises the following steps: - pre-filtering the shunt resistance voltage (US) to an amplifier input voltage (Ue); - detecting and amplifying the amplifier input voltage (Ue) to an amplifier output signal (133); - sampling the amplifier output signal (133) at a sampling rate to form a decimation filter input signal (301); - filtering the decimation filter input signal (301) to a decimation filter output signal (302); - providing the decimation filter output signal (302) as a measured value signal for at least one value of the electrical line current (ILTG) in a line, characterized in that that the prefiltering of the shunt resistance voltage (US) to the amplifier input voltage (Ue) and / or the detection and amplification of the amplifier input voltage (Ue) to the amplifier output signal (133), and / or sampling the amplifier output signal (133) at the sampling rate to the decimation filter input signal (301), and / or filtering the decimation filter input signal (301) to the decimation filter output signal (302) - depends on a value of the amplifier output signal (133) as a clock input value, and / or - depends on a value of the decimation filter input signal (301) as a timer input value, and / or - depends on a value of the decimation filter output signal (302) as a timer input value.

52. Method according to claim 51, characterized in that that a filter characteristic of the prefiltering of the shunt resistance voltage (US) to the amplifier input voltage (Ue), in particular a prefilter cutoff frequency (foV), depends on the timer input value.

53. Method according to claim 51, characterized in that that a property of detecting and amplifying the amplifier input voltage (Ue) to the amplifier output signal (133), in particular an amplification or an attenuation, depends on the timer input value.

54. Method according to claim 51, characterized in that that a property of sampling the amplifier output signal (133) to the decimation filter input signal (301), in particular a sampling time and / or a sampling period, depends on the clock input value.

55. Method according to claim 51, characterized in that that a property of the filtering of the decimation filter input signal (301) to the decimation filter output signal (302), in particular a filter cutoff frequency (fo), depends on the clock input value.

56. Method according to claim 52, characterized in that that the prefilter cutoff frequency (foV) is above a prefilter cutoff value when amounts of clock input values are below a first input threshold value, and the prefilter limit frequency (foV) is below the prefilter limit value when amounts of timer input values are above the first input threshold value, or the prefilter limit frequency (foV) is below the prefilter limit value when amounts of timer input values are below the first input threshold value, and the prefilter limit frequency (foV) is above the prefilter limit value when amounts of timer input values are above the first input threshold value.

57. Method according to claim 53, characterized in that that an amount of the gain is above a gain limit value when amounts of timer input values are below a second input threshold value, and the amount of gain is below the gain limit value when amounts of timer input values are above the second input threshold value, or the amount of amplification is below the amplification limit value when amounts of timer input values are below the second input threshold value, and the amount of gain is above the gain limit value when amounts of timer input values are above the second input threshold value.

58. Method according to claim 54, characterized in that the sampling period is above a sampling period limit value when amounts of clock input values are below a third input threshold value, and the sampling period is below the sampling period limit value when amounts of clock input values are above the third input threshold value, or the sampling period is below the sampling period limit value when amounts of timer input values are below the third input threshold value, and the sampling period is above the sampling period limit value when amounts of timer input values are above the third input threshold value.

59. Method according to claim 55, characterized in that that an amount of the filter cutoff frequency (fo) is above a filter cutoff frequency limit value when amounts of timer input values are below a fourth input threshold value, and the amount of the filter cutoff frequency (fo) is below the filter cutoff frequency limit value when amounts of timer input values are above the fourth input threshold value, or the amount of the filter cutoff frequency (fo) is below the filter cutoff frequency limit value when amounts of timer input values are below the fourth input threshold value, and the amount of the filter cutoff frequency (fo) is above the filter cutoff frequency limit value when amounts of timer input values are above the fourth input threshold value.