MOLDED EMBEDDED BRIDGE FOR ENHANCED EMIB APPLICATIONS

Description

TECHNICAL FIELD

[0001] Embodiments described herein relate generally to electronic device packages, and more particularly to interconnect bridges in package substrates.BACKGROUND

[0002] Microelectronics generally include a central processing unit (CPU). In order to enhance performance, CPU products are increasingly integrating multiple dies within the CPU package in a side-by-side or other multi-chip module (MCM) format. An embedded multi-die interconnect bridge (EMIB) is a way to electrically connecting multiple dies within a microelectronic package. Document US 2014 / 174807 relates to an organic bridge device. Document JP 2006 / 2700065 shows a circuit device comprising resin layers. Document US72006043567 shows a package structure including multiple devices.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. FIG. 1 illustrates a microelectronic package. FIG. 2 illustrates a cross-section of a microelectronic package. FIG. 3 illustrates a layered EMIB. FIGS. 4A and 4B illustrate an encapsulated EMIB in accordance with some embodiments disclosed herein. FIG. 5 illustrates an encapsulated layered EMIB in accordance with some embodiments disclosed herein. FIG. 6 illustrates a method. FIGS. 7A and 7B illustrated process steps. FIG. 8 illustrates a system level diagram in accordance with some embodiments disclosed herein. DETAILED DESCRIPTION

[0004] An embedded multi-die interconnect bridge (EMIB) enables low cost and 2.5D packaging for high density interconnects between heterogeneous die on a single package. Instead of an expensive silicon (Si) interposer with through silicon vias (TSV), a small silicon bridge chip, termed as EMIB, can be embedded in an organic package substrate, and can enable high-density die-to-die connections only where needed. Standard flip-chip assembly can be used for robust power delivery and to connect high-speed signals directly from a chip to the package substrate using this bridge. EMIBs eliminate the need for TSVs and specialized interposer silicon that add complexity and cost.

[0005] While an EMIB offers significant advantages and cost benefits over silicon interposer or high-density substrate surface layers, it does have some issues. The bridge that is Si-based is still manufactured using costly wafer fab processes. In addition, a low coefficient of thermal expansion (CTE) of the Si bridge compared to the buildup dielectric that it is embedded in, EMIB substrates suffer from thermomechanical issues such as heat induced stresses, warpage, delamination, etc both within the substrate as well as post flip chip attachment. The thermomechanical issues can therefore limit the Si bridge size that can be embedded. Furthermore, use of silicon design rules, can restrict creation of metal reference planes that are crucial for high speed input / output (I / O) signaling in the embedded silicon bridge.

[0006] As disclosed herein, to overcome the thermomechanical issues, a molded fine line and spaced (FLS) interconnect bridge with graded CTEs can be employed to balance / minimize the CTE mismatch that can occur in EMIB substrates and can be manufactured using low cost substrate, molded embedded pane-level ball (EPLB) grid array packaging processes. A further benefit of this architecture is the ability to use substrate design rule like reference planes in the design in that can truly offer wider flexibility for design in enabling a high-speed embedded bridge.

[0007] Turning now to the figures, FIG. 1 illustrates a microelectronic package 100. FIG. 2 illustrates a cross-section of the microelectronic package 100. The microelectronic package 100 can include a first die 102, a second die 104, an EMIB 106, and substrate 108. As shown in FIG. 1, the microelectronic package 100 can also include electrical connections 110 that can be used to power the first die 102 and the second die 104 and allow signals to pass between the first die 102 and the second die 104. The electrical connections 110 can also be used to provide ground references.

[0008] As shown in FIG. 1, the EMIB 106 can be surrounded, or embedded, in the substrate 108. The substrate 108 may have a high CTE. For example, the substrate 108 may be made of a dielectric with a CTE of approximately 30 / °C or higher. The EMIB 106 may have a low CTE compared to the substrate 108. For example, the EMIB 106 may be made of a silicon (Si) alloy or epoxy / Si material that has a CTE of approximately 3 / °C.

[0009] The mismatch in CTE between the buildup dielectric and EMIB can cause thermal stresses and warpage within the substrate 108. The thermal stresses and warpage can lead to delamination and fracturing of the various layers that make up the EMIB substrate 108. FIGS. 3-5 show various solutions to combat the mismatch in CTE in accordance with embodiments disclosed herein.

[0010] FIG. 3 illustrates a layered EMIB 300. As shown in FIG. 3, the EMIB 300 can include a first layer 302, a second layer 304, a third layer 306, and a fourth layer 308 (collectively referred to as layers). During operation, heat generated with the EMIB 300 can be dissipated into the substrate 108 and other components, such as heat sinks attached to the first die 102 and the second die 104. As the heat is both generated and dissipated, the layers within the EMIB 300 can heat at different rates due to the amount of electric current flowing through the layers, their proximity to other heat sources and sinks and layer material properties. The layers can be molded layers. As such, each of the layers can include a molded material.

[0011] To combat the uneven heating, and hence warpage, delamination, etc., each of the layers can be created to have a different CTE. For example, the CTE of the first layer 302 may be 25 / °C, the CTE of the second layer 304 may be 18 / °C, the CTE of the third layer 306 may be 12 / °C, and the CTE of the fourth layer 308 may be 7 / °C. The CTE of the layers need not decrease in a direction away from the first die 102 and the second die 104 and instead may increase. For example, the CTE of the first layer 302 may be 7 / °C, the CTE of the second layer 304 may be 12 / °C, the CTE of the third layer 306 may be 18 / °C, and the CTE of the fourth layer 308 may be 25 / °C.

[0012] The variation in CTE from one layer to another can be adjusted depending on the application and materials used to build the layers. For example, the CTE can vary linearly or non-linearly. The CTE range can also differ from application to application. For example, an EMIB substrate in a liquid cooled computer may able to dissipate heat faster and therefore the CTE range of the EMIB 300 may not to be as large as an EMIB substrate in a computer that used a gas (e.g., air) as a cooling fluid.

[0013] The variation in CTE can be achieved using differing levels of a dopant used to manufacture the layers. For example, the layers can be manufactured from materials such as, but not limited to, Epoxy Phenol, Epoxy Anhydride, or Epoxy Amine and a filler material such as, but not limited to, silica. By varying the ration of silica to epoxy, the CTE of the layers can be varied. For instance, a layer with an approximately 9:1 ratio of epoxy to filler may have a CTE of 7 / °C and a layer with an approximately 7:3 ratio of epoxy to filler may have a CTE of 30 / °C.

[0014] In addition, the variation in CTE can be achieved by using different filler materials. For example, the layers can be manufactured from Epoxy Phenol and materials such as, but not limited to, silica, alumina, or an organic compound can be used as fillers for different layers. Using the various filler materials, the CTE of the layers can be varied from between approximately 7 / °C to approximately 50 / °C.

[0015] As disclosed herein, each of the layers can be routing layers or ground layers embedded within the substrate 108. Each of the layers can include various traces or other electrically conductive pathways. Each of the layers can be positioned such that adj acent layers have CTEs that vary from one another as described herein.

[0016] FIG. 4A illustrates an encapsulated EMIB 400 in accordance with some embodiment disclosed herein. As shown in FIG. 4A, the EMIB 106 can be encapsulated by a mold 402. The mold 402 can have a CTE that is close to the CTE of the substrate 108 in which the EMIB 106 is embedded in. For example, the CTE of the substrate 108 may be 25 / °C and the CTE of the mold 402 may be 20 / °C. In addition, the CTE of the mold 402 can be close to the CTE of the EMIB 106. For example, the CTE of the EMIB 106 may be 7 / °C and the CTE of the mold 402 may be 11 / °C. Furthermore, the CTE of the mold 402 can be in between the CTEs of the EMIB 106 and the substrate 108. For example, the CTE of the EMIB 106 may be 7 / °C, the CTE of the substrate 108 may be 25 / °C, and the CTE of the mold 402 may be 11 / °C.

[0017] Having the CTE of the mold 402 be somewhere in between the CTE of the EMIB 106 and the substrate 108 can allow the mold 402 to absorb some of the thermal stresses that can be induced by the heating and CTE differences between the EMIB 106 and the substrate 108. In addition, the mold 402 can be manufactured of a material that can facilitate heat transfer in a desired direction. For example, to help dissipate heat from the EMIB 106 to the substrate 108, the mold 402 can be manufactured of a material with a high thermal conductivity. To help insulate the EMIB 106 from heat that may be generated within the substrate 108, the mold 402 may be manufactured with a material that has a low thermal conductivity. As such, heat generated within the EMIB 106 can be directed in a direction towards the first die 102 and the second die 104, to be removed from heat sinks attached to the first die 102 and the second die 104.

[0018] The mold 402 can encapsulate all or a portion of the EMIB 106. For example, as shown in FIG. 4A, the mold 402 can surround the EMIB 106 on all sides except a side proximate the first die 102 and the second die 104. Other sides of the EMIB 106 can be exposed.

[0019] The mold 402 can be manufactured from materials and fillers as described above with respect to the layers. In addition, the mold 402 can be manufactured from multiple layers as well. For example, as shown in FIG. 4B, the mold 402 can be manufactured from a first layer 404 and a second layer 406. While FIG. 4B shows only two layers, any number of layers can be used to manufacture the mold 402. Furthermore, the CTE for the layers of the mold 402 can be varied as described above.

[0020] FIG. 5 illustrates an encapsulated layered EMIB 500 in accordance with some embodiment disclosed herein. As shown in FIG. 5, the EMIB 500 can include the mold 402 and the EMIB 106. The EMIB 106 can include the first layer 302, the second layer 304, the third layer 306, and the fourth layer 308. In addition, the mold 402 can be layered as described above.

[0021] The combination of the mold 402 and the layers can allow for the CTE of the EMIB 500 to be further customized. For example, the layers can each have different CTEs for thermal management. The mold 402 can have a CTE that further reduces the mismatch in CTE between the layers and the substrate 108. For example, the CTEs of the layers can vary from, for example, 7 / °C to 25 / °C and the CTE of the mold 402 can be 30 / °C. For a layered mold 402, the CTEs of the layers can range from 7 / °C to 15 / °C and the layers of the mold 402 can vary from 20 / °C to 30 / °C.

[0022] FIG. 6 illustrates a method 600 for manufacturing an EMIB embedded substrate. FIG. 6 will be discussed with reference to FIGS. 7A and 7B showing the process steps for the method 600. The method 600 can be implemented in a high volume manufacturing (HVM) processing line.

[0023] The method 600 can begin at stage 602 where a substrate can be provided. From stage 602, the method 600 can proceed to stage 604 where layers can be created (process stage 702). For example, the very dense and fine line spaced layers can be created using high-resolution lithography. During the creation of the layers, very dense and fine line spaced layers can be created on a first layer using high-resolution lithography. The traces in the subsequent layers may not be as fine as in the first layer. However, the subsequent layers can be handled through fan out routing. In addition, subsequent layers can utilize small filler sizes coupled with less filling to result in CTE variations. For instance, using less filling material can result in progressively higher CTE as subsequent layers are produced. The result can be reasonably fine tracing that can reduce the amount of fan out needed.

[0024] As discussed herein, during the creations of the layers, the amount of filler can be varied to alter the CTE of each layer. In addition, the filler can be different for different layers to result in alteration of the CTE from layer to layer. Furthermore, as discussed above, the layers do not have to have a CTE that varies. For instance, the bridge formed by the layers can have a uniform CTE.

[0025] From stage 604, the method 600 can proceed to stage 606 where the layers can be encapsulated by a mold. As discussed above, the mold can have a CTE that is higher than the CTE of the layers forming the bridge. In addition, the mold can be formed of layers that have CTEs that vary from one another.

[0026] Encapsulating the layers can include utilizing an EPLB type process flow used to over-mold a high CTE material to encapsulate the layers. The material proximate the substrate can have a CTE that is as close as possible to that of the buildup dielectric.

[0027] Note that not all the stages in the method 600 have to be performed. For example, the layers can be created with CTEs that vary (stage 604) as described herein and the resulting bridge can be embedded to form the microelectronic package (process stage 704a). Stated another way, stage 606 can be omitted from the method 600. In addition, the bridge can be formed with layers that have a uniform CTE and the bridge can then be encapsulated (stage 606) and installed to form the microelectronic package (process stage 704b). Finally, the bridge can be formed with layers having CTEs that vary (stage 604) and the bridge encapsulated (stage 606). The encapsulated bridge can then be embedded to form the microelectronic package (process stage 704c).

[0028] FIG. 8 illustrates a system level diagram, according to one embodiment of the invention. For instance, FIG. 8 depicts an example of an electronic device (e.g., system) including the microelectronics package 100 as described herein. FIG. 8 is included to show an example of a higher level device application for the present invention. In one embodiment, system 800 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 800 is a system on a chip (SOC) system.

[0029] In one embodiment, processor 810 has one or more processing cores 812 and 812N, where 812N represents the Nth processor core inside processor 810 where N is a positive integer. In one embodiment, system 800 includes multiple processors including 810 and 805, where processor 805 has logic similar or identical to the logic of processor 810. In some embodiments, processing core 812 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 810 has a cache memory 816 to cache instructions and / or data for system 800. Cache memory 816 may be organized into a hierarchal structure including one or more levels of cache memory.

[0030] In some embodiments, processor 810 includes a memory controller 814, which is operable to perform functions that enable the processor 810 to access and communicate with memory 830 that includes a volatile memory 832 and / or a non-volatile memory 834. In some embodiments, processor 810 is coupled with memory 830 and chipset 820. Processor 810 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, the wireless antenna interface 878 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0031] In some embodiments, volatile memory 832 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and / or any other type of random access memory device. Non-volatile memory 834 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0032] Memory 830 stores information and instructions to be executed by processor 810. In one embodiment, memory 830 may also store temporary variables or other intermediate information while processor 810 is executing instructions. In the illustrated embodiment, chipset 820 connects with processor 810 via Point-to-Point (PtP or P-P) interfaces 817 and 822. Chipset 820 enables processor 810 to connect to other elements in system 800. In some embodiments of the invention, interfaces 817 and 822 operate in accordance with a PtP communication protocol such as the Intel ®< QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0033] In some embodiments, chipset 820 is operable to communicate with processor 810, 805N, display device 840, and other devices 872, 876, 874, 860, 862, 864, 866, 877, etc. Chipset 820 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and / or receive wireless signals.

[0034] Chipset 820 connects to display device 840 via interface 826. Display 840 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor 810 and chipset 820 are merged into a single SOC. In addition, chipset 820 connects to one or more buses 850 and 855 that interconnect various elements 874, 860, 862, 864, and 866. Buses 850 and 855 may be interconnected together via a bus bridge 872. In one embodiment, chipset 820 couples with a non-volatile memory 860, a mass storage device(s) 862, a keyboard / mouse 864, and a network interface 866 via interface 824 and / or 804, smart TV 876, consumer electronics 877, etc.

[0035] In one embodiment, mass storage device 862 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 866 is implemented by any type of well known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and / or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0036] While the modules shown in FIG. 8 are depicted as separate blocks within the system 800, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 816 is depicted as a separate block within processor 810, cache memory 816 (or selected aspects of 816) can be incorporated into processor core 812.Additional Notes & Examples:

[0037] The following examples are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

[0038] An example includes an embedded multi-die interconnect bridge (EMIB) substrate The EMIB substrate can comprise an organic substrate and a bridge. The bridge can include a plurality of routing layers. The bridge can be embedded in the organic substrate. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer. Further comprising a mold embedded in the organic substrate, the mold encapsulating all or a portion of the bridge and having a CTE between a CTE of the bridge and a CTE of the organic substrate

[0039] An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying linearly from one routing layer to another.

[0040] An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying non-linearly from one routing layer to another.

[0041] An example of the EMIB substrate can optionally include a routing layer of the plurality of routing layers with the lowest CTE being adjacent a die interconnect region of the EMIB substrate.

[0042] An example of the EMIB substrate can optionally include a mold having a CTE higher than a highest CTE of one of the plurality of routing layers. The mold can encapsulate a portion of the plurality of routing layers.

[0043] An example of the EMIB substrate can optionally include the variation in CTE for each of the plurality of routing layers resulting from each of the plurality of routing layers having a different silica filler content.

[0044] An example of the EMIB substrate can optionally include the CTE of the plurality of routing layers varying from about 7 / °C to about 25 / °C.

[0045] An example can include an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge, and a mold. The bridge can include a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. The mold can encapsulate a majority of the plurality of routing layers. The mold can have a coefficient of thermal expansion (CTE) that is greater than a CTE of the plurality of routing layers.

[0046] An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying linearly from one routing layer to another.

[0047] An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying non-linearly from one routing layer to another.

[0048] An example of the EMIB substrate can optionally include a routing layer of the plurality of routing layers is adjacent a die interconnect region of the EMIB substrate.

[0049] An example of the EMIB substrate can optionally include a variation in CTE for each of the plurality of routing layers resulting from each of the plurality of routing layers having a different silica filler content.

[0050] An example of the EMIB substrate can optionally include the CTE of the plurality of routing layers being about 7 / °C and the CTE of the mold is about 30 / °C.

[0051] An example can include an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge, and a mold. The bridge can include a plurality of routing layers. The bridge cam be embedded in the organic substrate. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from about 7 / °C to about 25 / °C. The mold can have a CTE higher than a highest CTE of one of the plurality of routing layers. The mold can encapsulate a portion of the plurality of routing layers.

[0052] An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying linearly from one routing layer to another.

[0053] An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying non-linearly from one routing layer to another.

[0054] An example of the EMIB substrate can optionally include a routing layer of the plurality of routing layers with the lowest CTE being adjacent a die interconnect region of the EMIB substrate.

[0055] An example of the EMIB substrate can optionally include the variation in CTE for each of the plurality of routing layers resulting from each of the plurality of routing layers having a different silica filler content.

[0056] An example of the EMIB substrate can optionally include the CTE of the mold being about 30 / °C.

[0057] An example can include a method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate. The method can comprise forming a bridge including a plurality of routing layers, each of the plurality of routing layers having a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer; and embedding the bridge in an organic substrate.

[0058] An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies linearly from one routing layer to another.

[0059] An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies non-linearly from one routing layer to another.

[0060] An example of the method can optionally include forming the plurality of routing layers including forming a routing layer of the plurality of routing layers with the lowest CTE adjacent a die interconnect region of the EMIB substrate.

[0061] An example of the method can optionally include encapsulating a portion of the plurality of routing layers with a mold. The mold can have a CTE higher than a highest CTE of one of the plurality of routing layers.

[0062] An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers with a different silica filler content.

[0063] An example of the method can optionally include the CTE of the plurality of routing layers varying from about 7 / °C to about 25 / °C.

[0064] An example can include a method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate. The method can comprise forming a bridge including a plurality of routing layers, each routing layer having a plurality of fine line and spaced (FLS) traces; encapsulating a majority of the plurality of routing layers with a mold, the mold having a coefficient of thermal expansion (CTE) that is greater than a CTE of the plurality of routing layers; and embedding the bridge in an organic substrate.

[0065] An example of the method can optionally include forming the plurality of routing layers includes forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies linearly from one routing layer to another.

[0066] An example of the method can optionally include forming the plurality of routing layers includes forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies non-linearly from one routing layer to another.

[0067] In Example 30, the method can optionally include forming the plurality of routing layers includes forming a routing layer of the plurality of routing layers with the lowest CTE adjacent a die interconnect region of the EMIB substrate.

[0068] An example of the method can optionally include forming the plurality of routing layers includes forming each of the plurality of routing layers with a different silica filler content.

[0069] An example of the method can optionally include the CTE of the plurality of routing layers being about 7 / °C and the CTE of the mold being about 30 / °C.

[0070] An example can include a method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate. The method can comprise forming a bridge including a plurality of routing layers, each routing layer having a plurality of traces, each of the plurality of routing layers having a coefficient of thermal expansion (CTE) that varies from about 7 / °C to about 25 / °C; encapsulating a portion of the plurality of routing layers with a mold having a CTE higher than a highest CTE of one of the plurality of routing layers; and embedding the bridge in an organic substrate.

[0071] An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies linearly from one routing layer to another.

[0072] An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies non-linearly from one routing layer to another.

[0073] An example of the method can optionally include forming the plurality of routing layers including forming a routing layer of the plurality of routing layers with the lowest CTE adjacent a die interconnect region of the EMIB.

[0074] An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers with a different silica filler content.

[0075] An example of the method can optionally include the CTE of the mold being about 30 / °C.

Claims

1. An embedded multi-die interconnect bridge, EMIB, substrate comprising: an organic substrate (108); a bridge (106) embedded in the organic substrate (108), the bridge (106) including a plurality of routing layers (302), (304), (306), (308) embedded within the bridge (106), each routing layer having a plurality of traces, each of the plurality of routing layers (302), (304), (306), (308) having a coefficient of thermal expansion, CTE, that varies from an adjacent routing layer; and a mold (402) embedded in the organic substrate (108), the mold (402) encapsulating all or a portion of the bridge (106) and having a CTE between a CTE of the bridge and a CTE of the organic substrate (108).

2. The EMIB substrate of claim 1, wherein the CTE of each of the plurality of routing layers (302), (304), (306), (308) varies linearly from one routing layer to another.

3. The EMIB substrate of claim 1, wherein the CTE of each of the plurality of routing layers (302), (304), (306), (308) varies non-linearly from one routing layer to another.

4. The EMIB substrate of any one of claims 1-3, wherein a routing layer of the plurality of routing layers (302), (304), (306), (308) with the lowest CTE is adjacent a die interconnect region of the EMIB substrate.

5. The EMIB substrate of any one of claims 1-4, wherein the mold (402) has a CTE higher than a highest CTE of one of the plurality of routing layers (302), (304), (306), (308), the mold (402) encapsulating a portion of the routing layers (302), (304), (306), (308).

6. The EMIB substrate of any one of claims 1-5, wherein the variation in CTE for each of the plurality of routing layers (302), (304), (306), (308) results from each of the plurality of routing layers (302), (304), (306), (308) having a different silica filler content.

7. The EMIB substrate of any one of claims 1-6, wherein the CTE of the plurality of routing layers (302), (304), (306), (308) varies from about 7 ×10-6 / °C to about 25 ×10-6 / °C.

8. A method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate, the method comprising: forming an organic substrate (108); forming a mold (402) embedded in the organic substrate (108); forming a plurality of routing layers (302), (304), (306), (308), each of the plurality of routing layers (302), (304), (306), (308) having a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer, the plurality of routing layers (302), (304), (306), (308) forming a bridge (106); wherein the bridge (106) is embedded in the organic substrate (108);and wherein the mold (402) is encapsulating all or a portion of the bridge (106) and the having a CTE between a CTE of the bridge (106) and the CTE of the organic substrate (108).

9. The method of claim 8, wherein forming the plurality of routing layers (302), (304), (306), (308) includes forming each of the plurality of routing layers (302), (304), (306), (308) such that the CTE of each of the plurality of routing layers (302), (304), (306), (308) varies linearly from one routing layer to another.

10. The method of claim 8, wherein forming the plurality of routing layers (302), (304), (306), (308) includes forming each of the plurality of routing layers (302), (304), (306), (308) such that the CTE of each of the plurality of routing layers (302), (304), (306), (308) varies non-linearly from one routing layer to another.

11. The method of any one of claims 8-10, wherein forming the plurality of routing layers (302), (304), (306), (308) includes forming a routing layer of the plurality of routing layers (302), (304), (306), (308) with the lowest CTE adjacent a die interconnect region of the EMIB.

12. The method of any one of claims 8-11, further comprising encapsulating a portion of the plurality of routing layers (302), (304), (306), (308) with the mold (402), the mold (402) having a CTE higher than a highest CTE of one of the plurality of routing layers (302), (304), (306), (308).

13. The method of any one of claims 8-12, wherein forming the plurality of routing layers (302), (304), (306), (308) includes forming each of the plurality of routing layers (302), (304), (306), (308) with a different silica filler content.