Integrated circuit with a chip formed by a high-voltage transmitter and a chip formed by a low-voltage transmitter

Description

DOMAINE DE L'INVENTION

[0001] The present invention relates to an integrated circuit comprising a chip formed from a high voltage transistor and comprising a chip formed from a low voltage transistor. ARRIERE PLAN TECHNOLOGIQUE DE L'INVENTION

[0002] HEMTs (high electron mobility transistors) made from III-N semiconductor materials are typically "normally on", meaning they have a negative threshold voltage and can conduct current with a gate-to-source voltage of 0V. These components with negative threshold voltages are called depletion mode or "D-mode" components.

[0003] It is preferable for power electronics applications to have so-called "normally off" components, i.e., components with a positive threshold voltage that cannot conduct current when the gate voltage is at 0 V. These components are commonly referred to as "E-mode" components.

[0004] The fabrication of high-voltage components on III-N semiconductor materials in E-mode is complex and these components often have lower intrinsic performance than similar components in D-mode.

[0005] An alternative to a single high-voltage E-mode component is to combine a high-voltage D-mode component, such as a D-mode HEMT transistor made from III-N semiconductor materials, with a low-voltage E-mode component, such as an E-mode MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made from silicon. Two chips 1, 2 comprising the HEMT and MOSFET components respectively are then combined to form a hybrid integrated circuit 3, for example a switching integrated circuit.

[0006] There figure 1a represents the schematic diagram of a so-called “cascode” hybrid circuit combining HEMT and MOSFET components. An integrated circuit 3 implementing this first configuration is shown on the figure 1b . The drain 21 and the source 22 of an E-mode 2 MOSFET chip are respectively connected to the source 12 and the gate 13 of a D-mode 1 HEMT chip. This electrical connection is made in the package 4 of the integrated circuit 3 comprising the two electronic chips 1, 2, usually by wire bonding 5 between the gate 13, 23, source 12, 22 and drain 11, 21 contact pads accessible on each of the chips 1, 2. In the cascode integrated circuit 3, the gate 23 of the MOSFET chip 2 controls the switching on or off of the integrated circuit 3.

[0007] The gate contact pad 23 of the MOSFET chip 2 is connected in the package 4 of the integrated circuit 3 to a gate pin 33. The source contact pad 22 of the MOSFET chip 2 is connected in the package 4 to a source pin 32. Finally, the drain contact pad of the HEMT chip 1 is connected, still in the package 4, to a drain pin 31. The three pins 31, 32, 33 constitute the electrical connections of the integrated circuit 3 outside the package 4.

[0008] There figure 1c represents the schematic diagram of a so-called “dual control” hybrid circuit combining HEMT and MOSFET components. An integrated circuit 3 implementing this second configuration is shown on the figure 1d . According to this alternative configuration, the chips 1, 2 comprising respectively the HEMT and MOSFET components are simply connected in series, the drain 21 of the E-mode 2 MOSFET chip being connected to the source 12 of the D-mode 1 HEMT chip. In this configuration, the package 4 of the integrated circuit 3 has an additional gate pin 34, electrically connected to the gate contact pad 13 of the D-mode 1 HEMT chip in order to allow direct control of this transistor.

[0009] For a detailed discussion of the operating principles of a cascode circuit or a dual-control circuit, please refer to the document “A dual-mode Driver IC with Monolithic Negative Drive-Voltage Capability and Digital Current-Mode Controller for Depletion-Mode GaN HEMT”, Yue Wen et al, IEEE Transaction on Power Electronic, Issue 99, 1996.

[0010] Regardless of the configuration chosen, the integrated circuit 3 is intended to be placed on a printed circuit for its interconnection to other components.

[0011] As is well known per se, for example from US92683512 or US8624662, it is usual to place, in the integrated circuit 3, additional components, such as resistors or capacitors, to form a protection device. This protection device has the function of controlling, in particular during transient switching phases, the voltage (or current) which can develop (or circulate) in certain nodes of the hybrid circuit.

[0012] The nature of the protection device may depend on the intended application (for example the intended switching frequency, the amplitude of the voltage to be switched, etc.), or on the nature of the other components with which the integrated circuit 3 may be connected on the printed circuit.

[0013] State-of-the-art integrated circuits implementing a hybrid circuit do not offer the possibility of adjusting the configuration of the protection device which is previously provided by the manufacturer.

[0014] Additionally, one might wish to have an integrated circuit comprising a high-voltage E-mode component and a low-voltage D-mode component, which can be used, as needed, in a "cascode" configuration or in a "dual-control" configuration.

[0015] Document US 2014 / 175454 discloses a power conversion device provided with a high voltage transistor, equipped with a package and several pins and two chips respectively with GaN and CMOS transistor with contact pads between the two chips.

[0016] More generally, there is currently no integrated circuit for applications in the field of power switching, comprising a high voltage E-mode component and a low voltage D-mode component, which is versatile, simple to compose and robust, i.e. which can be used in a wide range of applications (presenting very variable currents, voltages and switching frequencies) and environments (in particular thermal or electromagnetic) without modifying the internal architecture. OBJET DE L'INVENTION

[0017] The present invention aims to overcome all or part of the aforementioned drawbacks. BREVE DESCRIPTION DE L'INVENTION

[0018] The invention is defined by the appended claims. BREVE DESCRIPTION DES DESSINS

[0019] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which: THE figures 1a et 1b respectively represent a block diagram and an integrated circuit of a cascode circuit of the state of the art; figures 1c et 1d respectively represent a block diagram and an integrated circuit of a “dual control” circuit of the state of the art; figures 2a et 2b respectively represent a first block diagram and a first integrated circuit in accordance with the invention; the figures 3a et 3b respectively represent a second block diagram and a second integrated circuit in accordance with the invention; figures 4a à 4c represent different modes of implementation of an integrated circuit according to the invention comprising a passive resistive protection component; the figures 5a à 5c represent an integrated circuit according to another aspect of the invention. DESCRIPTION DETAILLEE DE L'INVENTION

[0020] The figures are for illustrative purposes only and do not represent the elements to scale. Furthermore, the same reference may be used for identical elements or elements fulfilling the same functions in the different embodiments of the invention or in the state of the art.

[0021] Various examples of implementation and embodiment are set forth below. Regardless of the designation given to these examples (embodiments, examples, variants, etc.) and the qualifiers used (e.g., preferably, etc.), only those parts of the description which are included within the scope of the claims are part of the present invention, the other examples being set forth only for illustrative purposes and being useful only to highlight specific aspects of the invention in relation to what is not part of it.

[0022] There figure 2a represents a block diagram of an integrated circuit 3 according to the invention. Inside a housing 4, represented by the dotted lines on the figure 2a , a high voltage transistor in depletion mode 1 (which will be referred to as the “high voltage transistor” in the remainder of this description) and a low voltage transistor in enhancement mode 2 (which will be referred to as the “low voltage transistor” in the remainder of this description) are connected to each other in a cascode configuration. More precisely, the source 12 of the high voltage transistor 1 is electrically connected to the drain 21 of the low voltage transistor 2. This connection defines a middle node of the circuit. The gate 13 of the high voltage transistor 1 is electrically connected to the source 22 of the low voltage transistor 2.

[0023] A plurality of nodes of the circuit are made accessible outside the housing 4 by means of pins in order to be able to electrically connect this circuit to other circuits.

[0024] In the remainder of this description, the term “pin” will refer to any element of the integrated circuit 3 emerging from the housing 4 and providing electrical access to one of the nodes of the circuit 3. It may thus be a conductive element projecting from the housing 4 or a simple contact surface arranged on one of the faces of the housing 4. .

[0025] As shown in the schematic diagram of the figure 2a , the circuit 3 comprises a gate pin 33, a source pin 32, respectively electrically connected to the gate 23 and to the source 22 of the low voltage transistor 2. This circuit also comprises a drain pin 31 electrically connected to the drain 11 of the high voltage transistor 1 and a midpoint pin 35 making it possible to provide electrical access to the midpoint of the circuit 3.

[0026] Circuit 3 of the figure 2a can be used as a power switch. For this purpose, the source pin 32 is connected to an electrical ground, the drain pin 31 is connected to a load. The switching of circuit 3 is controlled by a control signal applied to the gate pin 33. When the control signal has a zero voltage, circuit 3 is blocking. When the control signal has a positive voltage (typically a few volts) circuit 3 is conducting. Several amperes can then flow between the drain pin 31 and the source pin 32 of circuit 3.

[0027] As previously mentioned in the introduction to this application, the switching of circuit 3 between an on state and a blocking state (or conversely between a blocking state and an on state) can lead to the appearance of uncontrolled currents or voltages in the circuit, in particular at the middle node. These transient voltages or currents can damage the high voltage 1 and low voltage 2 transistors if they exceed predefined thresholds.

[0028] In order to protect against these phenomena, the device of the present description makes it possible to place, outside the housing 4, a countermeasure circuit between the midpoint pin 35 and the source pin 32. This may for example be a circuit comprising a resistor, possibly supplemented by a parallel capacitor, arranged between the aforementioned pins 35, 32. The countermeasure circuit makes it possible in particular to limit the transient voltage developing at the midpoint, and to divert the excessive static or transient current which could circulate in the low voltage transistor 2 during these switching phases.

[0029] When the switching frequency of the control signal is high, for example greater than 100 kHz, the internal electrical connections of the circuit (for example the electrical connections connecting the electrodes of the high and low voltage transistors 1, 2 to the pins of the package 4) may exhibit inductive behavior. The sudden variations in the current flowing in these connections lead to the generation of a significant transient voltage at their terminals. This is particularly the case for the connection connecting the source 22 of the low voltage transistor 2 and the source pin 32 of the circuit.In order to avoid injecting these transient currents and voltages on the side of the control circuit, which can be connected to the gate 33 and source 32 pins, or on the side of the countermeasures circuit which can be connected to the midpoint 35 and source 32 pins, the circuit provides a first kelvin pin 36 electrically connected to the source 22 of the low voltage transistor 2 by a kelvin connection.

[0030] As is well known per se, a kelvin connection, or voltage detection connection, is intended to be connected to a circuit having a very high impedance in steady state, so that the current flowing through this connection is extremely low. On the kelvin pin 36 of the case 4, there is therefore a measurement of the voltage present at the source 22 of the low voltage transistor 2. The current flowing in the connection connecting the source 22 to the kelvin pin 36 being very low, the voltage measurement is not disturbed by inductive voltages.

[0031] The kelvin pin 36 can be connected to a control circuit external to the package, the control circuit itself being connected to the gate pin 33. In addition, the kelvin pin 36 can be connected to the countermeasure circuit external to the package, the countermeasure circuit itself being connected to the midpoint pin 35. The joint availability of the midpoint voltage at the midpoint pin 35 and the kelvin pin 36, offers the possibility of forming a countermeasure device very adapted to the environment in which the integrated circuit 3 is placed.

[0032] In order to allow easy mounting of the integrated circuit 3 on a printed circuit, facilitate the configuration or routing of the conductive tracks on this circuit and minimize the control loops, it is possible to choose to arrange, on the package 4, the first kelvin pin 36 adjacent to the gate pin 33 or arranged on the same side of the package as the gate pin 33 (as shown in the figure 2a ), or adjacent to the midpoint pin 35 or arranged on the same side of the housing as the midpoint pin 35.

[0033] According to the claimed invention, the circuit 3 is provided with a first kelvin pin 36 and a second kelvin pin 36', which can both be of similar constructions. In this case, the first kelvin pin 36 can be arranged on the housing 4 adjacent to the grid pin 33 (or arranged on the same side of the housing as the grid pin 33) and the second kelvin pin 36' adjacent to the midpoint pin 35 (or arranged on the same side of the housing as the midpoint pin 35).

[0034] There figure 2b presents an embodiment, in the form of an integrated circuit 3, of the schematic circuit shown in the figure 2a .

[0035] The integrated circuit 3 comprises a package 4, a first chip 1 comprising a high voltage transistor in depletion mode and a second chip 2 comprising a low voltage transistor in enhancement mode. The first and second chips 1, 2 respectively comprise gate contact pads 13, 23, drain contact pads 11, 21 and source contact pads 12, 22. Advantageously, the high voltage transistor is a HEMT transistor made on III-N semiconductor materials and the low voltage transistor is a MOSFET (Metal / Oxide / Semiconductor Field Effect Transistor) made on silicon.

[0036] The drain contact pads 11, 21 of the first chip 1 and the second chip 2 are respectively connected to contact plates 311a, 311b either by a wire connection (as shown in the figure 2b ), or by a vertical connection having a drain contact at the rear face of the first and / or second chip 1, 2 in contact with the plates 311a, 311b.

[0037] The contact plate 311b forms an electrical terminal to which the source contact pad 12 of the first chip 1 is electrically connected, and constitutes the midpoint of the circuit 3. The contact plate 311b is electrically connected to the midpoint pin 35 of the integrated circuit 3. The second contact plate 311a is in turn electrically connected to (or constitutes) the drain pin 31 of the integrated circuit 3.

[0038] The gate contact pad 13 of the first chip 1 is connected to the source contact pad 22 of the second chip 2. This forms a cascode circuit. These contact pads 13, 22 are themselves connected to the source pin 32.

[0039] Gate pin 33 of circuit 3 is connected to gate contact pad 23 of the second chip 2.

[0040] According to the claimed invention, the package 4 of the integrated circuit 3 comprises a first and a second kelvin pin 36, 36'. The first kelvin pin 36 and the second kelvin pin 36' are electrically connected to the source contact pad 22 of the low voltage transistor formed on the second chip 2.

[0041] As seen previously, the first kelvin pin 36 may be arranged, on the housing 4, adjacent to, or on the same side of the housing 4, as the grid pin 33. The second kelvin pin 36' may be arranged, on the housing 4, adjacent to the midpoint pin 35 (or on the same side of the housing 4 as this pin).

[0042] Furthermore, the midpoint pin 35 may be arranged adjacent to the source pin 32 to facilitate the implementation of the countermeasure circuit on the printed circuit.

[0043] As shown in the figure 2b , the electrical connections or links are formed (or comprise) wired connections 5. Although this is not shown in the figures, these electrical links or connections may also comprise passive elements, such as resistors or diodes, which may for example be integrated into one of the first and second chips 1, 2 or on a complementary chip placed in the package.

[0044] The package 4 may also include additional circuits integrated into one of the chips 1 or 2, or in the complementary chip. This may be, for example, a gate control circuit.

[0045] Thus, the integrated circuit 3 can be provided with a resistive passive component 9 arranged in the housing 4 and electrically connected between the gate contact pad 23 of the low-voltage transistor (also called the second gate contact pad 23) and the source contact pad 22 of the low-voltage transistor (also called the second source contact pad 22).

[0046] In this way, potential gate connection failures are contained which would lead to setting the latter to a floating potential and to losing control of the integrated circuit operating as a high-power switch. The presence of the resistive passive component 9, as close as possible to the second electronic chip 2 whose gate 23 controls the on or off mode of the integrated circuit 3, makes it possible to bring the potential of the gate 23, if it is floating, back to the source potential (i.e. to a potential close to 0) and thus to switch to off mode if there is a loss of control of the gate potential. Failures occurring at the level of the printed circuit (cutting of a PCB track for example) are contained, as are those occurring between the integrated circuit 3 and the printed circuit (dropping of a pin for example).This creates a particularly robust and secure circuit, capable of containing failures to meet established operating safety standards.

[0047] There figure 4a represents a first embodiment of an integrated circuit 3 comprising a resistive passive component 9 arranged in the housing 4 and electrically connected between the second gate contact pad 23 and the second source contact pad 22. The resistive passive component 9 is formed in a third chip 90 electrically connected to the second chip 2 by wire connection 5. Two wire connections are added compared to the conventional configuration to connect on the one hand, the second gate contact pad 23 (of the second chip 2), to a contact pad of the third chip 90 and on the other hand, the second source contact pad 22 (of the second chip 2) to another contact pad of the third chip 90.

[0048] There figure 4b represents a second embodiment of an integrated circuit 3 comprising a resistive passive component 9 integrated in the second chip 2. This configuration is very advantageous in that it does not add complexity to the assembly of the integrated circuit 3 because no additional wire connection is required. The resistive passive component 9 can be produced during the development of the low-voltage transistor included in the second chip 2, in semiconductor technology, at the wafer level before singulating the chip 2. The connection of the resistive component 9 between the second gate contact pad 23 and the source contact pad 22 can thus be made in the metal interconnection layer, at the substrate level. The resistive passive component 9 could for example be formed by a metal coil whose ends are respectively connected to the pads 23 and 22.

[0049] There figure 4c represents a third embodiment of an integrated circuit 3 comprising a resistive passive component 9 integrated in the first chip 1. Two wire connections 5 are added compared to the conventional configuration to connect on the one hand, the second gate contact pad 23 (of the second chip 2), to a contact pad of the resistor 9 of the first chip 1 and on the other hand, the second source contact pad 22 (of the second chip 2) to another contact pad of the resistor 9.

[0050] In the case where the first chip 1 is based on III-N materials, the high voltage transistor operating with a conduction channel formed in a 2-dimensional electronic gas layer (2DEG layer), the resistor 9 may advantageously be formed by a segment of said 2DEG layer, connected at its two ends to contact pads.

[0051] In all these embodiments, the passive component 9 advantageously has a resistance greater than 100 kilo-ohms. This high resistance value is required to limit the leakage current between the gate and the source, in the on mode of the integrated circuit 3. Considering a potential difference of the order of 10 Volts between gate and source, the leakage current is estimated at 100 micro-Amperes, which is acceptable, in particular for high power switching applications (650 V - 10 A).

[0052] The resistance value of passive component 9 is preferably chosen to be less than 1 mega-ohm, to maintain an acceptable reaction time in the event of a failure, meeting safety standards. Indeed, the switching time in blocking mode, i.e. the time it will take for the floating gate potential to return to the source potential, is defined by the time constant τ=RC. R is the resistance between gate and source, mainly constituted by the resistance of passive component 9; C is the capacitance between gate and source. Considering that the capacitance C is of the order of 100 picofarad in a 30V MOSFET component and that the time constant is expected to be less than or equal to 100 microseconds, the resistance of passive component 9 must preferably remain less than 1 mega-ohm.

[0053] There figure 3a represents another schematic diagram of a circuit 3 according to the invention.

[0054] Unlike the schematic diagram of integrated circuit 3 of the figure 2a , the source 22 of the low voltage transistor 2 is not electrically connected to the gate 13 of the high voltage transistor 1 inside the housing 4. The gate 13 of the high voltage transistor 1 is, on the other hand, electrically connected to a second gate pin 37 of the housing 4.

[0055] The other elements of circuit 3 on this figure 3a are identical to those of the circuit of the figure 2a , and their description will therefore be omitted for the sake of brevity.

[0056] Circuit 3 of the figure 3a can be used to form a cascode circuit. This is achieved by connecting, outside the housing 4, for example via a conductive track of a printed circuit on which the circuit 3 is arranged, the source pin 32 to the second gate pin 37.

[0057] Circuit 3 of the figure 3a can also be used in dual control. In this case, a first control circuit can be connected to the first gate pin 33, and a second control circuit (or an additional output of the first control circuit) connected to the second gate pin 37.

[0058] Advantageously, the control circuit associated with the second gate pin 37 is a differential control circuit, connected on the one hand to the gate pin 37 and on the other hand to the midpoint pin 35 of the integrated circuit 3. This configuration makes it possible to impose a differential voltage between the gate 13 and the source 12 of the high voltage transistor in depletion mode 1. A negative differential voltage makes it possible to block this transistor, and therefore to make the integrated circuit 3 block.

[0059] The control circuit associated with the first gate pin 33 acts in this case as a safety control making it possible to ensure the blocking of circuit 3 during the power-up or power-down phases of circuit 3 and the peripheral circuits during which the blocked state of the high-voltage transistor cannot be ensured.

[0060] There figure 3b represents an embodiment, in the form of an integrated circuit 3, of the schematic circuit shown in the figure 3a .

[0061] The integrated circuit 3 has a second gate pin 37. This is electrically connected to the gate contact pad 13 of the high-voltage transistor of the first chip 1.

[0062] In the integrated circuit 3 of the figure 3b , the gate contact pad 13 of the high voltage transistor of the first chip 1 is not electrically connected inside the package to the source contact pad 22 of the second chip 2. The other elements and advantages of the integrated circuit 3 shown in this figure are identical to those of the integrated circuit of the figure 2b , and their description will therefore be omitted for the sake of brevity.

[0063] Similar to what was stated for the integrated circuit of the figure 2b , the package 4 may also include additional circuits or components, such as a resistive passive component 9. These may be integrated into the first chip 1 or the second chip 2, or be arranged on a complementary chip placed in the package 4, as has been made explicit in the three implementation modes detailed previously.

[0064] There figure 5a represents a block diagram of another integrated circuit 3 in accordance with another aspect of the invention.

[0065] Inside a case 4 represented by dotted lines in this figure, a low voltage transistor 2 is connected in cascode configuration to two high voltage transistors 1, 1', themselves connected in parallel with each other. More precisely, the sources 12, 12' of the high voltage transistors 1, 1' are both electrically connected to the drain 21 of the low voltage transistor 2. In this way, similar to the configurations presented previously, a midpoint of the circuit is defined. The gates 13, 13' of the high voltage transistors 1, 1' are electrically connected to the source 22 of the low voltage transistor 2.

[0066] This configuration can be generalized to more than two high voltage transistors 1, 1', these transistors all being placed in parallel with each other, their sources electrically connected to the drain 21 of the low voltage transistor 2, and their gates being electrically connected to the source 22 of the low voltage transistor 2.

[0067] High voltage transistors 1, 1' have identical or similar threshold voltages Vt.

[0068] Surprisingly, the inventors of the present application observed that even when the high voltage transistors 1, 1' did not have exactly identical characteristics (which is very difficult to obtain because components, even from the same manufacturing batch, can always have very slight differences), the cascode configuration shown in figure 5a remains perfectly functional. However, preferably, the high-voltage transistors 1, 1' will be chosen so that they have a threshold voltage Vt within an interval of plus or minus 10% of their average threshold voltages.

[0069] This configuration helps make the integrated circuit 3 very versatile, that is to say it can be adapted to a very wide range of applications. In particular, a chosen number of high-voltage transistors 1, 1' of the integrated circuit 3 can be connected to a printed circuit board depending on the expected current intensity in the application. For a high current intensity, it may, for example, be chosen to connect the two drains 11, 11' of the high-voltage transistors 1, 1' to the load, so as to distribute the current in the two transistors. This leads to a very favorable thermal behavior of the integrated circuit 2, compared to an integrated circuit in which all the current flows in a single high-voltage transistor. The heating of the chips 1, 1' is in fact less and, above all, distributed over a larger surface, which doubly favors its dissipation.

[0070] The package 4 according to this aspect of the invention is advantageously provided with a plurality of drain pins 31, 31', electrically insulated from one another, each drain pin being electrically connected to a drain 11, 11' of a high voltage transistor 1, 1'. This pinout configuration makes it possible to connect the integrated circuit 3 to the rest of the components of a printed circuit, in an electrical diagram where a chosen number of high voltage chips 1, 1' can be used. This configuration also makes it possible to separately test the functionality of each of the high voltage chips 1, 1' of the integrated circuit after its manufacture, which would not be the case if a single drain pin 31 were electrically connected to the drains 11, 11' of the high voltage transistors 1, 1'.

[0071] Advantageously, the first chips 1, 1' comprise HEMT transistors made from III-N materials and the low voltage transistor 2 is a MOSFET transistor made on silicon.

[0072] The integrated circuit 3 also comprises a gate pin 33, a source pin 32 respectively connected to the gate 23 and the source 22 of the high voltage transistor 2.

[0073] Integrated circuit 3 is also fully compatible with all the features of integrated circuit 3 previously discussed in relation to the figures 2b , 3b And 4a has 4c . Although this is not shown on the figure 5a , a midpoint pin, a first and a second Kelvin pin are provided making it possible to compose outside the housing 4 a control or countermeasure circuit adapted to the particular application environment in which the circuit 3 is used. To facilitate the production of these assemblies, the Kelvin pins can be respectively placed adjacent to, or arranged on the same side of the housing as, the grid pin 33; or adjacent to, or arranged on the same side of the housing as, the midpoint pin.

[0074] It is also possible to place other components in the housing 4, such as a resistive passive component, similarly to what has been described previously.

[0075] Similarly, rather than forming the cascode circuit directly inside the package by connecting the source 22 of the low voltage transistor 2 to the gates 13, 13' of the high voltage transistors 1, 1', it may be preferable to electrically connect the gates 13, 13' to free pins of the package 4 and thus form a cascade circuit having a plurality of gate pins, making it possible to control the high voltage and low voltage transistors separately.

[0076] THE figures 5b et 5c represents a particular embodiment of the circuit shown in the figure 5a .

[0077] In a package 4, there are a plurality of first chips 1, 1' each comprising a high voltage transistor in depletion mode and a second chip 2 comprising a low voltage transistor in enhancement mode. The first chips 1, 1' and the second chip 2 respectively comprise gate contact pads 13, 13', 23, drain contact pads 11, 11', 21 and source contact pads 12, 12', 22.

[0078] On the figure 5b , the second drain contact pad 21 is placed on the rear face of the second chip 2 and brought into electrical contact with a second contact plate 311b. The first chips 1, 1' are arranged on a first contact plate 311a without the latter being connected to any contact pad of these first chips 1, 1'. The first contact plate 311a and the second contact plate 311b are electrically insulated from each other.

[0079] The first contact plate 311a can form an electrical ground of the integrated circuit. For this purpose, the second source contact pad 22 of the second chip 2 can be electrically connected to the contact plate 311a.

[0080] In the case of circuit 3 shown on the figure 5b , the pins consist of a simple contact surface for “surface” mounting of the integrated circuit 3 (“Surface Mount Package” according to the English terminology used). These contact surfaces forming the pins can be arranged on the rear face of the package 4, along the sides of this face or on its central part. It would of course be possible to consider using another pinning technology.

[0081] The gate contact pads 13, 13' of the first chips 1, 1' are connected to the source contact pad 22 of the second chip 2 to form a cascode circuit. The source contact pad 22 is itself connected to the source pin 32, the gate pin 33 is connected to the second gate contact pad 23 of the second chip 2.

[0082] The second contact plate 311b is electrically connected to the source contact pads 12, 12' of the first chips 1, 1' and the drain contact pads 11, 11' of the first chips 1, 1' electrically connected to the drain pins 31, 31' of the circuit 3.

[0083] The electrical connections and links inside the housing 4 may be formed by wire connections. The housing 4 may be provided on its rear face with an opening allowing the first and second contact plates 311a, 311b to be exposed in order to constitute additional pins in the form of central contact surfaces, as mentioned previously.

[0084] We have thus represented on the figure 5c a view of the rear face of the integrated circuit 3. In this view, the gate pin 33, source pin 32, and drain pins 31, 31' of the circuit 3 are observed on the sides of the rear face of the package 4. Central openings formed on this package 4 expose the contact plates 311a, 311b then respectively forming ground pins, and midpoint pins 35 of the integrated circuit 3.

[0085] The unused pins of circuit 3 can be used, for example, to form the kelvin connection pins, or to transfer the gate pads 13, 13' of the high-voltage chips 1, 1' in the case where it is preferred to configure circuit 3 in a cascade circuit.

[0086] The invention therefore proposes an integrated circuit 3 which can have a power switching function and which can have a midpoint pin 35 giving access to a midpoint node of the circuit. It is provided with Kelvin pins 36, 36' and comprises a plurality of first high-voltage chips, which makes it possible to manage its heating as well as possible. This integrated circuit 3 has the advantage of being very versatile, that is to say that it can be combined with other circuits (control or countermeasure) for a wide range of applications, the combination of these characteristics making it possible to configure these additional circuits to the particularities (frequency, amplitude of the signals, transient phases, current intensity, etc.) of the application.

Claims

1. Integrated circuit (3) comprising a package (4) and a plurality of connection pins, a first chip (1) comprising a high voltage transistor in depletion mode, and comprising a second chip (2) comprising a low-voltage transistor in enhancement mode, the first and the second chip respectively comprising gate (13, 23), drain (11, 21) and source (12, 22) contact pads ; the source contact pad (12) of the high-voltage transistor being electrically coupled to the drain contact pad (21) of the low-voltage transistor to thus form a middle node of the circuit, the integrated circuit comprising a first kelvin pin (36) electrically coupled to the source contact pad (22) of the low voltage transistor, the integrated circuit comprising a middle point pin (35) electrically coupled to the middle node of the circuit, the integrated circuit further including a drain pin (31) electrically coupled to a drain contact pad (11) of the high-voltage transistor, a source pin (32) electrically coupled to the source contact pad (22) of the low voltage transistor, a gate pin (33) electrically coupled to the gate contact pad (23) of the low voltage transistor, the integrated circuit being characterised in that it further comprises a second kelvin pin (36') electrically coupled to the source contact pad (22) of the low voltage transistor.

2. Integrated circuit according to claim 1, wherein the first kelvin pin (36) is adjacent to the gate pin (33), or arranged on the same side of the package as the gate pin (33), and the second kelvin pin (36') is adjacent to the middle point pin (35), or arranged on the same side of the package (4) as the middle point pin (35).

3. Integrated circuit (3) according to claim 1 or 2, wherein the middle point pin (35) is adjacent to the source pin (32).

4. Integrated circuit (3) according to one of the preceding claims, comprising a second gate pin (37) electrically coupled to the gate contact pad (13) of the high voltage transistor.

5. Integrated circuit (3) according to the preceding claim, wherein the second gate pin (37) is adjacent to the middle point pin (35).

6. Integrated circuit (3) according to one of claims 1, 2, and 3, wherein the source contact pad (22) of the low voltage transistor is electrically coupled to the gate contact pad (13) of the high voltage transistor.

7. Integrated circuit (3) according to one of the preceding claims, wherein electrical coupling consists of wire connections (5).

8. Integrated circuit (3) according to one of the preceding claims, comprising a resistive passive component (9) arranged in the package (4) and electrically coupled between the gate contact pad (23) of the second chip (2) and the source contact pad (22) of the second chip (2).

9. Integrated circuit (3) according to the preceding claim, wherein the resistive passive component (9) is formed within a third chip (90) electrically coupled to the second chip (2) via wire connection (5).

10. Integrated circuit (3) according to claim 9, wherein the resistive passive component (9) is formed within the second chip (2) or the first chip (1).

11. Integrated circuit (3) according to claim 9 or 10, wherein the resistive passive component (9) has a resistance of between 100 kilo-ohms and 1 mega-ohm.

12. Integrated circuit (3) according to one of the preceding claims, wherein the first chip includes a plurality of chips (1, 1') each comprising a high voltage transistor in depletion mode, and parallelly connected to each other.

13. Integrated circuit (3) according to the preceding claim, comprising a plurality of drain pin (31, 31') each drain pin being electrically coupled to a drain contact pad (11, 11') of a chip (1, 1') of the first chip.