ELECTRONIC DEVICE CONTAINING TWO MEMORIES AND CORRESPONDING PAIRING METHOD

Abstract

The invention relates to an electronic device (10A, 10B) intended to interact with at least one other electronic device (10A, 10B), the electronic device (10A, 10B) comprising a processor (12A, 12B), a first memory (16A, 16B) and a second memory (18A, 18B) distinct from the first memory (16A, 16B), the first memory (16A, 16B) being a wired memory and the second memory (18A, 18B) being a dual-port access memory, the first port (20A, 20B) being a wired port and the second port (22A, 22B) being a port allowing access to the second memory (18A, 18B) by wireless communication.

Description

[0001] The present invention relates to an electronic device. The present invention also relates to a method for pairing such an electronic device.

[0002] The present invention relates to the field of pairing electronic devices, an electronic device being an electrically powered device comprising electronic components such as transistors.

[0003] Electronic device pairing refers to devices designed to interact with at least one other electronic device. This is particularly relevant for a device called "FreePlug" by the applicant. A FreePlug is a device that uses power line communication (PLC) technology to enable data communication with another FreePlug over the electrical network. This allows a customer to receive telephone, television, or other services in multiple locations without using Ethernet cables, thus simplifying service installation in some homes.

[0004] Freeplugs act as a gateway between an Ethernet network and a powerline network. Since most devices connected via Freeplugs are Ethernet-based, at least one pair of Freeplugs is typically provided, allowing two Ethernet networks to be connected through two gateways. This pair of Freeplugs must be configured to function correctly using a pairing mechanism. While the user can perform this configuration, to simplify Freeplug use, it is often configured at the factory.

[0005] To achieve this, it is known that Freeplugs are mass-produced without any particular differentiation, so that the selection of two Freeplugs is done randomly, with pairing occurring later. To minimize handling marks on the Freeplugs, they are stored in protective packaging.

[0006] Pairing is achieved by sharing a common secret between the two Freeplugs. This shared secret will then allow the Freeplugs to communicate and function at the customer's premises. However, sharing the common secret requires physical, wired access to the Freeplugs, which necessitates breaking their protective packaging. Since handling the Freeplugs is delicate, some may be damaged during this process. Furthermore, such an operation adds a significant amount of pairing time.

[0007] There is therefore a need for an electronic device, in particular a Freeplug, that allows pairing with another electronic device in a way that is easier to implement.

[0008] For this purpose, the present description relates in particular to an electronic device intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory distinct from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port allowing access to the second memory by wireless communication.

[0009] In particular embodiments, the electronic device comprises one or more of the following features, taken individually or in any technically possible combination: The second port is designed to operate according to a near-field communication protocol. A private key and a public key together form an asymmetric key pair, with the first memory storing a private key and the second memory storing a public key. The electronic device is designed to be powered by a power supply. The electronic device is intended to be paired with another electronic device, preferably of the same type. The electronic device is chosen from the following group: an electronic device serving as an interface between a user's computer and / or audiovisual equipment and an Internet access network, a device using power line communication technology, a remote control, and a home automation node.

[0010] This description also relates to an electronic device set comprising at least two electronic devices, each electronic device (being intended to interact with at least one other electronic device), the electronic device comprising a processor, a first memory and a second memory separate from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port allowing access to the second memory by wireless communication.

[0011] This description also describes a method for pairing two electronic devices, each electronic device being intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory separate from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port for accessing the second memory by wireless communication, the method comprising at least the step of: for each electronic device, generation of an asymmetric key pair, the key pair comprising a private key and a public key, for each electronic device, storage of the private key in the first memory and of the public key and the device identifier in the second memory, reading of the public keys, generation of a secret, writing of the secret encoded by the public key and the respective identifiers on each second memory of the electronic device.

[0012] This description also relates to a method for pairing electronic devices, each electronic device being intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory distinct from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port allowing access to the second memory by wireless communication, the method comprising at least the step of generating a token common to the two electronic devices, for each electronic device, a step of storing in the second memory the token and an identifier specific to the electronic device with which the electronic device is intended to interact,a step of establishing a secure channel between the two electronic devices and a step of sharing a security key between the two electronic devices.

[0013] This description also describes a method for pairing two electronic devices, each electronic device being intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory separate from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port allowing access to the second memory by wireless communication, the method comprising at least the step of, for each electronic device, generating an asymmetric key pair, the key pair comprising a private key and a public key, for each electronic device, a step of storing the private key in the first memory, for each electronic device,a step involving the memorization of an identifier specific to the electronic device with which the electronic device is intended to interact, and of the two public keys in the second memory, and a step of verifying that the two public keys in each second memory are identical.

[0014] This description also relates to a method for pairing electronic devices, each electronic device being intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory distinct from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port allowing access to the second memory by wireless communication, the method comprising at least the step of: for each electronic device, generation, by the processor and the first memory, of a pair of asymmetric keys, the key pair comprising a private key and a public key, storage, by each electronic device, of the private key in the first memory and of the public key and the identifier of the device in the second memory, reading of the public keys by an association bank, generation of a secret by the association bank, writing by the association bank of the secret encoded by the public key and the respective identifiers on each second memory of the electronic device.

[0015] This description also describes a method for pairing electronic devices, each electronic device being intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory separate from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port for accessing the second memory by wireless communication, the method comprising at least the step of: generation, by an association bench, of a token common to the two electronic devices, storage, by each electronic device, in the second memory of the token and an identifier specific to the electronic device with which the electronic device is intended to interact, establishment of a secure channel between the two electronic devices by an establishment means, and sharing, by the electronic device, of a security key between the two electronic devices.

[0016] This description also relates to a method for pairing electronic devices, each electronic device being intended to interact with at least one other electronic device, the electronic device comprising a processor, a first memory and a second memory distinct from the first memory, the first memory being a wired memory and the second memory being a dual-port access memory, the first port being a wired port and the second port being a port allowing access to the second memory by wireless communication, the method comprising at least the step of: For each electronic device, generation, by the processor and the first memory, of a pair of asymmetric keys, the key pair comprising a private key and a public key, storage, by each electronic device, of the private key in the first memory, storage, by each electronic device, of an identifier specific to the electronic device with which the electronic device is intended to interact and of the two public keys in the second memory, and verification, by the electronic device, that the two public keys in each second memory are identical.

[0017] Other features and advantages of the invention will become apparent from the following description of embodiments of the invention, given by way of example only and with reference to the drawings which are: figure 1 a schematic representation of an electronic device, figure 2 , a flowchart of an example of the implementation of a matching process comprising a first, a second and a third phase, figure 3 , a schematic view of one of the two electronic devices during the first phase, figure 4 , a schematic representation of the two electronic devices during the second phase, and. figure 5 , a schematic view of one of the two electronic devices during the third phase.

[0018] An electronic device 10 is shown on the figure 1 .

[0019] For the remainder, it is assumed that electronic device 10 is a device using power line carrier technology.

[0020] Several names are used for such an electronic device. In particular, the term "enclosure" or the English terms "homeplug" or "plug" are found in the literature. In the following description, the term "plug" is used to refer to the electronic device.

[0021] Plug 10 includes a processor 12, a versatile memory 14 and two persistent memories 16 and 18.

[0022] The processor 12 is often referred to by the acronym CPU (for the English term "central processing unit").

[0023] Processor 12 is designed to perform operations and interact with other memories 14, 16 and 18.

[0024] Volatile memory 14 is, for example, random access memory or direct access memory (more commonly referred to by the English term "RAM" for "Random Access Memory").

[0025] Each persistent memory 16 and 18 is specific to storing data.

[0026] The first persistent memory 16 is a hardwired memory.

[0027] Wired memory refers to memory that requires power via a cable to read or write data to it. For example, the first persistent memory was a flash memory i2< C.

[0028] By definition, the term "I2<C" refers to a bidirectional half-duplex synchronous serial bus.

[0029] In the rest of the description, the first persistent memory 16 is denoted hardwired memory 16.

[0030] The second persistent memory 18 is a separate memory from the hardwired memory 18.

[0031] The second memory 18 is a dual-port access memory.

[0032] The first port 20 is a cabled port.

[0033] Typically, the first port is an i2C port.

[0034] The second port 22 is a port allowing access to the second memory 18 via wireless communication.

[0035] RFID technology or WIFI are examples of wireless communication protocols.

[0036] According to the example described, the second memory 18 is suitable for communicating according to a near field communication protocol.

[0037] Near Field Communication (NFC) is a short-range, high-frequency wireless communication technology that enables the exchange of information between devices up to a distance of approximately 10 cm in general. This technology is an extension of the ISO / IEC 14443 standard for proximity cards using radio-frequency identification (RFID), which combine a smart card and a reader in a single device.

[0038] The second port 22 is therefore an NFC port.

[0039] The second port 22 also allows access to the second memory 18 without powering plug 10 or processor 12. Power to the second memory 18 is supplied by the magnetic field of the second port 22. In this example, the near field serves to carry both power and data.

[0040] In the following, the second memory 18 is referred to as dual port memory 18.

[0041] As is known in itself, plug 10 includes other elements such as an Ethernet port 24, an adapter 26 for PLC network and a power supply 28 which are not detailed further below.

[0042] In the example shown, plug 10 is intended to be paired with an electronic device.

[0043] In the case described, the electronic device is a device of the same type, so the two plugs 10 are matched.

[0044] To distinguish the 10 plugs to be paired in the sequence, each plug or each element of a plug is qualified as first or second and the corresponding reference signs are followed by a letter.

[0045] Thus, in the following, the first 10A plug contains the first 12A processor, the first 14A versatile memory, the first 16A wired memory, the first 18A dual-port memory, the first 24A Ethernet port, the first 26A adapter, and the first 28A power supply, while the second 10B plug contains the second 12B processor, the second 14B versatile memory, the second 16B wired memory, the second 18B dual-port memory, the second 24B Ethernet port, the second 24B adapter, and the second 28B power supply.

[0046] The pairing of the two plugs 10A and 10B is now described with reference to an example of the implementation of a pairing process, using the flowchart of the figure 2 .

[0047] The pairing process includes a first generation step 30, a memorization step 32, a reading step 34, a second generation step 36 and a writing step 38.

[0048] The pairing process is implemented at several distinct locations corresponding to a different phase.

[0049] The first phase, P1, is the unit manufacturing phase for each plug. This first phase, P1, is implemented by the plug manufacturer.

[0050] In the figure 3 The illustration shows the manufacturing process of the first 10A plug.

[0051] The first 10A plug is initially powered by the R network.

[0052] The first step of generation 30 is then implemented.

[0053] During the first generation step 30, for the first plug 10A, a first pair of asymmetric keys is generated, consisting of a first private key K private A and a first public key K public A.

[0054] For example, the first generation step 30 is implemented by implementing an initialization sequence.

[0055] The initialization sequence is stored on the first hardwired memory 16A and triggered by the first processor 12A.

[0056] The memorization step 32 is then implemented.

[0057] During the memorization step 32, the first processor 12A of the first plug 10A makes the first wired memory 16A memorize the first private key K private A and makes the first dual port memory 18A memorize the first public key K public A as well as the identifier IdA of the first plug 10A.

[0058] The first 10A plug is then packed in an initial 40A package.

[0059] The first phase P1 is similarly implemented for the second plug 10B.

[0060] Thus, the second wired memory 16B stores a second private key K private B and the second dual port memory 18B stores a second public key K public B with the identifier IdB.

[0061] The second private key K private B and the second public key K public B together form a second pair of asymmetric keys.

[0062] The first 10A plug is then packed in a second 40B package.

[0063] The second association phase, P2, is then implemented. This second association phase, P2, is implemented at the factory.

[0064] In the figure 4 , a 42 association bench is shown to which are supplied the packages 40A and 40B, each comprising respectively the first 10A plug and the second 10B plug.

[0065] This provision is implemented by an arbitrary choice of plugs from a set of plugs.

[0066] During the second phase, it is not possible to access the wired memory 16A and 16B of each plug 10A, 10B due to the presence of each package 40A and 40B except by destroying the package 40A and 40B in question.

[0067] The association bench 42 includes a processor 44, a volatile memory 46 and a PCD device 48.

[0068] The PCD 48 (Proximity Coupling Device) is designed to power PICC (Proximity Integrated Circuit Card) devices within a limited area known as the operating range. The PCD 48 is a device with its own power source that generates the magnetic field. It is generally considered the "master" device from a protocol perspective, while the PICC device is passively powered by the PCD during communication, and is generally considered the "slave" device from a protocol perspective. The power supplied by the PCD to the PICC device is approximately 10 mW, which allows the operation of a dual-port 18A or 18B memory chip, but not a 12A or 12B processor or a 10A or 10B plug. The operation of dual-port 18A and 18B memories is therefore passive NFC operation.

[0069] The two plugs 10A and 10B are positioned within the range of the association bench 42 to power the first dual port memory 18A and the second dual port memory 18B.

[0070] To illustrate that the shape of the scope of action of association bench 42 can be arbitrary, the scope of action of association bench 42 is represented on the figure 4 in the form of a Z-shaped area delimited by dotted lines, which is not symmetrical. In fact, the Z-shaped area includes part of the first plug 10A and all the elements of the second plug 10B. The only condition to be met for the scope of association bench 42 is to include at least the first dual-port memory 18A and the second dual-port memory 18B.

[0071] Only the first dual-port 18A memory and the second dual-port 18B memory are powered, the other memories 14A, 14B, 16A and 16B being wired access only memories.

[0072] Reading step 34 is then implemented.

[0073] During the read stage, the association bench 42 reads the contents of the dual port memories 18A and 18B, namely the first public key K public A and the second public key K public B, as well as the identifier IdA and IdB of each plug 10A and 10B.

[0074] It should be noted that reading step 34 does not involve removing the 40A and 40B packaging from the first and second 10A and 10B plugs.

[0075] Furthermore, association bench 42 does not have access to the contents of wired memories 16A and 16B.

[0076] The second generation stage 36 is then implemented.

[0077] During the second generation step 36, the association bench 42 generates a secret S.

[0078] The secret S is specific to the pair of first and second plugs 10A and 10B.

[0079] The secret S is therefore a secret shared between the pair of first and second plugs 10A and 10B.

[0080] Association bench 42 then encodes the secret S using the public key read during read step 34.

[0081] More specifically, for the first plug 10A, the association bench 42 uses the first public key K public A to encode the secret S, which allows obtaining a first coded secret SA.

[0082] Similarly, for the second plug 10B, the association bench 42 uses the second public key K public B to encode the secret S, resulting in a second coded secret SB.

[0083] A writing step 40 is then implemented.

[0084] During the write step 40, the association bank 42 writes each coded secret SA and SB onto the dual port memories 18A and 18B. During the write step, the first identifier IdA is also written onto the dual port memory 18B of the second plug 10B and, correspondingly, the second identifier IdB onto the dual port memory 18A of the first plug 10A.

[0085] At the end of the write step 40, the first dual port memory 18A and the second dual port memory 18B respectively store the first coded secret SA and the second coded secret SB, and the identifiers IdA, IdB of their associated plug 10A, 10B.

[0086] Since the coded secrets SA and SB originate from the same shared secret S, the two plugs 10A and 10B have a privileged link.

[0087] The two plugs 10A and 10B are then placed in a common package, for example a cardboard box, and then delivered to the user.

[0088] Alternatively, to avoid errors, plugs 10A and 10B are placed in the same box before even being tested on the matching bench. This ensures that the pair of plugs 10A and 10B is indeed packaged in the same box for which the matching process was carried out.

[0089] The actual pairing of the two plugs 10A and 10B takes place at the user's premises during the third phase P3, as schematically illustrated on the figure 5 .

[0090] On the figure 5 , part of the user's information installation 50 is represented, the part comprising two interfaces 52, 54 to a communication network 51. The communication network 51 is usually a global network such as the internet.

[0091] Each interface 52 and 54 is an electronic device serving as an interface between a user's computer and / or audiovisual equipment 55 and the network.

[0092] Interfaces 52 and 54 are sometimes referred to by the English term "box".

[0093] More specifically, the first interface 52 is a first box called gateway serving as an interface with the communication network 51 while the second interface 54 is a second box called STB serving as an interface with an audiovisual equipment 55.

[0094] Each 10A and 10B plug is connected on one side to the house's electrical network R and on the other side to an interface 52 and 54.

[0095] In the example described, the first plug 10A is connected to the first interface 52 and the second plug 10B is connected to the second interface 54.

[0096] Once powered by the R network, each plug 10A and 10B reads the wired memory 16A and 16B to obtain the private key K private A and K private B.

[0097] Each plug 10A and 10B also reads the dual port memory 18A and 18B via the wired port 20A and 20B to obtain the coded SA and SB secret, as well as the IdB and IdA identifiers.

[0098] Each plug 10A and 10B uses the private key K private A and K private B to decode the coded secret SA and SB and deduce the shared secret S.

[0099] Plugs 10A and 10B then use the shared secret S to initiate a data exchange session across network R, with the first plug 10A searching for the device identified by the second IdB identifier on network R, and the second plug 10B searching for the device identified by the first IdA identifier on the network.

[0100] Plugs 10A and 10B are then paired. The two plugs 10A and 10B then form a set of electronic devices 10A and 10B.

[0101] The pairing process is simple for the user, as it is sufficient to power the 10A and 10B plugs for pairing to take place between the two 10A and 10B plugs.

[0102] For the manufacturer of 10A and 10B plugs, the implementation of the pairing process allows operation even with packaged 10A and 10B plugs without physical connection.

[0103] The possibility of implementing the pairing process even with packaged 10A and 10B plugs allows the 10A and 10B plugs to be protected permanently while allowing the plugs to be paired at the last moment.

[0104] It should be noted that the process is also applicable to re-pairing 10A and 10B plugs that have already been paired, for example, if a user returns 10A and 10B plugs, these can be re-paired for another user.

[0105] In particular, it should be noted that the pairs of plugs 10 can be broken to create new pairs of plugs. This is especially useful if one of the plugs 10 in the old pair is no longer functional.

[0106] In addition, the security of plugs 10A and 10B is ensured by the fact that the shared secret S is only accessible by having access to the wired memory 16A and 16B, which a third party can only obtain by destroying the cardboard and plastic packaging.

[0107] Furthermore, the method is applicable to any type of electronic device 10 intended to interact with at least one other electronic device 10, provided that the electronic device 10 includes a processor 12, a hardwired memory 16 and a dual-port memory 18, the hardwired memory 16 being separate from the dual-port memory 18.

[0108] According to another example, electronic device 10 is an electronic device serving as an interface between a user's computer and / or audiovisual equipment and an Internet access network, i.e. that the electronic device is an interface 52 or 54.

[0109] Alternatively, electronic device 10 is a remote control.

[0110] According to another variant, electronic device 10 is a home automation node. A radio sensor, a controlled socket, or a radio switch are specific examples of home automation nodes.

[0111] Furthermore, it should be noted that the process works for all types of asymmetric key encryption, allowing the security of the process to be adapted to the desired application. A more advanced encryption method is chosen if it is necessary to further increase the security of the pairing process.

[0112] Other methods of implementing the pairing process are also conceivable.

[0113] According to a particular embodiment, it is thus possible to perform the pairing without writing by the association bank 42 of each coded secret SA and SB in the appropriate memories.

[0114] Instead, the association bank 42 writes the same token to the dual-port memories 18A and 18B. The token is a message long enough to have a negligible collision probability. Typically, a 256-bit message satisfies the previous condition.

[0115] In addition, for each plug 10A and 10B, the association bank 42 writes the identifier IdA, IdB of the plug 10A and 10B to be paired with the plug 10A and 10B under consideration in the dual port memory 18A and 18B of the plug 10A and 10B under consideration.

[0116] The pairing between the two plugs 10A and 10B is then done by constructing a secure channel between the two plugs 10A and 10B. The construction is implemented cryptographically, for example, using a Diffie-Hellman algorithm which allows the generation of ephemeral keys.

[0117] To verify that no third party has interfered, the common token injected by the key matching system is used to validate each of the ephemeral keys of the Diffie-Hellman algorithm. Typically, the token is used in conjunction with the key generated by the Diffie-Hellman algorithm in a signature, which is only validated by the paired 10A and 10B plugs if the communication is not subject to a man-in-the-middle (MITM) attack. After this verification, the channel is considered secure.

[0118] When the channel is considered secure, the two plugs 10A and 10B exchange a shared key.

[0119] The shared key is kept in the long term.

[0120] At the cost of vulnerability to a MITM attack, such an implementation avoids the creation of an asymmetric key pair by plug 10A and 10B.

[0121] According to another particular embodiment, it is thus possible to carry out the pairing without writing by the association bank 42 of each coded secret S1 and S2 in the adapted memories.

[0122] Instead, the association bench 42 also writes the public key of plug 10A and 10B to be paired, as well as the identifier of plug 10A and 10B, to each dual port memory 18A and 18B. To do this, the association bench 42 can read the public key of plug 10A and 10B to be paired.

[0123] During pairing at the user's site, a secure key exchange is performed between the two plugs 10A and 10B by verifying the equality of the public keys on each of the dual-port memories. The RSA algorithm enables this verification.

[0124] In these different embodiments, the association bench systematically provides each plug 10A and 10B with the IdA and IdB identifiers of its peer 10A and 10B.

[0125] All the embodiments described above can be combined where technically possible to obtain new embodiments.

Claims

1. Electronic device (10A, 10B) intended to interact with at least one other electronic device (10A, 10B), the electronic device (10A, 10B) comprising a processor (12A, 12B), a first memory (16A, 16B) and a second memory (18A, 18B) separate from the first memory (16A, 16B), the first memory (16A, 16B) being a wired memory and the second memory (18A, 18B) being a dual-port access memory, the first port (20A, 20B) being a wired port and the second port (22A, 22B) being a port allowing access to the second memory (18A, 18B) by wireless communication.

2. Electronic device according to claim 1, in which the second port (22A, 22B) is suitable for operating according to a near field communication protocol.

3. Electronic device according to claim 1 or 2, wherein a set of a private key (K privée A K privée B ) and a public key (K pubiique A K publique B) forms an asymmetric key pair, the first memory (16A, 16B) storing a private key (K privée A K privée B ) and the second memory (18A, 18B) storing a public key (K publique A K publique B ).

4. Electronic device according to any one of claims 1 to 3, wherein the electronic device (10A, 10B) is suitable for being powered by a power supply.

5. Electronic device according to any one of claims 1 to 4, wherein the electronic device (10A, 10B) is intended to be paired with an electronic device (10A, 10B), the two electronic devices (10A, 10B) preferably being of the same nature.

6. Electronic device according to any one of claims 1 to 5, wherein the electronic device (10A, 10B) is selected from the group consisting of: • an electronic device serving as an interface between a user's computer and / or audiovisual equipment and an Internet access network, • a device using power line carrier technology, • a remote control, and • a home automation node.

7. Set of electronic devices (10A, 10B) comprising at least two electronic devices (10A, 10B), each electronic device (10A, 10B) being intended to interact with at least one other electronic device (10A, 10B), the electronic device (10A, 10B) comprising a processor (12A, 12B), a first memory (16A, 16B) and a second memory (18A, 18B) separate from the first memory (16A, 16B), the first memory (16A, 16B) being a wired memory and the second memory (18A, 18B) being a dual-port access memory, the first port (20A, 20B) being a wired port and the second port (22A, 22B) being a port allowing access to the second memory (18A, 18B) by wireless communication.

8. A method for pairing electronic devices (10A, 10B), each electronic device (10A, 10B) being intended to interact with at least one other electronic device (10A, 10B), the electronic device (10A, 10B) comprising a processor (12A, 12B), a first memory (16A, 16B) and a second memory (18A, 18B) separate from the first memory (16A, 16B), the first memory (16A, 16B) being a wired memory and the second memory (18A, 18B) being a dual-port access memory, the first port (20A, 20B) being a wired port and the second port (22A, 22B) being a port allowing access to the second memory (18A, 18B) by wireless communication, the method comprising at least the step of: - for each electronic device (10A, 10B), generation of an asymmetric key pair, the key pair including a private key (K privée A K privée B ) and a public key (K publique A K publique B), - for each electronic device (10A, 10B), storage of the private key (K privée A K privée B ) in the first memory (16A, 16B) and the public key (K publique A K publique B ) and the device identifier (IdA, IdB) (10A, 10B) in the second memory (18A, 18B), - reading the public keys (K publique A K publique B ), - generation of a secret (S), - writing the coded secret (SA, SB) using the public key (K publique A K publique B ) and respective identifiers (IdB, IdA) on each second memory (18A, 18B) of the electronic device (10A, 10B).

9. Method for pairing electronic devices (10A, 10B), each electronic device (10A, 10B) being intended to interact with at least one other electronic device (10A, 10B), the electronic device (10A, 10B) comprising a processor (12A, 12B), a first memory (16A, 16B) and a second memory (18A, 18B) distinct from the first memory (16A, 16B), the first memory (16A, 16B) being a wired memory and the second memory (18A, 18B) being a dual-port access memory, the first port (20A, 20B) being a wired port and the second port (22A, 22B) being a port allowing access to the second memory (18A, 18B) by wireless communication, the method comprising at least the step of: - generating a token common to both electronic devices (10A, 10B), - for each electronic device (10A, 10B), storage in the second memory (18A, 18B) of the token and an identifier (IdB, IdA) specific to the electronic device (10A,10B) with which the electronic device (10A, 10B) is intended to interact, - establishment of a secure channel between the two electronic devices (10A, 10B), and - sharing of a security key between the two electronic devices (10A, 10B).

10. Method for pairing electronic devices (10A, 10B), each electronic device (10A, 10B) being intended to interact with at least one other electronic device (10A, 10B), the electronic device (10A, 10B) comprising a processor (12A, 12B), a first memory (16A, 16B) and a second memory (18A, 18B) separate from the first memory (16A, 16B), the first memory (16A, 16B) being a wired memory and the second memory (18A, 18B) being a dual-port access memory, the first port (20A, 20B) being a wired port and the second port (22A, 22B) being a port allowing access to the second memory (18A, 18B) by wireless communication, the method comprising at least the step of: - for each electronic device (10A, 10B), generation of an asymmetric key pair, the key pair including a private key (K privée A K privée B) and a public key, - for each electronic device (10A, 10B), storage of the private key (10A, 10B) in the first memory (16A, 16B), - for each electronic device (10A, 10B), storage of an identifier (IdB, IdA) specific to the electronic device (10A, 10B) with which the electronic device (10A, 10B) is intended to interact and of the two public keys (K publique A K publique B ) in the second memory (18A, 18B), and - verification that the two public keys (K publique A K publique B ) in each second memory (18A, 18B) are identical.