ELECTRONIC CIRCUIT BOARD WITH SMDS SOLDERED ON BURIED SOLDER PADS

Description

FIELD OF INVENTION

[0001] The invention relates to the field of electronic boards, particularly in the field of aeronautics and space, and more specifically the fixing of surface-mounted components on printed circuits. TECHNOLOGICAL BACKGROUND

[0002] As is known in itself, an electronic board can include surface-mount components (SMD), that is, electronic components soldered directly to the surface of the printed circuit board of an electronic board.

[0003] Usually, CMS are surface soldered either by reflow soldering or by wave soldering.

[0004] In reflow soldering, the bare printed circuit board is first screen-printed by covering the conductive layers (usually copper) with solder paste using a screen printing stencil. This ensures that only the areas intended to receive the component leads are covered. The solder paste consists of a metal alloy suspended in a solder flux. The component leads (SMDs) are then placed on the solder paste before undergoing a reflow heat treatment. During this process, the heat remelts the alloy and evaporates the solder flux, forming solder joints from the metal alloy in the solder paste.

[0005] The reliability and lifespan of the solder joints that secure surface-mount components (SMDs) to the printed circuit board depend on the vertical height (usually referred to as "standoff") between the top surface of the copper solder pad and the lowest point of the SMD's conductive leads after soldering. The standoff therefore corresponds to the height of the solder alloy at the interface between the SMD and the copper layer. In use, the SMD and the surface to which it is soldered expand and contract differently, causing relative displacements, particularly in the plane of the surface (X, Y). Thus, the greater the standoff, the more flexible and therefore more robust the solder joint.

[0006] However, the increase in standoff is limited by the usual assembly methods available in production and by the diversity of geometries of component packages to be surface soldered.

[0007] It has therefore been proposed to increase the amount of solder paste applied to the printed circuit board layers. To achieve this, the size (width) of the holes in the silkscreen can be increased, for example, so that during the reflow step, the height of the solder joint is increased by coalescence: the thickness of the solder joint is greater than the equivalent thickness of alloy obtained after reflow with smaller holes in the silkscreen, since the metal alloy cannot spread beyond the printed circuit board layers due to wettability in its liquid phase (liquidus) during reflow. This method does indeed increase the standoff. However, this remains limited by the volume of solder paste that can be introduced into the holes of the screen due to demolding issues and the limit of solder paste coalescence without generating microbeads.

[0008] Furthermore, all components on the same circuit board are subject to common process parameters, including the stencil thickness and the printed circuit board itself. Indeed, the thickness of solder paste applied to the printed circuit board for soldering multiple surface-mount components (SMDs) is essentially the same for each SMD, since it is applied using a silkscreen. Moreover, silkscreening the solder paste application limits the component placement density on the printed circuit board and / or the types of components that can be used, particularly in the case of fine-pitch or large components.More specifically, the size of the screen printing window is limited by the following condition to ensure the screen can be removed from the mold without damaging the applied solder paste: the ratio between the window area (in the plane of the screen, which is parallel to the (X, Y) plane) and the area of ​​the internal walls of the window (which extend perpendicularly to the plane of the screen) must be greater than or equal to 0.66. To maintain this ratio, when the component has a fine pitch, it is therefore necessary to reduce the screen thickness, which necessarily implies decreasing the amount of solder paste applied to the connecting face and / or increasing the window area. Conversely, when the component is large or includes "gull-foot," J-shaped, or C-shaped terminations, it is necessary to increase the amount of solder paste in the opening and therefore to use a stencil with a greater thickness.The implantation of both fine-pitch and large-volume SMT therefore requires both a thin stencil and a thick stencil.

[0009] While screens with variable thicknesses exist to locally increase the height of the screen holes, and therefore the amount of solder paste deposited, these variable thicknesses often lead to screen printing problems for adjacent surface-mount components (SMDs) (insufficient solder paste height in adjacent holes) and make it difficult to optimize SMD placement on the printed circuit board. Furthermore, the minimum and maximum screen thicknesses that can be considered, while ensuring sufficient hole filling, remain inadequate to guarantee both a long lifespan for large components and the ability to solder fine-pitch components onto the printed circuit board.

[0010] US document 2014 / 158414 describes a method and device comprising a multilayer substrate having electronic components placed inward from the substrate. SUMMARY OF THE INVENTION

[0011] One objective of the invention is therefore to propose a new method of fixing surface-mounted components on a printed circuit board which makes it possible to increase the density of the components, to increase their lifespan, to increase the mix of electronic components by making it possible to assemble without constraint, various components, whether they are fine pitch components, large sizes, with gull-wing leads, etc., this new method being also simple to carry out and of moderate cost regardless of the density of implantation of the components on the printed circuit board and / or the type of component, without impacting the assembly yield of the electronic board.

[0012] To this end, the invention proposes a method for manufacturing an electronic card according to claim 1 and an electronic card according to claim 14. Embodiments are further defined in the dependent claims.

[0013] The manufacturing process includes the following steps: form a first cavity in the first conductive skin layer and in the first insulating layer, opposite the soldering area of ​​the first internal conductive layer, so that at least part of the soldering area is exposed, fill the first cavity with a metal alloy accompanied by a soldering flux, place a first electronic component opposite the first cavity, apply a heat treatment to the printed circuit on which the first component is placed in order to transform the metal alloy accompanied by the soldering flux into a solder joint so as to fix the first component to the printed circuit.

[0014] Some preferred but not limiting characteristics of the manufacturing process described above are as follows, taken individually or in combination: The first cavity is formed using at least one of the following techniques: surface photolithography, laser drilling, mechanical drilling, or mechanical cutting. The process further includes a metallization step of the first cavity to deposit a metallic layer within it. The process also includes an additional step in which a portion of the metallic layer of the first cavity is removed prior to the filling step. This partial removal of the metallic layer is carried out by laser, mechanical cutting, or mechanical drilling.The first internal conductive layer includes an additional solder area, and the manufacturing process further includes the following additional steps prior to the heat treatment step: forming a second cavity in the first insulating layer opposite the additional solder area, so that at least an additional portion of the additional solder area is exposed; filling the second cavity with the metal alloy along with a solder flux; and placing a second electronic component opposite the second cavity, the steps of filling the first and second cavities and placing the components being carried out substantially simultaneously. The process further includes a step of etching the first conductive skin layer.the first cavity is filled in accordance with at least one of the following filling techniques: screen printing with screen printing, screen printing without screen printing, inkjet printing, passing through a turbulent wave, by dipping or passing through a bath of remelted metal alloy, wave soldering, hand soldering.the second internal conductive layer is treated so as to form at least one solder pad, the manufacturing process further comprising the following steps, prior to the heat treatment step: forming a third cavity in the first insulating layer and in the third insulating layer, opposite the solder pad of the second internal conductive layer, so that at least part of the solder pad of the second internal conductive layer is exposed; filling the third cavity with the metal alloy accompanied by a soldering flux; and placing a third additional electronic component opposite the third cavity.The second internal conductive layer is treated to form at least one solder pad. The manufacturing process further comprises the following steps, prior to the heat treatment step: forming a fourth cavity in the second conductive skin layer and in the second insulating layer, opposite the solder pad of the second internal conductive layer, so that at least a portion of the solder pad of the second internal conductive layer is exposed; filling the fourth cavity with the metal alloy along with a solder flux; and placing a fourth electronic component opposite the fourth cavity. The process further comprises, prior to the heat treatment step, a step in which an additional layer comprising an electrically insulating material is applied to the first conductive skin layer, the first cavity being formed partially within said additional layer.The electrically insulating material of the additional layer has a first coefficient of thermal expansion along the Z-axis, the metallic alloy has a second coefficient of thermal expansion along the Z-axis, and in which the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion. A surface area of ​​the first cavity, in the plane, is at least equal to 0.04 mm².

[0015] The electronic board comprises a multilayer printed circuit board, said printed circuit board comprising at least four conductive layers separated in pairs by insulating layers, including: a first and a second conductive skin layer fixed to a first and a second insulating layer, respectively, the first conductive layer being substantially planar and defining a plane normal to a Z-axis, a first and a second internal conductive layer, extending between the first and second insulating layer, respectively, and separated by a third insulating layer, at least the first internal conductive layer being treated so as to form at least one solder pad, a first cavity, formed in the first conductive skin layer and in the first insulating layer, said first cavity exposing at least part of the solder pad, and a first surface-mount electronic component comprising at least one termination, said first component being in contact with or at a distance from the first conductive skin layer,The termination of the first component is fixed in the first cavity by means of a brazed joint.

[0016] Some preferred but not exhaustive features of the electronic board described above are as follows, taken individually or in combination: The first cavity includes a metallic metallization layer. The first cavity is partially covered with a metallic metallization layer. The electronic board further includes a solder mask applied to the first conductive layer and to the top of the at least partially exposed insulating layer, and / or a metallic finish applied to the first conductive skin layer and the areas of the first internal conductive layer that form the first cavity. The first component includes an additional termination, said termination being attached to the first conductive skin layer by means of a solder joint.the second internal conductive layer is treated so as to form at least one solder pad, the electronic board further comprising: a second cavity, formed in the first insulating layer and in the third insulating layer, opposite the second internal conductive layer, and a second surface-mounted electronic component comprising at least one termination, said second component being in contact with or at a distance from the first conductive skin layer, the termination of the second component being fixed in the second cavity by means of a solder joint.the first component further includes an additional termination, the second internal conductive layer is treated so as to form at least one solder pad and the electronic board further includes an additional cavity, formed in the first insulating layer and in the third insulating layer, opposite the solder pad of the second internal conductive layer, the additional termination of the component being fixed to said solder pad in the additional cavity by means of a solder joint.The second internal conductive layer is treated to form at least one solder pad, the electronic board further comprising: a fourth cavity, formed in the second conductive skin layer and in the second insulating layer, opposite the second internal conductive layer, and a fourth surface-mounted electronic component comprising at least one termination, said fourth component being in contact with or at a distance from the second conductive skin layer, the termination of the fourth component being fixed in the fourth cavity by means of a solder joint. A surface area of ​​the first cavity, in the plane, is at least equal to 0.04 mm². BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, purposes, and advantages of the present invention will become more apparent upon reading the detailed description that follows, and with reference to the accompanying drawings, which are given by way of non-limiting examples and on which: THE figures 1a to 1l illustrate steps in an example of implementing a fastening method according to the invention. figures 2a to 2c These are partial cross-sectional views of three examples of electronic circuit board implementations comprising partially or fully metallized cavities into which an example of a component is brazed. figure 3a is a cross-sectional view of another example of partial cavity metallization at different depths, while the figure 3b is a view of two examples of the realization of the left cavity of the example of the figure 3a before filling, The figure 4a is a cross-sectional view of another example of partial cavity metallization at different depths, while the figure 4b is a top view of the cavity in the example of the figure 4a before filling, The figures 5 to 8 are examples of electronic boards conforming to the invention, and The figure 9is a flowchart illustrating an example of the manufacturing steps of an electronic board conforming to an embodiment of the invention. DETAILED DESCRIPTION OF A METHOD OF IMPLEMENTATION

[0018] An electronic card 1 includes a printed circuit 2 having conductive layers separated by insulating layers 10, 11, 12, on which surface-mounted electronic components (hereinafter SMT 3) are fixed.

[0019] Generally, a printed circuit board 2 can be of the single-layer type (also called single layer) and include only one conductive layer, double-layer (also called double-sided) and include a conductive layer on either side of an insulating layer, or multi-layer and include at least four conductive layers.

[0020] The present invention is of particular interest when the printed circuit board 2 is multilayer and comprises at least four conductive layers, separated in pairs by insulating layers 10, 11, 12. In what follows, the invention will be described more specifically in the case of a printed circuit board 2 comprising exactly four conductive layers, of which: a first and second conductive skin layers (hereinafter layer C 1 and layer C 2, respectively) fixed on a first and second insulating layer 10 and 11, respectively, a first and second internal conductive layers (hereinafter layer C 3 and layer C 4, respectively), extending between the first and second insulating layers 10 and 11, respectively, and separated by a third insulating layer 12.

[0021] This is not limiting, however, since, as we shall see later, the invention also applies in the case where the printed circuit 2 comprises a greater number of internal conductive layers (for example, C 5 and C 6 layers) separated in pairs by additional insulating layers 10, 11, 12.

[0022] Layer C1 is substantially planar and defines a plane (X; Y) normal to an axis Z. Layers C1 and C2 correspond to the outermost layers of printed circuit 2 and sandwich the insulating layers 10, 11, 12 and the internal conductive layers C3 and C4.

[0023] To increase the diversity of electronic board 1 and improve the lifespan of the components, electronic board 1 can be manufactured according to the following steps: form S1 a cavity 20 in layer C 1 (respectively, in layer C 2) and in the first insulating layer 10 (respectively, in the second insulating layer 11), opposite a solder area 4 of layer C 3 or layer C 4, so that at least part of the solder area 4 is exposed, fill S5 the cavity 20 with a metal alloy accompanied by a soldering flux, place S6 a termination 8 of the SMT 3 on layer C 1 (respectively, on layer C 2) opposite the cavity 20, apply a heat treatment S7 to the printed circuit board 2 on which the SMT is placed in order to transform the metal alloy accompanied by the soldering flux into a solder joint 5 so as to fix the SMT 3 to the printed circuit board 2.

[0024] A cavity surface area, in the (X; Y) plane, is at least equal to 0.04 mm² in order to achieve the desired lifespan for the CMS 3.

[0025] A cavity depth p of cavity 20 can, for example, be at least 60 µm. For example, for a cavity 20 with a depth p of 60 µm, the lifetime is increased by 50%. For a cavity 20 with a depth p of 120 µm, the lifetime is increased by 100%.

[0026] As mentioned above, the cavity 20 can be formed (step S1) so as to reveal a soldering area 4 of the C3 layer or a soldering area 4 of the C4 layer. Only the depth p of the cavity 20 and the number of insulating layers 10, 11, 12 traversed change, the steps of the process S not being modified.

[0027] Furthermore, cavity 20 can be formed from layer C1 or from layer C2. One or more cavities 20 can also be formed from both layer C1 and layer C2.

[0028] Finally, several cavities 20 can be formed in the printed circuit 2. These cavities 20 can have different depths p and therefore reach a soldering range 4 of the C3 layer or the C4 layer.

[0029] The number of cavities 20, their depth p (and therefore the internal conductive layer C3 or C4 reached) and the layer C1 or C2 from which the cavities 20 are formed depend on the type of SMD 3 fixed on the printed circuit 2, but also on the mix and the density to be achieved for the printed circuit 2.

[0030] In what follows, to simplify the description, the invention will be described more particularly in the case where four cavities 20 are formed in the printed circuit board 2, two cavities 20 from layer C1, opposite two solder pads 4 of layer C3, and two cavities 20 from layer C2, opposite two solder pads 4 of layer C4. This is not, however, limiting, as we have seen above, a different number of cavities 20 can be formed in the printed circuit board 2, from layer C1 and / or from layer C2, each of said cavities 20 being able to pass through one or more insulating layers.

[0031] The order described above for the steps of placing the SMD 3 and filling the cavity 20 is not exhaustive. The SMD 3 can be placed on top of the cavity 20 (step S6) before or after it is filled (step S5), depending on the filling technique chosen. Indeed, the filling step S5 can be performed by filling the cavity 20 with a solder paste containing a metal alloy suspended in a solder flux. In this case, the SMD 3 is placed on the solder paste (step S6), above the cavity 20. Alternatively, the filling step S5 of the cavity 20 can be performed by filling it through a molten alloy bath, in which case the SMD 3 is placed on a spot of adhesive on layer C1 (step S6) before the printed circuit board 2 is immersed in the molten alloy bath.

[0032] The solder area 4 of layer C3 can be obtained, in a manner known per se, by chemical treatment of layer C3, typically by etching. This chemical treatment step can notably be implemented during the manufacture of the printed circuit board 2, prior to the stacking step of the conductive layers C1 and C2 and the insulating layers 10, 11, 12 intended to form the printed circuit board 2. For example, the multilayer circuit can be obtained according to the following substeps (see Figure 1a ) : to provide a double-sided printed circuit board 2, that is to say comprising an insulating layer (intended to become the third insulating layer 12) and two conductive layers (intended to become layers C 3 and C 4) on either side of the insulating layer, to etch at least one of the layers C 3 and C 4, preferably both, in order to form solder pads 4 in the layers C 3 and C 4, to apply and fix another insulating layer on each layer C 3 and C 4, the said insulating layers being intended to become respectively the first and second insulating layers 10, 11 of the multilayer circuit, to apply and fix a conductive layer on each of the additional insulating layers 11, 12, the said conductive layers being intended to become layers C 1 and C 2, and to compress the whole thus formed in order to obtain the multilayer printed circuit board 2. This gives us printed circuit board 2 of the figure 1b .

[0033] Alternatively, the multilayer circuit can be supplied directly 2.

[0034] If necessary, layers C1 and C2 can also be etched, before or after the temperature compression substep, to form solder pads 4 and / or conductive tracks.

[0035] The insulating layers 10, 11, and 12 of the printed circuit board 2 may comprise, in a manner known per se, an epoxy resin and glass fibers. The conductive layers C1 to C4, on the other hand, may be made of copper (or a copper-based alloy).

[0036] The cavities 20 can be formed by cutting through layer C1 and the first insulating layer 10. The cutting can be carried out mechanically (using a mechanical milling, drilling, or laser drilling tool). Laser drilling is only feasible if the surface area (in the (X, Y) plane) at the bottom 21 of a cavity 20 is smaller than the copper brazing area 4, so that the brazing area 4 extends beyond the bottom 21 of the cavity 20 to allow the CO2 laser to stop at a depth p on the copper.

[0037] When cavities 20 are created by laser drilling, the laser can be a gas laser (carbon dioxide). The parameters chosen for the laser can then be similar to those usually used for creating laser vias.

[0038] Laser drilling allows for the formation of cavities with high precision. In particular, it is possible to position cavities with high accuracy and tight dimensional tolerances. Typically, the dimensional tolerance is on the order of 25 microns (for cavities with a minimum side size of 100 µm) when the cavities are created by laser drilling, as opposed to approximately 100 microns (for cavities with a minimum side size of 300 µm) when they are created by cutting (mechanical or chemical).

[0039] Laser drilling thus allows an increase in the density of the CMS 3 on the printed circuit 2, since the dimension of the cavities 20 can be reduced (the minimum size of the cavity that can be obtained by laser drilling being smaller).

[0040] Laser drilling thus allows an increase in the density of SMT 3 on the printed circuit board 2, since the distance between two cavities 20 can be reduced (positioning and dimensional tolerances being smaller).

[0041] The shape of the cavities 20 is preferably cylindrical, particularly when obtained by laser drilling, mechanical cutting, or mechanical drilling. The cross-section in the (X, Y) plane of the cavities 20 can be arbitrary, for example, circular, rectangular, etc.

[0042] If necessary, one or more through-vias 6 can also be made in the printed circuit 2 using conventional techniques.

[0043] If necessary, one or more laser vias 6' can also be made in the printed circuit board 2 using conventional techniques (see in particular figure 7 ).

[0044] In a first variant of the implementation illustrated on the figure 1dThe cavities 20 can be metallized (step S2) before being filled S5 with a metallic alloy and a brazing flux. Metallization S2 deposits a thin metallic layer 13 (a few micrometers thick) on the walls of each cavity 20.

[0045] Since layers C1 and C2 and brazing areas 4 are generally made of copper, the deposited metallic layer 13 is a copper layer whose thickness can be on the order of twenty micrometers.

[0046] The metallization of the cavities 20 can be carried out by any conventional technique, for example by electrolysis. The copper layer 13 can comprise a first copper layer called "chemical" followed by a deposit of a second copper layer called "electrolytic" and covers the bottom 21 of the cavities 20 (corresponding approximately to the brazing area 4) and the exposed surfaces of the first and second insulating layers 10, 11 (which form the vertical walls 22 of the cavities 20).

[0047] In one embodiment, both layers C1, C2 and the cavities 20 are metallized during this step. Layers C1, C2, the brazing areas 4 and the vertical walls 22 of the cavities 20 are coated with a layer of copper 13, resulting from the deposition of chemical copper followed by the deposition of electrolytic copper.

[0048] The S process may further include a step of etching layer C1 ( figure 1eFor this purpose, in a manner known per se, a photosensitive film 14 is applied to the free side of layers C1 and C2. The photosensitive film 14 is preferably a positive resin (ultraviolet radiation causes the macromolecules to break down, thus increasing the solubility of the exposed areas in the developing solvent). The resin may, in particular, be an epoxy resin.

[0049] A mask 15 (or transparencies) is then applied to the photosensitive film 14. The mask 15 includes transparent and opaque areas to allow the etching of layer C 1 and to form, for example, conductive tracks 16 and / or a flange 23 at the exit of one or more cavities 20. In the example illustrated on the figure 1e , typon 15 includes for example opaque areas at the level of two cavities 20, the via 6 and two areas intended to form conductive tracks 16.

[0050] Finally, the photosensitive film 14 is exposed to light: in the case of a positive resin (typically epoxy resin), the parts of the film 14 located under the transparent areas will react to this light and dissolve, while the parts located under the opaque areas will be protected. Alternatively, the film positive 15 is exposed by a laser process (generally known by its English terminology, Laser Direct Insolation, LDI).

[0051] In all cases, the solubilized parts are then removed using a developing solvent, which allows the C1 layer to be partially revealed. The unsolubilized parts of the photosensitive film 14 remain above the two cavities 20, the via 6 and the two areas intended to form conductive tracks 16.

[0052] Areas not protected by the photosensitive film 14 can then be etched until the copper disappears completely, for example by electrolysis ( figure 1g ).

[0053] Since this S engraving process is known in itself, it will not be detailed further here.

[0054] Optionally, part of the metallization can be removed (step S3), so as to obtain one or more partially metallized cavities 20 ( figures 1k and 1l ). This S3 shrinkage can be carried out at the level of all the cavities 20 formed in the layers C 1 and C 2, at the level of only part of the cavities 20 formed in the layers C 1 and C 2, or differently depending on the cavities 20 formed in the layers C 1 and C 2, in order to adapt the metallization of each cavity 20 to the type of termination 8 intended to be fixed in said cavities 20. The partial shrinkage can also concern the layers C 1 and C 2, in whole or in part, in order to form one or more collars 23 (complete or partial).

[0055] This removal can be carried out, in particular, using a laser to pierce the chemical copper layer. Partial removal S3 may involve: all or part of the metallic layer 13 deposited on the vertical walls 22 of one or more cavities 20 and / or all or part of the metallic layer 13 deposited on the bottom 21 of one or more cavities 20 and / or all or part of the metallic layer 13 deposited on the layers C 1 and / or C 2.

[0056] If necessary, the laser can be tilted relative to the vertical walls 22 of the cavity 20 in order to present a non-zero striking angle to better remove the metallization from the vertical walls 22.

[0057] For example, we illustrated on the figure 2a an example of part of an electronic board 1, in which cavity 20 has been metallized but where the metallic layer 13 has not been removed.

[0058] We have also illustrated on the figure 2bthe case where the metallic layer 13 was removed from the entire vertical wall 22 of the cavities 20 and at the exit of the cavities 20, but was left at the bottom 21 of the cavity 20.

[0059] There figure 2c illustrates the case where the metallic layer 13 has been removed from the entire vertical wall 22 of the cavities 20 but has been left at the bottom 21 of the cavity 20 and at the exit of the cavity 20, thus forming two collars 23 in the layer C 1.

[0060] THE figures 3a and 3b illustrate the case where the metallic layer 13 has been removed from the entire vertical wall 22 of the cavities 20 but has been left at the bottom 21 of the cavity 20 and on part of the outlet of the cavities 20, thus forming two half-collars 23 in the layer C 1.

[0061] THE figures 4a and 4billustrate the case where the metallic layer 13 has been removed on half of the periphery of the vertical wall 22 of the cavities 20, on half of the bottom 21 of the cavity 20 and on part of the outlet of the cavities 20 to form two half-collars 23 in the layer C 1.

[0062] It will be understood that the S3 step of partial removal of the metallic layer 13 can be carried out before or after the etching step of the C 1 layer.

[0063] If necessary, one or more non-metallized cavities 20 can also be made in the C 1 layer (step S4) after the S2 metallization step, by laser drilling of the C 1 layer and the first insulating layer 10.

[0064] Alternatively, the non-metallized cavities 20 can be obtained, as indicated above, by removing the copper layer from the cavity 20 already formed (during step S3).

[0065] Conventionally, a layer of masking varnish 17 can then be applied to the exposed surfaces of the first insulating layer 10 and, where appropriate, to the conductive tracks 16, without covering the parts requiring electrical contact with the outside (such as the vertical walls 22 of the cavities 20, their possible collar 23 or a ground connection contact for example).

[0066] A finish 18 can also be applied to protect the exposed copper and maintain the ability of the pads 4 to receive a solder joint 5. The finish 18 may comprise, in a manner known per se, an organic solder preservative (OSP) or a metallic finish comprising at least one of the following alloys: electroless nickel / gold, electroplated nickel / gold, electroless tin, or electroless silver. The thickness of the finish 18 may be on the order of a few microns and may be applied to all exposed copper surfaces.

[0067] If necessary, an 18 finish by hot air levelling (HAL) based on lead / tin or tin alloy may be used.

[0068] The cavities 20 can be filled by screen printing with a solder paste 24 comprising the metal alloy suspended in the solder flux.

[0069] For this, during a first sub-step, a silkscreen 7 (or stencil) in which two windows 9 have been formed (one per cavity 20 formed) is placed on the layer C 1. The screen 7 is positioned so that each window is opposite the corresponding cavity 20 to be filled.

[0070] Of course, screen 7 can include a different number of windows 9 if a different number of cavities 20 need to be filled.

[0071] The dimensions of the windows 9 are approximately equal to the dimensions of the associated cavity 20 to be filled, in order to optimize the filling of cavity 20. Preferably, the dimensional accuracy for the windows 9 is on the order of thirty micrometers. The windows 9 may be slightly larger than the associated cavity 20 to ensure proper filling and to increase the amount of solder paste 24 deposited.

[0072] In a second substep, solder paste 24 is deposited on the screen 7 and then forced into the windows 9 and cavities 20 using a squeegee (see figure 1j ). As is known in itself, the scraper may include a metal sheet, which is inclined at an angle of between 45° and 60° in order to better push the soldering cream 24 into the cavity 20.

[0073] During a third sub-step, the screen 7 can be demolded so as to leave the solder paste 24 in the cavities 20. It will be noted that the thickness of the solder paste 24 deposited is greater than the thickness of the layer C 1 and the first insulating layer 10, due to the presence of the screen 7 during the filling.

[0074] A CMS 3 can then be placed on the C 1 layer, so that each termination 8 is above a cavity (step S 6), then the S7 heat treatment can be applied to the electronic board 1.

[0075] The three sub-steps described above for filling cavities 20 by screen printing are then repeated for cavities 20 of layer C 2.

[0076] In one embodiment, the cavities 20 can be filled by screen printing with a solder paste 24 without using a screen 7. Indeed, the squeegee can be moved directly on the free face of the printed circuit board 10: the C1 layer and the first insulating layer 10 (respectively, the C2 layer and the second insulating layer 11) serve as a screen 7. When the squeegee reaches a cavity 20, it then forces the solder paste 24 into the cavity 20 in a similar way to what is usually done with a screen 7.

[0077] To avoid the presence of solder paste 24 on top of layers C1 and C2, it is best to use a polymer scraper 6. Any remaining alloy beads can then be washed off after the heat treatment step. After filling the cavities 20, layer C1 and the first insulating layer 10 (respectively, layer C2 and the second insulating layer 11) are not removed from the mold. They will also serve as a support for the SMT 3 and will help retain the solder paste 24 during heat treatment.

[0078] This screen-free embodiment reduces the manufacturing costs of the electronic board 1, as it eliminates the need for a silkscreen 7 and the use of highly precise equipment (no more screen 7 to be positioned directly against the printed circuit board 2). Furthermore, step S5, which involves filling the cavities 20, is simplified since it is no longer necessary to precisely position a screen 7 on layers C1 and C2.

[0079] According to yet another variant, the cavities 20 can be filled S5 by inkjet printing (“jetting” in English) of the metal alloy accompanied by the brazing flux, by passing through a turbulent wave of molten metal alloy accompanied by the brazing flux, by dipping or passing through a bath of remelted metal alloy, or by wave brazing or by hand brazing.

[0080] The dimensions of the cavities 20 are chosen so that each cavity 20 exposes at least part of the adjacent solder area 4 and that the lifespan of the termination 8 of the SMD 3 soldered into that cavity 20 is sufficient. For example, each cavity 20 can be sized to cover and extend beyond the solder area 4. The definition of the dimensions of each cavity 20 depends on the terminations 8 of the SMD component 3 to be assembled. For example, for a size 0603 package, which includes several terminations 8, the cavities 20 can have dimensions on the order of 0.5 mm * 1 mm; for size 1206 packages: 1 mm * 2 mm; for size 2010 packages, the cavities 20 can have dimensions on the order of 1.5 mm * 4.5 mm. For cases of a not-thin type, the width of the cavities 20 could be, for example, on the order of 0.3 mm.The surface area of ​​the bottom 21 of each cavity 20 is therefore larger than the surface area it reveals of the brazing area 4. This is not limiting however, the cavities 20 can be dimensioned so as not to extend beyond the brazing area 4 they reveal.

[0081] The thicker the first insulating layer 10 and the C1 layer, the greater the depth p of the cavities 20 and the greater the thickness of solder paste 24 that can be introduced into the cavities 20. Indeed, if the cavities 20 are filled with solder paste 24 by screen printing with a screen 7, the size of the windows 9 of the screen printing screen 7 is no longer limited by the possibility of removing the screen 7 after filling the cavity 20, since the C1 layer and the first insulating layer 10 remain on the soldering area 4 and are not removed from the mold. Therefore, the height of solder paste 24 introduced into each cavity 20 is equal to the sum of the depth p of the cavity 20 and the thickness of the screen 7, the thickness of the screen 7 being able to be small when the thickness of the layer C 1 and the first insulating layer 10 is large.

[0082] More specifically, the size of a window 9 of a silkscreen 7 is limited by the ratio between the area of ​​the window 9 (in the plane of the screen 7, which is parallel to the (X, Y) plane) and the area of ​​the internal walls of the window 9 (which extend perpendicularly to the plane of the screen 7), which must be greater than or equal to 0.66. Until now, it was either necessary to reduce the thickness of the screen 7, which implied a decrease in the amount of solder paste 24 and therefore in the standoff of the SMDs 3, or to increase the area of ​​the window 9, which prevented the implantation of fine-pitch SMDs 3 or limited the density of SMDs 3 implantable on the printed circuit board 2.

[0083] The formation of the cavities 20 in layer C 1 and in the first insulating layer 10 thus moves the upper face of the soldering pad 4 away from the lowest point of the conductive terminations 8 of the SMD 3 once soldered. This advantageously overcomes this limitation, as it becomes possible to drastically increase the thickness of solder paste 24 applied to the printed circuit board 2 without altering the thickness of the silkscreen 7. If necessary, it is even possible, during the fabrication of the printed circuit board 2, to increase the thickness of the first insulating layer 10 as needed and to create a window 9 with a surface area adapted to the surface of the associated cavity 20, its thickness being dictated by the ratio above so that it remains greater than 0.66.

[0084] Thus, the invention makes it possible to overcome the difficulties of demolding the silkscreen 7, when such a screen 7 is used and makes it possible to implant fine pitch SMD 3s and / or a high density of SMD 3s on the electronic board 1. Typically, it can be envisaged to use a screen 7 having a thickness of the order of 50 µm to 100 µm with possible local thicknesses of 100 µm to 300 µm if needed.

[0085] It will be understood of course that the removal of the silkscreen 7, made possible by the formation of the cavity 20 in the layer C 1 and in the first insulating layer 10, also makes it possible to implant fine pitch CMS 3s on the printed circuit 2 and / or to increase the density of CMS 3s on the printed circuit 2, since the process S of filling the cavities 20 does not require demolding a screen 7.

[0086] Optionally, in order to increase the depth p of the cavity 20, the process S may further include a step of applying an additional layer 19 comprising an electrically insulating material to one or both of the layers C1, C2, before the heat treatment step S7 and, where appropriate, after the etching step of layer C1. In the embodiment illustrated in figure 5 , the additional layer 19 is for example applied on the layer C 1 .

[0087] The additional layer 19 may cover all or part of the underlying layer (C1 and / or C2). The cavities 20 are then formed partly within said additional layer 19. In other words, the upper part 25 of the cavities 20 may be formed within the additional layer 19. If so, this upper part 25 may have larger dimensions than the rest of the associated cavity 20.

[0088] The additional layer 19 may include any electrically insulating material. If necessary, the material of the additional layer 19 may be thermally conductive. Furthermore, depending on the thermal and vibrational environment, and in order to further increase the lifespan of the printed circuit board 2, the material of the additional layer 19 may be chosen to have a higher coefficient of thermal expansion along the Z-axis than that of the metallic alloy.

[0089] Typically, the additional layer 19 may include at least one of the following materials: glass fibers, epoxy resin, polyimide, polyester, polymer, Teflon.

[0090] The additional layer 19 can be applied by any means to the layer C 1, before or after the formation of the cavities 20 in the layer C 1 and in the first insulating layer 10.

[0091] In one embodiment, the additional layer 19 can be attached to and fixed onto layer C1 and / or C2, for example by lamination or bonding with an adhesive layer. The adhesive layer can comprise any type of adhesive material conventionally used in the field of printed circuit boards for bonding layers together, typically an epoxy adhesive. The upper portion 25 of the cavities 20 can then be pre-formed in the additional layer 19 before it is placed on layer C1 and / or C2, or even after it has been fixed.

[0092] For example, the upper part 25 of the cavities 20 can be formed by cutting the additional layer 19. The cutting of the upper part 25 of the cavities 20 in the additional layer 19 being analogous to that of the rest of the cavities 20 (e.g. mechanical milling or mechanical drilling or laser drilling) in the insulating layers 10, 11, it will not be detailed again here.

[0093] If necessary, the additional layer 19 may include a printed circuit board 2, which can be attached to and fixed to layer C1 and / or C2 by soldering or gluing. In one embodiment, the upper part 25 of the cavities 20 are then formed in the printed circuit board 2. The printed circuit board 2 forming the additional layer 19 can then extend over all or part of layer C1. Alternatively, it can extend only locally, under the SMD 3. This embodiment is particularly advantageous when the SMD 3 has gull-wing pins 8, the assembly of which tends to break.

[0094] It should be noted that the moment when the additional layer 19 is placed on the layer C 1 and / or C 2 depends on the technique of deposition of the additional layer 19 and of formation of the cavities 20. For example, in the case where the cavities 20 are made by laser drilling, it is preferable to form the cavities 20 in the additional layer 19 before its deposition on the layer C 1 and / or C 2, to guarantee the stopping of the laser.

[0095] The addition of the additional layer 19 makes it possible to increase the depth p of the cavities 20 and thus increase the standoff of the CMS 3. This additional layer 19 is also interesting when the thickness of the first insulating layer 10 is small and therefore does not allow on its own to form cavities 20 with a depth p sufficient to achieve the desired lifetime.

[0096] If necessary, the additional layer 19 may only be applied to part of the C1 layer, for example under certain CMS 3 only, as illustrated in figure 5 . A stepped silkscreen can then be used to fill the cavities 20 underlying the additional layer 19 at the same time as the other cavities 20.

[0097] The S5 heat treatment step may include reflow soldering of the metal alloy present in the solder paste 24. To achieve this, during a first sub-step called a ramp-up, the temperature is gradually increased. This ramp-up step can, in a manner known per se, be carried out at a rate of between 1°C / s and 4°C / s up to 100°C to 150°C (maximum 7°C / s, the maximum temperature ramp recommended for SMD components 3 before soldering).

[0098] During a second sub-step called preheating (“preheat” in English), the drying operation of the fluxes (“soak” or “preflow” in English) and the preparation for cleaning of the solder terminations 8 of the printed circuit board 2 and the SMC 3 takes place. The temperature is gradually increased to about 170°C and maintained for at least one and a half minutes to several minutes (depending on the fluxes used) in order to allow the evaporation of the volatile parts of the soldering flux and the temperature homogeneity of all the components before the reflow phase.

[0099] During a third sub-step called reflow, the temperature is again increased until it reaches a critical temperature, generally 20 to 50 °C above the melting temperature of the metal alloy used. When the temperature passes through the melting point of the metal alloy contained in the solder paste 24 (i.e. for example about 180°C when the metal alloy includes a tin / lead alloy 63 / 37, about 217°C in the case of a tin / silver / copper metal alloy 95.6 / 3.0 / 0.5 and about 221°C in the case of a tin / silver metal alloy 96.5 / 3.5), the metal alloy melts 21. It should be noted that at all times, the metal alloy which is liquid remains in contact with the terminations 8 of the CMS 3 and the soldering area 4 of the C layer 3 under the effect of wettability.

[0100] Preferably, the temperature increase during the reflow stage is rapid and, in any case, faster than the heating stage to prevent the SMD 3 from being subjected to prolonged high temperatures. The printed circuit board 2 can also be held at a critical temperature above the alloy's melting point for a period ranging from twenty to ninety seconds, depending on the thermal mass of the components to be assembled. This time above the alloy's melting point allows the formation of intermetallics that will secure the components between the metallic alloy and the parts to be assembled.

[0101] In a fourth substep, the printed circuit board 2 is rapidly cooled to room temperature. When the temperature drops below the melting point and becomes lower than the melting temperature of the metal alloy, the alloy solidifies, forming the solder joint 5. The first insulating layer 10 (which extends between the first layer C1 and layer C3) then ensures a minimum standoff between the top surface of the solder pad 4 and the bottom point of the conductive terminations 8 of the SMD 3 once soldered, which cannot be less than the thickness of the first insulating layer 10. If applicable, when an additional insulating layer 19 is applied over layer C1, the minimum standoff is at least equal to the sum of the thickness of the first insulating layer 10 and the thickness of the additional layer 19.

[0102] It should be noted that the brazing flux gradually evaporates during the temperature rise (and preheating / drying) stage, leaving only the metal alloy on the brazing range 4. The brazing joint 5 therefore only includes the metal alloy.

[0103] The reflow heat treatment is well-known in the technical field of SMD soldering, so further details are unnecessary here. Moreover, the temperatures, slopes, and durations of the various heat treatment steps are given here as examples and naturally depend on the solder paste used. A skilled professional will therefore be able to easily adapt them according to the type of metal alloy and soldering flux used.

[0104] As can be seen, the S process of the invention allows the use of any type of solder paste 24, and in particular lead-free solder pastes, thus making it possible to comply with current standards and in particular the European RoHS Directive No. 2002 / 95 / EC - banning Lead, Hexavalent Chromium, Mercury, Cadmium, Polybromobiphenyl and decabromodiphenyl ethers. For example, the metal alloy of soldering cream 24 may include one of the following compositions, which are the most commonly used: tin / lead 63 / 37 or 10 / 90 or 90 / 10, tin / lead / silver 62 / 36 / 2, for products exempt from the RoHS directive, or tin / silver alloys 96.5 / 3.5, tin / silver / copper 96.5 / 3.8 / 0.7 or 96.6 / 3.0 / 0.5 or 98.5 / 1.0 / 0.5. This technique is suitable for all types of alloys (including those containing bismuth, antimony, etc.).

[0105] As is well known, the soldering flux depends on the type of metal alloy suspended in the solder paste 24 and the assembly process, with or without cleaning. The soldering flux generally comprises a resin (typically a natural, modified, or synthetic resin), activators, and additives to optimize screen printing and reflow soldering. The role of the soldering flux is to ensure the cleaning of the solder pads 4 (using the activators), to protect them during the heating stages, and to act as a surfactant to promote wetting of the metal alloy. For example, the soldering flux may contain rosin.

[0106] It can be advantageous to braze terminations 8 of the same CMS 3 in cavities 20 of different depth p, or to braze at least one termination 8 on the surface while the other terminations 8 are brazed in cavities 20. Indeed, in general, the forces applied to the terminations 8 are not identical for the same CMS 3: the staggered brazing of the terminations 8 thus makes it possible to adapt the brazing to the forces received by each termination 8.

[0107] For example, it is possible to solder part of the terminations 8 on the surface, on layer C 1 (respectively, layer C 2) and the rest of the terminations 8 in cavities 20. Preferably, the terminations 8 subjected to the most stress are soldered in cavities 20, in order to increase their lifetime by reducing the shear angle for the same relative displacement of the SMT 3 with respect to the printed circuit 2, while the others can be surface soldered.

[0108] This embodiment is particularly advantageous in the case of BGA (Ball Grid Array) type SMD components: the terminations 8 located in areas adjacent to the corners of the BGA are exposed to greater stress than the terminations 8 located in the central part of the BGA or in the middle of the sides of the BGA. The terminations 8 located in these areas can therefore be brazed into cavities 20.

[0109] This embodiment can also be advantageous when the CMS 3 includes legs: the legs located in the central part of the CMS 3 can be brazed on the surface (respectively, in a cavity 20 at a first depth p) while the legs located at the end of the CMS 3 can be brazed in a cavity 20 (respectively, in a cavity 20 at a second depth p, greater than the first depth p).

[0110] Examples of electronic boards 1 comprising various SMDs 3 fixed according to method S of the invention will now be described with reference to figures 6 to 8 .

[0111] There figure 6 illustrates an electronic card 1 comprising two conductive skin layers C 1 and C 2 and six internal conductive layers C 3 , C 4 , C 5 , C 6 , C 7 and C 8 which extend between layers C 1 and C 2 and are separated in pairs by insulating layers 10, 11, 12, 30, 31, 32 and 33.

[0112] A first CMS 3 (CMS#1) is brazed into cavities 20 formed in layer C 1 and in the first insulating layer 10. As can be seen in this figure, the vertical walls 22 of these cavities 20 are partially metallized (on half of the periphery of the vertical wall 22 of the cavities 20, at the bottom 21 and on part of the exit of the cavities 20 to form half-collars 23).

[0113] A second CMS 3 (CMS#2) is conventionally brazed onto layer C 1.

[0114] A third and fourth through-hole components (SMD#3 and SMD#4), mounted in an unconventional "surface-mount" manner, are brazed into cavities 20 formed in layer C1 and in the first (10), third (12), fourth (30), and fifth (31) insulating layers. As can be seen in this figure, the vertical walls 22 of these cavities 20 and their outlets are metallized through a flange 23.

[0115] A fifth CMS 3 (CMS#5), comprising gull-wing legs, is brazed into cavities 20 formed from layer C 1 to layer C 4 through the first insulating layer 10, layer C 3 and the third insulating layer 12. As can be seen in this figure, the vertical walls 22 of these cavities 20 and their outlets are metallized through a collar 23.

[0116] A sixth CMS 3 (CMS#6), comprising gull-wing-shaped legs 8, is brazed into cavities 20 formed in layer C 2 and in the second insulating layer 11. As can be seen in this figure, only the bottom 21 of these cavities 20 is metallized.

[0117] A seventh CMS 3 (CMS#7), comprising 8 gull-wing legs, is conventionally brazed onto layer C 2.

[0118] An eighth CMS 3 (CMS#8) is brazed into cavities 20 formed in layer C 2 and in the second insulating layer 11. As can be seen in this figure, the vertical walls 22 of these cavities 20 are partially metallized (on half of the periphery of the vertical wall 22 of the cavities 20, on half of their bottom 21 and on part of the exit of the cavities 20 to form half-collars 23).

[0119] A ninth CMS 3 (CMS#9), which can correspond to a BGA and includes a plurality of terminations 8, is brazed partly conventionally on the C 2 layer and partly in cavities 20 formed in the C 2 layer and in the second insulating layer 11. The terminations 8 brazed in cavities 20 here correspond to the terminations 8 located at the ends of the ninth CMS 3.

[0120] Thus, this electronic board 1 comprises nine CMS 3s of different sizes and all have a standoff suitable for the CMS 3. We see in particular that the standoff of the second and seventh CMS (CMS#2 and CMS#7) is low, while the standoff of the other CMS 3s is high and at least equal to the number of insulating layers 10, 11, 12 and conductive layers between the layer C 1 or C 2 on which the CMS 3 is fixed and the solder area 4 of the CMS 3.

[0121] There figure 7illustrates an electronic card 1 comprising two conductive skin layers C 1 and C 2 and four internal conductive layers C 3 , C 4 , C 5 and C 6 , which extend between layers C 1 and C 2 and are separated in pairs by insulating layers 10, 11, 12, 30, 31.

[0122] A first CMS 3 (CMS#1) is brazed conventionally onto layer C 1.

[0123] A second CMS 3 (CMS#2) is brazed into cavities 20 formed in the first insulating layer 10. As can be seen in this figure, the vertical walls 22 and the exit of these cavities 20 are not metallized.

[0124] A third CMS 3 (CMS#3) is brazed into cavities 20 formed in the first insulating layer 10 and in the third insulating layer 12. As can be seen in this figure, the vertical walls 22 and the exit of these cavities 20 are also not metallized.

[0125] A fourth CMS 3 (CMS#4) is brazed into a cavity 20 formed in the second insulating layer 11 and in a fifth insulating layer 31. As can be seen in this figure, the vertical walls 22 and the bottom 21 of these cavities 20 are metallized, but not their outlet.

[0126] Thus, this electronic board 1 comprises four SMD 3s of different sizes, each with a standoff value adapted to the SMD 3. It is particularly noticeable that the standoff value of the first SMD 3 is low, while the standoff values ​​of the second, third, and fourth SMD 3s are high. For example, the standoff value of the third SMD 3 (SMD#3) is equal to the thickness of layer C1, the first insulating layer 10, layer C3, and the third insulating layer 12.

[0127] Thus, this electronic board 1 comprises four CMS 3s of different sizes and all have a standoff adapted to the CMS 3. We see more particularly that the standoff of the first CMS (CMS#1) is low, while the standoff of the third and fourth (CMS#3 and CMS#4) is high and equal, respectively, to the thickness of the first and third insulating layers 10, 12 and to the thickness of the second and fifth insulating layers 11, 31.

[0128] There figure 8 illustrates an electronic card 1 comprising two conductive skin layers C 1 and C 2 and four internal conductive layers C 3 , C 4 , C 5 and C 6 , which extend between layers C 1 and C 2 and are separated in pairs by insulating layers 10, 11, 12, 30, 31.

[0129] A first CMS 3 (CMS#1), which can be of the LCC (English acronym for Leadless Chip Carrier for pinless package), LGA (English acronym for Land Grid Array for array matrix) or QFN (English acronym for Quad Flat No-lead) type, is brazed into cavities 20 formed from the C 1 layer in the first insulating layer 10. As can be seen in this figure, the walls of these cavities 20 are not metallized.

[0130] A second CMS 3 (CMS#2), which includes 8 J-shaped tab terminations, is brazed into cavities 20 formed from layer C 1 in the first and third insulating layers 10, 12. As can be seen in this figure, the vertical walls 22 and the exit of these cavities 20 are also not metallized.

[0131] A third SMD 3 (SMD#3), which may be a through-hole component assembled using the "pin-in-paste" method, is soldered into a cavity 20 formed from layer C 2 into the second (11), fifth (31), fourth (30), and third (12) insulating layers. As can be seen in this figure, the vertical walls 22 and the bottom 21 of this cavity 20 are metallized, but not its opening (no flange 23).

[0132] A fourth CMS 3 (CMS#4), which can for example be a BGA, is brazed into a cavity 20 formed from the C 2 layer in the second and fifth insulating layers 11, 31. As can be seen in this figure, the vertical walls 22 and the bottom 21 of these cavities 20 are metallized, but not their exit (no collar 23).

Claims

1. A method for manufacturing (S) an electronic board (1), said electronic board (1) comprising a multilayer printed circuit (2), said printed circuit (2) comprising at least four conductive layers (C1, C2, C3, C4, C5, C6, C7, C8) separated in pairs by insulating layers (10, 11, 12, 30, 31, 32, 33), including: - a first and a second conductive skin layer (C1, C2) attached on a first and a second insulating layer (10, 11), respectively, the first conductive skin layer (C1) being substantially planar and defining a plane (X; Y) normal to an axis Z, - a first and a second inner conductive layer (C3, C4), extending between the first and the second insulating layer (10, 11), respectively, and separated by a third insulating layer (12), at least the first inner conductive layer (C3) being treated so as to form at least one solder pad (4), the manufacturing method (S) being characterized in that it comprises the following steps: - forming (S1, S4) a first cavity (20) in the first conductive skin layer (C1) and in the first insulating layer (10), opposite the solder pad (4) of the first inner conductive layer (C3), so that at least part of the solder pad (4) is exposed, - filling (S5) the first cavity (20) with a metal alloy accompanied by a solder flux (24), - placing (S6) a first electronic component (3) in contact with the first conductive skin layer (C1) opposite the first cavity (20), - applying a heat treatment (S7) to the printed circuit (2) on which the first component (3) is placed in order to transform the metal alloy accompanied by the solder flux (24) into a solder joint (5) so as to attach the first component (3) to the printed circuit (2).

2. The manufacturing method (S) according to claim 1, wherein the first component (3) comprises at least one terminal and which comprises the formation (S1, S4) of as many first cavities (20) in the first conductive skin layer as the electronic component comprises terminals.

3. The manufacturing method (S) according to one of claims 1 to 2, wherein the first cavity (20) is formed (S1, S4) using at least one of the following techniques: surface photolithography, laser drilling, mechanical drilling, mechanical cutting.

4. The manufacturing method (S) according to one of claims 1 to 3, further comprising a step of metallizing (S2) the first cavity (20) in order to deposit a metal layer (13) in the first cavity (20).

5. The manufacturing method (S) according to claim 5, further comprising an additional step (S3) wherein part of the metal layer (13) of the first cavity (20) is removed prior to the step of filling (S5) the first cavity (20).

6. The manufacturing method (S) according to claim 5, wherein the partial removal (S3) of the metal layer (13) is carried out by laser or by mechanical cutting or by mechanical drilling.

7. The manufacturing method (S) according to one of claims 1 to 6, wherein the first inner conductive layer (C3) comprises an additional solder pad (4) and the manufacturing method (S) further comprises the following additional steps, prior to the heat treatment step: - forming (S1, S4) a second cavity (20) in the first insulating layer (10), opposite the additional solder pad (4), so that at least an additional part of the additional solder pad (4) is exposed, - filling (S5) the second cavity (20) with the metal alloy accompanied by a solder flux (24), and - placing (S6) a second electronic component (3) opposite the second cavity (20), the steps of filling (S5) of the first and second cavities (20) and of placing the components (3) being carried out substantially simultaneously.

8. The manufacturing method (S) according to one of claims 1 to 7, further comprising a step of etching the first conductive skin layer (C1).

9. The manufacturing method (S) according to one of claims 1 to 8, wherein the first cavity (20) is filled in accordance with at least one of the following filling techniques (S5): screen-printing with a screen-printing screen (7), screen-printing without screen-printing screen (7), jetting, passing through a turbulent wave, by soaking or passing through a metal alloy bath in reflow, wave soldering, manual soldering.

10. The manufacturing method (S) according to one of claims 1 to 9, wherein the second inner conductive layer (C4) is treated so as to form at least one solder pad (4), the manufacturing method (S) further comprising the following steps, prior to the heat treatment step (S7): - forming (S1, S4) a third cavity (20) in the first insulating layer (10) and in the third insulating layer (12), opposite the solder pad (4) of the second inner conductive layer (C4), so that at least part of the solder pad (4) of the second inner conductive layer (C4) is exposed, - filling (S5) the third cavity (20) with the metal alloy accompanied by a solder flux (24), and - placing (S6) a third additional electronic component (3) opposite the third cavity (20).

11. The manufacturing method (S) according to one of claims 1 to 10, wherein the second inner conductive layer (C4) is treated so as to form at least one solder pad (4), the manufacturing method (S) further comprising the following steps, prior to the heat treatment step: - forming (S1, S4) a fourth cavity (20) in the second conductive skin layer (C2) and in the second insulating layer (11), opposite the solder pad (4) of the second inner conductive layer (C4), so that at least part of the solder pad (4) of the second inner conductive layer (C4) is exposed, - filling (S5) the fourth cavity (20) with the metal alloy accompanied by a solder flux (24), and - placing (S6) a fourth electronic component (3) opposite the fourth cavity (20).

12. The method according to one of claims 1 to 11, further comprising, prior to the heat treatment step (S7), a step during which an additional layer (19) comprising an electrically insulating material is applied on the first conductive skin layer (C1), the first cavity (20) being partly formed in said additional layer (19) and the first component (3) being placed on the additional layer (19).

13. The method according to claim 12, wherein the electrically insulating material of the additional layer (19) has a first coefficient of thermal expansion along the axis Z, the metal alloy has a second coefficient of thermal expansion along the axis Z, and wherein the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion.

14. An electronic board (1) comprising a multilayer printed circuit (2), said printed circuit (2) comprising at least four conductive layers (C1, C2, C3, C4, C5, C6, C7, C8) separated in pairs by insulating layers (10, 11, 12), including: - a first and a second conductive skin layers (C1, C2) attached on a first and a second insulating layer (10, 11), respectively, the first conductive layer being substantially planar and defining a plane (X; Y) normal to an axis Z, - a first and a second inner conductive layers (C3, C4), extending between the first and the second insulating layers (10, 11), respectively, and separated by a third insulating layer (12), at least the first inner conductive layer (C3) being treated so as to form at least one solder pad (4), - a first cavity (20), formed in the first conductive skin layer (C1) and in the first insulating layer (10), said first cavity (20) exposing at least partly the solder pad (4), and - a first surface-mounted electronic component (3) comprising at least one terminal (8), said first component (3) being placed on the first conductive skin layer (C1) so as to be in contact or at a distance from the first conductive skin layer (C1) by means of a solder joint (5), the terminal (8) of the first component (3) being attached into the first cavity (20) by means of the solder joint (5).

15. The electronic board (1) according to claim 14, wherein an area of the first cavity, in the plane (X; Y), is at least equal to 0.04 mm2.

16. The electronic board (1) according to one of claims 14 and 15, comprising as many first cavities (20) as the electronic component has terminals.

17. The electronic board (1) according to one of claims 14 to 16, wherein the first cavity (20) comprises a metal layer (13) of metallization.

18. The electronic board (1) according to claim 17, wherein the first cavity (20) is partially covered by a metal layer (13) of metallization.

19. The electronic board (1) according to one of claims 14 to 18, further comprising a solder mask (17) applied on the first conductive layer (C1) and on top of the insulating layer (10) which is at least partially exposed and / or a metallic finish (18) applied on the first conductive skin layer (C1) and the areas of the first inner conductive layer (C3) which form the first cavity (20).

20. The electronic board (1) according to one of claims 14 to 19, wherein the first component (3) comprises an additional terminal (8), said terminal (8) being attached on the first conductive skin layer (C1) by means of a solder joint (5).

21. The electronic board (1) according to one of claims 14 to 20, wherein the second inner conductive layer (C4) is treated so as to form at least one solder pad (4), the electronic board (1) further comprising: - a second cavity (20), formed in the first insulating layer (10) and in the third insulating layer (12), opposite the second inner conductive layer (C4), and - a second surface-mounted electronic component (3) comprising at least one terminal (8), said second component (3) being in contact or at a distance from the first conductive skin layer (C1), the terminal (8) of the second component (3) being attached into the second cavity (20) by means of a solder joint (5).

22. The electronic board (1) according to one of claims 14 to 21, wherein the first component (3) further comprises an additional terminal (8), the second inner conductive layer (C4) is treated so as to form at least one solder pad (4) and the electronic board (1) further comprises an additional cavity (20), formed in the first insulating layer (10) and in the third insulating layer (12), opposite the solder pad (4) of the second inner conductive layer (C4), the additional terminal (8) of the component (3) being attached on said solder pad (4) in the additional cavity (20) by means of a solder joint (5).

23. The electronic board (1) according to one of claims 14 to 22, wherein the second inner conductive layer (C4) is treated so as to form at least one solder pad (4), the electronic board (1) further comprising: - a fourth cavity (20), formed in the second conductive skin layer (C2) and in the second insulating layer (11), opposite the second inner conductive layer (C4), and - a fourth surface-mounted electronic component (3) comprising at least one terminal (8), said fourth component (3) being in contact or at a distance from the second conductive skin layer (C2), the terminal (8) of the fourth component (3) being attached into the fourth cavity (20) by means of a solder joint (5).